Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.73 99.75 95.12 98.85 79.03 99.82 92.92 83.63


Total test records in report: 850
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T751 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.63519762069703556554633932924817081891726590980281411164908329793968644775939 Nov 22 12:34:13 PM PST 23 Nov 22 12:34:32 PM PST 23 407776267 ps
T752 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.106429718967595495245895692897108666384199991304058570176741285522015335458050 Nov 22 12:34:30 PM PST 23 Nov 22 12:34:49 PM PST 23 407776267 ps
T753 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.53485186476861819492825190350939513686322846146487387711473414831296881044505 Nov 22 12:34:16 PM PST 23 Nov 22 12:39:50 PM PST 23 7309292483 ps
T754 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.9855874769638269750256957958725181399653814867505449081238307883910188702791 Nov 22 12:34:15 PM PST 23 Nov 22 12:39:20 PM PST 23 7309292483 ps
T755 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.18400377161259133065164585857728860425306077074563980957871912107265080527907 Nov 22 12:34:32 PM PST 23 Nov 22 12:34:53 PM PST 23 407776267 ps
T756 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.67949779749419752984412520248920437175050008363380999335212337796971003526125 Nov 22 12:34:19 PM PST 23 Nov 22 12:34:35 PM PST 23 110671501 ps
T757 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.110894246181392356775629635025090765676515609523633501914412912108110844453797 Nov 22 12:34:26 PM PST 23 Nov 22 12:34:37 PM PST 23 162171089 ps
T758 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.65692974737890173962453415534014506168608228380368919909896238945750875343434 Nov 22 12:34:18 PM PST 23 Nov 22 12:39:27 PM PST 23 7309292483 ps
T759 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.66828529073545771604174657417240474152143546058839677767680903439593254962329 Nov 22 12:34:08 PM PST 23 Nov 22 12:34:23 PM PST 23 162171089 ps
T760 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.87534525038864671796020798098491626327670828647060032195728300181381913821044 Nov 22 12:34:21 PM PST 23 Nov 22 12:38:10 PM PST 23 5866161171 ps
T761 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.29379094107636741402021057184977163247246372037031827458080889029460969864994 Nov 22 12:33:59 PM PST 23 Nov 22 12:34:07 PM PST 23 162171089 ps
T762 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.13802980583713827900261353845824187010629126992619464371733590998380258103903 Nov 22 12:34:26 PM PST 23 Nov 22 12:39:28 PM PST 23 7309292483 ps
T763 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.61440332425338072529502343260893955540434642316934442151176085182907564801641 Nov 22 12:34:31 PM PST 23 Nov 22 12:35:07 PM PST 23 867915443 ps
T764 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.10880591175463989709850828416696261985352614543254568760753566712986708316344 Nov 22 12:34:15 PM PST 23 Nov 22 12:39:19 PM PST 23 7309292483 ps
T765 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.48405188856691594897251544805871844767815888782344099532101246980135977823521 Nov 22 12:34:30 PM PST 23 Nov 22 12:34:40 PM PST 23 110671501 ps
T766 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.23617695612301785416399194442340386705977147836594513987798973957622255698800 Nov 22 12:34:34 PM PST 23 Nov 22 12:34:48 PM PST 23 162171089 ps
T767 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.57779311099880404448716618739552515694029075469498090649083714036624198190995 Nov 22 12:34:19 PM PST 23 Nov 22 12:34:29 PM PST 23 10547302 ps
T768 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.63577963699062914219437420562087516865070484542553117438790261970776776892917 Nov 22 12:34:39 PM PST 23 Nov 22 12:34:46 PM PST 23 10547302 ps
T769 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.129522810382273998318247681961173468537395363453661637143056501737446165335 Nov 22 12:34:18 PM PST 23 Nov 22 12:34:35 PM PST 23 171671013 ps
T770 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.8281710467030457080707039425828157307063969232765907268477212903337790999371 Nov 22 12:35:26 PM PST 23 Nov 22 12:40:12 PM PST 23 7309292483 ps
T771 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.87146068323472486396400396388017022891936777383697639563167192389403734418884 Nov 22 12:34:17 PM PST 23 Nov 22 12:34:32 PM PST 23 110671501 ps
T772 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.13501054620356987403637333702024577765132416954256050009715614090517186209272 Nov 22 12:34:04 PM PST 23 Nov 22 12:34:21 PM PST 23 407776267 ps
T773 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.15176324477010306117799158836256607723563063500280525451409540622642591276210 Nov 22 12:34:19 PM PST 23 Nov 22 12:34:29 PM PST 23 10547302 ps
T774 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.76882797669182066018139629715286442300650335022854037225199284163850066593967 Nov 22 12:34:16 PM PST 23 Nov 22 12:34:59 PM PST 23 867915443 ps
T775 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.18339005298116956266918223561856448463984123579156386386446561712042576260959 Nov 22 12:34:55 PM PST 23 Nov 22 12:34:57 PM PST 23 10547302 ps
T776 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.45649345600395799474068974446690414965191257021598044881470770638497640744750 Nov 22 12:34:32 PM PST 23 Nov 22 12:35:43 PM PST 23 1596552471 ps
T777 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.110165306402714547523363869043230396226257439536884242470038905314866852872577 Nov 22 12:34:03 PM PST 23 Nov 22 12:38:58 PM PST 23 7309292483 ps
T778 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.7049473799589771180637958042951022457572153474834561413496271198794946374797 Nov 22 12:34:20 PM PST 23 Nov 22 12:34:29 PM PST 23 10547302 ps
T779 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.93913837793128932399973386396850977648971020567751196654431647798395606483160 Nov 22 12:34:36 PM PST 23 Nov 22 12:34:43 PM PST 23 10547302 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.76069156519238285147284704809245410630479056179362875662194699689471623363929 Nov 22 12:34:11 PM PST 23 Nov 22 12:34:23 PM PST 23 110671501 ps
T781 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.68543606189886922293768181753702276256207059377415077467522508586358159873147 Nov 22 12:34:24 PM PST 23 Nov 22 12:49:58 PM PST 23 22019264088 ps
T782 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.28742971271601474361135249386220532175322504609126550708977580966656365649857 Nov 22 12:34:18 PM PST 23 Nov 22 12:35:02 PM PST 23 867915443 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.80846503241143192795635509505625491188725064172814070677256011614796668898254 Nov 22 12:34:08 PM PST 23 Nov 22 12:34:48 PM PST 23 867915443 ps
T784 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.28945188289215547301692067745931953719922103704690672575708579170209735544807 Nov 22 12:34:31 PM PST 23 Nov 22 12:34:35 PM PST 23 10547302 ps
T785 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.24130378542365810251328703173454212935240063099572667988719091610542949965701 Nov 22 12:34:54 PM PST 23 Nov 22 12:34:57 PM PST 23 10547302 ps
T786 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.94045602631860706497053570858352059748440340973500745840031954878139372224650 Nov 22 12:34:33 PM PST 23 Nov 22 12:34:39 PM PST 23 10547302 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.33785468681726146670648223655336918982311722635564834154715222066150428046980 Nov 22 12:34:18 PM PST 23 Nov 22 12:50:28 PM PST 23 22019264088 ps
T788 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.114340108249850160129051446126089518456729189844780803718040188464178584722138 Nov 22 12:34:46 PM PST 23 Nov 22 12:34:52 PM PST 23 10547302 ps
T789 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.7573747690303783223372706210742788477140696730623789987774131606314601848998 Nov 22 12:34:08 PM PST 23 Nov 22 12:34:23 PM PST 23 162171089 ps
T790 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.108569535291820291843784197440026585796421197627601132870398375324222294615767 Nov 22 12:35:18 PM PST 23 Nov 22 12:35:27 PM PST 23 110671501 ps
T791 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.40053613484552368803140394070809264980828255184835270470474224740284699498437 Nov 22 12:34:11 PM PST 23 Nov 22 12:39:25 PM PST 23 7309292483 ps
T792 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.100312404638912491252921134225020712409073219258891994682969151396166544763319 Nov 22 12:34:07 PM PST 23 Nov 22 12:35:10 PM PST 23 1596552471 ps
T793 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.12172276845965515052907874085618246245125894379378053397430801792074206563336 Nov 22 12:34:22 PM PST 23 Nov 22 12:34:36 PM PST 23 162171089 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.82442366627086033871780963193642463182886359899579920932084096818113797091846 Nov 22 12:34:06 PM PST 23 Nov 22 12:34:14 PM PST 23 10547302 ps
T795 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4884154850906548411499084082187059912757586468275324672611763755522368967649 Nov 22 12:34:31 PM PST 23 Nov 22 12:34:49 PM PST 23 407776267 ps
T796 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.19868556767283341220409231144623645350366864140370873581753314018706729279004 Nov 22 12:34:34 PM PST 23 Nov 22 12:50:36 PM PST 23 22019264088 ps
T797 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.77099287703749871611407601480556653188572496964158581561478478356187738856610 Nov 22 12:34:07 PM PST 23 Nov 22 12:34:21 PM PST 23 110671501 ps
T798 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.71039475347584370166428025124885796326601077287028322617810678382833298733609 Nov 22 12:34:52 PM PST 23 Nov 22 12:34:55 PM PST 23 10547302 ps
T799 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.65551452343479971335666747557882081966034855038013894715702614263412817607220 Nov 22 12:34:19 PM PST 23 Nov 22 12:34:29 PM PST 23 10547302 ps
T800 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.76783303992128760430461645093101994350694013226449725705161849483582327438458 Nov 22 12:34:15 PM PST 23 Nov 22 12:40:01 PM PST 23 10186483751 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.22260294389062603691157310896654248662534968877521502167932744580358208422241 Nov 22 12:34:13 PM PST 23 Nov 22 12:35:20 PM PST 23 1596552471 ps
T802 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.43956509018292352424258912948742784823709843455219145136439540463276769326531 Nov 22 12:34:31 PM PST 23 Nov 22 12:34:43 PM PST 23 162171089 ps
T803 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.27357694617764499504025285692870736582992866762528446158725482352311119909628 Nov 22 12:34:46 PM PST 23 Nov 22 12:34:57 PM PST 23 162171089 ps
T804 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.11804855723303920309236689932986119123318986592495699972930688814655217044205 Nov 22 12:34:32 PM PST 23 Nov 22 12:35:12 PM PST 23 867915443 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.69836005954036869851754638357131474850601165462212162339080189353847400046188 Nov 22 12:34:28 PM PST 23 Nov 22 12:49:03 PM PST 23 22019264088 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.22363992841926511526705667288991272587281922519994028524289271440117079883085 Nov 22 12:34:21 PM PST 23 Nov 22 12:35:29 PM PST 23 1596552471 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.44884280187402305823652412931515479282601422835533183406575781548183270458969 Nov 22 12:34:10 PM PST 23 Nov 22 12:34:17 PM PST 23 10547302 ps
T808 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.27891395303223242475999929376750916827786249922034599721354015801218875570684 Nov 22 12:34:54 PM PST 23 Nov 22 12:34:57 PM PST 23 10547302 ps
T809 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.83852275630202082741577838808418102273591828397429566648044030379194591516032 Nov 22 12:34:30 PM PST 23 Nov 22 12:34:34 PM PST 23 10547302 ps
T810 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.38734378586649478371729150439488241924876046070244013674717922608885789229834 Nov 22 12:34:22 PM PST 23 Nov 22 12:35:01 PM PST 23 867915443 ps
T811 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.75226821034794805812639179436182505147395381395439030760332877019394895470037 Nov 22 12:34:36 PM PST 23 Nov 22 12:39:35 PM PST 23 7309292483 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.79409351823733065601204988609485417070644083691275852537518699299731300162946 Nov 22 12:34:10 PM PST 23 Nov 22 12:34:24 PM PST 23 171671013 ps
T813 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.88369765424619183740948421474964332559402945756782479885945921087052403224427 Nov 22 12:34:14 PM PST 23 Nov 22 12:34:36 PM PST 23 407776267 ps
T814 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.73345949775859867576366340182556900578558970119643981489537678102230428398375 Nov 22 12:34:32 PM PST 23 Nov 22 12:39:40 PM PST 23 7309292483 ps
T815 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.104182599643329131948735989945640480581959073786744781208080353740359992365626 Nov 22 12:34:23 PM PST 23 Nov 22 12:39:29 PM PST 23 7309292483 ps
T816 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.103923289902070718283242748550805149988031176219483780515687242820607144202565 Nov 22 12:34:25 PM PST 23 Nov 22 12:39:31 PM PST 23 7309292483 ps
T817 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.111821695074286505076654540064745263408419415080869178159835458637499351527375 Nov 22 12:34:38 PM PST 23 Nov 22 12:34:45 PM PST 23 10547302 ps
T818 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.86992619231301533618149038826680622793861565891942777277264323025322035161585 Nov 22 12:34:22 PM PST 23 Nov 22 12:35:32 PM PST 23 1596552471 ps
T819 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.85884632127427678904070142949080877278499773285993505138187216417473961028332 Nov 22 12:34:04 PM PST 23 Nov 22 12:49:52 PM PST 23 22019264088 ps
T820 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.53515487721228644788501402460261469997868838040713299940474425600057812985419 Nov 22 12:34:16 PM PST 23 Nov 22 12:50:11 PM PST 23 22019264088 ps
T821 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.100908562312692595333842116257475712096750007080291465033365524359467458427355 Nov 22 12:34:51 PM PST 23 Nov 22 12:34:55 PM PST 23 10547302 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.58403746073067191327521349807644505251766228286867951753820309724686756112114 Nov 22 12:34:01 PM PST 23 Nov 22 12:37:58 PM PST 23 5866161171 ps
T823 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.104021818216208732136776107460490871942789301472542387642847895758709390478445 Nov 22 12:34:21 PM PST 23 Nov 22 12:34:29 PM PST 23 10547302 ps
T824 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.49851261075141369444633271878069177552335525348083216482552867351109159437443 Nov 22 12:34:26 PM PST 23 Nov 22 12:34:31 PM PST 23 10547302 ps
T825 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.89359320463849269601341874604993150987283197323420067358078592010953736983087 Nov 22 12:34:16 PM PST 23 Nov 22 12:34:25 PM PST 23 10547302 ps
T826 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.110450628508340661293539125113198336202288367459263270677942777258299503349449 Nov 22 12:34:33 PM PST 23 Nov 22 12:35:39 PM PST 23 1596552471 ps
T827 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.108707880957100942636811721583183009263803631143478953323535881036510664142690 Nov 22 12:34:21 PM PST 23 Nov 22 12:39:41 PM PST 23 7309292483 ps
T828 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.69929993400775887712521505056986678033962571016849172425243890094355867632832 Nov 22 12:34:08 PM PST 23 Nov 22 12:34:17 PM PST 23 10547302 ps
T829 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.57523758290454462721544289066080526012423335105375340502783439468562873351490 Nov 22 12:34:31 PM PST 23 Nov 22 12:34:52 PM PST 23 407776267 ps
T830 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.55710931570197927872574515265447196757013507996311851879192508703312705021599 Nov 22 12:34:26 PM PST 23 Nov 22 12:49:48 PM PST 23 22019264088 ps
T831 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.59233182324841666654895094370403998274104269711577491643270945808157601098124 Nov 22 12:34:23 PM PST 23 Nov 22 12:35:32 PM PST 23 1596552471 ps
T832 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.103906492630423042640672262743234537429664247725936796085671172694542295598821 Nov 22 12:35:00 PM PST 23 Nov 22 12:35:03 PM PST 23 10547302 ps
T833 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.14393292621337466115044786848458681333106356418774923154391045360535508969759 Nov 22 12:34:22 PM PST 23 Nov 22 12:49:40 PM PST 23 22019264088 ps
T834 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.12195867894283216487423424863137634503232039766110033359183767121652564865907 Nov 22 12:34:22 PM PST 23 Nov 22 12:39:33 PM PST 23 7309292483 ps
T835 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.34317374521912115231214827338018668146306587685747746553956688164520990924558 Nov 22 12:34:15 PM PST 23 Nov 22 12:38:13 PM PST 23 5866161171 ps
T836 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2731879962177165692998672317276902471157402732056668146588735864777241160506 Nov 22 12:34:10 PM PST 23 Nov 22 12:49:24 PM PST 23 22019264088 ps
T837 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.29028950894591003518478057169821791715740710474740147371687674364251748686160 Nov 22 12:34:20 PM PST 23 Nov 22 12:35:33 PM PST 23 1596552471 ps
T838 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.61024348934774077197677333211307907856903411651572892263599937297440881252776 Nov 22 12:34:15 PM PST 23 Nov 22 12:35:30 PM PST 23 1596552471 ps
T839 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.106945499880890511267730189900180303007701964011428798980396575650253845880382 Nov 22 12:34:08 PM PST 23 Nov 22 12:34:32 PM PST 23 407776267 ps
T840 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.79042503275009437271692259197399461663734269262173169449322288343842543775122 Nov 22 12:34:57 PM PST 23 Nov 22 12:35:00 PM PST 23 10547302 ps
T841 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.72276850152976168850434781207325577250298268440289630725407709830262331738692 Nov 22 12:34:37 PM PST 23 Nov 22 12:34:51 PM PST 23 110671501 ps
T842 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.44952579859519537612346286603288576045542588300547573971875360642491295195646 Nov 22 12:34:51 PM PST 23 Nov 22 12:34:54 PM PST 23 10547302 ps
T843 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.97252998599862036051066426251067784513280819705554878541500940476608811635379 Nov 22 12:34:27 PM PST 23 Nov 22 12:34:43 PM PST 23 162171089 ps
T844 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.63617427819510464002468017202945228172068288307894917966693954316193178493476 Nov 22 12:34:22 PM PST 23 Nov 22 12:34:35 PM PST 23 162171089 ps
T845 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.32837211617757947662843591475052915820790670752182106031517202562265622532758 Nov 22 12:34:21 PM PST 23 Nov 22 12:34:35 PM PST 23 162171089 ps
T846 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.14534530329631905172660186327595594215659250744831270930676498516552859588860 Nov 22 12:34:32 PM PST 23 Nov 22 12:34:38 PM PST 23 10547302 ps
T847 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.32102757268148905282449551059744435718472634353543205118749746527328286917038 Nov 22 12:34:18 PM PST 23 Nov 22 12:34:34 PM PST 23 162171089 ps
T848 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.46226794556345951721019915715668435541640015827775163193504803757085766243965 Nov 22 12:34:26 PM PST 23 Nov 22 12:35:33 PM PST 23 1596552471 ps
T849 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.52651293897383382804193254146802809187991453827282449923140243136830961636336 Nov 22 12:34:03 PM PST 23 Nov 22 12:40:10 PM PST 23 10186483751 ps
T850 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.52680555487994155431644538763008373788344433150588445596748012526978525982677 Nov 22 12:34:13 PM PST 23 Nov 22 12:48:49 PM PST 23 22019264088 ps

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.40081934242230483079309583219198149894023402202747486923312979055460008194905
Short name T90
Test name
Test status
Simulation time 162171089 ps
CPU time 7.04 seconds
Started Nov 22 12:34:35 PM PST 23
Finished Nov 22 12:34:48 PM PST 23
Peak memory 240352 kb
Host smart-b95dd0e2-67b9-44a2-a78a-97c0d94734be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=40081934242230483079309583219198149894023402202747486923312979055460008194905 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.alert_handler_csr_rw.40081934242230483079309583219198149894023402202747486923312979055460008194905
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.46084497407050125048210736703189506127799690387113828185784337423746889921143
Short name T17
Test name
Test status
Simulation time 79866015596 ps
CPU time 2862.04 seconds
Started Nov 22 01:12:12 PM PST 23
Finished Nov 22 01:59:57 PM PST 23
Peak memory 298184 kb
Host smart-0d06902c-32a6-4479-9a87-255d9f80a258
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460844974070501250482107367031895061277996903871
13828185784337423746889921143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.460844974
07050125048210736703189506127799690387113828185784337423746889921143
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.55758988474910601824220399053015343756374989618235950738459233125297297865803
Short name T34
Test name
Test status
Simulation time 10547302 ps
CPU time 1.4 seconds
Started Nov 22 12:34:36 PM PST 23
Finished Nov 22 12:34:44 PM PST 23
Peak memory 235660 kb
Host smart-61b9cbd2-15e3-4ad2-829e-25839343c81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=55758988474910601824220399053015343756374989618235950738459233125297297865803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 26.alert_handler_intr_test.55758988474910601824220399053015343756374989618235950738459233125297297865803
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.56104507788807112009681617927515932249733611562202499429988753803727104390815
Short name T6
Test name
Test status
Simulation time 1596552471 ps
CPU time 64.08 seconds
Started Nov 22 12:34:15 PM PST 23
Finished Nov 22 12:35:26 PM PST 23
Peak memory 240400 kb
Host smart-28db7a79-c527-4853-8eda-be86c12f78ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=56104507788807112009681617927515932249733611562202499429988753803727104390815 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.56104507788807112009681617927515932249733611562202499429988753803727104390815
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.25841173181390873602698100028683548674496533584097882984347853705537496238933
Short name T21
Test name
Test status
Simulation time 740845031 ps
CPU time 22.92 seconds
Started Nov 22 01:12:11 PM PST 23
Finished Nov 22 01:12:37 PM PST 23
Peak memory 274844 kb
Host smart-f7c035d7-afdc-487d-ae23-b53ce87346d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=25841173181390873602698100028683548674496533584097882984347853705537496238933 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.alert_handler_sec_cm.25841173181390873602698100028683548674496533584097882984347853705537496238933
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.19706361997559123149483254368856148273205915385426491185307264346212609117096
Short name T57
Test name
Test status
Simulation time 1452482195 ps
CPU time 34.33 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:12:41 PM PST 23
Peak memory 240544 kb
Host smart-9bb19101-2e93-44fb-bef0-2ec28fb0b42a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=19706361997559123149483254368856148273205915385426491185307264346212609117096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.alert_handler_entropy_stress.19706361997559123149483254368856148273205915385426491185307264346212609117096
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.48656030601094360095809864757989543259311672423997591028424829737077923926311
Short name T105
Test name
Test status
Simulation time 7309292483 ps
CPU time 302.44 seconds
Started Nov 22 12:34:28 PM PST 23
Finished Nov 22 12:39:34 PM PST 23
Peak memory 272312 kb
Host smart-dedb67b8-66c0-44d6-85f2-4186e7256d31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48656030601094360095809864757989543259311672423997591028424829737077923926311 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.48656030601094360095809864757989543259311672423997591028424829737077923926311
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.16129309945027659303290525194197866064874264409286047773074367501997525210973
Short name T30
Test name
Test status
Simulation time 58351884139 ps
CPU time 1870.93 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:43:24 PM PST 23
Peak memory 289316 kb
Host smart-aa2ad744-4980-4e9e-848b-1905d0dc8cf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16129309945027659303290525194197866064874264409286047773074367501997525210973 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.alert_handler_lpg.16129309945027659303290525194197866064874264409286047773074367501997525210973
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.8810391360263304579586713064523394381834101340806045071468746002818055109653
Short name T12
Test name
Test status
Simulation time 22019264088 ps
CPU time 901.73 seconds
Started Nov 22 12:34:24 PM PST 23
Finished Nov 22 12:49:30 PM PST 23
Peak memory 273396 kb
Host smart-77fa0186-7e77-4b57-aed3-df8f6df58305
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88103913602633045795867130645233943818341013408060450714687460028180551
09653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.88103913602633045795867
13064523394381834101340806045071468746002818055109653
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.32801037474880512370287184196497843970887149483896598699953538210437735433697
Short name T26
Test name
Test status
Simulation time 63383433172 ps
CPU time 2065.62 seconds
Started Nov 22 01:13:47 PM PST 23
Finished Nov 22 01:48:22 PM PST 23
Peak memory 289756 kb
Host smart-76f298bb-3ffc-4ac4-8a69-f19d7c9589c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32801037474880512370287184196497843970887149483896598699953538210437735433697 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.32801037474880512370287184196497843970887149483896598699953538
210437735433697
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.9542875837701917613220965885202812179983352136274502630597072768940435880425
Short name T32
Test name
Test status
Simulation time 17273552054 ps
CPU time 389.81 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 247412 kb
Host smart-7c29cf12-2643-45d1-9c89-2753a4ce33b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9542875837701917613220965885202812179983352136274502630597072768940435880425 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.9542875837701917613220965885202812179983352136274502630597072768940435880425
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.34342144189558730237781277628032258165744814125063698753468211184323211819577
Short name T66
Test name
Test status
Simulation time 30823729350 ps
CPU time 1040.28 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:29:28 PM PST 23
Peak memory 272260 kb
Host smart-a45c971e-7247-44a8-a33e-493fbe34ed01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34342144189558730237781277628032258165744814125063698753468211184323211819577 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.alert_handler_entropy.34342144189558730237781277628032258165744814125063698753468211184323211819577
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.103502935348752871995964694633441487597379824449297999862589418072328257192262
Short name T166
Test name
Test status
Simulation time 48172572717 ps
CPU time 1590.07 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:38:38 PM PST 23
Peak memory 272504 kb
Host smart-5e73a46e-c0ae-4426-9f61-7f3b577665d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103502935348752871995964694633441487597379824449297999862589418072328257192262 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.103502935348752871995964694633441487597379824449297999862589418072328257192262
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.74991609142350354992786167825417809297127680390238887118987240957766414827237
Short name T2
Test name
Test status
Simulation time 407776267 ps
CPU time 16.22 seconds
Started Nov 22 12:34:03 PM PST 23
Finished Nov 22 12:34:20 PM PST 23
Peak memory 248528 kb
Host smart-041efc33-aa17-479c-86fe-90416768eb0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74991609142350354992786167825417809297127680390238887118987240957766414827237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.alert_handler_tl_errors.74991609142350354992786167825417809297127680390238887118987240957766414827237
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.33798228115508058028233330722992667161116340412389382720263037539489498610393
Short name T23
Test name
Test status
Simulation time 1399732617 ps
CPU time 45.43 seconds
Started Nov 22 01:12:14 PM PST 23
Finished Nov 22 01:13:02 PM PST 23
Peak memory 255480 kb
Host smart-3cb1a992-f164-406b-b970-c0edcc6a3be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33798
228115508058028233330722992667161116340412389382720263037539489498610393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
alert_handler_random_alerts.33798228115508058028233330722992667161116340412389382720263037539489498610393
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.74929927974738507267674424513013509335303394378523812570085781894701129962403
Short name T74
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.1 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:54 PM PST 23
Peak memory 254808 kb
Host smart-74dc40c9-ba4b-43a6-9879-afba35a964ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74929
927974738507267674424513013509335303394378523812570085781894701129962403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.alert_handler_random_classes.74929927974738507267674424513013509335303394378523812570085781894701129962403
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.82978788974452321429572132597770613343403034083688663108592382009627923779284
Short name T119
Test name
Test status
Simulation time 49707703 ps
CPU time 2.97 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:14 PM PST 23
Peak memory 249036 kb
Host smart-c739d3da-c5a1-427b-b540-ecd188ac8490
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=82978788974452321429572132597770613343403034083688663108592382009627923779284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.alert_handler_alert_accum_saturation.82978788974452321429572132597770613343403034083688663108592382009627923779284
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.58403746073067191327521349807644505251766228286867951753820309724686756112114
Short name T822
Test name
Test status
Simulation time 5866161171 ps
CPU time 234.44 seconds
Started Nov 22 12:34:01 PM PST 23
Finished Nov 22 12:37:58 PM PST 23
Peak memory 240408 kb
Host smart-0aa8dd4e-75e5-4029-8395-56d894932080
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=58403746073067191327521349807644505251766228286867951753820309724686756112114 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.58403746073067191327521349807644505251766228286867951753820309724686756112114
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.60397745953031632917485636414383697242362747002882418881817194267269332488163
Short name T112
Test name
Test status
Simulation time 10186483751 ps
CPU time 353.12 seconds
Started Nov 22 12:34:25 PM PST 23
Finished Nov 22 12:40:22 PM PST 23
Peak memory 240460 kb
Host smart-1de0ab74-2a5c-43af-ad6f-2c727fbef31a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=60397745953031632917485636414383697242362747002882418881817194267269332488163 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.60397745953031632917485636414383697242362747002882418881817194267269332488163
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.8653127148235841183587827564718951217534270420939647864803032533892403408838
Short name T715
Test name
Test status
Simulation time 171671013 ps
CPU time 7.82 seconds
Started Nov 22 12:35:18 PM PST 23
Finished Nov 22 12:35:27 PM PST 23
Peak memory 240396 kb
Host smart-50f8fd4e-76b5-4da6-afc3-83d7e987f318
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=8653127148235841183587827564718951217534270420939647864803032533892403408838 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.8653127148235841183587827564718951217534270420939647864803032533892403408838
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.77099287703749871611407601480556653188572496964158581561478478356187738856610
Short name T797
Test name
Test status
Simulation time 110671501 ps
CPU time 7.02 seconds
Started Nov 22 12:34:07 PM PST 23
Finished Nov 22 12:34:21 PM PST 23
Peak memory 253976 kb
Host smart-21f123d5-1186-46c1-b820-da9afc8e669d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77099287703749871611407601480556653188572496964158581561478478356187738856
610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_rw_with_rand_reset.77099287703749871611407601480
556653188572496964158581561478478356187738856610
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.97437699555280835312693402122819254508769911511706352310278279674542784383222
Short name T714
Test name
Test status
Simulation time 162171089 ps
CPU time 7.08 seconds
Started Nov 22 12:34:03 PM PST 23
Finished Nov 22 12:34:11 PM PST 23
Peak memory 240280 kb
Host smart-47a1b264-ef1d-4eab-b038-87acfb03fc77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=97437699555280835312693402122819254508769911511706352310278279674542784383222 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.alert_handler_csr_rw.97437699555280835312693402122819254508769911511706352310278279674542784383222
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.69929993400775887712521505056986678033962571016849172425243890094355867632832
Short name T828
Test name
Test status
Simulation time 10547302 ps
CPU time 1.37 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:17 PM PST 23
Peak memory 235696 kb
Host smart-77de9e46-9556-4bc5-afc7-32130d8a1391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=69929993400775887712521505056986678033962571016849172425243890094355867632832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.alert_handler_intr_test.69929993400775887712521505056986678033962571016849172425243890094355867632832
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.93140319331781164129033879309625235646995229827640661261316959903229932914010
Short name T88
Test name
Test status
Simulation time 867915443 ps
CPU time 32.09 seconds
Started Nov 22 12:34:05 PM PST 23
Finished Nov 22 12:34:40 PM PST 23
Peak memory 248516 kb
Host smart-67fac6de-4919-486b-80be-b93676c1d6ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=93140319331781164129033879309625235646995229827640661261316959903229932914010 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.93140319331781164129033879309625235646995229827640661261316959903229932914010
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.12195867894283216487423424863137634503232039766110033359183767121652564865907
Short name T834
Test name
Test status
Simulation time 7309292483 ps
CPU time 305.22 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:39:33 PM PST 23
Peak memory 272356 kb
Host smart-8cb5ea70-5640-47f3-baf9-fbf50de25d54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12195867894283216487423424863137634503232039766110033359183767121652564865907 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.12195867894283216487423424863137634503232039766110033359183767121652564865907
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.10308645437815554445357970010934046308505117385521287870572509551862380314263
Short name T698
Test name
Test status
Simulation time 22019264088 ps
CPU time 855.22 seconds
Started Nov 22 12:34:06 PM PST 23
Finished Nov 22 12:48:28 PM PST 23
Peak memory 273344 kb
Host smart-0d5c6a9e-d3b7-48c9-8d6c-ff222506a4a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10308645437815554445357970010934046308505117385521287870572509551862380
314263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.10308645437815554445357
970010934046308505117385521287870572509551862380314263
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.29028950894591003518478057169821791715740710474740147371687674364251748686160
Short name T837
Test name
Test status
Simulation time 1596552471 ps
CPU time 66.08 seconds
Started Nov 22 12:34:20 PM PST 23
Finished Nov 22 12:35:33 PM PST 23
Peak memory 240392 kb
Host smart-846150b9-1ee4-450f-943e-18c38ce206e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=29028950894591003518478057169821791715740710474740147371687674364251748686160 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.29028950894591003518478057169821791715740710474740147371687674364251748686160
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.89886928655085139155532051690153459651353052859805020824549048621607241261030
Short name T16
Test name
Test status
Simulation time 5866161171 ps
CPU time 219.28 seconds
Started Nov 22 12:34:10 PM PST 23
Finished Nov 22 12:37:55 PM PST 23
Peak memory 240444 kb
Host smart-f9aeec5f-b77b-4c54-a1c8-5753a0f010e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=89886928655085139155532051690153459651353052859805020824549048621607241261030 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.89886928655085139155532051690153459651353052859805020824549048621607241261030
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.107671829002134003248728381680199021169571718973205994120125670431854394337425
Short name T729
Test name
Test status
Simulation time 10186483751 ps
CPU time 361.11 seconds
Started Nov 22 12:34:14 PM PST 23
Finished Nov 22 12:40:22 PM PST 23
Peak memory 240460 kb
Host smart-8ca038ec-3938-46e6-890b-14fbd442f0d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=107671829002134003248728381680199021169571718973205994120125670431854394337425 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.107671829002134003248728381680199021169571718973205994120125670431854394337425
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.79409351823733065601204988609485417070644083691275852537518699299731300162946
Short name T812
Test name
Test status
Simulation time 171671013 ps
CPU time 8.1 seconds
Started Nov 22 12:34:10 PM PST 23
Finished Nov 22 12:34:24 PM PST 23
Peak memory 240384 kb
Host smart-d8272d8e-78fc-47cb-a981-72b46b3dd7f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=79409351823733065601204988609485417070644083691275852537518699299731300162946 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.79409351823733065601204988609485417070644083691275852537518699299731300162946
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.62389440678274562311897713723022570673837699088065554516779142265513552195678
Short name T716
Test name
Test status
Simulation time 110671501 ps
CPU time 6.87 seconds
Started Nov 22 12:34:10 PM PST 23
Finished Nov 22 12:34:23 PM PST 23
Peak memory 253940 kb
Host smart-6fa23f83-f73a-42b8-8052-8cd3428f6ea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62389440678274562311897713723022570673837699088065554516779142265513552195
678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_rw_with_rand_reset.62389440678274562311897713723
022570673837699088065554516779142265513552195678
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.66828529073545771604174657417240474152143546058839677767680903439593254962329
Short name T759
Test name
Test status
Simulation time 162171089 ps
CPU time 7.38 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:23 PM PST 23
Peak memory 240340 kb
Host smart-f37f9560-4d3b-44ea-bd4c-609ec3051d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=66828529073545771604174657417240474152143546058839677767680903439593254962329 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.alert_handler_csr_rw.66828529073545771604174657417240474152143546058839677767680903439593254962329
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.44884280187402305823652412931515479282601422835533183406575781548183270458969
Short name T807
Test name
Test status
Simulation time 10547302 ps
CPU time 1.44 seconds
Started Nov 22 12:34:10 PM PST 23
Finished Nov 22 12:34:17 PM PST 23
Peak memory 235640 kb
Host smart-2d307e88-3ba4-4da9-b3af-6078bc4db441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=44884280187402305823652412931515479282601422835533183406575781548183270458969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.alert_handler_intr_test.44884280187402305823652412931515479282601422835533183406575781548183270458969
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.21376580051354236007436671496041541340327747869159169813728888711253623155034
Short name T104
Test name
Test status
Simulation time 867915443 ps
CPU time 33.37 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:49 PM PST 23
Peak memory 248516 kb
Host smart-7915598f-355a-49e1-a34f-71135b521642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=21376580051354236007436671496041541340327747869159169813728888711253623155034 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.21376580051354236007436671496041541340327747869159169813728888711253623155034
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.12424540290489365359917622825033151777849440404540842253870381750018223649241
Short name T712
Test name
Test status
Simulation time 7309292483 ps
CPU time 314.11 seconds
Started Nov 22 12:34:13 PM PST 23
Finished Nov 22 12:39:32 PM PST 23
Peak memory 272344 kb
Host smart-25f4c75f-eeda-400a-8125-879714b1c25e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12424540290489365359917622825033151777849440404540842253870381750018223649241 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.12424540290489365359917622825033151777849440404540842253870381750018223649241
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.85884632127427678904070142949080877278499773285993505138187216417473961028332
Short name T819
Test name
Test status
Simulation time 22019264088 ps
CPU time 946.43 seconds
Started Nov 22 12:34:04 PM PST 23
Finished Nov 22 12:49:52 PM PST 23
Peak memory 273408 kb
Host smart-43ac1af6-32e8-4a9a-baa7-178cd1cd080b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85884632127427678904070142949080877278499773285993505138187216417473961
028332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.85884632127427678904070
142949080877278499773285993505138187216417473961028332
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.13501054620356987403637333702024577765132416954256050009715614090517186209272
Short name T772
Test name
Test status
Simulation time 407776267 ps
CPU time 15.86 seconds
Started Nov 22 12:34:04 PM PST 23
Finished Nov 22 12:34:21 PM PST 23
Peak memory 248596 kb
Host smart-38675730-0008-40a9-a5e7-29e3571a901b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=13501054620356987403637333702024577765132416954256050009715614090517186209272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.alert_handler_tl_errors.13501054620356987403637333702024577765132416954256050009715614090517186209272
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.80647882823961182235279202779714299131037784346583871463752708020693603221260
Short name T705
Test name
Test status
Simulation time 1596552471 ps
CPU time 62.71 seconds
Started Nov 22 12:34:11 PM PST 23
Finished Nov 22 12:35:19 PM PST 23
Peak memory 240268 kb
Host smart-a5b2bd80-fc5d-46c5-ac2d-5a8b2300d431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=80647882823961182235279202779714299131037784346583871463752708020693603221260 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.80647882823961182235279202779714299131037784346583871463752708020693603221260
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.67949779749419752984412520248920437175050008363380999335212337796971003526125
Short name T756
Test name
Test status
Simulation time 110671501 ps
CPU time 7.38 seconds
Started Nov 22 12:34:19 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 253744 kb
Host smart-bd45a875-1ad0-481f-88a8-363306979702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67949779749419752984412520248920437175050008363380999335212337796971003526
125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem_rw_with_rand_reset.6794977974941975298441252024
8920437175050008363380999335212337796971003526125
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.110894246181392356775629635025090765676515609523633501914412912108110844453797
Short name T757
Test name
Test status
Simulation time 162171089 ps
CPU time 7.35 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:34:37 PM PST 23
Peak memory 240304 kb
Host smart-35c4b1cb-f42a-414e-96ad-259c2e201951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=110894246181392356775629635025090765676515609523633501914412912108110844453797 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.alert_handler_csr_rw.110894246181392356775629635025090765676515609523633501914412912108110844453797
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.49851261075141369444633271878069177552335525348083216482552867351109159437443
Short name T824
Test name
Test status
Simulation time 10547302 ps
CPU time 1.42 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:34:31 PM PST 23
Peak memory 235644 kb
Host smart-d06284f8-384e-4ec6-8265-688a6c30b981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=49851261075141369444633271878069177552335525348083216482552867351109159437443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.alert_handler_intr_test.49851261075141369444633271878069177552335525348083216482552867351109159437443
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.28742971271601474361135249386220532175322504609126550708977580966656365649857
Short name T782
Test name
Test status
Simulation time 867915443 ps
CPU time 35.33 seconds
Started Nov 22 12:34:18 PM PST 23
Finished Nov 22 12:35:02 PM PST 23
Peak memory 248636 kb
Host smart-fdff4e68-4bd0-4a3d-845f-07210fffac8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=28742971271601474361135249386220532175322504609126550708977580966656365649857 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.28742971271601474361135249386220532175322504609126550708977580966656365649857
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.8281710467030457080707039425828157307063969232765907268477212903337790999371
Short name T770
Test name
Test status
Simulation time 7309292483 ps
CPU time 284.49 seconds
Started Nov 22 12:35:26 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 272352 kb
Host smart-f90c219e-12be-4a8f-8460-ab7ac67755fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8281710467030457080707039425828157307063969232765907268477212903337790999371 -assert nopostproc +UVM_TESTNAME=al
ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.8281710467030457080707039425828157307063969232765907268477212903337790999371
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.27223037098324093560646396391273595781659961543074129830172626461684371598251
Short name T719
Test name
Test status
Simulation time 22019264088 ps
CPU time 849.94 seconds
Started Nov 22 12:34:19 PM PST 23
Finished Nov 22 12:48:37 PM PST 23
Peak memory 273352 kb
Host smart-e7db6b26-246c-4a17-8e57-f0e024dd1a8f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223037098324093560646396391273595781659961543074129830172626461684371
598251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2722303709832409356064
6396391273595781659961543074129830172626461684371598251
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.59705350791107795224374587871747084024703595437016571675326626808862721911870
Short name T701
Test name
Test status
Simulation time 407776267 ps
CPU time 16.23 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:34:46 PM PST 23
Peak memory 248552 kb
Host smart-f2604d25-c6f7-480a-97b5-efd18f94de37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=59705350791107795224374587871747084024703595437016571675326626808862721911870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.alert_handler_tl_errors.59705350791107795224374587871747084024703595437016571675326626808862721911870
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.22260294389062603691157310896654248662534968877521502167932744580358208422241
Short name T801
Test name
Test status
Simulation time 1596552471 ps
CPU time 63.06 seconds
Started Nov 22 12:34:13 PM PST 23
Finished Nov 22 12:35:20 PM PST 23
Peak memory 240376 kb
Host smart-1a88abe6-dfe5-48dd-b297-59545610e21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=22260294389062603691157310896654248662534968877521502167932744580358208422241 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.22260294389062603691157310896654248662534968877521502167932744580358208422241
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.115189784679450871285117824060931496849219376345070456988584408486069372277763
Short name T727
Test name
Test status
Simulation time 110671501 ps
CPU time 6.83 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 253924 kb
Host smart-8d3414a8-486b-49d2-8627-d1e828487a1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11518978467945087128511782406093149684921937634507045698858440848606937227
7763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem_rw_with_rand_reset.115189784679450871285117824
060931496849219376345070456988584408486069372277763
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.24005098347717134689008055887046069104817385610983677855199273867346667302728
Short name T15
Test name
Test status
Simulation time 162171089 ps
CPU time 7.54 seconds
Started Nov 22 12:34:09 PM PST 23
Finished Nov 22 12:34:23 PM PST 23
Peak memory 240292 kb
Host smart-2731afc3-a533-4440-b692-ebfde0f984b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=24005098347717134689008055887046069104817385610983677855199273867346667302728 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.alert_handler_csr_rw.24005098347717134689008055887046069104817385610983677855199273867346667302728
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.111863101847742008604941440599344843367121973086468311318935165769159286798288
Short name T696
Test name
Test status
Simulation time 10547302 ps
CPU time 1.42 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:34:29 PM PST 23
Peak memory 235656 kb
Host smart-1a888689-487a-47ec-ae21-d7d3c7014591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=111863101847742008604941440599344843367121973086468311318935165769159286798288 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.alert_handler_intr_test.111863101847742008604941440599344843367121973086468311318935165769159286798288
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.7740913951504028707959640848279817694679617200613887376863666395270830618650
Short name T89
Test name
Test status
Simulation time 867915443 ps
CPU time 33.55 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:35:09 PM PST 23
Peak memory 248592 kb
Host smart-d7bcf6e4-b378-4b93-b801-03ffb1f28582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=7740913951504028707959640848279817694679617200613887376863666395270830618650 -assert nopostproc +UVM_TESTNAME
=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.7740913951504028707959640848279817694679617200613887376863666395270830618650
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.13802980583713827900261353845824187010629126992619464371733590998380258103903
Short name T762
Test name
Test status
Simulation time 7309292483 ps
CPU time 298.46 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:39:28 PM PST 23
Peak memory 272344 kb
Host smart-9517119a-6b37-4779-b0db-722329f2d8ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13802980583713827900261353845824187010629126992619464371733590998380258103903 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.13802980583713827900261353845824187010629126992619464371733590998380258103903
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2731879962177165692998672317276902471157402732056668146588735864777241160506
Short name T836
Test name
Test status
Simulation time 22019264088 ps
CPU time 907.96 seconds
Started Nov 22 12:34:10 PM PST 23
Finished Nov 22 12:49:24 PM PST 23
Peak memory 273424 kb
Host smart-8a860c69-bad9-431c-9e96-35663d7dcae0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318799621771656929986723172769024711574027320566681465887358647772411
60506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.27318799621771656929986
72317276902471157402732056668146588735864777241160506
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.88369765424619183740948421474964332559402945756782479885945921087052403224427
Short name T813
Test name
Test status
Simulation time 407776267 ps
CPU time 15.2 seconds
Started Nov 22 12:34:14 PM PST 23
Finished Nov 22 12:34:36 PM PST 23
Peak memory 248548 kb
Host smart-d8ee75c4-2650-4e22-986e-7780dc3f51cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=88369765424619183740948421474964332559402945756782479885945921087052403224427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.alert_handler_tl_errors.88369765424619183740948421474964332559402945756782479885945921087052403224427
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.92957304637069768865246630080099677923896704777057179232325437899745085264229
Short name T96
Test name
Test status
Simulation time 1596552471 ps
CPU time 61.47 seconds
Started Nov 22 12:34:12 PM PST 23
Finished Nov 22 12:35:18 PM PST 23
Peak memory 240400 kb
Host smart-fb88a6b7-db36-4914-a967-ba8dabcb7574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=92957304637069768865246630080099677923896704777057179232325437899745085264229 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.92957304637069768865246630080099677923896704777057179232325437899745085264229
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.48405188856691594897251544805871844767815888782344099532101246980135977823521
Short name T765
Test name
Test status
Simulation time 110671501 ps
CPU time 7.27 seconds
Started Nov 22 12:34:30 PM PST 23
Finished Nov 22 12:34:40 PM PST 23
Peak memory 253912 kb
Host smart-15920242-aa03-4be8-bcb4-bd29a93d1abf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48405188856691594897251544805871844767815888782344099532101246980135977823
521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem_rw_with_rand_reset.4840518885669159489725154480
5871844767815888782344099532101246980135977823521
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.32837211617757947662843591475052915820790670752182106031517202562265622532758
Short name T845
Test name
Test status
Simulation time 162171089 ps
CPU time 8.06 seconds
Started Nov 22 12:34:21 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 240340 kb
Host smart-b1e62bfc-3dba-4ab1-b8c2-9b49dbf440a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=32837211617757947662843591475052915820790670752182106031517202562265622532758 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.alert_handler_csr_rw.32837211617757947662843591475052915820790670752182106031517202562265622532758
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.96581228300567226993500906760050442629995763160157034293255331085734460351779
Short name T717
Test name
Test status
Simulation time 10547302 ps
CPU time 1.4 seconds
Started Nov 22 12:34:20 PM PST 23
Finished Nov 22 12:34:29 PM PST 23
Peak memory 235644 kb
Host smart-9c64bc5a-0cef-42fb-ba34-81faf5548f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=96581228300567226993500906760050442629995763160157034293255331085734460351779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.alert_handler_intr_test.96581228300567226993500906760050442629995763160157034293255331085734460351779
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.112954742786128958629029311529093086531292876802358553956024916831309756125463
Short name T102
Test name
Test status
Simulation time 867915443 ps
CPU time 33.85 seconds
Started Nov 22 12:34:25 PM PST 23
Finished Nov 22 12:35:03 PM PST 23
Peak memory 248596 kb
Host smart-ac7d3a2d-c1e1-4ff4-9189-f41cb78ebd95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=112954742786128958629029311529093086531292876802358553956024916831309756125463 -assert nopostproc +UVM_TESTNA
ME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.112954742786128958629029311529093086531292876802358553956024916831309756125463
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.24910802699644628205139805740628334415800597484310293449790849291611933572034
Short name T741
Test name
Test status
Simulation time 7309292483 ps
CPU time 299.13 seconds
Started Nov 22 12:35:28 PM PST 23
Finished Nov 22 12:40:30 PM PST 23
Peak memory 272380 kb
Host smart-342c9c6a-ee3f-43d1-b7f4-7a31e0a6fea3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24910802699644628205139805740628334415800597484310293449790849291611933572034 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.24910802699644628205139805740628334415800597484310293449790849291611933572034
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.55710931570197927872574515265447196757013507996311851879192508703312705021599
Short name T830
Test name
Test status
Simulation time 22019264088 ps
CPU time 918.73 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:49:48 PM PST 23
Peak memory 273424 kb
Host smart-56fd22c9-9e6d-4368-90b0-52b32b3a2ee5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55710931570197927872574515265447196757013507996311851879192508703312705
021599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.5571093157019792787257
4515265447196757013507996311851879192508703312705021599
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.63519762069703556554633932924817081891726590980281411164908329793968644775939
Short name T751
Test name
Test status
Simulation time 407776267 ps
CPU time 14.5 seconds
Started Nov 22 12:34:13 PM PST 23
Finished Nov 22 12:34:32 PM PST 23
Peak memory 248544 kb
Host smart-f7f3bfda-b0d9-4bc6-adfd-b45a9bb57d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=63519762069703556554633932924817081891726590980281411164908329793968644775939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.alert_handler_tl_errors.63519762069703556554633932924817081891726590980281411164908329793968644775939
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.86992619231301533618149038826680622793861565891942777277264323025322035161585
Short name T818
Test name
Test status
Simulation time 1596552471 ps
CPU time 63.68 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:35:32 PM PST 23
Peak memory 240360 kb
Host smart-9c4bd9be-dc70-4b2b-84ca-9488b3d29c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=86992619231301533618149038826680622793861565891942777277264323025322035161585 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.86992619231301533618149038826680622793861565891942777277264323025322035161585
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.5978293067499271467010706173591047838129515418863764994771520278839045194983
Short name T4
Test name
Test status
Simulation time 110671501 ps
CPU time 7.3 seconds
Started Nov 22 12:34:28 PM PST 23
Finished Nov 22 12:34:39 PM PST 23
Peak memory 253884 kb
Host smart-16301cd2-e4c6-40e7-86e2-7533afaa2b95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59782930674992714670107061735910478381295154188637649947715202788390451949
83 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem_rw_with_rand_reset.59782930674992714670107061735
91047838129515418863764994771520278839045194983
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.97252998599862036051066426251067784513280819705554878541500940476608811635379
Short name T843
Test name
Test status
Simulation time 162171089 ps
CPU time 7.28 seconds
Started Nov 22 12:34:27 PM PST 23
Finished Nov 22 12:34:43 PM PST 23
Peak memory 240344 kb
Host smart-011297d7-7fa5-44cd-8368-73b19747eb79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=97252998599862036051066426251067784513280819705554878541500940476608811635379 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.alert_handler_csr_rw.97252998599862036051066426251067784513280819705554878541500940476608811635379
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.61234853470240013832481641358842226087605333471011912694747715258730398933419
Short name T718
Test name
Test status
Simulation time 10547302 ps
CPU time 1.56 seconds
Started Nov 22 12:34:28 PM PST 23
Finished Nov 22 12:34:32 PM PST 23
Peak memory 235660 kb
Host smart-cf4f222e-28e2-4360-8f3a-42a9ca0ce9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=61234853470240013832481641358842226087605333471011912694747715258730398933419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.alert_handler_intr_test.61234853470240013832481641358842226087605333471011912694747715258730398933419
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.80831581753329138595435293933357667548722793828506200953189582339956565395137
Short name T724
Test name
Test status
Simulation time 867915443 ps
CPU time 33.29 seconds
Started Nov 22 12:34:23 PM PST 23
Finished Nov 22 12:35:02 PM PST 23
Peak memory 248544 kb
Host smart-26c3c0d5-c1a8-492c-a0f0-7721092a77ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=80831581753329138595435293933357667548722793828506200953189582339956565395137 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.80831581753329138595435293933357667548722793828506200953189582339956565395137
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.103923289902070718283242748550805149988031176219483780515687242820607144202565
Short name T816
Test name
Test status
Simulation time 7309292483 ps
CPU time 301.84 seconds
Started Nov 22 12:34:25 PM PST 23
Finished Nov 22 12:39:31 PM PST 23
Peak memory 272468 kb
Host smart-c4ac4a6b-9cee-4a5c-85ab-4ca5e81a13c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103923289902070718283242748550805149988031176219483780515687242820607144202565 -assert nopostproc +UVM_TESTNAME=
alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.103923289902070718283242748550805149988031176219483780515687242820607144202565
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.101693707883713132860385823191260245795567632153153600604474706164659981642605
Short name T736
Test name
Test status
Simulation time 22019264088 ps
CPU time 912.12 seconds
Started Nov 22 12:34:25 PM PST 23
Finished Nov 22 12:49:41 PM PST 23
Peak memory 273456 kb
Host smart-e4a3e38d-4438-4250-b770-34fddaa8e08f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10169370788371313286038582319126024579556763215315360060447470616465998
1642605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.101693707883713132860
385823191260245795567632153153600604474706164659981642605
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.112914322410390436212036827134678778959513280186151319715369244611671642768345
Short name T91
Test name
Test status
Simulation time 407776267 ps
CPU time 16.95 seconds
Started Nov 22 12:34:29 PM PST 23
Finished Nov 22 12:34:49 PM PST 23
Peak memory 248636 kb
Host smart-bf85e572-1556-46d4-9dc1-ec15d091ff86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=112914322410390436212036827134678778959513280186151319715369244611671642768345 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.alert_handler_tl_errors.112914322410390436212036827134678778959513280186151319715369244611671642768345
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.46226794556345951721019915715668435541640015827775163193504803757085766243965
Short name T848
Test name
Test status
Simulation time 1596552471 ps
CPU time 64.21 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:35:33 PM PST 23
Peak memory 240376 kb
Host smart-239a9b0c-7fe8-4038-b180-0824d1b9a181
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=46226794556345951721019915715668435541640015827775163193504803757085766243965 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.46226794556345951721019915715668435541640015827775163193504803757085766243965
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.101014461534439034077196300368834109452673658651315900156633071108135465137485
Short name T5
Test name
Test status
Simulation time 110671501 ps
CPU time 7.11 seconds
Started Nov 22 12:34:27 PM PST 23
Finished Nov 22 12:34:37 PM PST 23
Peak memory 253948 kb
Host smart-e710a5f3-bf5a-46ff-8704-39db0e44f4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10101446153443903407719630036883410945267365865131590015663307110813546513
7485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_rw_with_rand_reset.101014461534439034077196300
368834109452673658651315900156633071108135465137485
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.23617695612301785416399194442340386705977147836594513987798973957622255698800
Short name T766
Test name
Test status
Simulation time 162171089 ps
CPU time 8.05 seconds
Started Nov 22 12:34:34 PM PST 23
Finished Nov 22 12:34:48 PM PST 23
Peak memory 240352 kb
Host smart-d2ba645f-2a34-48dd-b409-73ca6654be20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=23617695612301785416399194442340386705977147836594513987798973957622255698800 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.alert_handler_csr_rw.23617695612301785416399194442340386705977147836594513987798973957622255698800
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.7049473799589771180637958042951022457572153474834561413496271198794946374797
Short name T778
Test name
Test status
Simulation time 10547302 ps
CPU time 1.4 seconds
Started Nov 22 12:34:20 PM PST 23
Finished Nov 22 12:34:29 PM PST 23
Peak memory 235688 kb
Host smart-3ca4ed2c-c5fc-433c-9023-9e4bad0d9732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=7049473799589771180637958042951022457572153474834561413496271198794946374797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.alert_handler_intr_test.7049473799589771180637958042951022457572153474834561413496271198794946374797
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.36285652182749420345932175820102491974224206180144896820072559428261119109094
Short name T742
Test name
Test status
Simulation time 867915443 ps
CPU time 36.86 seconds
Started Nov 22 12:34:24 PM PST 23
Finished Nov 22 12:35:06 PM PST 23
Peak memory 248624 kb
Host smart-04a3d758-ea41-4cd8-a84f-7a2a6cddbe43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=36285652182749420345932175820102491974224206180144896820072559428261119109094 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.36285652182749420345932175820102491974224206180144896820072559428261119109094
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.104182599643329131948735989945640480581959073786744781208080353740359992365626
Short name T815
Test name
Test status
Simulation time 7309292483 ps
CPU time 300.96 seconds
Started Nov 22 12:34:23 PM PST 23
Finished Nov 22 12:39:29 PM PST 23
Peak memory 272484 kb
Host smart-2c46a2e0-98a7-4649-99d0-a1355d90b67f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104182599643329131948735989945640480581959073786744781208080353740359992365626 -assert nopostproc +UVM_TESTNAME=
alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.104182599643329131948735989945640480581959073786744781208080353740359992365626
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.91169150128178371624029617946693275800156908117589301357343320343055783792013
Short name T97
Test name
Test status
Simulation time 407776267 ps
CPU time 15.62 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:34:45 PM PST 23
Peak memory 248552 kb
Host smart-cfc5d992-ad7c-4338-84e2-c10cd3ddf511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=91169150128178371624029617946693275800156908117589301357343320343055783792013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.alert_handler_tl_errors.91169150128178371624029617946693275800156908117589301357343320343055783792013
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.59233182324841666654895094370403998274104269711577491643270945808157601098124
Short name T831
Test name
Test status
Simulation time 1596552471 ps
CPU time 63.56 seconds
Started Nov 22 12:34:23 PM PST 23
Finished Nov 22 12:35:32 PM PST 23
Peak memory 240340 kb
Host smart-8bcfbd1a-bac8-4a8a-9c7b-6098872db4fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=59233182324841666654895094370403998274104269711577491643270945808157601098124 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.59233182324841666654895094370403998274104269711577491643270945808157601098124
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.72276850152976168850434781207325577250298268440289630725407709830262331738692
Short name T841
Test name
Test status
Simulation time 110671501 ps
CPU time 7.29 seconds
Started Nov 22 12:34:37 PM PST 23
Finished Nov 22 12:34:51 PM PST 23
Peak memory 254072 kb
Host smart-5b7a6700-3ee2-4cc5-9d92-48f0551dd6eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72276850152976168850434781207325577250298268440289630725407709830262331738
692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem_rw_with_rand_reset.7227685015297616885043478120
7325577250298268440289630725407709830262331738692
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.43956509018292352424258912948742784823709843455219145136439540463276769326531
Short name T802
Test name
Test status
Simulation time 162171089 ps
CPU time 7.35 seconds
Started Nov 22 12:34:31 PM PST 23
Finished Nov 22 12:34:43 PM PST 23
Peak memory 240280 kb
Host smart-1f2a8f77-a2bf-4f18-8e62-d83fe2f5e5d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=43956509018292352424258912948742784823709843455219145136439540463276769326531 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.alert_handler_csr_rw.43956509018292352424258912948742784823709843455219145136439540463276769326531
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.54541714192450481376954708295377294666392039946235502155818362565121595370846
Short name T730
Test name
Test status
Simulation time 10547302 ps
CPU time 1.46 seconds
Started Nov 22 12:34:34 PM PST 23
Finished Nov 22 12:34:42 PM PST 23
Peak memory 235708 kb
Host smart-e65284d5-0b4d-49e6-83f7-67a469e96170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=54541714192450481376954708295377294666392039946235502155818362565121595370846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.alert_handler_intr_test.54541714192450481376954708295377294666392039946235502155818362565121595370846
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.15500253113349892247574440624364890055513303376598951991347535670778726890265
Short name T99
Test name
Test status
Simulation time 867915443 ps
CPU time 34.5 seconds
Started Nov 22 12:34:29 PM PST 23
Finished Nov 22 12:35:07 PM PST 23
Peak memory 248552 kb
Host smart-378ed4a5-48d3-4b43-b79f-e40aeeedf12c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=15500253113349892247574440624364890055513303376598951991347535670778726890265 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.15500253113349892247574440624364890055513303376598951991347535670778726890265
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.62406741053598436145807676124732537105960913103722436693305194648557812672105
Short name T110
Test name
Test status
Simulation time 7309292483 ps
CPU time 297.09 seconds
Started Nov 22 12:34:28 PM PST 23
Finished Nov 22 12:39:28 PM PST 23
Peak memory 272384 kb
Host smart-e6873a43-6a96-433b-8bf4-6a30b9878255
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62406741053598436145807676124732537105960913103722436693305194648557812672105 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.62406741053598436145807676124732537105960913103722436693305194648557812672105
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.26218816544976460559548882066380007740083506962843754185842060000512916347304
Short name T111
Test name
Test status
Simulation time 22019264088 ps
CPU time 920.22 seconds
Started Nov 22 12:34:20 PM PST 23
Finished Nov 22 12:49:48 PM PST 23
Peak memory 273436 kb
Host smart-d3cd3aa9-cd34-41a4-ab43-7a9dc255c6bc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26218816544976460559548882066380007740083506962843754185842060000512916
347304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2621881654497646055954
8882066380007740083506962843754185842060000512916347304
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.77945549884756590866538112611180459022936310639116621055243484581096729069820
Short name T707
Test name
Test status
Simulation time 407776267 ps
CPU time 15.64 seconds
Started Nov 22 12:34:27 PM PST 23
Finished Nov 22 12:34:46 PM PST 23
Peak memory 248588 kb
Host smart-c399e7da-d55b-438e-9b71-4a0a88cb7f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=77945549884756590866538112611180459022936310639116621055243484581096729069820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.alert_handler_tl_errors.77945549884756590866538112611180459022936310639116621055243484581096729069820
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.79232136569979338449444657786402597244530029670305050419640232084576838620401
Short name T720
Test name
Test status
Simulation time 1596552471 ps
CPU time 65.22 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:35:35 PM PST 23
Peak memory 240380 kb
Host smart-12dcb331-506a-4005-bcac-e65b364a081b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=79232136569979338449444657786402597244530029670305050419640232084576838620401 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.79232136569979338449444657786402597244530029670305050419640232084576838620401
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.20024617705777821327868973479140945397260435867704677002425116522357023510481
Short name T8
Test name
Test status
Simulation time 110671501 ps
CPU time 6.91 seconds
Started Nov 22 12:34:27 PM PST 23
Finished Nov 22 12:34:37 PM PST 23
Peak memory 253960 kb
Host smart-41a4066c-4f85-4b23-bb7e-e2f8a629f905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20024617705777821327868973479140945397260435867704677002425116522357023510
481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem_rw_with_rand_reset.2002461770577782132786897347
9140945397260435867704677002425116522357023510481
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.27357694617764499504025285692870736582992866762528446158725482352311119909628
Short name T803
Test name
Test status
Simulation time 162171089 ps
CPU time 7.8 seconds
Started Nov 22 12:34:46 PM PST 23
Finished Nov 22 12:34:57 PM PST 23
Peak memory 240324 kb
Host smart-bd838c57-e66f-44df-9364-0ab1b5de4c97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=27357694617764499504025285692870736582992866762528446158725482352311119909628 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.alert_handler_csr_rw.27357694617764499504025285692870736582992866762528446158725482352311119909628
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.83852275630202082741577838808418102273591828397429566648044030379194591516032
Short name T809
Test name
Test status
Simulation time 10547302 ps
CPU time 1.45 seconds
Started Nov 22 12:34:30 PM PST 23
Finished Nov 22 12:34:34 PM PST 23
Peak memory 235648 kb
Host smart-ce471211-a293-44b1-bd37-fa3195f68f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=83852275630202082741577838808418102273591828397429566648044030379194591516032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.alert_handler_intr_test.83852275630202082741577838808418102273591828397429566648044030379194591516032
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.61440332425338072529502343260893955540434642316934442151176085182907564801641
Short name T763
Test name
Test status
Simulation time 867915443 ps
CPU time 33.45 seconds
Started Nov 22 12:34:31 PM PST 23
Finished Nov 22 12:35:07 PM PST 23
Peak memory 248556 kb
Host smart-e6f038cf-d4d5-4c01-9468-d7ecd96c97ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=61440332425338072529502343260893955540434642316934442151176085182907564801641 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.61440332425338072529502343260893955540434642316934442151176085182907564801641
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.69836005954036869851754638357131474850601165462212162339080189353847400046188
Short name T805
Test name
Test status
Simulation time 22019264088 ps
CPU time 871.39 seconds
Started Nov 22 12:34:28 PM PST 23
Finished Nov 22 12:49:03 PM PST 23
Peak memory 273364 kb
Host smart-0600f263-9beb-47c5-97ae-686b4eb7fdaa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69836005954036869851754638357131474850601165462212162339080189353847400
046188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.6983600595403686985175
4638357131474850601165462212162339080189353847400046188
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.18400377161259133065164585857728860425306077074563980957871912107265080527907
Short name T755
Test name
Test status
Simulation time 407776267 ps
CPU time 15.83 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:34:53 PM PST 23
Peak memory 248112 kb
Host smart-646b6c69-68a9-4b95-a876-f1067df3e0e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=18400377161259133065164585857728860425306077074563980957871912107265080527907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.alert_handler_tl_errors.18400377161259133065164585857728860425306077074563980957871912107265080527907
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.896783702978944780921535153714024322169576032201470190847060220394677333062
Short name T94
Test name
Test status
Simulation time 1596552471 ps
CPU time 64.27 seconds
Started Nov 22 12:34:34 PM PST 23
Finished Nov 22 12:35:44 PM PST 23
Peak memory 240432 kb
Host smart-bff89a8a-64a2-4617-a4b4-b4eec9fdac5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=896783702978944780921535153714024322169576032201470190847060220394677333062 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.896783702978944780921535153714024322169576032201470190847060220394677333062
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.6316211890014653858852679308474795875543220119268464927005026445474700266466
Short name T733
Test name
Test status
Simulation time 110671501 ps
CPU time 7.01 seconds
Started Nov 22 12:34:30 PM PST 23
Finished Nov 22 12:34:40 PM PST 23
Peak memory 253900 kb
Host smart-2fad5e89-57df-43cd-84cf-1d969f85632f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63162118900146538588526793084747958755432201192684649270050264454747002664
66 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem_rw_with_rand_reset.63162118900146538588526793084
74795875543220119268464927005026445474700266466
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.108614049790952536409468622711033163283304055712912395623668205277902471456737
Short name T106
Test name
Test status
Simulation time 162171089 ps
CPU time 7.21 seconds
Started Nov 22 12:34:46 PM PST 23
Finished Nov 22 12:34:57 PM PST 23
Peak memory 240344 kb
Host smart-8f8b36a6-61b1-4804-b01a-e555b20803ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=108614049790952536409468622711033163283304055712912395623668205277902471456737 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.alert_handler_csr_rw.108614049790952536409468622711033163283304055712912395623668205277902471456737
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.94990156325955518754210774088891895007671545188720483873660118076512021508501
Short name T13
Test name
Test status
Simulation time 10547302 ps
CPU time 1.44 seconds
Started Nov 22 12:34:24 PM PST 23
Finished Nov 22 12:34:30 PM PST 23
Peak memory 235660 kb
Host smart-1f552657-378b-4b7d-a2dc-3d4f4ed66b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=94990156325955518754210774088891895007671545188720483873660118076512021508501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.alert_handler_intr_test.94990156325955518754210774088891895007671545188720483873660118076512021508501
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.97011701934775008553771035624269193965295329796772916619386803889756270218934
Short name T103
Test name
Test status
Simulation time 867915443 ps
CPU time 34.81 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:35:04 PM PST 23
Peak memory 248068 kb
Host smart-650306f8-0075-47b2-9947-e279dd7349a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=97011701934775008553771035624269193965295329796772916619386803889756270218934 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.97011701934775008553771035624269193965295329796772916619386803889756270218934
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.38646933070294513965888125311583068749399455543059673497156888278947829379679
Short name T109
Test name
Test status
Simulation time 7309292483 ps
CPU time 299.14 seconds
Started Nov 22 12:34:33 PM PST 23
Finished Nov 22 12:39:37 PM PST 23
Peak memory 272336 kb
Host smart-87134c47-b4f9-441e-968d-bd645e1b7e2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38646933070294513965888125311583068749399455543059673497156888278947829379679 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.38646933070294513965888125311583068749399455543059673497156888278947829379679
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.61625653214545758244398415172004835082642502928974260359268834314466725101420
Short name T100
Test name
Test status
Simulation time 22019264088 ps
CPU time 885.01 seconds
Started Nov 22 12:34:36 PM PST 23
Finished Nov 22 12:49:27 PM PST 23
Peak memory 273424 kb
Host smart-a6c07e7f-e199-474b-9147-b3365e0f5ec9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61625653214545758244398415172004835082642502928974260359268834314466725
101420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.6162565321454575824439
8415172004835082642502928974260359268834314466725101420
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4884154850906548411499084082187059912757586468275324672611763755522368967649
Short name T795
Test name
Test status
Simulation time 407776267 ps
CPU time 15.34 seconds
Started Nov 22 12:34:31 PM PST 23
Finished Nov 22 12:34:49 PM PST 23
Peak memory 248552 kb
Host smart-ef70857e-20bd-4320-9d62-ac47bfdf29df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4884154850906548411499084082187059912757586468275324672611763755522368967649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.alert_handler_tl_errors.4884154850906548411499084082187059912757586468275324672611763755522368967649
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.25020436191082927679815430023870037855628549044515064949452053109655620440217
Short name T706
Test name
Test status
Simulation time 1596552471 ps
CPU time 62.5 seconds
Started Nov 22 12:34:30 PM PST 23
Finished Nov 22 12:35:36 PM PST 23
Peak memory 240336 kb
Host smart-c2fd8cda-8f2d-4af2-a720-0cee9a82fb34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=25020436191082927679815430023870037855628549044515064949452053109655620440217 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.25020436191082927679815430023870037855628549044515064949452053109655620440217
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.88992915300886613238457486699103007362592767306650613410897984660660642667637
Short name T9
Test name
Test status
Simulation time 110671501 ps
CPU time 6.91 seconds
Started Nov 22 12:34:26 PM PST 23
Finished Nov 22 12:34:36 PM PST 23
Peak memory 253536 kb
Host smart-2b1e5826-a06c-4b58-8b81-925de82b8e38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88992915300886613238457486699103007362592767306650613410897984660660642667
637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem_rw_with_rand_reset.8899291530088661323845748669
9103007362592767306650613410897984660660642667637
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.99364843188743876079265324604171026211825314864322398162508696648677179097306
Short name T728
Test name
Test status
Simulation time 10547302 ps
CPU time 1.43 seconds
Started Nov 22 12:34:34 PM PST 23
Finished Nov 22 12:34:42 PM PST 23
Peak memory 235708 kb
Host smart-a72c1041-d784-41a1-a9c7-5c5ded7c3462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=99364843188743876079265324604171026211825314864322398162508696648677179097306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.alert_handler_intr_test.99364843188743876079265324604171026211825314864322398162508696648677179097306
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.11804855723303920309236689932986119123318986592495699972930688814655217044205
Short name T804
Test name
Test status
Simulation time 867915443 ps
CPU time 35.42 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:35:12 PM PST 23
Peak memory 248592 kb
Host smart-2542b44e-4978-4e90-b647-ed3d9103239c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=11804855723303920309236689932986119123318986592495699972930688814655217044205 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.11804855723303920309236689932986119123318986592495699972930688814655217044205
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.73345949775859867576366340182556900578558970119643981489537678102230428398375
Short name T814
Test name
Test status
Simulation time 7309292483 ps
CPU time 302.75 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:39:40 PM PST 23
Peak memory 271852 kb
Host smart-1f062aa4-715d-4451-a54a-1f3c350b158a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73345949775859867576366340182556900578558970119643981489537678102230428398375 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.73345949775859867576366340182556900578558970119643981489537678102230428398375
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.19868556767283341220409231144623645350366864140370873581753314018706729279004
Short name T796
Test name
Test status
Simulation time 22019264088 ps
CPU time 954.88 seconds
Started Nov 22 12:34:34 PM PST 23
Finished Nov 22 12:50:36 PM PST 23
Peak memory 273432 kb
Host smart-e4e73e41-a47d-46b0-95bd-42ceeef87cd6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868556767283341220409231144623645350366864140370873581753314018706729
279004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1986855676728334122040
9231144623645350366864140370873581753314018706729279004
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.106429718967595495245895692897108666384199991304058570176741285522015335458050
Short name T752
Test name
Test status
Simulation time 407776267 ps
CPU time 16.23 seconds
Started Nov 22 12:34:30 PM PST 23
Finished Nov 22 12:34:49 PM PST 23
Peak memory 248552 kb
Host smart-c88b1c28-879f-4cfa-b6d5-afcccf5d3d33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=106429718967595495245895692897108666384199991304058570176741285522015335458050 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.alert_handler_tl_errors.106429718967595495245895692897108666384199991304058570176741285522015335458050
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.110450628508340661293539125113198336202288367459263270677942777258299503349449
Short name T826
Test name
Test status
Simulation time 1596552471 ps
CPU time 61.87 seconds
Started Nov 22 12:34:33 PM PST 23
Finished Nov 22 12:35:39 PM PST 23
Peak memory 240380 kb
Host smart-c34f92d1-fca2-4a04-813d-3984e807adc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=110450628508340661293539125113198336202288367459263270677942777258299503349449 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.110450628508340661293539125113198336202288367459263270677942777258299503349449
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.42561105981114237264199436124906568007815563285553142962195243455257095414615
Short name T3
Test name
Test status
Simulation time 110671501 ps
CPU time 7.17 seconds
Started Nov 22 12:34:51 PM PST 23
Finished Nov 22 12:35:00 PM PST 23
Peak memory 253996 kb
Host smart-8ff81ac5-9581-4cd2-a254-855c6e763fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42561105981114237264199436124906568007815563285553142962195243455257095414
615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem_rw_with_rand_reset.4256110598111423726419943612
4906568007815563285553142962195243455257095414615
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.46744445365259940928825417671498930864338181642454865153011403090067804093273
Short name T11
Test name
Test status
Simulation time 162171089 ps
CPU time 7.25 seconds
Started Nov 22 12:34:48 PM PST 23
Finished Nov 22 12:34:58 PM PST 23
Peak memory 240288 kb
Host smart-c55720ec-fdec-4712-a548-970ee6e505c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=46744445365259940928825417671498930864338181642454865153011403090067804093273 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.alert_handler_csr_rw.46744445365259940928825417671498930864338181642454865153011403090067804093273
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.18902481176663852134327166799323598689273294897592522683992168375762962407628
Short name T130
Test name
Test status
Simulation time 10547302 ps
CPU time 1.39 seconds
Started Nov 22 12:34:33 PM PST 23
Finished Nov 22 12:34:39 PM PST 23
Peak memory 235652 kb
Host smart-5b18b213-3cb8-4b00-a0e9-5a4a2fabe2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=18902481176663852134327166799323598689273294897592522683992168375762962407628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.alert_handler_intr_test.18902481176663852134327166799323598689273294897592522683992168375762962407628
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.113310919005602707659815704330596918237477397183730698435249064839809216705744
Short name T721
Test name
Test status
Simulation time 867915443 ps
CPU time 32.51 seconds
Started Nov 22 12:34:31 PM PST 23
Finished Nov 22 12:35:09 PM PST 23
Peak memory 248540 kb
Host smart-ccc20598-674e-40ad-9aa1-861fc69c6103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=113310919005602707659815704330596918237477397183730698435249064839809216705744 -assert nopostproc +UVM_TESTNA
ME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.113310919005602707659815704330596918237477397183730698435249064839809216705744
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.75226821034794805812639179436182505147395381395439030760332877019394895470037
Short name T811
Test name
Test status
Simulation time 7309292483 ps
CPU time 292.85 seconds
Started Nov 22 12:34:36 PM PST 23
Finished Nov 22 12:39:35 PM PST 23
Peak memory 272372 kb
Host smart-020cb1a8-f58c-4fcd-b2a4-02c3f2fe5fd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75226821034794805812639179436182505147395381395439030760332877019394895470037 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.75226821034794805812639179436182505147395381395439030760332877019394895470037
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.112309892831514391933357262623359571227041272588194262422659684936313114920926
Short name T744
Test name
Test status
Simulation time 22019264088 ps
CPU time 919.25 seconds
Started Nov 22 12:34:29 PM PST 23
Finished Nov 22 12:49:51 PM PST 23
Peak memory 273412 kb
Host smart-af1bc52b-4b2a-488a-add3-6f390d25695a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11230989283151439193335726262335957122704127258819426242265968493631311
4920926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.112309892831514391933
357262623359571227041272588194262422659684936313114920926
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.57523758290454462721544289066080526012423335105375340502783439468562873351490
Short name T829
Test name
Test status
Simulation time 407776267 ps
CPU time 16.38 seconds
Started Nov 22 12:34:31 PM PST 23
Finished Nov 22 12:34:52 PM PST 23
Peak memory 248584 kb
Host smart-ed58e34a-fada-4553-9160-e0c14a769fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=57523758290454462721544289066080526012423335105375340502783439468562873351490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.alert_handler_tl_errors.57523758290454462721544289066080526012423335105375340502783439468562873351490
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.45649345600395799474068974446690414965191257021598044881470770638497640744750
Short name T776
Test name
Test status
Simulation time 1596552471 ps
CPU time 66.06 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:35:43 PM PST 23
Peak memory 240392 kb
Host smart-40da372e-7ea7-44ef-94a7-fbfea008275e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=45649345600395799474068974446690414965191257021598044881470770638497640744750 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.45649345600395799474068974446690414965191257021598044881470770638497640744750
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.34317374521912115231214827338018668146306587685747746553956688164520990924558
Short name T835
Test name
Test status
Simulation time 5866161171 ps
CPU time 230.53 seconds
Started Nov 22 12:34:15 PM PST 23
Finished Nov 22 12:38:13 PM PST 23
Peak memory 240412 kb
Host smart-4cb1b824-0c66-4183-91df-9af70aed06fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=34317374521912115231214827338018668146306587685747746553956688164520990924558 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.34317374521912115231214827338018668146306587685747746553956688164520990924558
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.76783303992128760430461645093101994350694013226449725705161849483582327438458
Short name T800
Test name
Test status
Simulation time 10186483751 ps
CPU time 339.1 seconds
Started Nov 22 12:34:15 PM PST 23
Finished Nov 22 12:40:01 PM PST 23
Peak memory 240412 kb
Host smart-91f60a69-600f-4eb3-a4d9-26ffa66b6d6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=76783303992128760430461645093101994350694013226449725705161849483582327438458 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.76783303992128760430461645093101994350694013226449725705161849483582327438458
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.129522810382273998318247681961173468537395363453661637143056501737446165335
Short name T769
Test name
Test status
Simulation time 171671013 ps
CPU time 8.69 seconds
Started Nov 22 12:34:18 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 240400 kb
Host smart-44ad08bf-f973-4061-b352-4be9d1590389
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=129522810382273998318247681961173468537395363453661637143056501737446165335 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.129522810382273998318247681961173468537395363453661637143056501737446165335
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.87146068323472486396400396388017022891936777383697639563167192389403734418884
Short name T771
Test name
Test status
Simulation time 110671501 ps
CPU time 7.02 seconds
Started Nov 22 12:34:17 PM PST 23
Finished Nov 22 12:34:32 PM PST 23
Peak memory 253956 kb
Host smart-f55ad684-20c9-4a0a-98ec-d93a817e588a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87146068323472486396400396388017022891936777383697639563167192389403734418
884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_rw_with_rand_reset.87146068323472486396400396388
017022891936777383697639563167192389403734418884
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.32102757268148905282449551059744435718472634353543205118749746527328286917038
Short name T847
Test name
Test status
Simulation time 162171089 ps
CPU time 7.82 seconds
Started Nov 22 12:34:18 PM PST 23
Finished Nov 22 12:34:34 PM PST 23
Peak memory 240308 kb
Host smart-33c9fbf9-8f31-424d-a675-01998847a37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=32102757268148905282449551059744435718472634353543205118749746527328286917038 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.alert_handler_csr_rw.32102757268148905282449551059744435718472634353543205118749746527328286917038
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.38046999260357305182233082534565433892956792528694699327389029138901606869601
Short name T709
Test name
Test status
Simulation time 10547302 ps
CPU time 1.4 seconds
Started Nov 22 12:34:09 PM PST 23
Finished Nov 22 12:34:17 PM PST 23
Peak memory 235692 kb
Host smart-511b2824-1ac3-4181-a289-178057e12dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=38046999260357305182233082534565433892956792528694699327389029138901606869601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.alert_handler_intr_test.38046999260357305182233082534565433892956792528694699327389029138901606869601
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.80846503241143192795635509505625491188725064172814070677256011614796668898254
Short name T783
Test name
Test status
Simulation time 867915443 ps
CPU time 32.31 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:48 PM PST 23
Peak memory 248600 kb
Host smart-bbc0b447-bcdd-49da-8719-a46074884dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=80846503241143192795635509505625491188725064172814070677256011614796668898254 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.80846503241143192795635509505625491188725064172814070677256011614796668898254
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.10880591175463989709850828416696261985352614543254568760753566712986708316344
Short name T764
Test name
Test status
Simulation time 7309292483 ps
CPU time 296.82 seconds
Started Nov 22 12:34:15 PM PST 23
Finished Nov 22 12:39:19 PM PST 23
Peak memory 272268 kb
Host smart-8c583edb-0bd9-4ee6-8b73-5e4c0730abdc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10880591175463989709850828416696261985352614543254568760753566712986708316344 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.10880591175463989709850828416696261985352614543254568760753566712986708316344
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.77029091256750562892479762655296638677372359016933171012882842807856427360176
Short name T700
Test name
Test status
Simulation time 22019264088 ps
CPU time 955.61 seconds
Started Nov 22 12:34:16 PM PST 23
Finished Nov 22 12:50:20 PM PST 23
Peak memory 273436 kb
Host smart-49d1f2c4-4401-4956-b35b-b567fa86bc35
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77029091256750562892479762655296638677372359016933171012882842807856427
360176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.77029091256750562892479
762655296638677372359016933171012882842807856427360176
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.106945499880890511267730189900180303007701964011428798980396575650253845880382
Short name T839
Test name
Test status
Simulation time 407776267 ps
CPU time 15.75 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:32 PM PST 23
Peak memory 248592 kb
Host smart-37ca0f42-cea9-400e-925f-23bd3d0d2155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=106945499880890511267730189900180303007701964011428798980396575650253845880382 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.alert_handler_tl_errors.106945499880890511267730189900180303007701964011428798980396575650253845880382
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.61024348934774077197677333211307907856903411651572892263599937297440881252776
Short name T838
Test name
Test status
Simulation time 1596552471 ps
CPU time 67.94 seconds
Started Nov 22 12:34:15 PM PST 23
Finished Nov 22 12:35:30 PM PST 23
Peak memory 240264 kb
Host smart-febfad35-6157-4d25-9b8d-51b6e332ea83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=61024348934774077197677333211307907856903411651572892263599937297440881252776 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.61024348934774077197677333211307907856903411651572892263599937297440881252776
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.94045602631860706497053570858352059748440340973500745840031954878139372224650
Short name T786
Test name
Test status
Simulation time 10547302 ps
CPU time 1.41 seconds
Started Nov 22 12:34:33 PM PST 23
Finished Nov 22 12:34:39 PM PST 23
Peak memory 235656 kb
Host smart-43694db2-44e4-4269-bdca-0f094d67ea7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=94045602631860706497053570858352059748440340973500745840031954878139372224650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 20.alert_handler_intr_test.94045602631860706497053570858352059748440340973500745840031954878139372224650
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.111346231227756880360003096290811533652483317296972041676277565175433074980085
Short name T126
Test name
Test status
Simulation time 10547302 ps
CPU time 1.43 seconds
Started Nov 22 12:34:29 PM PST 23
Finished Nov 22 12:34:34 PM PST 23
Peak memory 235704 kb
Host smart-69cba6f4-bb20-4786-85d9-8ca00a9a2aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=111346231227756880360003096290811533652483317296972041676277565175433074980085 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 21.alert_handler_intr_test.111346231227756880360003096290811533652483317296972041676277565175433074980085
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.100908562312692595333842116257475712096750007080291465033365524359467458427355
Short name T821
Test name
Test status
Simulation time 10547302 ps
CPU time 1.49 seconds
Started Nov 22 12:34:51 PM PST 23
Finished Nov 22 12:34:55 PM PST 23
Peak memory 235680 kb
Host smart-7fb4df2e-0d11-43de-8f4a-ea79c76a9b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=100908562312692595333842116257475712096750007080291465033365524359467458427355 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 22.alert_handler_intr_test.100908562312692595333842116257475712096750007080291465033365524359467458427355
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.105979419132321864180058683669513039700759076054651681044356652091578744975515
Short name T745
Test name
Test status
Simulation time 10547302 ps
CPU time 1.47 seconds
Started Nov 22 12:34:56 PM PST 23
Finished Nov 22 12:34:59 PM PST 23
Peak memory 235684 kb
Host smart-d355710e-159c-45f9-85bf-4059904a6ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=105979419132321864180058683669513039700759076054651681044356652091578744975515 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 23.alert_handler_intr_test.105979419132321864180058683669513039700759076054651681044356652091578744975515
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.111757252353174134969081802808058835615181612578385632271849099711074066391730
Short name T128
Test name
Test status
Simulation time 10547302 ps
CPU time 1.4 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:34:39 PM PST 23
Peak memory 235652 kb
Host smart-8e896bad-eb95-492a-9a04-b9379ec93afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=111757252353174134969081802808058835615181612578385632271849099711074066391730 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 24.alert_handler_intr_test.111757252353174134969081802808058835615181612578385632271849099711074066391730
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.71039475347584370166428025124885796326601077287028322617810678382833298733609
Short name T798
Test name
Test status
Simulation time 10547302 ps
CPU time 1.37 seconds
Started Nov 22 12:34:52 PM PST 23
Finished Nov 22 12:34:55 PM PST 23
Peak memory 235680 kb
Host smart-7b918960-45bb-4ba8-8894-f3f202b3a1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=71039475347584370166428025124885796326601077287028322617810678382833298733609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 25.alert_handler_intr_test.71039475347584370166428025124885796326601077287028322617810678382833298733609
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.93913837793128932399973386396850977648971020567751196654431647798395606483160
Short name T779
Test name
Test status
Simulation time 10547302 ps
CPU time 1.46 seconds
Started Nov 22 12:34:36 PM PST 23
Finished Nov 22 12:34:43 PM PST 23
Peak memory 235712 kb
Host smart-57b37ebe-5357-4c96-8f84-c7c218d8e803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=93913837793128932399973386396850977648971020567751196654431647798395606483160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 27.alert_handler_intr_test.93913837793128932399973386396850977648971020567751196654431647798395606483160
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.105691797949009736901943806262720826263869381672245615392343881992168827472904
Short name T14
Test name
Test status
Simulation time 10547302 ps
CPU time 1.41 seconds
Started Nov 22 12:34:33 PM PST 23
Finished Nov 22 12:34:40 PM PST 23
Peak memory 235680 kb
Host smart-e648eaea-c8ea-4a74-bd3b-9afedaa3045c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=105691797949009736901943806262720826263869381672245615392343881992168827472904 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 28.alert_handler_intr_test.105691797949009736901943806262720826263869381672245615392343881992168827472904
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.32737953334832718878458187979815679925527323278118291998904194227385719963626
Short name T737
Test name
Test status
Simulation time 10547302 ps
CPU time 1.43 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:34:38 PM PST 23
Peak memory 235656 kb
Host smart-5f910c7f-cd8d-4f17-808e-04efbfeed1b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=32737953334832718878458187979815679925527323278118291998904194227385719963626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 29.alert_handler_intr_test.32737953334832718878458187979815679925527323278118291998904194227385719963626
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.87534525038864671796020798098491626327670828647060032195728300181381913821044
Short name T760
Test name
Test status
Simulation time 5866161171 ps
CPU time 222.36 seconds
Started Nov 22 12:34:21 PM PST 23
Finished Nov 22 12:38:10 PM PST 23
Peak memory 240572 kb
Host smart-18335366-becb-4274-8047-14dddb94385f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=87534525038864671796020798098491626327670828647060032195728300181381913821044 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.87534525038864671796020798098491626327670828647060032195728300181381913821044
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.91400400497985814946682853809173972271155969674862903585827137213566910662993
Short name T704
Test name
Test status
Simulation time 10186483751 ps
CPU time 347.26 seconds
Started Nov 22 12:34:17 PM PST 23
Finished Nov 22 12:40:12 PM PST 23
Peak memory 240572 kb
Host smart-511f3cf6-da0e-4925-a070-a91a9873a459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=91400400497985814946682853809173972271155969674862903585827137213566910662993 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.91400400497985814946682853809173972271155969674862903585827137213566910662993
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.99934646133917491376618309046118199343363741972418919971033430069877109691300
Short name T703
Test name
Test status
Simulation time 171671013 ps
CPU time 8.3 seconds
Started Nov 22 12:34:27 PM PST 23
Finished Nov 22 12:34:38 PM PST 23
Peak memory 240412 kb
Host smart-a65a3074-f015-417f-b957-2eeeee5c33a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=99934646133917491376618309046118199343363741972418919971033430069877109691300 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.99934646133917491376618309046118199343363741972418919971033430069877109691300
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.23932007816321797929699361966814233949091484368927376871281622557591456745669
Short name T1
Test name
Test status
Simulation time 110671501 ps
CPU time 6.92 seconds
Started Nov 22 12:34:23 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 253940 kb
Host smart-1c9848c8-dce1-433a-9964-c541e6e8b12e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23932007816321797929699361966814233949091484368927376871281622557591456745
669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_rw_with_rand_reset.23932007816321797929699361966
814233949091484368927376871281622557591456745669
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.63617427819510464002468017202945228172068288307894917966693954316193178493476
Short name T844
Test name
Test status
Simulation time 162171089 ps
CPU time 7.24 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 240316 kb
Host smart-044eca40-b285-483a-85d5-3a14a105ad77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=63617427819510464002468017202945228172068288307894917966693954316193178493476 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.alert_handler_csr_rw.63617427819510464002468017202945228172068288307894917966693954316193178493476
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.57779311099880404448716618739552515694029075469498090649083714036624198190995
Short name T767
Test name
Test status
Simulation time 10547302 ps
CPU time 1.38 seconds
Started Nov 22 12:34:19 PM PST 23
Finished Nov 22 12:34:29 PM PST 23
Peak memory 235636 kb
Host smart-f7c71c43-fd11-4901-9ef0-5174ad145cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=57779311099880404448716618739552515694029075469498090649083714036624198190995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.alert_handler_intr_test.57779311099880404448716618739552515694029075469498090649083714036624198190995
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.76882797669182066018139629715286442300650335022854037225199284163850066593967
Short name T774
Test name
Test status
Simulation time 867915443 ps
CPU time 34.43 seconds
Started Nov 22 12:34:16 PM PST 23
Finished Nov 22 12:34:59 PM PST 23
Peak memory 248712 kb
Host smart-2f917be9-1b8c-483f-8b7f-2905e70d093d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=76882797669182066018139629715286442300650335022854037225199284163850066593967 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.76882797669182066018139629715286442300650335022854037225199284163850066593967
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.53485186476861819492825190350939513686322846146487387711473414831296881044505
Short name T753
Test name
Test status
Simulation time 7309292483 ps
CPU time 325.91 seconds
Started Nov 22 12:34:16 PM PST 23
Finished Nov 22 12:39:50 PM PST 23
Peak memory 272376 kb
Host smart-4e3306a3-ae16-4d39-a504-abcb5f87f7c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53485186476861819492825190350939513686322846146487387711473414831296881044505 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.53485186476861819492825190350939513686322846146487387711473414831296881044505
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.33785468681726146670648223655336918982311722635564834154715222066150428046980
Short name T787
Test name
Test status
Simulation time 22019264088 ps
CPU time 961.88 seconds
Started Nov 22 12:34:18 PM PST 23
Finished Nov 22 12:50:28 PM PST 23
Peak memory 273408 kb
Host smart-7c1cfdf5-af3c-4be8-a6d0-523b3b0bab7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33785468681726146670648223655336918982311722635564834154715222066150428
046980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.33785468681726146670648
223655336918982311722635564834154715222066150428046980
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.63925308110259539222981885840177231421944096063173582111627761204170291869239
Short name T92
Test name
Test status
Simulation time 407776267 ps
CPU time 15.38 seconds
Started Nov 22 12:34:13 PM PST 23
Finished Nov 22 12:34:33 PM PST 23
Peak memory 248576 kb
Host smart-89546e47-2bf1-431e-8e6d-a085628ef872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=63925308110259539222981885840177231421944096063173582111627761204170291869239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.alert_handler_tl_errors.63925308110259539222981885840177231421944096063173582111627761204170291869239
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.22363992841926511526705667288991272587281922519994028524289271440117079883085
Short name T806
Test name
Test status
Simulation time 1596552471 ps
CPU time 61.85 seconds
Started Nov 22 12:34:21 PM PST 23
Finished Nov 22 12:35:29 PM PST 23
Peak memory 240416 kb
Host smart-90f5a1b2-d786-49de-8c78-8ae5eb49307b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=22363992841926511526705667288991272587281922519994028524289271440117079883085 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.22363992841926511526705667288991272587281922519994028524289271440117079883085
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.24130378542365810251328703173454212935240063099572667988719091610542949965701
Short name T785
Test name
Test status
Simulation time 10547302 ps
CPU time 1.45 seconds
Started Nov 22 12:34:54 PM PST 23
Finished Nov 22 12:34:57 PM PST 23
Peak memory 235700 kb
Host smart-dba17ebd-381f-4716-bdcf-ab970f8dfa61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=24130378542365810251328703173454212935240063099572667988719091610542949965701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 30.alert_handler_intr_test.24130378542365810251328703173454212935240063099572667988719091610542949965701
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.68105726866552578270905466140989747844693619482978768948802510654283815790531
Short name T125
Test name
Test status
Simulation time 10547302 ps
CPU time 1.38 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:34:38 PM PST 23
Peak memory 235720 kb
Host smart-7e851a64-f97c-44c3-9fb1-5d6d656f55d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=68105726866552578270905466140989747844693619482978768948802510654283815790531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 31.alert_handler_intr_test.68105726866552578270905466140989747844693619482978768948802510654283815790531
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.14534530329631905172660186327595594215659250744831270930676498516552859588860
Short name T846
Test name
Test status
Simulation time 10547302 ps
CPU time 1.44 seconds
Started Nov 22 12:34:32 PM PST 23
Finished Nov 22 12:34:38 PM PST 23
Peak memory 235680 kb
Host smart-03d6b28a-9706-4a4a-a904-b14eba73473e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=14534530329631905172660186327595594215659250744831270930676498516552859588860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 32.alert_handler_intr_test.14534530329631905172660186327595594215659250744831270930676498516552859588860
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.20619023242040474249627421868741375148732140721783185807992362709743220370851
Short name T133
Test name
Test status
Simulation time 10547302 ps
CPU time 1.42 seconds
Started Nov 22 12:34:49 PM PST 23
Finished Nov 22 12:34:53 PM PST 23
Peak memory 235644 kb
Host smart-b7c8cb1c-ce05-479c-ab3f-80ab9901fde6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=20619023242040474249627421868741375148732140721783185807992362709743220370851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 33.alert_handler_intr_test.20619023242040474249627421868741375148732140721783185807992362709743220370851
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.111821695074286505076654540064745263408419415080869178159835458637499351527375
Short name T817
Test name
Test status
Simulation time 10547302 ps
CPU time 1.39 seconds
Started Nov 22 12:34:38 PM PST 23
Finished Nov 22 12:34:45 PM PST 23
Peak memory 235628 kb
Host smart-f01de86b-29df-4849-8553-92975437bcab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=111821695074286505076654540064745263408419415080869178159835458637499351527375 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 34.alert_handler_intr_test.111821695074286505076654540064745263408419415080869178159835458637499351527375
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.18339005298116956266918223561856448463984123579156386386446561712042576260959
Short name T775
Test name
Test status
Simulation time 10547302 ps
CPU time 1.47 seconds
Started Nov 22 12:34:55 PM PST 23
Finished Nov 22 12:34:57 PM PST 23
Peak memory 235692 kb
Host smart-05f537ee-7bca-4e9a-9a32-416e3f269f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=18339005298116956266918223561856448463984123579156386386446561712042576260959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 35.alert_handler_intr_test.18339005298116956266918223561856448463984123579156386386446561712042576260959
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.44952579859519537612346286603288576045542588300547573971875360642491295195646
Short name T842
Test name
Test status
Simulation time 10547302 ps
CPU time 1.45 seconds
Started Nov 22 12:34:51 PM PST 23
Finished Nov 22 12:34:54 PM PST 23
Peak memory 235680 kb
Host smart-dff6fe08-4df5-4385-8e80-4b65fdeb994b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=44952579859519537612346286603288576045542588300547573971875360642491295195646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 36.alert_handler_intr_test.44952579859519537612346286603288576045542588300547573971875360642491295195646
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.28945188289215547301692067745931953719922103704690672575708579170209735544807
Short name T784
Test name
Test status
Simulation time 10547302 ps
CPU time 1.45 seconds
Started Nov 22 12:34:31 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 235604 kb
Host smart-8f41c82e-dd76-42e9-8ce7-dbb0b887d01e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=28945188289215547301692067745931953719922103704690672575708579170209735544807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 37.alert_handler_intr_test.28945188289215547301692067745931953719922103704690672575708579170209735544807
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.30459650403662922199805215917480491934534516301512505067261349986214272117605
Short name T734
Test name
Test status
Simulation time 10547302 ps
CPU time 1.5 seconds
Started Nov 22 12:34:56 PM PST 23
Finished Nov 22 12:35:00 PM PST 23
Peak memory 235620 kb
Host smart-4103465a-fb08-41c2-b377-9fb026e96b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=30459650403662922199805215917480491934534516301512505067261349986214272117605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 38.alert_handler_intr_test.30459650403662922199805215917480491934534516301512505067261349986214272117605
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.114340108249850160129051446126089518456729189844780803718040188464178584722138
Short name T788
Test name
Test status
Simulation time 10547302 ps
CPU time 1.46 seconds
Started Nov 22 12:34:46 PM PST 23
Finished Nov 22 12:34:52 PM PST 23
Peak memory 235672 kb
Host smart-28867d68-8aae-43ab-94c3-d2a920d1067c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=114340108249850160129051446126089518456729189844780803718040188464178584722138 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 39.alert_handler_intr_test.114340108249850160129051446126089518456729189844780803718040188464178584722138
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.80205382092044500575707655622114825725441852893918452034731178998685499403694
Short name T697
Test name
Test status
Simulation time 5866161171 ps
CPU time 229.93 seconds
Started Nov 22 12:34:21 PM PST 23
Finished Nov 22 12:38:17 PM PST 23
Peak memory 240496 kb
Host smart-0c948f3b-8960-41e8-9b32-ccf9ba575951
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=80205382092044500575707655622114825725441852893918452034731178998685499403694 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.80205382092044500575707655622114825725441852893918452034731178998685499403694
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.52651293897383382804193254146802809187991453827282449923140243136830961636336
Short name T849
Test name
Test status
Simulation time 10186483751 ps
CPU time 366.22 seconds
Started Nov 22 12:34:03 PM PST 23
Finished Nov 22 12:40:10 PM PST 23
Peak memory 240500 kb
Host smart-0cebed15-ea8e-4112-8f93-9df32d6db442
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=52651293897383382804193254146802809187991453827282449923140243136830961636336 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.52651293897383382804193254146802809187991453827282449923140243136830961636336
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.32291643724081751278148415866720287223353317345634028068340125504727105185973
Short name T726
Test name
Test status
Simulation time 171671013 ps
CPU time 8.44 seconds
Started Nov 22 12:34:09 PM PST 23
Finished Nov 22 12:34:24 PM PST 23
Peak memory 240308 kb
Host smart-5d5ba363-b572-4b06-9c0f-709315b1d8dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=32291643724081751278148415866720287223353317345634028068340125504727105185973 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.32291643724081751278148415866720287223353317345634028068340125504727105185973
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.76069156519238285147284704809245410630479056179362875662194699689471623363929
Short name T780
Test name
Test status
Simulation time 110671501 ps
CPU time 6.76 seconds
Started Nov 22 12:34:11 PM PST 23
Finished Nov 22 12:34:23 PM PST 23
Peak memory 253920 kb
Host smart-acc9cfe8-c2ac-40f9-a408-5773f5587879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76069156519238285147284704809245410630479056179362875662194699689471623363
929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_rw_with_rand_reset.76069156519238285147284704809
245410630479056179362875662194699689471623363929
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.29379094107636741402021057184977163247246372037031827458080889029460969864994
Short name T761
Test name
Test status
Simulation time 162171089 ps
CPU time 7.78 seconds
Started Nov 22 12:33:59 PM PST 23
Finished Nov 22 12:34:07 PM PST 23
Peak memory 240388 kb
Host smart-9d775472-b8ae-4b54-a8a1-4520ba7f8b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=29379094107636741402021057184977163247246372037031827458080889029460969864994 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.alert_handler_csr_rw.29379094107636741402021057184977163247246372037031827458080889029460969864994
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.82442366627086033871780963193642463182886359899579920932084096818113797091846
Short name T794
Test name
Test status
Simulation time 10547302 ps
CPU time 1.37 seconds
Started Nov 22 12:34:06 PM PST 23
Finished Nov 22 12:34:14 PM PST 23
Peak memory 235608 kb
Host smart-560d017a-5d30-4828-aee2-595af5cdabd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=82442366627086033871780963193642463182886359899579920932084096818113797091846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.alert_handler_intr_test.82442366627086033871780963193642463182886359899579920932084096818113797091846
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.49700437601966929442720689831720572464906470899998381647636545848024661871036
Short name T739
Test name
Test status
Simulation time 867915443 ps
CPU time 33.1 seconds
Started Nov 22 12:34:10 PM PST 23
Finished Nov 22 12:34:49 PM PST 23
Peak memory 248620 kb
Host smart-c58f06df-5567-4de0-82e1-8d4e2f840eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=49700437601966929442720689831720572464906470899998381647636545848024661871036 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.49700437601966929442720689831720572464906470899998381647636545848024661871036
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.62934769330374016261658882839665969213322573970595020927732182804575004940180
Short name T746
Test name
Test status
Simulation time 7309292483 ps
CPU time 291.91 seconds
Started Nov 22 12:34:19 PM PST 23
Finished Nov 22 12:39:19 PM PST 23
Peak memory 272312 kb
Host smart-f80569d6-73fc-4364-a872-e09139f16944
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62934769330374016261658882839665969213322573970595020927732182804575004940180 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.62934769330374016261658882839665969213322573970595020927732182804575004940180
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.14393292621337466115044786848458681333106356418774923154391045360535508969759
Short name T833
Test name
Test status
Simulation time 22019264088 ps
CPU time 912.43 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:49:40 PM PST 23
Peak memory 273392 kb
Host smart-59dd4924-78f3-43cf-9618-a475d5a3e000
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14393292621337466115044786848458681333106356418774923154391045360535508
969759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.14393292621337466115044
786848458681333106356418774923154391045360535508969759
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.71079058908197109434468406225112502675792734797177324485976133096701184169556
Short name T731
Test name
Test status
Simulation time 407776267 ps
CPU time 17.22 seconds
Started Nov 22 12:34:01 PM PST 23
Finished Nov 22 12:34:20 PM PST 23
Peak memory 248624 kb
Host smart-b86a37c0-5b89-4078-b1fe-f842ef203fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=71079058908197109434468406225112502675792734797177324485976133096701184169556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.alert_handler_tl_errors.71079058908197109434468406225112502675792734797177324485976133096701184169556
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.68400305696594796871867047134276297993301262790650225721943196568008217391414
Short name T748
Test name
Test status
Simulation time 1596552471 ps
CPU time 62.62 seconds
Started Nov 22 12:34:03 PM PST 23
Finished Nov 22 12:35:07 PM PST 23
Peak memory 240440 kb
Host smart-467eadba-7423-4afd-89a4-4f3b65859fba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=68400305696594796871867047134276297993301262790650225721943196568008217391414 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.68400305696594796871867047134276297993301262790650225721943196568008217391414
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.53631870389837278757468256648339845757470447606815973419930707062285865298253
Short name T124
Test name
Test status
Simulation time 10547302 ps
CPU time 1.42 seconds
Started Nov 22 12:34:30 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 235648 kb
Host smart-89c60cf0-0628-4f19-89b4-ba40f82ea944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=53631870389837278757468256648339845757470447606815973419930707062285865298253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 40.alert_handler_intr_test.53631870389837278757468256648339845757470447606815973419930707062285865298253
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.42144566158646013738835180939018620157369825333337695425454865053481537402195
Short name T98
Test name
Test status
Simulation time 10547302 ps
CPU time 1.52 seconds
Started Nov 22 12:34:42 PM PST 23
Finished Nov 22 12:34:48 PM PST 23
Peak memory 235640 kb
Host smart-2dbe1db6-341e-48e9-a21c-9e9d0d33df1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=42144566158646013738835180939018620157369825333337695425454865053481537402195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 41.alert_handler_intr_test.42144566158646013738835180939018620157369825333337695425454865053481537402195
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.34344133367811657803697142079440646591134096954802530497350192333594709661545
Short name T132
Test name
Test status
Simulation time 10547302 ps
CPU time 1.38 seconds
Started Nov 22 12:34:52 PM PST 23
Finished Nov 22 12:34:55 PM PST 23
Peak memory 235680 kb
Host smart-b0c077d9-6dca-4eae-826b-146904ba815e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34344133367811657803697142079440646591134096954802530497350192333594709661545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 42.alert_handler_intr_test.34344133367811657803697142079440646591134096954802530497350192333594709661545
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.27891395303223242475999929376750916827786249922034599721354015801218875570684
Short name T808
Test name
Test status
Simulation time 10547302 ps
CPU time 1.39 seconds
Started Nov 22 12:34:54 PM PST 23
Finished Nov 22 12:34:57 PM PST 23
Peak memory 235680 kb
Host smart-da889f84-d4eb-4bdf-a9fe-d07ce5562804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=27891395303223242475999929376750916827786249922034599721354015801218875570684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 43.alert_handler_intr_test.27891395303223242475999929376750916827786249922034599721354015801218875570684
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.103906492630423042640672262743234537429664247725936796085671172694542295598821
Short name T832
Test name
Test status
Simulation time 10547302 ps
CPU time 1.52 seconds
Started Nov 22 12:35:00 PM PST 23
Finished Nov 22 12:35:03 PM PST 23
Peak memory 235720 kb
Host smart-03eabad9-b59c-4519-a7de-8009158b687b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=103906492630423042640672262743234537429664247725936796085671172694542295598821 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 44.alert_handler_intr_test.103906492630423042640672262743234537429664247725936796085671172694542295598821
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.79042503275009437271692259197399461663734269262173169449322288343842543775122
Short name T840
Test name
Test status
Simulation time 10547302 ps
CPU time 1.42 seconds
Started Nov 22 12:34:57 PM PST 23
Finished Nov 22 12:35:00 PM PST 23
Peak memory 235684 kb
Host smart-f782bec7-4dd1-4ed2-a721-6b5deb6d4125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=79042503275009437271692259197399461663734269262173169449322288343842543775122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 45.alert_handler_intr_test.79042503275009437271692259197399461663734269262173169449322288343842543775122
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.63577963699062914219437420562087516865070484542553117438790261970776776892917
Short name T768
Test name
Test status
Simulation time 10547302 ps
CPU time 1.39 seconds
Started Nov 22 12:34:39 PM PST 23
Finished Nov 22 12:34:46 PM PST 23
Peak memory 235708 kb
Host smart-5216c866-fcb4-4a1e-925d-65bf9c26dd79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=63577963699062914219437420562087516865070484542553117438790261970776776892917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 46.alert_handler_intr_test.63577963699062914219437420562087516865070484542553117438790261970776776892917
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.73245489292196762385661862549267744536105428102580150621705675831462201335657
Short name T743
Test name
Test status
Simulation time 10547302 ps
CPU time 1.43 seconds
Started Nov 22 12:34:52 PM PST 23
Finished Nov 22 12:34:54 PM PST 23
Peak memory 235636 kb
Host smart-6d2e1a69-b08b-4535-baf5-e3997ccefb1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=73245489292196762385661862549267744536105428102580150621705675831462201335657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 47.alert_handler_intr_test.73245489292196762385661862549267744536105428102580150621705675831462201335657
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.17639788122345171060856414369114279775276470247179862996438814196146532358150
Short name T732
Test name
Test status
Simulation time 10547302 ps
CPU time 1.43 seconds
Started Nov 22 12:34:56 PM PST 23
Finished Nov 22 12:35:00 PM PST 23
Peak memory 235680 kb
Host smart-9a249a92-490b-4da7-bbb6-2f207c23890d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=17639788122345171060856414369114279775276470247179862996438814196146532358150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 48.alert_handler_intr_test.17639788122345171060856414369114279775276470247179862996438814196146532358150
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.71421422811306621578055294002985055602248067148607689193963536791434951767773
Short name T722
Test name
Test status
Simulation time 10547302 ps
CPU time 1.39 seconds
Started Nov 22 12:34:58 PM PST 23
Finished Nov 22 12:35:00 PM PST 23
Peak memory 235680 kb
Host smart-8d3714be-9b53-4311-8e68-dc021110c528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=71421422811306621578055294002985055602248067148607689193963536791434951767773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 49.alert_handler_intr_test.71421422811306621578055294002985055602248067148607689193963536791434951767773
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.33920933931466647757269711301545162941696655920871172907843106891552504239742
Short name T749
Test name
Test status
Simulation time 110671501 ps
CPU time 6.78 seconds
Started Nov 22 12:34:18 PM PST 23
Finished Nov 22 12:34:33 PM PST 23
Peak memory 253996 kb
Host smart-5cbad2af-a908-4c8f-a650-264159ada32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920933931466647757269711301545162941696655920871172907843106891552504239
742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_rw_with_rand_reset.33920933931466647757269711301
545162941696655920871172907843106891552504239742
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.7573747690303783223372706210742788477140696730623789987774131606314601848998
Short name T789
Test name
Test status
Simulation time 162171089 ps
CPU time 7.29 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:23 PM PST 23
Peak memory 240344 kb
Host smart-8e8813c2-5c54-439e-9023-99c8c5faac30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=7573747690303783223372706210742788477140696730623789987774131606314601848998 -assert nopostproc +UVM_TESTNAME=alert_handler_bas
e_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.alert_handler_csr_rw.7573747690303783223372706210742788477140696730623789987774131606314601848998
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.40381405206558091243031066488113986267736848159814185322604899445646719338482
Short name T127
Test name
Test status
Simulation time 10547302 ps
CPU time 1.41 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:17 PM PST 23
Peak memory 235668 kb
Host smart-2941632f-83b1-41c7-801b-05b4a91880ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=40381405206558091243031066488113986267736848159814185322604899445646719338482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.alert_handler_intr_test.40381405206558091243031066488113986267736848159814185322604899445646719338482
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.26080786118712160452813045421087048632191317982861336031088406225491035796836
Short name T713
Test name
Test status
Simulation time 867915443 ps
CPU time 33.07 seconds
Started Nov 22 12:34:07 PM PST 23
Finished Nov 22 12:34:46 PM PST 23
Peak memory 248612 kb
Host smart-e8fb2c77-d559-4a1c-9adb-c00ece17dbf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=26080786118712160452813045421087048632191317982861336031088406225491035796836 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.26080786118712160452813045421087048632191317982861336031088406225491035796836
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.110165306402714547523363869043230396226257439536884242470038905314866852872577
Short name T777
Test name
Test status
Simulation time 7309292483 ps
CPU time 294.01 seconds
Started Nov 22 12:34:03 PM PST 23
Finished Nov 22 12:38:58 PM PST 23
Peak memory 272436 kb
Host smart-9644b37a-f50d-4a80-a464-45c8fd899e14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110165306402714547523363869043230396226257439536884242470038905314866852872577 -assert nopostproc +UVM_TESTNAME=
alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.110165306402714547523363869043230396226257439536884242470038905314866852872577
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.43342877928938139465576319737820911086375546471412351166758535205908394668084
Short name T735
Test name
Test status
Simulation time 22019264088 ps
CPU time 922.02 seconds
Started Nov 22 12:33:59 PM PST 23
Finished Nov 22 12:49:22 PM PST 23
Peak memory 273404 kb
Host smart-05f066ee-327a-43b0-9b49-b9c425bc8915
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43342877928938139465576319737820911086375546471412351166758535205908394
668084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.43342877928938139465576
319737820911086375546471412351166758535205908394668084
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.36459457914801687893935918109225020139603080733981994496240289049525165119732
Short name T702
Test name
Test status
Simulation time 407776267 ps
CPU time 15.74 seconds
Started Nov 22 12:34:08 PM PST 23
Finished Nov 22 12:34:31 PM PST 23
Peak memory 248492 kb
Host smart-c81cdd2b-5d7a-4741-940f-4bef9045bcc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=36459457914801687893935918109225020139603080733981994496240289049525165119732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.alert_handler_tl_errors.36459457914801687893935918109225020139603080733981994496240289049525165119732
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.100312404638912491252921134225020712409073219258891994682969151396166544763319
Short name T792
Test name
Test status
Simulation time 1596552471 ps
CPU time 57.83 seconds
Started Nov 22 12:34:07 PM PST 23
Finished Nov 22 12:35:10 PM PST 23
Peak memory 240412 kb
Host smart-d2446f83-4eb5-4627-b2c5-733e8bd8cc92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=100312404638912491252921134225020712409073219258891994682969151396166544763319 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.100312404638912491252921134225020712409073219258891994682969151396166544763319
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.89966258876356677104681821531688498615947242569239131249137121908437191288679
Short name T708
Test name
Test status
Simulation time 110671501 ps
CPU time 6.99 seconds
Started Nov 22 12:34:11 PM PST 23
Finished Nov 22 12:34:23 PM PST 23
Peak memory 253920 kb
Host smart-a65d5442-7cf7-4dd9-b9e0-ef845015fe98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89966258876356677104681821531688498615947242569239131249137121908437191288
679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_rw_with_rand_reset.89966258876356677104681821531
688498615947242569239131249137121908437191288679
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.10364649538308891694817897657653267996467470845285575642921196889662982747889
Short name T723
Test name
Test status
Simulation time 162171089 ps
CPU time 8.23 seconds
Started Nov 22 12:34:15 PM PST 23
Finished Nov 22 12:34:31 PM PST 23
Peak memory 240344 kb
Host smart-8dfaef4b-e2a8-413d-97f0-ddc0c3ffb8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=10364649538308891694817897657653267996467470845285575642921196889662982747889 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.alert_handler_csr_rw.10364649538308891694817897657653267996467470845285575642921196889662982747889
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.89359320463849269601341874604993150987283197323420067358078592010953736983087
Short name T825
Test name
Test status
Simulation time 10547302 ps
CPU time 1.41 seconds
Started Nov 22 12:34:16 PM PST 23
Finished Nov 22 12:34:25 PM PST 23
Peak memory 235664 kb
Host smart-60db4e6a-69d6-406e-8c5e-e9d68fd4ce43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=89359320463849269601341874604993150987283197323420067358078592010953736983087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.alert_handler_intr_test.89359320463849269601341874604993150987283197323420067358078592010953736983087
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.37810585706755097342440109370286930297385533401825018279473375547413684004223
Short name T101
Test name
Test status
Simulation time 867915443 ps
CPU time 34.97 seconds
Started Nov 22 12:34:17 PM PST 23
Finished Nov 22 12:35:00 PM PST 23
Peak memory 248576 kb
Host smart-b9960b64-ae01-4721-ab40-47ce07b68ae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=37810585706755097342440109370286930297385533401825018279473375547413684004223 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.37810585706755097342440109370286930297385533401825018279473375547413684004223
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.40053613484552368803140394070809264980828255184835270470474224740284699498437
Short name T791
Test name
Test status
Simulation time 7309292483 ps
CPU time 307.8 seconds
Started Nov 22 12:34:11 PM PST 23
Finished Nov 22 12:39:25 PM PST 23
Peak memory 272228 kb
Host smart-232a2bbe-db03-4dd4-93e2-1aa63f45b099
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40053613484552368803140394070809264980828255184835270470474224740284699498437 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.40053613484552368803140394070809264980828255184835270470474224740284699498437
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.38650742711326373095796816339982726650524412361177889401590583267875318236374
Short name T738
Test name
Test status
Simulation time 22019264088 ps
CPU time 887.85 seconds
Started Nov 22 12:34:09 PM PST 23
Finished Nov 22 12:49:04 PM PST 23
Peak memory 273404 kb
Host smart-671669d5-aed0-4165-99ab-7aeb4c4854e7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650742711326373095796816339982726650524412361177889401590583267875318
236374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.38650742711326373095796
816339982726650524412361177889401590583267875318236374
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.17450499403792531487951799362539103370103197106877126960756382874259985338910
Short name T93
Test name
Test status
Simulation time 407776267 ps
CPU time 15.25 seconds
Started Nov 22 12:34:20 PM PST 23
Finished Nov 22 12:34:42 PM PST 23
Peak memory 248636 kb
Host smart-d86de786-b2c2-4ad3-aa17-84246c27bc02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=17450499403792531487951799362539103370103197106877126960756382874259985338910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.alert_handler_tl_errors.17450499403792531487951799362539103370103197106877126960756382874259985338910
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.99372578896978855293139672626429979201193486552286024857590579297896038685266
Short name T10
Test name
Test status
Simulation time 110671501 ps
CPU time 7.43 seconds
Started Nov 22 12:34:17 PM PST 23
Finished Nov 22 12:34:33 PM PST 23
Peak memory 253940 kb
Host smart-d68819b2-a9c6-469c-80d9-fa302913c8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99372578896978855293139672626429979201193486552286024857590579297896038685
266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_rw_with_rand_reset.99372578896978855293139672626
429979201193486552286024857590579297896038685266
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.16369914116731463554528393276834407847603553333696283795919561051319340544960
Short name T129
Test name
Test status
Simulation time 162171089 ps
CPU time 8 seconds
Started Nov 22 12:34:16 PM PST 23
Finished Nov 22 12:34:32 PM PST 23
Peak memory 240328 kb
Host smart-9d09a3c9-9934-478d-8d02-f58cb132e8c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=16369914116731463554528393276834407847603553333696283795919561051319340544960 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.alert_handler_csr_rw.16369914116731463554528393276834407847603553333696283795919561051319340544960
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.104021818216208732136776107460490871942789301472542387642847895758709390478445
Short name T823
Test name
Test status
Simulation time 10547302 ps
CPU time 1.41 seconds
Started Nov 22 12:34:21 PM PST 23
Finished Nov 22 12:34:29 PM PST 23
Peak memory 235676 kb
Host smart-44e99fc9-970d-4223-9ff1-eab7953003f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=104021818216208732136776107460490871942789301472542387642847895758709390478445 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.alert_handler_intr_test.104021818216208732136776107460490871942789301472542387642847895758709390478445
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.19908187678601022387103556698274166401051626679683799246868196260728910426114
Short name T740
Test name
Test status
Simulation time 867915443 ps
CPU time 31.99 seconds
Started Nov 22 12:34:21 PM PST 23
Finished Nov 22 12:34:59 PM PST 23
Peak memory 248592 kb
Host smart-534cf5f8-8cbc-45a9-89d9-3ba99a5d500d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=19908187678601022387103556698274166401051626679683799246868196260728910426114 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.19908187678601022387103556698274166401051626679683799246868196260728910426114
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.9855874769638269750256957958725181399653814867505449081238307883910188702791
Short name T754
Test name
Test status
Simulation time 7309292483 ps
CPU time 298.14 seconds
Started Nov 22 12:34:15 PM PST 23
Finished Nov 22 12:39:20 PM PST 23
Peak memory 272344 kb
Host smart-a478c910-91b7-4faa-bea3-2d807f6686bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9855874769638269750256957958725181399653814867505449081238307883910188702791 -assert nopostproc +UVM_TESTNAME=al
ert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.9855874769638269750256957958725181399653814867505449081238307883910188702791
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.53515487721228644788501402460261469997868838040713299940474425600057812985419
Short name T820
Test name
Test status
Simulation time 22019264088 ps
CPU time 946.91 seconds
Started Nov 22 12:34:16 PM PST 23
Finished Nov 22 12:50:11 PM PST 23
Peak memory 273428 kb
Host smart-b5fd6c27-831a-4d31-8759-d5fa99638e42
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53515487721228644788501402460261469997868838040713299940474425600057812
985419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.53515487721228644788501
402460261469997868838040713299940474425600057812985419
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.100915435502754904906409727965720067319040778279105176170425848655074799965266
Short name T750
Test name
Test status
Simulation time 407776267 ps
CPU time 16.73 seconds
Started Nov 22 12:34:17 PM PST 23
Finished Nov 22 12:34:42 PM PST 23
Peak memory 248584 kb
Host smart-eb79cc62-bdc8-4697-bf4b-78e1894e58b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=100915435502754904906409727965720067319040778279105176170425848655074799965266 -assert nopostproc +UVM_TESTNAME=alert_handler_base
_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.alert_handler_tl_errors.100915435502754904906409727965720067319040778279105176170425848655074799965266
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.74487298209778606692853297890846923759081580654267577781663750671129372022749
Short name T7
Test name
Test status
Simulation time 1596552471 ps
CPU time 64.05 seconds
Started Nov 22 12:34:20 PM PST 23
Finished Nov 22 12:35:31 PM PST 23
Peak memory 240376 kb
Host smart-99c7ff82-7a8d-4b4c-afc7-8c2dafff204f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=74487298209778606692853297890846923759081580654267577781663750671129372022749 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.74487298209778606692853297890846923759081580654267577781663750671129372022749
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.112256886516483735048529210934078603973875974461165062505440501865965157414505
Short name T131
Test name
Test status
Simulation time 110671501 ps
CPU time 7.47 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:34:35 PM PST 23
Peak memory 253972 kb
Host smart-a2bfcf5a-d4d6-40f9-8152-fe120ebc3fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11225688651648373504852921093407860397387597446116506250544050186596515741
4505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_rw_with_rand_reset.1122568865164837350485292109
34078603973875974461165062505440501865965157414505
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.98170742125850320270143022500814069781393780919552744848692160578910212968534
Short name T725
Test name
Test status
Simulation time 162171089 ps
CPU time 7.56 seconds
Started Nov 22 12:34:07 PM PST 23
Finished Nov 22 12:34:20 PM PST 23
Peak memory 240460 kb
Host smart-84e4684f-0ba1-4d81-939f-d79806564c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=98170742125850320270143022500814069781393780919552744848692160578910212968534 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.alert_handler_csr_rw.98170742125850320270143022500814069781393780919552744848692160578910212968534
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.65551452343479971335666747557882081966034855038013894715702614263412817607220
Short name T799
Test name
Test status
Simulation time 10547302 ps
CPU time 1.49 seconds
Started Nov 22 12:34:19 PM PST 23
Finished Nov 22 12:34:29 PM PST 23
Peak memory 235692 kb
Host smart-266f3f6f-ca95-4aa3-891b-6056a11b4b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=65551452343479971335666747557882081966034855038013894715702614263412817607220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.alert_handler_intr_test.65551452343479971335666747557882081966034855038013894715702614263412817607220
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.38734378586649478371729150439488241924876046070244013674717922608885789229834
Short name T810
Test name
Test status
Simulation time 867915443 ps
CPU time 32.61 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:35:01 PM PST 23
Peak memory 248388 kb
Host smart-4a963c10-e2f5-4b4b-8364-b0fcea596603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=38734378586649478371729150439488241924876046070244013674717922608885789229834 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.38734378586649478371729150439488241924876046070244013674717922608885789229834
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.65692974737890173962453415534014506168608228380368919909896238945750875343434
Short name T758
Test name
Test status
Simulation time 7309292483 ps
CPU time 301.14 seconds
Started Nov 22 12:34:18 PM PST 23
Finished Nov 22 12:39:27 PM PST 23
Peak memory 272356 kb
Host smart-0cde6bf9-909d-4821-86aa-1a3bbb67214e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65692974737890173962453415534014506168608228380368919909896238945750875343434 -assert nopostproc +UVM_TESTNAME=a
lert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.65692974737890173962453415534014506168608228380368919909896238945750875343434
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.52680555487994155431644538763008373788344433150588445596748012526978525982677
Short name T850
Test name
Test status
Simulation time 22019264088 ps
CPU time 871.61 seconds
Started Nov 22 12:34:13 PM PST 23
Finished Nov 22 12:48:49 PM PST 23
Peak memory 273396 kb
Host smart-29ccdd3c-47bd-42d4-8a06-93a98008a1bc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52680555487994155431644538763008373788344433150588445596748012526978525
982677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.52680555487994155431644
538763008373788344433150588445596748012526978525982677
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.46649263080022932289412225067467418825151900924234794809351137339457942995024
Short name T711
Test name
Test status
Simulation time 407776267 ps
CPU time 17.1 seconds
Started Nov 22 12:34:24 PM PST 23
Finished Nov 22 12:34:46 PM PST 23
Peak memory 248600 kb
Host smart-7077d11f-32f4-4c22-813d-6e6dc68a88b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=46649263080022932289412225067467418825151900924234794809351137339457942995024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.alert_handler_tl_errors.46649263080022932289412225067467418825151900924234794809351137339457942995024
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.100926376773677269553243884970192988523443586431419918809893765815142861124947
Short name T95
Test name
Test status
Simulation time 1596552471 ps
CPU time 61.95 seconds
Started Nov 22 12:34:30 PM PST 23
Finished Nov 22 12:35:35 PM PST 23
Peak memory 240376 kb
Host smart-5f13c75b-94c7-4e46-9acc-08f718e78fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=100926376773677269553243884970192988523443586431419918809893765815142861124947 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.100926376773677269553243884970192988523443586431419918809893765815142861124947
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.108569535291820291843784197440026585796421197627601132870398375324222294615767
Short name T790
Test name
Test status
Simulation time 110671501 ps
CPU time 6.91 seconds
Started Nov 22 12:35:18 PM PST 23
Finished Nov 22 12:35:27 PM PST 23
Peak memory 253928 kb
Host smart-31589b8e-7420-4b7d-aeb7-3b2ead6fb92d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10856953529182029184378419744002658579642119762760113287039837532422229461
5767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_rw_with_rand_reset.1085695352918202918437841974
40026585796421197627601132870398375324222294615767
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.12172276845965515052907874085618246245125894379378053397430801792074206563336
Short name T793
Test name
Test status
Simulation time 162171089 ps
CPU time 7.75 seconds
Started Nov 22 12:34:22 PM PST 23
Finished Nov 22 12:34:36 PM PST 23
Peak memory 240192 kb
Host smart-c5c9cfdf-db41-43d4-bc30-a434933103e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=12172276845965515052907874085618246245125894379378053397430801792074206563336 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.alert_handler_csr_rw.12172276845965515052907874085618246245125894379378053397430801792074206563336
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.15176324477010306117799158836256607723563063500280525451409540622642591276210
Short name T773
Test name
Test status
Simulation time 10547302 ps
CPU time 1.43 seconds
Started Nov 22 12:34:19 PM PST 23
Finished Nov 22 12:34:29 PM PST 23
Peak memory 235472 kb
Host smart-06cc53e2-b050-40c9-84f4-5be6d8dc7724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=15176324477010306117799158836256607723563063500280525451409540622642591276210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.alert_handler_intr_test.15176324477010306117799158836256607723563063500280525451409540622642591276210
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.59287630218879472151980097515222361794229318991819259131928145213241045985711
Short name T747
Test name
Test status
Simulation time 867915443 ps
CPU time 32.3 seconds
Started Nov 22 12:34:18 PM PST 23
Finished Nov 22 12:34:58 PM PST 23
Peak memory 248532 kb
Host smart-d40bc746-f95a-40e0-8970-eaa806791099
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=59287630218879472151980097515222361794229318991819259131928145213241045985711 -assert nopostproc +UVM_TESTNAM
E=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.59287630218879472151980097515222361794229318991819259131928145213241045985711
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.108707880957100942636811721583183009263803631143478953323535881036510664142690
Short name T827
Test name
Test status
Simulation time 7309292483 ps
CPU time 313.48 seconds
Started Nov 22 12:34:21 PM PST 23
Finished Nov 22 12:39:41 PM PST 23
Peak memory 272464 kb
Host smart-c5d082ea-0666-4504-994f-253a2a1beef9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108707880957100942636811721583183009263803631143478953323535881036510664142690 -assert nopostproc +UVM_TESTNAME=
alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.108707880957100942636811721583183009263803631143478953323535881036510664142690
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.68543606189886922293768181753702276256207059377415077467522508586358159873147
Short name T781
Test name
Test status
Simulation time 22019264088 ps
CPU time 929.22 seconds
Started Nov 22 12:34:24 PM PST 23
Finished Nov 22 12:49:58 PM PST 23
Peak memory 273456 kb
Host smart-fb83eed5-0e18-4375-ba82-90ffc537c652
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68543606189886922293768181753702276256207059377415077467522508586358159
873147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.68543606189886922293768
181753702276256207059377415077467522508586358159873147
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.34464437848997680232967656905714397687196521359238873087351308821027837006197
Short name T699
Test name
Test status
Simulation time 407776267 ps
CPU time 14.93 seconds
Started Nov 22 12:34:20 PM PST 23
Finished Nov 22 12:34:42 PM PST 23
Peak memory 248712 kb
Host smart-4a6b23b0-ca4c-4adc-9f1b-9e75cdf55861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34464437848997680232967656905714397687196521359238873087351308821027837006197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_
test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.alert_handler_tl_errors.34464437848997680232967656905714397687196521359238873087351308821027837006197
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.96624918697822306198435465642523443536394840812857158689727160244434788551387
Short name T710
Test name
Test status
Simulation time 1596552471 ps
CPU time 62.11 seconds
Started Nov 22 12:34:19 PM PST 23
Finished Nov 22 12:35:29 PM PST 23
Peak memory 240300 kb
Host smart-2195c6eb-72b4-4730-b0bc-20d2557eb396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=96624918697822306198435465642523443536394840812857158689727160244434788551387 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.96624918697822306198435465642523443536394840812857158689727160244434788551387
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.96316142507159634545552064641572682122284813163911553411230136356138607208077
Short name T135
Test name
Test status
Simulation time 6994902141 ps
CPU time 240.93 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:16:11 PM PST 23
Peak memory 251044 kb
Host smart-5b8087e7-dc40-4abe-8811-10ebbf6599ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96316
142507159634545552064641572682122284813163911553411230136356138607208077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.alert_handler_esc_alert_accum.96316142507159634545552064641572682122284813163911553411230136356138607208077
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.82416970969545949256587781372722355598927558365781157863762723505215530332423
Short name T545
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.93 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 255652 kb
Host smart-f9274e1e-e817-403d-ad5f-6ffc5818a203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82416
970969545949256587781372722355598927558365781157863762723505215530332423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.alert_handler_esc_intr_timeout.82416970969545949256587781372722355598927558365781157863762723505215530332423
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.17228710667580985736968859110527586462265719648528247019871133401885601452856
Short name T342
Test name
Test status
Simulation time 58351884139 ps
CPU time 1973.54 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:45:04 PM PST 23
Peak memory 289284 kb
Host smart-4e5010ae-b794-4d63-a015-dc1138ed9d51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17228710667580985736968859110527586462265719648528247019871133401885601452856 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.alert_handler_lpg.17228710667580985736968859110527586462265719648528247019871133401885601452856
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3140193308946034597723199600868189967784341007510493473074992062341530133473
Short name T248
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.3 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:12:54 PM PST 23
Peak memory 254876 kb
Host smart-96cac6b9-bc6a-4194-bc8a-9692813c9994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31401
93308946034597723199600868189967784341007510493473074992062341530133473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
alert_handler_random_classes.3140193308946034597723199600868189967784341007510493473074992062341530133473
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.45752783721090455703991003903987097122117812963349857379021268968866405052580
Short name T87
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.19 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:12:58 PM PST 23
Peak memory 255524 kb
Host smart-3dcd4353-079c-425a-b54d-2e7022283132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45752
783721090455703991003903987097122117812963349857379021268968866405052580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
lert_handler_sig_int_fail.45752783721090455703991003903987097122117812963349857379021268968866405052580
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.85157968518018217793773969742700854026966185232231044875498505898436791537200
Short name T158
Test name
Test status
Simulation time 1558784916 ps
CPU time 48.3 seconds
Started Nov 22 01:12:11 PM PST 23
Finished Nov 22 01:13:02 PM PST 23
Peak memory 248880 kb
Host smart-7fc61316-eada-4356-a784-076df1379e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85157
968518018217793773969742700854026966185232231044875498505898436791537200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_ha
ndler_smoke.85157968518018217793773969742700854026966185232231044875498505898436791537200
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.107957241545412014144184517078793077028558317998804911994615847958359701858606
Short name T496
Test name
Test status
Simulation time 63383433172 ps
CPU time 2100.8 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:47:12 PM PST 23
Peak memory 289668 kb
Host smart-ae462406-1171-4580-a6b0-6d451dbb8b79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107957241545412014144184517078793077028558317998804911994615847958359701858606 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.10795724154541201414418451707879307702855831799880491199461584
7958359701858606
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.75398260853020772843574594322668711393356181456052757132579195706834959350716
Short name T69
Test name
Test status
Simulation time 79866015596 ps
CPU time 2724.79 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:57:34 PM PST 23
Peak memory 298172 kb
Host smart-dd53f1ce-8da7-4986-9489-4820954bc394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753982608530207728435745943226687113933561814560
52757132579195706834959350716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.753982608
53020772843574594322668711393356181456052757132579195706834959350716
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.98196734980500563099417250100225607942931095950253709695887928068941959355145
Short name T633
Test name
Test status
Simulation time 49707703 ps
CPU time 3.02 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 249016 kb
Host smart-d65f94ba-783e-4cb4-ba46-919e28b1074f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=98196734980500563099417250100225607942931095950253709695887928068941959355145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.alert_handler_alert_accum_saturation.98196734980500563099417250100225607942931095950253709695887928068941959355145
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.74322837237744113086195522161256945581261264574737049572414733256094479617387
Short name T542
Test name
Test status
Simulation time 30823729350 ps
CPU time 1072.72 seconds
Started Nov 22 01:12:15 PM PST 23
Finished Nov 22 01:30:10 PM PST 23
Peak memory 272496 kb
Host smart-c662aeb7-0d08-4622-a262-1610c4a90e2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74322837237744113086195522161256945581261264574737049572414733256094479617387 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.alert_handler_entropy.74322837237744113086195522161256945581261264574737049572414733256094479617387
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.18233941039472880684270407271663521635466989735093296200555383097619499497360
Short name T405
Test name
Test status
Simulation time 1452482195 ps
CPU time 36.84 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:12:46 PM PST 23
Peak memory 240648 kb
Host smart-8da8a9bc-deca-4b85-b52b-7080754f9c1a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=18233941039472880684270407271663521635466989735093296200555383097619499497360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.alert_handler_entropy_stress.18233941039472880684270407271663521635466989735093296200555383097619499497360
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.100161519732370991578846588036686606064014115206458609675901760283410352906243
Short name T410
Test name
Test status
Simulation time 6994902141 ps
CPU time 226.75 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:15:59 PM PST 23
Peak memory 251028 kb
Host smart-c2770609-3e7c-4296-8c66-61555396266c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10016
1519732370991578846588036686606064014115206458609675901760283410352906243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.alert_handler_esc_alert_accum.100161519732370991578846588036686606064014115206458609675901760283410352906243
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.17071561996109850072203519681733349429909192224467621291566477542685811059923
Short name T547
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.42 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 255508 kb
Host smart-837803c1-2091-432b-adbb-7598f9e4c654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17071
561996109850072203519681733349429909192224467621291566477542685811059923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.alert_handler_esc_intr_timeout.17071561996109850072203519681733349429909192224467621291566477542685811059923
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.629281000417762005471179122048221505070573477327930979830755426636251943052
Short name T286
Test name
Test status
Simulation time 58351884139 ps
CPU time 1821.96 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:42:35 PM PST 23
Peak memory 284124 kb
Host smart-af8386f0-f657-43a2-8155-83a86a06f317
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629281000417762005471179122048221505070573477327930979830755426636251943052 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.alert_handler_lpg.629281000417762005471179122048221505070573477327930979830755426636251943052
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.65625592126889827688612080281018244556921056371696862502835678301808876546103
Short name T495
Test name
Test status
Simulation time 48172572717 ps
CPU time 1556.38 seconds
Started Nov 22 01:12:05 PM PST 23
Finished Nov 22 01:38:03 PM PST 23
Peak memory 272520 kb
Host smart-edb9af03-f863-4136-95b8-e085d49f5fbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65625592126889827688612080281018244556921056371696862502835678301808876546103 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.65625592126889827688612080281018244556921056371696862502835678301808876546103
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.50945818446736153309270746439448639910351562130281685078029923903231482014607
Short name T660
Test name
Test status
Simulation time 17273552054 ps
CPU time 408.78 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:18:58 PM PST 23
Peak memory 247532 kb
Host smart-a90af54e-ea0f-4f55-aace-9b2dd3b1d359
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50945818446736153309270746439448639910351562130281685078029923903231482014607 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.50945818446736153309270746439448639910351562130281685078029923903231482014607
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.48072136067004504308167367025961924736560775438456284522007705724708108264881
Short name T282
Test name
Test status
Simulation time 1399732617 ps
CPU time 43.26 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 255428 kb
Host smart-c6254498-ba82-459c-845a-2f078a47b747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48072
136067004504308167367025961924736560775438456284522007705724708108264881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
alert_handler_random_alerts.48072136067004504308167367025961924736560775438456284522007705724708108264881
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.79860423771984177905430600967972539508014628858327611851470706748526371674706
Short name T37
Test name
Test status
Simulation time 740845031 ps
CPU time 22.9 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:12:31 PM PST 23
Peak memory 274848 kb
Host smart-16612391-262b-417d-ab50-2a8f28786fe4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=79860423771984177905430600967972539508014628858327611851470706748526371674706 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.alert_handler_sec_cm.79860423771984177905430600967972539508014628858327611851470706748526371674706
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.45142671842405184102484214972624469062876914336082955631281242314385929588376
Short name T398
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.54 seconds
Started Nov 22 01:12:15 PM PST 23
Finished Nov 22 01:13:02 PM PST 23
Peak memory 255472 kb
Host smart-b68bfba6-404f-4d99-a627-305e72f5fe51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45142
671842405184102484214972624469062876914336082955631281242314385929588376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
lert_handler_sig_int_fail.45142671842405184102484214972624469062876914336082955631281242314385929588376
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.114418835050920524445377078249429658905933764095150079257169804099826855512457
Short name T336
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.29 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:13:04 PM PST 23
Peak memory 248856 kb
Host smart-d446e6ce-b28e-496f-bb38-bdab2b8925c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11441
8835050920524445377078249429658905933764095150079257169804099826855512457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_h
andler_smoke.114418835050920524445377078249429658905933764095150079257169804099826855512457
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.37834863079516584596922798684685536774998000428439209904216218362751779361309
Short name T567
Test name
Test status
Simulation time 63383433172 ps
CPU time 2117.41 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:47:28 PM PST 23
Peak memory 289780 kb
Host smart-6c7b7d82-abc0-4679-b3e1-f55b13a8afb4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37834863079516584596922798684685536774998000428439209904216218362751779361309 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.378348630795165845969227986846855367749980004284392099042162183
62751779361309
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.25004550749381114450657064206290823846011994010952286341262366993162611121706
Short name T641
Test name
Test status
Simulation time 79866015596 ps
CPU time 2744.93 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 298168 kb
Host smart-f30edf73-7eb0-4958-885f-b4e135f0f078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250045507493811144506570642062908238460119940109
52286341262366993162611121706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.250045507
49381114450657064206290823846011994010952286341262366993162611121706
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.106469618863340520983833468200451233516491279762802870227928744472037868439981
Short name T115
Test name
Test status
Simulation time 49707703 ps
CPU time 2.9 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 01:12:46 PM PST 23
Peak memory 248868 kb
Host smart-9f6c215c-6be4-47b1-864c-db4737a7dd98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=106469618863340520983833468200451233516491279762802870227928744472037868439981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.alert_handler_alert_accum_saturation.106469618863340520983833468200451233516491279762802870227928744472037868439981
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.12393214629150900370091457217602298036445301669026979163762697640961172093499
Short name T552
Test name
Test status
Simulation time 30823729350 ps
CPU time 1059.73 seconds
Started Nov 22 01:12:26 PM PST 23
Finished Nov 22 01:30:15 PM PST 23
Peak memory 272496 kb
Host smart-c226670b-cb74-4627-9e1a-58dbc6a829e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12393214629150900370091457217602298036445301669026979163762697640961172093499 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.alert_handler_entropy.12393214629150900370091457217602298036445301669026979163762697640961172093499
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.20504581262049324928419555555611610077997225556981012848333300289097610075894
Short name T318
Test name
Test status
Simulation time 1452482195 ps
CPU time 36.28 seconds
Started Nov 22 01:12:41 PM PST 23
Finished Nov 22 01:13:23 PM PST 23
Peak memory 240396 kb
Host smart-c38d6740-99fc-4d66-a4b2-e071bd213504
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=20504581262049324928419555555611610077997225556981012848333300289097610075894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.alert_handler_entropy_stress.20504581262049324928419555555611610077997225556981012848333300289097610075894
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.100954620725484701195095901405144458671719328604165904435212001486602319624508
Short name T587
Test name
Test status
Simulation time 6994902141 ps
CPU time 231.7 seconds
Started Nov 22 01:12:34 PM PST 23
Finished Nov 22 01:16:34 PM PST 23
Peak memory 251084 kb
Host smart-b3b8f920-2ce0-430b-a88f-6e1614333567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10095
4620725484701195095901405144458671719328604165904435212001486602319624508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.alert_handler_esc_alert_accum.100954620725484701195095901405144458671719328604165904435212001486602319624508
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.96635599096363123690484130478661539795838338648571031096496708636283067779378
Short name T683
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.63 seconds
Started Nov 22 01:12:29 PM PST 23
Finished Nov 22 01:13:25 PM PST 23
Peak memory 255628 kb
Host smart-8a882ee3-5c50-4d70-ae15-4a13f05ffc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96635
599096363123690484130478661539795838338648571031096496708636283067779378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.alert_handler_esc_intr_timeout.96635599096363123690484130478661539795838338648571031096496708636283067779378
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.99745642676430833138084947682217682924517587129138155212017906359911295310208
Short name T240
Test name
Test status
Simulation time 58351884139 ps
CPU time 1894.59 seconds
Started Nov 22 01:12:27 PM PST 23
Finished Nov 22 01:44:10 PM PST 23
Peak memory 289300 kb
Host smart-12f59419-a944-4f2f-9283-c36264a8099a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99745642676430833138084947682217682924517587129138155212017906359911295310208 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.alert_handler_lpg.99745642676430833138084947682217682924517587129138155212017906359911295310208
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.52986211752126102955180088275107600736507557743494093976174524488524776180593
Short name T156
Test name
Test status
Simulation time 48172572717 ps
CPU time 1485.62 seconds
Started Nov 22 01:12:32 PM PST 23
Finished Nov 22 01:37:26 PM PST 23
Peak memory 272488 kb
Host smart-f100f8d2-4da4-48ea-abfa-ff0285b9a426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52986211752126102955180088275107600736507557743494093976174524488524776180593 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.52986211752126102955180088275107600736507557743494093976174524488524776180593
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.45382671773101646572432207425785555806248577941135668895739298710248725506235
Short name T494
Test name
Test status
Simulation time 17273552054 ps
CPU time 384.22 seconds
Started Nov 22 01:12:39 PM PST 23
Finished Nov 22 01:19:09 PM PST 23
Peak memory 247096 kb
Host smart-9e585953-d192-4b7d-a66c-034136d047f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45382671773101646572432207425785555806248577941135668895739298710248725506235 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.45382671773101646572432207425785555806248577941135668895739298710248725506235
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.41195839897349751710757019368408362366913584511134138747871827608666695598206
Short name T484
Test name
Test status
Simulation time 1399732617 ps
CPU time 46.79 seconds
Started Nov 22 01:12:26 PM PST 23
Finished Nov 22 01:13:22 PM PST 23
Peak memory 255464 kb
Host smart-15b4db90-2049-43b9-ae86-979f14c40249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41195
839897349751710757019368408362366913584511134138747871827608666695598206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.alert_handler_random_alerts.41195839897349751710757019368408362366913584511134138747871827608666695598206
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.31334199375280714086565114661414190954775453049589202599270486715138886985043
Short name T62
Test name
Test status
Simulation time 1291269199 ps
CPU time 44.7 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 01:13:28 PM PST 23
Peak memory 254848 kb
Host smart-456dbc35-cf5d-4885-9875-e135a819d057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31334
199375280714086565114661414190954775453049589202599270486715138886985043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.alert_handler_random_classes.31334199375280714086565114661414190954775453049589202599270486715138886985043
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.99987331064130252857714599485430308244052066834208913307560891781506712423600
Short name T502
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.29 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 01:13:26 PM PST 23
Peak memory 255552 kb
Host smart-d8b77e64-3838-4104-9c62-e6b4a6f1a2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99987
331064130252857714599485430308244052066834208913307560891781506712423600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
alert_handler_sig_int_fail.99987331064130252857714599485430308244052066834208913307560891781506712423600
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.88399178725460871519636902371428833741260259343714012731447571022120376327564
Short name T185
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.5 seconds
Started Nov 22 01:12:26 PM PST 23
Finished Nov 22 01:13:26 PM PST 23
Peak memory 248748 kb
Host smart-d1b98c92-3019-4937-ab46-52926cde9ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88399
178725460871519636902371428833741260259343714012731447571022120376327564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_h
andler_smoke.88399178725460871519636902371428833741260259343714012731447571022120376327564
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.564286181700111380268807730933413055478079430217407774828034421392418524549
Short name T196
Test name
Test status
Simulation time 63383433172 ps
CPU time 2142.34 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 01:48:27 PM PST 23
Peak memory 289720 kb
Host smart-794cf76b-06c1-42f5-866c-d17486e67387
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564286181700111380268807730933413055478079430217407774828034421392418524549 -assert nopost
proc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.564286181700111380268807730933413055478079430217407774828034421392418524549
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.96294485006029260158118973480732294802291575268822356537893582273423457717159
Short name T356
Test name
Test status
Simulation time 79866015596 ps
CPU time 2743.09 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:58:31 PM PST 23
Peak memory 298076 kb
Host smart-c0b2a5d0-799a-4aed-a819-54dced774d1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962944850060292601581189734807322948022915752688
22356537893582273423457717159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.96294485
006029260158118973480732294802291575268822356537893582273423457717159
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.83427741275213082876964337427504261235321711799563461021454935046053453822144
Short name T117
Test name
Test status
Simulation time 49707703 ps
CPU time 2.98 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:12:51 PM PST 23
Peak memory 248180 kb
Host smart-dfe185cf-22af-4ff1-b0cf-6d7c01ab86d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=83427741275213082876964337427504261235321711799563461021454935046053453822144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.alert_handler_alert_accum_saturation.83427741275213082876964337427504261235321711799563461021454935046053453822144
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.8556322548371544050073304977416168150889692333729550781975470438741263068103
Short name T231
Test name
Test status
Simulation time 30823729350 ps
CPU time 1023.22 seconds
Started Nov 22 01:12:34 PM PST 23
Finished Nov 22 01:29:46 PM PST 23
Peak memory 272436 kb
Host smart-b0d1c029-757e-4cbf-ba2f-11b1d4b6bbd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8556322548371544050073304977416168150889692333729550781975470438741263068103 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.alert_handler_entropy.8556322548371544050073304977416168150889692333729550781975470438741263068103
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.86691602935030432018223454037719014142046616920169451470992826999534557105739
Short name T486
Test name
Test status
Simulation time 1452482195 ps
CPU time 37.42 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:13:26 PM PST 23
Peak memory 240644 kb
Host smart-5ba5b6ba-1a3b-4d52-ab9f-00209ff91cba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=86691602935030432018223454037719014142046616920169451470992826999534557105739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.alert_handler_entropy_stress.86691602935030432018223454037719014142046616920169451470992826999534557105739
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.7599024144685638297592839604088078855594045950676045964086346306988629207613
Short name T648
Test name
Test status
Simulation time 6994902141 ps
CPU time 238.52 seconds
Started Nov 22 01:12:27 PM PST 23
Finished Nov 22 01:16:33 PM PST 23
Peak memory 251192 kb
Host smart-ffbca82e-dad2-4c7d-b435-ef1e6bf0bea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75990
24144685638297592839604088078855594045950676045964086346306988629207613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.alert_handler_esc_alert_accum.7599024144685638297592839604088078855594045950676045964086346306988629207613
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.106337623119296981504240387341613265751655116862475566624055823044249725736536
Short name T202
Test name
Test status
Simulation time 1449142936 ps
CPU time 46.22 seconds
Started Nov 22 01:12:27 PM PST 23
Finished Nov 22 01:13:21 PM PST 23
Peak memory 256248 kb
Host smart-be3cb3cf-696e-4069-95f9-723c52753aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10633
7623119296981504240387341613265751655116862475566624055823044249725736536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.alert_handler_esc_intr_timeout.106337623119296981504240387341613265751655116862475566624055823044249725736536
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.96716976114591591097583009526890908547591094675995930363432244120482679630928
Short name T616
Test name
Test status
Simulation time 58351884139 ps
CPU time 1796.45 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:42:45 PM PST 23
Peak memory 289292 kb
Host smart-8976ca86-59fb-46c1-9976-cb7914862aa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96716976114591591097583009526890908547591094675995930363432244120482679630928 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.alert_handler_lpg.96716976114591591097583009526890908547591094675995930363432244120482679630928
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.25707323748874711834707860093644952374157229693427942593639097971026425826537
Short name T503
Test name
Test status
Simulation time 48172572717 ps
CPU time 1708.08 seconds
Started Nov 22 01:12:31 PM PST 23
Finished Nov 22 01:41:05 PM PST 23
Peak memory 272520 kb
Host smart-471f44c5-fab1-4407-a55e-11ea8801d849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25707323748874711834707860093644952374157229693427942593639097971026425826537 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.25707323748874711834707860093644952374157229693427942593639097971026425826537
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.87489877532789328251847523134047882492897384220414892018522332440042761003777
Short name T311
Test name
Test status
Simulation time 17273552054 ps
CPU time 405.48 seconds
Started Nov 22 01:12:41 PM PST 23
Finished Nov 22 01:19:33 PM PST 23
Peak memory 247564 kb
Host smart-eb3dd104-1096-489a-b71f-5166eff55f25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87489877532789328251847523134047882492897384220414892018522332440042761003777 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.87489877532789328251847523134047882492897384220414892018522332440042761003777
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.102076741417124526819905648035269535128240461785129875415797704285688906566258
Short name T353
Test name
Test status
Simulation time 1399732617 ps
CPU time 49.73 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 01:13:33 PM PST 23
Peak memory 255488 kb
Host smart-5a8d2bab-8ff7-487d-b0fa-b69d9a969c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
6741417124526819905648035269535128240461785129875415797704285688906566258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.alert_handler_random_alerts.102076741417124526819905648035269535128240461785129875415797704285688906566258
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.96501286871832969218598363176889626178741395975928202720440302723354553856621
Short name T576
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.98 seconds
Started Nov 22 01:12:28 PM PST 23
Finished Nov 22 01:13:21 PM PST 23
Peak memory 254848 kb
Host smart-a5d8fa14-54dc-49e7-b9c8-b688b129588c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96501
286871832969218598363176889626178741395975928202720440302723354553856621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.alert_handler_random_classes.96501286871832969218598363176889626178741395975928202720440302723354553856621
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.65150024598474311863493155293283626987778323147088771494006063127457960547575
Short name T527
Test name
Test status
Simulation time 1261680150 ps
CPU time 46.94 seconds
Started Nov 22 01:12:38 PM PST 23
Finished Nov 22 01:13:32 PM PST 23
Peak memory 255488 kb
Host smart-91ada47a-eebf-4032-b74a-ea75cbfb532a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65150
024598474311863493155293283626987778323147088771494006063127457960547575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
alert_handler_sig_int_fail.65150024598474311863493155293283626987778323147088771494006063127457960547575
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.99175595547220814584156665398534448014213665729588158204067666359624515164541
Short name T462
Test name
Test status
Simulation time 1558784916 ps
CPU time 54.01 seconds
Started Nov 22 01:12:28 PM PST 23
Finished Nov 22 01:13:29 PM PST 23
Peak memory 248844 kb
Host smart-33cbb10a-61a2-416a-8aa4-1383a308ac92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99175
595547220814584156665398534448014213665729588158204067666359624515164541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_h
andler_smoke.99175595547220814584156665398534448014213665729588158204067666359624515164541
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.48894186307937910113986534398531552491981864537247809368772866941239104207805
Short name T317
Test name
Test status
Simulation time 63383433172 ps
CPU time 2150.37 seconds
Started Nov 22 01:12:39 PM PST 23
Finished Nov 22 01:48:35 PM PST 23
Peak memory 289732 kb
Host smart-c2c67861-83e4-4b07-85de-e51a8abd0479
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48894186307937910113986534398531552491981864537247809368772866941239104207805 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.48894186307937910113986534398531552491981864537247809368772866
941239104207805
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.5443653576047504772698985250916034708703302809429457949928825853488566307800
Short name T618
Test name
Test status
Simulation time 79866015596 ps
CPU time 2886.54 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 02:00:51 PM PST 23
Peak memory 298204 kb
Host smart-25eee2a4-c29f-4ce8-abb5-9bd90e908229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544365357604750477269898525091603470870330280942
9457949928825853488566307800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.544365357
6047504772698985250916034708703302809429457949928825853488566307800
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.91355656581971618885909818659845194145591767416799852309976992690869298156815
Short name T499
Test name
Test status
Simulation time 49707703 ps
CPU time 3.11 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 01:12:47 PM PST 23
Peak memory 249028 kb
Host smart-c11479cb-a4ef-4313-8d9a-240513dff2ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=91355656581971618885909818659845194145591767416799852309976992690869298156815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.alert_handler_alert_accum_saturation.91355656581971618885909818659845194145591767416799852309976992690869298156815
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.113492884064399963210590829419644278045768417015429081188345399197882150008342
Short name T632
Test name
Test status
Simulation time 30823729350 ps
CPU time 1046.72 seconds
Started Nov 22 01:12:39 PM PST 23
Finished Nov 22 01:30:12 PM PST 23
Peak memory 272240 kb
Host smart-1b9ac2cc-e4d9-4d5a-ab58-320aa92e2671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113492884064399963210590829419644278045768417015429081188345399197882150008342 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.alert_handler_entropy.113492884064399963210590829419644278045768417015429081188345399197882150008342
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.28844178018104157078974955999479386592802797086957440973104330211049464282305
Short name T40
Test name
Test status
Simulation time 1452482195 ps
CPU time 35.34 seconds
Started Nov 22 01:12:34 PM PST 23
Finished Nov 22 01:13:17 PM PST 23
Peak memory 240600 kb
Host smart-3075dad7-8241-4904-acef-3c14bbf55cc8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=28844178018104157078974955999479386592802797086957440973104330211049464282305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.alert_handler_entropy_stress.28844178018104157078974955999479386592802797086957440973104330211049464282305
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.76473475430527462425682652157117645696372605014855066258419624541911449642120
Short name T428
Test name
Test status
Simulation time 6994902141 ps
CPU time 219.45 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 01:16:23 PM PST 23
Peak memory 251248 kb
Host smart-ce153777-2a1d-4b38-878b-ecc3012d2140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76473
475430527462425682652157117645696372605014855066258419624541911449642120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.alert_handler_esc_alert_accum.76473475430527462425682652157117645696372605014855066258419624541911449642120
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.13395366287971774997814463390349774324788933822099751193996153799518291687787
Short name T288
Test name
Test status
Simulation time 1449142936 ps
CPU time 44.67 seconds
Started Nov 22 01:12:28 PM PST 23
Finished Nov 22 01:13:20 PM PST 23
Peak memory 255652 kb
Host smart-e99c7eac-22f4-4c5f-970e-a82972adeeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
366287971774997814463390349774324788933822099751193996153799518291687787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.alert_handler_esc_intr_timeout.13395366287971774997814463390349774324788933822099751193996153799518291687787
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.73564350973931182695321592125873493305508592368364759489949021986972313036339
Short name T123
Test name
Test status
Simulation time 58351884139 ps
CPU time 1948.27 seconds
Started Nov 22 01:12:30 PM PST 23
Finished Nov 22 01:45:04 PM PST 23
Peak memory 289260 kb
Host smart-7709a401-622d-4dac-8de4-bb416cee5f27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73564350973931182695321592125873493305508592368364759489949021986972313036339 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.alert_handler_lpg.73564350973931182695321592125873493305508592368364759489949021986972313036339
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.18305451870818544349460998183210927111101588874837428341094896772189416160354
Short name T544
Test name
Test status
Simulation time 48172572717 ps
CPU time 1573.16 seconds
Started Nov 22 01:12:41 PM PST 23
Finished Nov 22 01:39:00 PM PST 23
Peak memory 272496 kb
Host smart-d7f34627-df2f-45e7-aab1-a3e658de91f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18305451870818544349460998183210927111101588874837428341094896772189416160354 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.18305451870818544349460998183210927111101588874837428341094896772189416160354
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.107011364436581774589266066558239514190224573198375494489877675815560697969075
Short name T139
Test name
Test status
Simulation time 17273552054 ps
CPU time 395.51 seconds
Started Nov 22 01:12:39 PM PST 23
Finished Nov 22 01:19:21 PM PST 23
Peak memory 247052 kb
Host smart-77b2badc-da20-4953-aa10-504a9de92d74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107011364436581774589266066558239514190224573198375494489877675815560697969075 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.107011364436581774589266066558239514190224573198375494489877675815560697969075
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.80110849467202940788557435289792355373765400266438232949788581009505802699486
Short name T569
Test name
Test status
Simulation time 1399732617 ps
CPU time 45.9 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:13:34 PM PST 23
Peak memory 255452 kb
Host smart-c4f11aa8-4ea2-4abe-89b8-ba10838b71f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80110
849467202940788557435289792355373765400266438232949788581009505802699486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.alert_handler_random_alerts.80110849467202940788557435289792355373765400266438232949788581009505802699486
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.62199360896202353998156288745029185470871408283064235581287715806074694170198
Short name T414
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.2 seconds
Started Nov 22 01:12:24 PM PST 23
Finished Nov 22 01:13:16 PM PST 23
Peak memory 254864 kb
Host smart-33781b63-6843-45c0-9edd-79bedd8213c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62199
360896202353998156288745029185470871408283064235581287715806074694170198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.alert_handler_random_classes.62199360896202353998156288745029185470871408283064235581287715806074694170198
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.66520940608006431121106946781991902236275468515601512242852963349260058398502
Short name T347
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.98 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 01:13:27 PM PST 23
Peak memory 255544 kb
Host smart-cb1cdef4-0771-47c8-9f0c-66788a52b3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66520
940608006431121106946781991902236275468515601512242852963349260058398502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
alert_handler_sig_int_fail.66520940608006431121106946781991902236275468515601512242852963349260058398502
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.90177129623265975263429365662041463711490260179633256294205822895732054183152
Short name T50
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.69 seconds
Started Nov 22 01:12:35 PM PST 23
Finished Nov 22 01:13:34 PM PST 23
Peak memory 248852 kb
Host smart-9720f345-a1d2-41a1-ba88-cfd952fc339b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90177
129623265975263429365662041463711490260179633256294205822895732054183152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_h
andler_smoke.90177129623265975263429365662041463711490260179633256294205822895732054183152
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.73839507398012836046786276494864271893424728732652929841459265325519202746838
Short name T613
Test name
Test status
Simulation time 63383433172 ps
CPU time 2131.29 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:48:20 PM PST 23
Peak memory 289780 kb
Host smart-e50968fb-f0a7-4403-9f06-126ffaadf4cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73839507398012836046786276494864271893424728732652929841459265325519202746838 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.73839507398012836046786276494864271893424728732652929841459265
325519202746838
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.18181632016505422055352582714904917886700669864752195379651127426025110577353
Short name T638
Test name
Test status
Simulation time 79866015596 ps
CPU time 2848.99 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 02:00:13 PM PST 23
Peak memory 298180 kb
Host smart-e839fd6a-9ac7-4837-ab84-bc4ca08a56aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181816320165054220553525827149049178867006698647
52195379651127426025110577353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.18181632
016505422055352582714904917886700669864752195379651127426025110577353
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.31888080594509141340410277372730058996178656232313641713164541753835273203857
Short name T627
Test name
Test status
Simulation time 49707703 ps
CPU time 3.08 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:02 PM PST 23
Peak memory 248816 kb
Host smart-cb181b8a-35d0-400e-9a42-a0baaede9008
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=31888080594509141340410277372730058996178656232313641713164541753835273203857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.alert_handler_alert_accum_saturation.31888080594509141340410277372730058996178656232313641713164541753835273203857
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.43815507756318456725397852833170664446864094440989566144805859387766945916279
Short name T650
Test name
Test status
Simulation time 30823729350 ps
CPU time 1056.71 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:30:29 PM PST 23
Peak memory 272320 kb
Host smart-2fddc2e2-5e63-4bd4-a390-fc6af81aa86a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43815507756318456725397852833170664446864094440989566144805859387766945916279 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.alert_handler_entropy.43815507756318456725397852833170664446864094440989566144805859387766945916279
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.52736100709233266959293690611601213971505826906215643828909793178196082348860
Short name T540
Test name
Test status
Simulation time 1452482195 ps
CPU time 36.37 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:13:28 PM PST 23
Peak memory 240608 kb
Host smart-8c31300b-8048-477f-9366-11f013535d00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=52736100709233266959293690611601213971505826906215643828909793178196082348860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.alert_handler_entropy_stress.52736100709233266959293690611601213971505826906215643828909793178196082348860
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.74922727565608956636598215105765292815802529019709847297244725685454260090526
Short name T669
Test name
Test status
Simulation time 6994902141 ps
CPU time 231.7 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 01:16:36 PM PST 23
Peak memory 251084 kb
Host smart-0fcbd5cc-3d51-4046-bd41-79fd9815af78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74922
727565608956636598215105765292815802529019709847297244725685454260090526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.alert_handler_esc_alert_accum.74922727565608956636598215105765292815802529019709847297244725685454260090526
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.102977801586507759699694160920914450035982951910492257051571611038782270495588
Short name T173
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.05 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 01:13:33 PM PST 23
Peak memory 256168 kb
Host smart-2de7845f-fddf-4605-b355-34bbdccff21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10297
7801586507759699694160920914450035982951910492257051571611038782270495588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.alert_handler_esc_intr_timeout.102977801586507759699694160920914450035982951910492257051571611038782270495588
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.71018096776288790347567542209050401245271028693937369797782846246319109225099
Short name T45
Test name
Test status
Simulation time 58351884139 ps
CPU time 1866.25 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:43:58 PM PST 23
Peak memory 289108 kb
Host smart-9e9a1923-1fa9-46d5-aa47-5f85eb968f6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71018096776288790347567542209050401245271028693937369797782846246319109225099 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.alert_handler_lpg.71018096776288790347567542209050401245271028693937369797782846246319109225099
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.952885216203568530488198005033197960157140824062427429654659809263773405023
Short name T386
Test name
Test status
Simulation time 48172572717 ps
CPU time 1551.37 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:38:40 PM PST 23
Peak memory 272540 kb
Host smart-1fa0fbc8-63ca-4875-a03e-c0f27616b855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952885216203568530488198005033197960157140824062427429654659809263773405023 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.952885216203568530488198005033197960157140824062427429654659809263773405023
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.95768748530573695496725344943828371752962944864496708450962193262374104193865
Short name T207
Test name
Test status
Simulation time 17273552054 ps
CPU time 383.69 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 01:19:07 PM PST 23
Peak memory 247544 kb
Host smart-7b6c2cc8-0f4c-4229-bf89-922d6303b379
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95768748530573695496725344943828371752962944864496708450962193262374104193865 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.95768748530573695496725344943828371752962944864496708450962193262374104193865
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.7847155921774154602279013055719392296927967432836431739369353358889245298242
Short name T322
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.33 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:13:40 PM PST 23
Peak memory 255344 kb
Host smart-ae5fe74d-2b0d-4587-a1a3-888c27fd7922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78471
55921774154602279013055719392296927967432836431739369353358889245298242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
alert_handler_random_alerts.7847155921774154602279013055719392296927967432836431739369353358889245298242
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.92264890080917132772240869559725887342190845414838626532900758193658080006452
Short name T75
Test name
Test status
Simulation time 1291269199 ps
CPU time 48.14 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:13:41 PM PST 23
Peak memory 254732 kb
Host smart-7155f03c-d28c-4eb5-803a-eff2991a6d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92264
890080917132772240869559725887342190845414838626532900758193658080006452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.alert_handler_random_classes.92264890080917132772240869559725887342190845414838626532900758193658080006452
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.68556901823123587919204831262382574246982904410975292342420643306761926981099
Short name T444
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.12 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:13:38 PM PST 23
Peak memory 255400 kb
Host smart-a0264ee0-3282-4e88-a753-5af7bde0dea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68556
901823123587919204831262382574246982904410975292342420643306761926981099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
alert_handler_sig_int_fail.68556901823123587919204831262382574246982904410975292342420643306761926981099
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.59570604592903123648882321829684040724593853918359244294957725555817182038361
Short name T298
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.67 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 01:13:36 PM PST 23
Peak memory 248856 kb
Host smart-58b48c87-daa1-4a34-88b8-6b38d2bcb215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59570
604592903123648882321829684040724593853918359244294957725555817182038361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_h
andler_smoke.59570604592903123648882321829684040724593853918359244294957725555817182038361
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.55310260664781004155807692674595241191332124792309879035480083871501568645373
Short name T179
Test name
Test status
Simulation time 63383433172 ps
CPU time 1990.77 seconds
Started Nov 22 01:12:51 PM PST 23
Finished Nov 22 01:46:04 PM PST 23
Peak memory 289644 kb
Host smart-c2bf4726-5df2-4e53-8fad-8cf9a77a3f95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55310260664781004155807692674595241191332124792309879035480083871501568645373 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.55310260664781004155807692674595241191332124792309879035480083
871501568645373
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.27625153929878556082040786921068922470118146624559031766221514743057489038144
Short name T64
Test name
Test status
Simulation time 79866015596 ps
CPU time 2730.09 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:58:29 PM PST 23
Peak memory 297980 kb
Host smart-9e12abd8-4c62-45a2-b380-b0783f41abf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276251539298785560820407869210689224701181466245
59031766221514743057489038144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.27625153
929878556082040786921068922470118146624559031766221514743057489038144
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.66933634061142468698268386884797382426003284056986327486275729373581239842166
Short name T33
Test name
Test status
Simulation time 49707703 ps
CPU time 2.63 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 248960 kb
Host smart-ee987f70-dac5-4474-bcf1-b7a562987189
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=66933634061142468698268386884797382426003284056986327486275729373581239842166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.alert_handler_alert_accum_saturation.66933634061142468698268386884797382426003284056986327486275729373581239842166
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.88774916227081171430205032607668736185215537664487620757094101582501893011773
Short name T184
Test name
Test status
Simulation time 30823729350 ps
CPU time 1054.14 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:30:33 PM PST 23
Peak memory 272408 kb
Host smart-592aae37-7c6b-48e0-a189-6b851b40a852
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88774916227081171430205032607668736185215537664487620757094101582501893011773 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.alert_handler_entropy.88774916227081171430205032607668736185215537664487620757094101582501893011773
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.62048377062266377851245806728901996325956047485480149795041944589268204694450
Short name T489
Test name
Test status
Simulation time 1452482195 ps
CPU time 37.2 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:36 PM PST 23
Peak memory 239932 kb
Host smart-1b86425d-a2fc-4fea-aaec-49e11e48fe2f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=62048377062266377851245806728901996325956047485480149795041944589268204694450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.alert_handler_entropy_stress.62048377062266377851245806728901996325956047485480149795041944589268204694450
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.21126477623959964783440527059839733767472659665713926288709753519552954687303
Short name T54
Test name
Test status
Simulation time 6994902141 ps
CPU time 241.58 seconds
Started Nov 22 01:12:51 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 251240 kb
Host smart-2522e1eb-d1e5-4a96-a36b-e5b9d1ecf496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21126
477623959964783440527059839733767472659665713926288709753519552954687303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.alert_handler_esc_alert_accum.21126477623959964783440527059839733767472659665713926288709753519552954687303
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.69747563344055777481668729306732288710046234445146143136004774761250479026722
Short name T281
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.79 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:46 PM PST 23
Peak memory 255432 kb
Host smart-735dd846-64df-4a05-86a7-85043ace6775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69747
563344055777481668729306732288710046234445146143136004774761250479026722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.alert_handler_esc_intr_timeout.69747563344055777481668729306732288710046234445146143136004774761250479026722
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.100990201369498405307122876288463231343986787742774805894470072649768673803872
Short name T515
Test name
Test status
Simulation time 58351884139 ps
CPU time 1897.84 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:44:27 PM PST 23
Peak memory 289296 kb
Host smart-3d853cce-4310-458a-89fc-5c7e0aaf5f89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100990201369498405307122876288463231343986787742774805894470072649768673803872 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.alert_handler_lpg.100990201369498405307122876288463231343986787742774805894470072649768673803872
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.14009568015809481908140602390782892956953338087968540140168992024338795395215
Short name T681
Test name
Test status
Simulation time 48172572717 ps
CPU time 1618.47 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:39:48 PM PST 23
Peak memory 272504 kb
Host smart-67c81d99-78c3-416d-95b5-53d08543c8a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14009568015809481908140602390782892956953338087968540140168992024338795395215 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.14009568015809481908140602390782892956953338087968540140168992024338795395215
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.55625644264316530051456619966034448961554521532493640589011569080321155365501
Short name T624
Test name
Test status
Simulation time 17273552054 ps
CPU time 392.47 seconds
Started Nov 22 01:12:55 PM PST 23
Finished Nov 22 01:19:32 PM PST 23
Peak memory 247488 kb
Host smart-7de63994-7614-4c39-9481-f666a390d047
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55625644264316530051456619966034448961554521532493640589011569080321155365501 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.55625644264316530051456619966034448961554521532493640589011569080321155365501
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.60817505084423679163172577561903935406740018203812582275089613735340305739966
Short name T643
Test name
Test status
Simulation time 1399732617 ps
CPU time 52.25 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:49 PM PST 23
Peak memory 255452 kb
Host smart-62a56c95-4e0c-44ed-b07b-154b6a1a6ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60817
505084423679163172577561903935406740018203812582275089613735340305739966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.alert_handler_random_alerts.60817505084423679163172577561903935406740018203812582275089613735340305739966
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.69419720553738304696701399678356828380701071843865214560629771284008826458191
Short name T319
Test name
Test status
Simulation time 1291269199 ps
CPU time 49.55 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:13:44 PM PST 23
Peak memory 254856 kb
Host smart-a8594c70-af2c-4ba0-9fa6-16d35cd6277f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69419
720553738304696701399678356828380701071843865214560629771284008826458191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.alert_handler_random_classes.69419720553738304696701399678356828380701071843865214560629771284008826458191
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.68089590774509000728507886598635957180647919871849175742824284700542882004837
Short name T263
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.83 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 01:13:29 PM PST 23
Peak memory 255556 kb
Host smart-fe79723e-f7fe-4801-9736-8d895a85c2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68089
590774509000728507886598635957180647919871849175742824284700542882004837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
alert_handler_sig_int_fail.68089590774509000728507886598635957180647919871849175742824284700542882004837
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.75743252257262043068340751774898832612969611560893786442155525718422778433807
Short name T340
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.1 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:13:48 PM PST 23
Peak memory 248852 kb
Host smart-27b5d5ed-d835-447f-a6ee-c4deaa90f037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75743
252257262043068340751774898832612969611560893786442155525718422778433807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_h
andler_smoke.75743252257262043068340751774898832612969611560893786442155525718422778433807
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.39151162203588528278628327782983793198299406525712851564137985130978798562667
Short name T360
Test name
Test status
Simulation time 63383433172 ps
CPU time 2035.04 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:46:47 PM PST 23
Peak memory 289740 kb
Host smart-107b2ff4-8aa5-4a76-91c7-45e889f889e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39151162203588528278628327782983793198299406525712851564137985130978798562667 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.39151162203588528278628327782983793198299406525712851564137985
130978798562667
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.47797552099930172585731175361174891711578694456457030643950616836676393402978
Short name T309
Test name
Test status
Simulation time 79866015596 ps
CPU time 2734.66 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:58:33 PM PST 23
Peak memory 298128 kb
Host smart-ef307be4-7002-41fa-abcb-78da23d97b2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477975520999301725857311753611748917115786944564
57030643950616836676393402978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.47797552
099930172585731175361174891711578694456457030643950616836676393402978
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.27091863987207273639599034654274178085884480989157129721494035157328106901069
Short name T114
Test name
Test status
Simulation time 49707703 ps
CPU time 3.04 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:02 PM PST 23
Peak memory 248956 kb
Host smart-c6a42c58-cbeb-44a0-bb23-cff119c27b99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=27091863987207273639599034654274178085884480989157129721494035157328106901069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.alert_handler_alert_accum_saturation.27091863987207273639599034654274178085884480989157129721494035157328106901069
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.41284404263041389714590398515279934525228967676460729835415125914417660868343
Short name T602
Test name
Test status
Simulation time 30823729350 ps
CPU time 1060.01 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:30:33 PM PST 23
Peak memory 272448 kb
Host smart-c95edbd4-ca8a-44f5-a361-bdfa73832313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41284404263041389714590398515279934525228967676460729835415125914417660868343 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.alert_handler_entropy.41284404263041389714590398515279934525228967676460729835415125914417660868343
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.18717020244509489174081787219864931640828160355123310953318105950653959221607
Short name T42
Test name
Test status
Simulation time 1452482195 ps
CPU time 35.76 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:13:27 PM PST 23
Peak memory 240608 kb
Host smart-636a32a4-92f8-46cd-9e1a-d6da1ed02a57
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=18717020244509489174081787219864931640828160355123310953318105950653959221607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.alert_handler_entropy_stress.18717020244509489174081787219864931640828160355123310953318105950653959221607
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.112749794976865602356307766851980802874538335607469048170612862263590473881450
Short name T55
Test name
Test status
Simulation time 6994902141 ps
CPU time 230.12 seconds
Started Nov 22 01:12:55 PM PST 23
Finished Nov 22 01:16:49 PM PST 23
Peak memory 251132 kb
Host smart-6ddb39d8-1a94-4972-b367-0a562f3b8b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11274
9794976865602356307766851980802874538335607469048170612862263590473881450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.alert_handler_esc_alert_accum.112749794976865602356307766851980802874538335607469048170612862263590473881450
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.26252483547116348040759305899084928276037434266586728560741662717025486905982
Short name T422
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.91 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 01:13:33 PM PST 23
Peak memory 255660 kb
Host smart-c6b2a88f-7470-43f7-a097-816a98ea4c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26252
483547116348040759305899084928276037434266586728560741662717025486905982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.alert_handler_esc_intr_timeout.26252483547116348040759305899084928276037434266586728560741662717025486905982
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.81708877841250100264032038789736088804306649787321790397261833238999390882439
Short name T186
Test name
Test status
Simulation time 58351884139 ps
CPU time 1831.14 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:43:20 PM PST 23
Peak memory 289320 kb
Host smart-54fc6d2f-27a3-4103-a228-f185904f0ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81708877841250100264032038789736088804306649787321790397261833238999390882439 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.alert_handler_lpg.81708877841250100264032038789736088804306649787321790397261833238999390882439
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.16262919988545676971807612486557511039988288963356072435281944920838082433057
Short name T679
Test name
Test status
Simulation time 48172572717 ps
CPU time 1517.28 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 272444 kb
Host smart-79b15f0f-d827-4ddf-a68f-18b0ef3eb7b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16262919988545676971807612486557511039988288963356072435281944920838082433057 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.16262919988545676971807612486557511039988288963356072435281944920838082433057
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.91861475743956168589621277575564880803079451298325174997620460010196830418684
Short name T310
Test name
Test status
Simulation time 17273552054 ps
CPU time 391.32 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:19:29 PM PST 23
Peak memory 247476 kb
Host smart-4b3efcc0-217c-4a39-a593-a6b85254bed2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91861475743956168589621277575564880803079451298325174997620460010196830418684 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.91861475743956168589621277575564880803079451298325174997620460010196830418684
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.27540743764869960133795580710012279608136684959066451957406075710533977792863
Short name T242
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.85 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:45 PM PST 23
Peak memory 255408 kb
Host smart-ce5a3663-085a-4ba3-9aa3-481e38dc267d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27540
743764869960133795580710012279608136684959066451957406075710533977792863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.alert_handler_random_alerts.27540743764869960133795580710012279608136684959066451957406075710533977792863
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.68675060687648506019078361670525030427623025426396125410812044986879907658728
Short name T532
Test name
Test status
Simulation time 1291269199 ps
CPU time 47.76 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:46 PM PST 23
Peak memory 254432 kb
Host smart-40efd0fc-c215-48be-90a0-740f0acb1a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68675
060687648506019078361670525030427623025426396125410812044986879907658728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.alert_handler_random_classes.68675060687648506019078361670525030427623025426396125410812044986879907658728
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.43902555079058542687900446629999875728864908565902739293264311103877232741981
Short name T161
Test name
Test status
Simulation time 1261680150 ps
CPU time 49.28 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:48 PM PST 23
Peak memory 255480 kb
Host smart-b82a6b12-7161-4adb-8e48-990fc973d449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43902
555079058542687900446629999875728864908565902739293264311103877232741981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
alert_handler_sig_int_fail.43902555079058542687900446629999875728864908565902739293264311103877232741981
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.5393364530133932024279627287427085495239260443642453502537259482827147487820
Short name T225
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.16 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:13:42 PM PST 23
Peak memory 248864 kb
Host smart-6d839af0-1654-48f8-891d-3fe31edc0e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53933
64530133932024279627287427085495239260443642453502537259482827147487820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_smoke.5393364530133932024279627287427085495239260443642453502537259482827147487820
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.24875014340605800041656488009773411428834023711350634659039265634941294861210
Short name T199
Test name
Test status
Simulation time 63383433172 ps
CPU time 2033.05 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:46:42 PM PST 23
Peak memory 289572 kb
Host smart-3236fb4c-24e0-4d36-b386-993f60db76e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875014340605800041656488009773411428834023711350634659039265634941294861210 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.24875014340605800041656488009773411428834023711350634659039265
634941294861210
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.22127184887086450157569499828116843187279790165653546709716720250001606511141
Short name T539
Test name
Test status
Simulation time 79866015596 ps
CPU time 2802.35 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:59:41 PM PST 23
Peak memory 297544 kb
Host smart-da5660ba-213a-43ac-8757-d3e8e483dffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221271848870864501575694998281168431872797901656
53546709716720250001606511141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.22127184
887086450157569499828116843187279790165653546709716720250001606511141
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.62191141331389278752672665726414733764869097313920273498449395217129930235213
Short name T671
Test name
Test status
Simulation time 49707703 ps
CPU time 3.06 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:01 PM PST 23
Peak memory 248948 kb
Host smart-5b7e3563-3676-48a8-b863-4c0ac4061450
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=62191141331389278752672665726414733764869097313920273498449395217129930235213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.alert_handler_alert_accum_saturation.62191141331389278752672665726414733764869097313920273498449395217129930235213
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.93238500240159679297670706390211231403497567943368239385874237266598007105074
Short name T370
Test name
Test status
Simulation time 30823729350 ps
CPU time 1104.83 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:31:23 PM PST 23
Peak memory 272400 kb
Host smart-cbf75625-0279-492b-9685-0d91249575dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93238500240159679297670706390211231403497567943368239385874237266598007105074 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.alert_handler_entropy.93238500240159679297670706390211231403497567943368239385874237266598007105074
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.29082838054831587149806111482258895658818269952523122014238825279963361061345
Short name T113
Test name
Test status
Simulation time 1452482195 ps
CPU time 36.25 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:13:25 PM PST 23
Peak memory 240640 kb
Host smart-c8944f14-3ad4-484c-a5d0-5d3cde02f499
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=29082838054831587149806111482258895658818269952523122014238825279963361061345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.alert_handler_entropy_stress.29082838054831587149806111482258895658818269952523122014238825279963361061345
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.82789429351202956067297035016652489206826493009265581540194193657219048447324
Short name T215
Test name
Test status
Simulation time 6994902141 ps
CPU time 236.34 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:16:46 PM PST 23
Peak memory 251056 kb
Host smart-399bf514-0f1c-4e98-ad11-bbc280f70fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82789
429351202956067297035016652489206826493009265581540194193657219048447324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.alert_handler_esc_alert_accum.82789429351202956067297035016652489206826493009265581540194193657219048447324
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.42150719652467846791149382675912140244974691132082871348309639509455524114263
Short name T293
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.29 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:48 PM PST 23
Peak memory 255596 kb
Host smart-d3fc34d6-1701-447c-b14e-7281dd6b39f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42150
719652467846791149382675912140244974691132082871348309639509455524114263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.alert_handler_esc_intr_timeout.42150719652467846791149382675912140244974691132082871348309639509455524114263
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.96922683749111701972727621574269997334430661292302484474259604436905950310773
Short name T152
Test name
Test status
Simulation time 58351884139 ps
CPU time 1868.44 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:44:04 PM PST 23
Peak memory 289316 kb
Host smart-89d76d2c-273b-4560-a3f7-0568c4c8cd03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96922683749111701972727621574269997334430661292302484474259604436905950310773 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.alert_handler_lpg.96922683749111701972727621574269997334430661292302484474259604436905950310773
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.39852009023323356713196564280131714205153994313353988247902980820922897511094
Short name T435
Test name
Test status
Simulation time 48172572717 ps
CPU time 1540 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:38:39 PM PST 23
Peak memory 272104 kb
Host smart-98313822-a9ca-468a-8192-8ab4707036ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39852009023323356713196564280131714205153994313353988247902980820922897511094 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.39852009023323356713196564280131714205153994313353988247902980820922897511094
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.7309494423877065063835149308646594758793282048369822504704605729309939320304
Short name T154
Test name
Test status
Simulation time 17273552054 ps
CPU time 390.95 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:19:23 PM PST 23
Peak memory 247500 kb
Host smart-ed2912b0-bd75-4784-bf52-6dba9252184e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7309494423877065063835149308646594758793282048369822504704605729309939320304 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.7309494423877065063835149308646594758793282048369822504704605729309939320304
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.22881288198447615654982287266757203197730092166849239968707195682069587724207
Short name T344
Test name
Test status
Simulation time 1399732617 ps
CPU time 46.82 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:13:36 PM PST 23
Peak memory 255496 kb
Host smart-e5c1904c-4b1a-4319-8112-702e8c478eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881
288198447615654982287266757203197730092166849239968707195682069587724207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.alert_handler_random_alerts.22881288198447615654982287266757203197730092166849239968707195682069587724207
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.89467566791525224532476053620358323665693759830660483162045148489143789700231
Short name T543
Test name
Test status
Simulation time 1291269199 ps
CPU time 47.62 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:45 PM PST 23
Peak memory 254796 kb
Host smart-08f1ce7d-ab5a-49ba-9170-e5e28000dfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89467
566791525224532476053620358323665693759830660483162045148489143789700231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.alert_handler_random_classes.89467566791525224532476053620358323665693759830660483162045148489143789700231
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.60040140104236411984642453604561159804772335736121197496726665651719981864073
Short name T267
Test name
Test status
Simulation time 1261680150 ps
CPU time 47.85 seconds
Started Nov 22 01:12:55 PM PST 23
Finished Nov 22 01:13:47 PM PST 23
Peak memory 255392 kb
Host smart-d5c412b2-3af7-4a89-bd15-1acc9133ca1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60040
140104236411984642453604561159804772335736121197496726665651719981864073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
alert_handler_sig_int_fail.60040140104236411984642453604561159804772335736121197496726665651719981864073
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.82385816341183453143196111825257520396756726873639464644369743200397917197213
Short name T472
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.02 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:13:42 PM PST 23
Peak memory 248656 kb
Host smart-3d3d5c1f-763e-49f6-9b0b-10df1bfa44f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82385
816341183453143196111825257520396756726873639464644369743200397917197213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_h
andler_smoke.82385816341183453143196111825257520396756726873639464644369743200397917197213
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.52912419828292473382015618427474056971343712962977760991217343661191022721325
Short name T610
Test name
Test status
Simulation time 63383433172 ps
CPU time 2012.73 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:46:21 PM PST 23
Peak memory 289792 kb
Host smart-771e6747-64aa-444c-958d-b62c8a233677
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52912419828292473382015618427474056971343712962977760991217343661191022721325 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.52912419828292473382015618427474056971343712962977760991217343
661191022721325
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.57374341454543723142662069686923834162665227883658422690636229352595641692459
Short name T70
Test name
Test status
Simulation time 79866015596 ps
CPU time 2771.36 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:59:07 PM PST 23
Peak memory 298116 kb
Host smart-33d5d089-0ee9-4d0a-9032-40588715e217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573743414545437231426620696869238341626652278836
58422690636229352595641692459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.57374341
454543723142662069686923834162665227883658422690636229352595641692459
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.113570499848379175688104384118443452283376664798725706991782643116884156082115
Short name T116
Test name
Test status
Simulation time 49707703 ps
CPU time 2.88 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:00 PM PST 23
Peak memory 248780 kb
Host smart-245cedbc-20b5-41a7-a1b7-8bcef2eb22b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=113570499848379175688104384118443452283376664798725706991782643116884156082115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.alert_handler_alert_accum_saturation.113570499848379175688104384118443452283376664798725706991782643116884156082115
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.23043235213647022464370217099558626980121998385046260294363397396736024984002
Short name T466
Test name
Test status
Simulation time 30823729350 ps
CPU time 1080.68 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:30:53 PM PST 23
Peak memory 272448 kb
Host smart-4b53806d-f87e-4aa5-8d5a-c14581d2a837
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23043235213647022464370217099558626980121998385046260294363397396736024984002 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.alert_handler_entropy.23043235213647022464370217099558626980121998385046260294363397396736024984002
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.66313163611004485331756290493124567267805973363556721968842237966437136615943
Short name T477
Test name
Test status
Simulation time 1452482195 ps
CPU time 35.27 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:32 PM PST 23
Peak memory 240416 kb
Host smart-d2682c87-01e2-4953-a978-8c1b09ce569c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=66313163611004485331756290493124567267805973363556721968842237966437136615943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.alert_handler_entropy_stress.66313163611004485331756290493124567267805973363556721968842237966437136615943
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.101167856496204400585549291601361176926774120129727872255149168703759520176234
Short name T670
Test name
Test status
Simulation time 6994902141 ps
CPU time 237.25 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 250604 kb
Host smart-ff85d48b-9e3a-4f26-9d36-e4d42429fe42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10116
7856496204400585549291601361176926774120129727872255149168703759520176234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.alert_handler_esc_alert_accum.101167856496204400585549291601361176926774120129727872255149168703759520176234
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.113729226039402867594823502111844575346261948824645384126664416810686921524467
Short name T401
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.55 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:46 PM PST 23
Peak memory 256152 kb
Host smart-09aed629-6de2-44ef-b0d5-3dad6d55ec79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11372
9226039402867594823502111844575346261948824645384126664416810686921524467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.alert_handler_esc_intr_timeout.113729226039402867594823502111844575346261948824645384126664416810686921524467
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.57065333384850248669166452760796136862984866888953819302175425206003644773073
Short name T151
Test name
Test status
Simulation time 58351884139 ps
CPU time 1852.91 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:43:50 PM PST 23
Peak memory 289092 kb
Host smart-834e6340-cf8f-4ec5-9d7f-fdbef1ae1b0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57065333384850248669166452760796136862984866888953819302175425206003644773073 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.alert_handler_lpg.57065333384850248669166452760796136862984866888953819302175425206003644773073
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.80848587947331213899524134685880822443670943697084917835033961245155418117042
Short name T536
Test name
Test status
Simulation time 48172572717 ps
CPU time 1583.7 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 272516 kb
Host smart-8269c90a-ae9e-4449-b1ad-fb956ab5e1ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80848587947331213899524134685880822443670943697084917835033961245155418117042 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.80848587947331213899524134685880822443670943697084917835033961245155418117042
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.31242833780520054307273511339087854714539899926490640052747298385081434263123
Short name T664
Test name
Test status
Simulation time 17273552054 ps
CPU time 389.6 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:19:21 PM PST 23
Peak memory 247500 kb
Host smart-a96f8539-07e3-4571-8e47-3e2f76a01c52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31242833780520054307273511339087854714539899926490640052747298385081434263123 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.31242833780520054307273511339087854714539899926490640052747298385081434263123
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.103839635336050508061723318069659697876843836846673427144601977631774759521739
Short name T574
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.18 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:45 PM PST 23
Peak memory 255412 kb
Host smart-bc39bbeb-043f-46b8-9411-950323f5fd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10383
9635336050508061723318069659697876843836846673427144601977631774759521739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.alert_handler_random_alerts.103839635336050508061723318069659697876843836846673427144601977631774759521739
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.33914913559761732951379203485548820339670521776693934377586946593500714186191
Short name T438
Test name
Test status
Simulation time 1291269199 ps
CPU time 48.71 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:45 PM PST 23
Peak memory 254856 kb
Host smart-0e3aa8ec-75c4-4dc9-9984-d2debbe7f5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33914
913559761732951379203485548820339670521776693934377586946593500714186191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.alert_handler_random_classes.33914913559761732951379203485548820339670521776693934377586946593500714186191
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.82845653855235183290796735845084677149581712035130151777340746400751393072259
Short name T397
Test name
Test status
Simulation time 1261680150 ps
CPU time 52.27 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:49 PM PST 23
Peak memory 255544 kb
Host smart-f382c420-dedd-444f-8eb1-cd0ef82e8ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82845
653855235183290796735845084677149581712035130151777340746400751393072259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
alert_handler_sig_int_fail.82845653855235183290796735845084677149581712035130151777340746400751393072259
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.30981679669651144722412465043945390311974717171311306586349105242935625106209
Short name T337
Test name
Test status
Simulation time 1558784916 ps
CPU time 54.48 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:52 PM PST 23
Peak memory 248784 kb
Host smart-90d0089b-ec5e-4365-b0dc-1b1aa6e55334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30981
679669651144722412465043945390311974717171311306586349105242935625106209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_h
andler_smoke.30981679669651144722412465043945390311974717171311306586349105242935625106209
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.94562537474708439845972500936348809028119409587743909133118218530742328704084
Short name T411
Test name
Test status
Simulation time 63383433172 ps
CPU time 2017.01 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:46:33 PM PST 23
Peak memory 289608 kb
Host smart-08c83058-44a5-486d-85b6-1336f1c118da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94562537474708439845972500936348809028119409587743909133118218530742328704084 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.94562537474708439845972500936348809028119409587743909133118218
530742328704084
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.55936895498246931734098904465429495444636258934871611273232546474121510854377
Short name T25
Test name
Test status
Simulation time 79866015596 ps
CPU time 2869.53 seconds
Started Nov 22 01:12:37 PM PST 23
Finished Nov 22 02:00:34 PM PST 23
Peak memory 298196 kb
Host smart-0df5ab93-1b95-427c-bcb4-97038ae7f707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559368954982469317340989044654294954446362589348
71611273232546474121510854377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.55936895
498246931734098904465429495444636258934871611273232546474121510854377
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.85736064612788200836833849139429061363526395162334618119720795711244002431371
Short name T592
Test name
Test status
Simulation time 49707703 ps
CPU time 2.74 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:12:57 PM PST 23
Peak memory 248804 kb
Host smart-bb7f73ea-7ad0-4a41-b251-a0af09cb9a04
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=85736064612788200836833849139429061363526395162334618119720795711244002431371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.alert_handler_alert_accum_saturation.85736064612788200836833849139429061363526395162334618119720795711244002431371
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.45091730869982914009072121848596961772330572523218365874351698996457777605750
Short name T273
Test name
Test status
Simulation time 30823729350 ps
CPU time 1058.84 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:30:35 PM PST 23
Peak memory 272316 kb
Host smart-e5f3b9a1-c40d-46ab-be67-ef2c5a041945
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45091730869982914009072121848596961772330572523218365874351698996457777605750 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.alert_handler_entropy.45091730869982914009072121848596961772330572523218365874351698996457777605750
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.74095440910402792560166690986830558746817962152654978314266084067503789860190
Short name T348
Test name
Test status
Simulation time 1452482195 ps
CPU time 34.65 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:31 PM PST 23
Peak memory 240472 kb
Host smart-86cf00e6-ca10-4d62-8893-90c9cf8260ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=74095440910402792560166690986830558746817962152654978314266084067503789860190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.alert_handler_entropy_stress.74095440910402792560166690986830558746817962152654978314266084067503789860190
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.39476077141689293091494338104017644830925929488992880107233643555489682120183
Short name T280
Test name
Test status
Simulation time 6994902141 ps
CPU time 232.24 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:16:48 PM PST 23
Peak memory 251084 kb
Host smart-47bef8e4-db87-4821-9064-8b904da31e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39476
077141689293091494338104017644830925929488992880107233643555489682120183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.alert_handler_esc_alert_accum.39476077141689293091494338104017644830925929488992880107233643555489682120183
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.6102815526502018041368704111583568007154084113379839009803816775741673946616
Short name T446
Test name
Test status
Simulation time 1449142936 ps
CPU time 50.48 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:13:46 PM PST 23
Peak memory 255500 kb
Host smart-1753146b-0ac9-4824-bdc8-35f586c60900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61028
15526502018041368704111583568007154084113379839009803816775741673946616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.alert_handler_esc_intr_timeout.6102815526502018041368704111583568007154084113379839009803816775741673946616
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.51045198517605174276548109236348159605104166231774929490771398533700686381476
Short name T374
Test name
Test status
Simulation time 58351884139 ps
CPU time 1789.91 seconds
Started Nov 22 01:12:40 PM PST 23
Finished Nov 22 01:42:36 PM PST 23
Peak memory 289316 kb
Host smart-42fc556a-8c47-48dd-906a-92da14e827d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51045198517605174276548109236348159605104166231774929490771398533700686381476 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.alert_handler_lpg.51045198517605174276548109236348159605104166231774929490771398533700686381476
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.78803187311939828440929652710438158634057300999257371113716066309296011062671
Short name T383
Test name
Test status
Simulation time 48172572717 ps
CPU time 1531.19 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 272348 kb
Host smart-1bbf62bf-e0eb-43a7-b77f-8a3e1631338f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78803187311939828440929652710438158634057300999257371113716066309296011062671 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.78803187311939828440929652710438158634057300999257371113716066309296011062671
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.44201655057391538967002289045221248073049148260307575883785166138447624336908
Short name T329
Test name
Test status
Simulation time 17273552054 ps
CPU time 381.77 seconds
Started Nov 22 01:12:51 PM PST 23
Finished Nov 22 01:19:16 PM PST 23
Peak memory 247356 kb
Host smart-a29d957a-a77c-4b3e-ad5c-9050328bdef5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44201655057391538967002289045221248073049148260307575883785166138447624336908 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.44201655057391538967002289045221248073049148260307575883785166138447624336908
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.43114823186230701384190826807043443277238397987250523359985703618329881735351
Short name T586
Test name
Test status
Simulation time 1399732617 ps
CPU time 45.53 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:41 PM PST 23
Peak memory 255312 kb
Host smart-817fd8f9-afb6-47cd-bffc-361e722452b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43114
823186230701384190826807043443277238397987250523359985703618329881735351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.alert_handler_random_alerts.43114823186230701384190826807043443277238397987250523359985703618329881735351
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.7455220811545778810707964209370733427657414624779179087488786481954794696071
Short name T306
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.55 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:41 PM PST 23
Peak memory 254316 kb
Host smart-cc05b7db-3a16-4970-9fc1-9f3cb5c793e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74552
20811545778810707964209370733427657414624779179087488786481954794696071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.alert_handler_random_classes.7455220811545778810707964209370733427657414624779179087488786481954794696071
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.58115365902746635609419099609503174254447026877403260235344322521024017769447
Short name T52
Test name
Test status
Simulation time 1261680150 ps
CPU time 46.81 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:45 PM PST 23
Peak memory 255316 kb
Host smart-d0d851d1-7b17-443d-914e-8019ab1ec319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58115
365902746635609419099609503174254447026877403260235344322521024017769447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
alert_handler_sig_int_fail.58115365902746635609419099609503174254447026877403260235344322521024017769447
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.111337199687974952283895314169681309192147730529431732859882756347766674430124
Short name T693
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.32 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:49 PM PST 23
Peak memory 248616 kb
Host smart-43ea5376-316b-45df-a415-b4d11d29b176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11133
7199687974952283895314169681309192147730529431732859882756347766674430124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_
handler_smoke.111337199687974952283895314169681309192147730529431732859882756347766674430124
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.74892147961376407440605297263033915028824985229389753507660409813866135085693
Short name T325
Test name
Test status
Simulation time 63383433172 ps
CPU time 2077.16 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:47:33 PM PST 23
Peak memory 289584 kb
Host smart-612d9298-b04f-4258-8199-ad767e891a1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74892147961376407440605297263033915028824985229389753507660409813866135085693 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.74892147961376407440605297263033915028824985229389753507660409
813866135085693
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.86666390525394166307807827802092613593572729412806348553271446013201615121030
Short name T177
Test name
Test status
Simulation time 79866015596 ps
CPU time 2710.35 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:58:06 PM PST 23
Peak memory 298024 kb
Host smart-3b9082d6-66f2-44c1-88d4-e9a2b8c88393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866663905253941663078078278020926135935727294128
06348553271446013201615121030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.86666390
525394166307807827802092613593572729412806348553271446013201615121030
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.17434618456094051335601194020785395065363332312743100970310339134156561888746
Short name T120
Test name
Test status
Simulation time 49707703 ps
CPU time 3 seconds
Started Nov 22 01:12:46 PM PST 23
Finished Nov 22 01:12:53 PM PST 23
Peak memory 248996 kb
Host smart-016f2ebd-41ba-49c1-8f32-7b28f587b563
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=17434618456094051335601194020785395065363332312743100970310339134156561888746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.alert_handler_alert_accum_saturation.17434618456094051335601194020785395065363332312743100970310339134156561888746
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.114687138614566455537913323309467021952865684725316528327768614227978429925592
Short name T176
Test name
Test status
Simulation time 30823729350 ps
CPU time 1117.26 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:31:29 PM PST 23
Peak memory 272448 kb
Host smart-fe8dfe19-7cd8-4ddd-93ff-8ffdc278bd2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114687138614566455537913323309467021952865684725316528327768614227978429925592 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.alert_handler_entropy.114687138614566455537913323309467021952865684725316528327768614227978429925592
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.35910662220972505050006098968499935998395680592847343017164176548334350842184
Short name T456
Test name
Test status
Simulation time 1452482195 ps
CPU time 35.31 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:13:24 PM PST 23
Peak memory 240596 kb
Host smart-5a711903-9baa-400f-af09-1b351947bbb5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=35910662220972505050006098968499935998395680592847343017164176548334350842184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.alert_handler_entropy_stress.35910662220972505050006098968499935998395680592847343017164176548334350842184
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.84846071938184714632620179785063935079541660050945317977599862654827538586293
Short name T529
Test name
Test status
Simulation time 6994902141 ps
CPU time 232.73 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:16:48 PM PST 23
Peak memory 251084 kb
Host smart-dab5a8b4-1898-4b45-a3e9-4d48a4598a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84846
071938184714632620179785063935079541660050945317977599862654827538586293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.alert_handler_esc_alert_accum.84846071938184714632620179785063935079541660050945317977599862654827538586293
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.44540905089069814263453064117898686310499687594182324611759542806005646587078
Short name T316
Test name
Test status
Simulation time 1449142936 ps
CPU time 52.44 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:50 PM PST 23
Peak memory 255648 kb
Host smart-bc9c19c8-216e-42c3-831e-7801466fb1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44540
905089069814263453064117898686310499687594182324611759542806005646587078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.alert_handler_esc_intr_timeout.44540905089069814263453064117898686310499687594182324611759542806005646587078
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.69081529054606696276687318947161761760235697011081276006133675148862360272997
Short name T595
Test name
Test status
Simulation time 58351884139 ps
CPU time 1835.27 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:43:38 PM PST 23
Peak memory 289128 kb
Host smart-d1a85810-7df1-4df1-ae5a-07123cb825a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69081529054606696276687318947161761760235697011081276006133675148862360272997 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.alert_handler_lpg.69081529054606696276687318947161761760235697011081276006133675148862360272997
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.62135535445731872085032917122202246812723384731134678717742795929617588999356
Short name T609
Test name
Test status
Simulation time 48172572717 ps
CPU time 1547.08 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:38:51 PM PST 23
Peak memory 272332 kb
Host smart-c2d604f6-26e8-4bb5-9ef6-184573043da6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62135535445731872085032917122202246812723384731134678717742795929617588999356 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.62135535445731872085032917122202246812723384731134678717742795929617588999356
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.71008232932625365446147823362784881314778172079427699677055443942592942247591
Short name T625
Test name
Test status
Simulation time 17273552054 ps
CPU time 381.9 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:19:26 PM PST 23
Peak memory 247372 kb
Host smart-f6eb4cf8-fca9-4b05-996f-53593f9413eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71008232932625365446147823362784881314778172079427699677055443942592942247591 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.71008232932625365446147823362784881314778172079427699677055443942592942247591
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.91129427168016164480054878307078333690868187984109076301456977300068555967697
Short name T589
Test name
Test status
Simulation time 1399732617 ps
CPU time 50.94 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:48 PM PST 23
Peak memory 255316 kb
Host smart-7c00e3fe-2324-4065-908d-240e5662f9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91129
427168016164480054878307078333690868187984109076301456977300068555967697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.alert_handler_random_alerts.91129427168016164480054878307078333690868187984109076301456977300068555967697
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.26790601708266935531275324866811405692541591153516459082697277691697734575544
Short name T533
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.86 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:13:40 PM PST 23
Peak memory 254696 kb
Host smart-685ede2e-9ec7-4985-a6f6-38d80c81e857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26790
601708266935531275324866811405692541591153516459082697277691697734575544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.alert_handler_random_classes.26790601708266935531275324866811405692541591153516459082697277691697734575544
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.52134720646371527024674399992990176040223520993255389214820419232125395813676
Short name T649
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.6 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:13:40 PM PST 23
Peak memory 255360 kb
Host smart-3592f472-8fc8-4ff5-8287-29c906a28684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52134
720646371527024674399992990176040223520993255389214820419232125395813676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
alert_handler_sig_int_fail.52134720646371527024674399992990176040223520993255389214820419232125395813676
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.38563060902055201571324097349755513934867719364643846083152941209564046961833
Short name T612
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.38 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:50 PM PST 23
Peak memory 248668 kb
Host smart-4279fbf7-6418-4995-8f89-78095d45b907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38563
060902055201571324097349755513934867719364643846083152941209564046961833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_h
andler_smoke.38563060902055201571324097349755513934867719364643846083152941209564046961833
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.15233116560544506801677898336056600542343003795615357560024948733738628065417
Short name T480
Test name
Test status
Simulation time 63383433172 ps
CPU time 2064.35 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:47:29 PM PST 23
Peak memory 289576 kb
Host smart-47848309-c7f3-43d4-9bea-319c22d62e6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233116560544506801677898336056600542343003795615357560024948733738628065417 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.15233116560544506801677898336056600542343003795615357560024948
733738628065417
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.36540099385605714654719020568211236388094793257108100628179572641679422007264
Short name T67
Test name
Test status
Simulation time 79866015596 ps
CPU time 2771.79 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:59:14 PM PST 23
Peak memory 298024 kb
Host smart-54de9d05-6c71-4293-8016-0b1c995bfe4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365400993856057146547190205682112363880947932571
08100628179572641679422007264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.36540099
385605714654719020568211236388094793257108100628179572641679422007264
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.104740281215196527278102096768104256419080846607381261330202418188108323675140
Short name T498
Test name
Test status
Simulation time 49707703 ps
CPU time 2.87 seconds
Started Nov 22 01:12:13 PM PST 23
Finished Nov 22 01:12:18 PM PST 23
Peak memory 249004 kb
Host smart-30597f3b-2fc5-4e6d-b87b-1340352ac35a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=104740281215196527278102096768104256419080846607381261330202418188108323675140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.alert_handler_alert_accum_saturation.104740281215196527278102096768104256419080846607381261330202418188108323675140
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.44243462668706290926575797354344092384579813414530628198068026375491791200767
Short name T211
Test name
Test status
Simulation time 30823729350 ps
CPU time 1092.08 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:30:21 PM PST 23
Peak memory 272284 kb
Host smart-7c4b8c2f-6826-43c4-a3db-b61fe9a9ff5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44243462668706290926575797354344092384579813414530628198068026375491791200767 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.alert_handler_entropy.44243462668706290926575797354344092384579813414530628198068026375491791200767
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.30517412661731833538396942369155242552252769767265151542283984112057629823911
Short name T339
Test name
Test status
Simulation time 1452482195 ps
CPU time 35.64 seconds
Started Nov 22 01:12:12 PM PST 23
Finished Nov 22 01:12:50 PM PST 23
Peak memory 240564 kb
Host smart-4da9a52c-eb7d-4385-9eff-ec4b8df9b024
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=30517412661731833538396942369155242552252769767265151542283984112057629823911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.alert_handler_entropy_stress.30517412661731833538396942369155242552252769767265151542283984112057629823911
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.91309849283355575885353297200194541958910390628792893691069481775451466508942
Short name T191
Test name
Test status
Simulation time 6994902141 ps
CPU time 238.92 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:16:08 PM PST 23
Peak memory 251132 kb
Host smart-cf1e7d25-0ea6-4f47-92ee-d7a9b3fd9ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91309
849283355575885353297200194541958910390628792893691069481775451466508942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.alert_handler_esc_alert_accum.91309849283355575885353297200194541958910390628792893691069481775451466508942
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.10481743164654692219728444437811865760785704555696335789960226165151711297515
Short name T402
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.17 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:58 PM PST 23
Peak memory 255528 kb
Host smart-ad6cbd6c-ff81-4cd5-8ed8-54033160c531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10481
743164654692219728444437811865760785704555696335789960226165151711297515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.alert_handler_esc_intr_timeout.10481743164654692219728444437811865760785704555696335789960226165151711297515
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.106755044293365064940049341559619857608044998144306338317113300127427841299900
Short name T601
Test name
Test status
Simulation time 58351884139 ps
CPU time 1825.8 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:42:38 PM PST 23
Peak memory 289292 kb
Host smart-f682ef4d-1131-43e3-a928-c64a4c94454b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106755044293365064940049341559619857608044998144306338317113300127427841299900 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.alert_handler_lpg.106755044293365064940049341559619857608044998144306338317113300127427841299900
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.70965192610849435073120228773519855019620086599591171647016830577811919047926
Short name T371
Test name
Test status
Simulation time 48172572717 ps
CPU time 1606.62 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:38:57 PM PST 23
Peak memory 272504 kb
Host smart-a432397f-2bcd-4e23-82fe-b07ccb671900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70965192610849435073120228773519855019620086599591171647016830577811919047926 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.70965192610849435073120228773519855019620086599591171647016830577811919047926
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.109537413237482397137075553312440083689263530413731542577214779773543852219870
Short name T47
Test name
Test status
Simulation time 17273552054 ps
CPU time 409.42 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 247544 kb
Host smart-00d23dde-ba82-4807-89a9-1f2bfedda75b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109537413237482397137075553312440083689263530413731542577214779773543852219870 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.109537413237482397137075553312440083689263530413731542577214779773543852219870
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.68775879264588693555653616829145572184461989796488418518124596433094838378064
Short name T44
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.08 seconds
Started Nov 22 01:12:14 PM PST 23
Finished Nov 22 01:13:04 PM PST 23
Peak memory 255488 kb
Host smart-647ffc55-633d-4ba2-82ed-d9cbf4f054fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68775
879264588693555653616829145572184461989796488418518124596433094838378064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
alert_handler_random_alerts.68775879264588693555653616829145572184461989796488418518124596433094838378064
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.114788893729286677316326825862492836215990370954873600641459477863280974240310
Short name T675
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.24 seconds
Started Nov 22 01:12:05 PM PST 23
Finished Nov 22 01:12:52 PM PST 23
Peak memory 254868 kb
Host smart-44598392-63c0-418e-b428-9b13a76b2133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
8893729286677316326825862492836215990370954873600641459477863280974240310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.alert_handler_random_classes.114788893729286677316326825862492836215990370954873600641459477863280974240310
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.21008885358899439264948387023456016636412886283216300156434898886952696894408
Short name T20
Test name
Test status
Simulation time 740845031 ps
CPU time 23.89 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:12:33 PM PST 23
Peak memory 274812 kb
Host smart-1148ee42-3fd9-4e26-88ab-77f265fdd975
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=21008885358899439264948387023456016636412886283216300156434898886952696894408 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.alert_handler_sec_cm.21008885358899439264948387023456016636412886283216300156434898886952696894408
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.40285368403875864741480329764733597486234777703659563973645585897312359972484
Short name T266
Test name
Test status
Simulation time 1261680150 ps
CPU time 41.12 seconds
Started Nov 22 01:12:16 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 255472 kb
Host smart-37f40b5e-9b38-4fec-8f3c-d3aa296c1b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40285
368403875864741480329764733597486234777703659563973645585897312359972484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
lert_handler_sig_int_fail.40285368403875864741480329764733597486234777703659563973645585897312359972484
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.50869946328032417012321657811846306748845178063159483673520329068993225682662
Short name T234
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.72 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:12:58 PM PST 23
Peak memory 248692 kb
Host smart-7ef9e439-0a6c-4ed0-a5b0-aa8f6c3c1655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50869
946328032417012321657811846306748845178063159483673520329068993225682662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_ha
ndler_smoke.50869946328032417012321657811846306748845178063159483673520329068993225682662
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.105334687867385430911136484596312460809922724844657336231482189336953731744815
Short name T554
Test name
Test status
Simulation time 63383433172 ps
CPU time 2084.1 seconds
Started Nov 22 01:12:13 PM PST 23
Finished Nov 22 01:47:00 PM PST 23
Peak memory 289784 kb
Host smart-a48a95c7-1ac9-4516-be36-7a207a340a17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105334687867385430911136484596312460809922724844657336231482189336953731744815 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.10533468786738543091113648459631246080992272484465733623148218
9336953731744815
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.48347077326080233691692461741537152524772087468866529418271420018844103729215
Short name T235
Test name
Test status
Simulation time 79866015596 ps
CPU time 2899.92 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 298088 kb
Host smart-3318b351-364f-4509-b538-ac7417de7488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483470773260802336916924617415371525247720874688
66529418271420018844103729215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.483470773
26080233691692461741537152524772087468866529418271420018844103729215
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.72574052809185962703929754128233932630591294025341500963066685049371331578303
Short name T167
Test name
Test status
Simulation time 30823729350 ps
CPU time 1030.45 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:30:09 PM PST 23
Peak memory 272284 kb
Host smart-45d10e63-68d0-461a-8d0e-88db309c6b90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72574052809185962703929754128233932630591294025341500963066685049371331578303 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.alert_handler_entropy.72574052809185962703929754128233932630591294025341500963066685049371331578303
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.114179157291361957487212713145738756949217345099038395598614975147530938128923
Short name T568
Test name
Test status
Simulation time 6994902141 ps
CPU time 228.36 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:16:46 PM PST 23
Peak memory 251068 kb
Host smart-bc23dda1-1f9d-46f8-8e85-c50bdd335c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11417
9157291361957487212713145738756949217345099038395598614975147530938128923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.alert_handler_esc_alert_accum.114179157291361957487212713145738756949217345099038395598614975147530938128923
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.50730024838370982914822693116637925128853408427530273500318155926645687055110
Short name T476
Test name
Test status
Simulation time 1449142936 ps
CPU time 46.69 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:44 PM PST 23
Peak memory 255488 kb
Host smart-391b201e-bbc3-43da-95a7-89f1cc27e0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50730
024838370982914822693116637925128853408427530273500318155926645687055110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.alert_handler_esc_intr_timeout.50730024838370982914822693116637925128853408427530273500318155926645687055110
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.85178271605461225523700662960810337039035089054018064727706743443213834553348
Short name T39
Test name
Test status
Simulation time 58351884139 ps
CPU time 1829.38 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 289292 kb
Host smart-29e6079d-d1fa-4684-bbe6-e11625c562c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85178271605461225523700662960810337039035089054018064727706743443213834553348 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.alert_handler_lpg.85178271605461225523700662960810337039035089054018064727706743443213834553348
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.37795103169868894357277876514329168916064393071150068183508601495717377280142
Short name T526
Test name
Test status
Simulation time 48172572717 ps
CPU time 1549.45 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:38:52 PM PST 23
Peak memory 272340 kb
Host smart-df73c0b7-f649-4ac3-b840-124b88210c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37795103169868894357277876514329168916064393071150068183508601495717377280142 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.37795103169868894357277876514329168916064393071150068183508601495717377280142
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.33459634686833405576517237544100574867548110679190305144358174141892460297968
Short name T228
Test name
Test status
Simulation time 17273552054 ps
CPU time 383.74 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 247384 kb
Host smart-f9da7fd4-73fe-4c51-bfd3-7e1b943e21ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33459634686833405576517237544100574867548110679190305144358174141892460297968 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.33459634686833405576517237544100574867548110679190305144358174141892460297968
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.70442773232987077970946337062955387328211270573226330465214314523927779236903
Short name T635
Test name
Test status
Simulation time 1399732617 ps
CPU time 51.5 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:49 PM PST 23
Peak memory 255484 kb
Host smart-8cb0072c-b974-43d8-8ba3-f7c369a9bd5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70442
773232987077970946337062955387328211270573226330465214314523927779236903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.alert_handler_random_alerts.70442773232987077970946337062955387328211270573226330465214314523927779236903
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.20136933407086605154989156237192626507853989380676691481880421761376071307693
Short name T262
Test name
Test status
Simulation time 1291269199 ps
CPU time 49.51 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:13:52 PM PST 23
Peak memory 254676 kb
Host smart-c6af171a-78aa-4c5e-b39e-04289ed43000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20136
933407086605154989156237192626507853989380676691481880421761376071307693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.alert_handler_random_classes.20136933407086605154989156237192626507853989380676691481880421761376071307693
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.96128235620063457419508228393398211973500536889811101959783299791994174500001
Short name T487
Test name
Test status
Simulation time 1261680150 ps
CPU time 43.36 seconds
Started Nov 22 01:12:45 PM PST 23
Finished Nov 22 01:13:33 PM PST 23
Peak memory 255428 kb
Host smart-8e1e4a7d-911b-4d5e-b689-a41024cbc022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96128
235620063457419508228393398211973500536889811101959783299791994174500001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
alert_handler_sig_int_fail.96128235620063457419508228393398211973500536889811101959783299791994174500001
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.112265741845496839178545776441579188402573179152779541840328309610054200720600
Short name T81
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.96 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:13:50 PM PST 23
Peak memory 248672 kb
Host smart-24e925b5-cad2-4e8b-bc6f-f1c56a83b1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11226
5741845496839178545776441579188402573179152779541840328309610054200720600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_
handler_smoke.112265741845496839178545776441579188402573179152779541840328309610054200720600
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.107840766564562830808942478146683634596559182631089441895670393885892313506251
Short name T433
Test name
Test status
Simulation time 63383433172 ps
CPU time 2046.85 seconds
Started Nov 22 01:12:47 PM PST 23
Finished Nov 22 01:46:57 PM PST 23
Peak memory 289752 kb
Host smart-5c06f368-a0de-48eb-abeb-d7d73fb93028
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107840766564562830808942478146683634596559182631089441895670393885892313506251 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.1078407665645628308089424781466836345965591826310894418956703
93885892313506251
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.33287885273098367350859243884762982504470396115405827629414702596203758615245
Short name T423
Test name
Test status
Simulation time 79866015596 ps
CPU time 2744.93 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:58:48 PM PST 23
Peak memory 298012 kb
Host smart-734435a8-99ab-4801-ad6d-1ecf6eadec8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332878852730983673508592438847629825044703961154
05827629414702596203758615245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.33287885
273098367350859243884762982504470396115405827629414702596203758615245
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.59499760831557501748945791409351419349566455012757383351126424916718854330375
Short name T628
Test name
Test status
Simulation time 30823729350 ps
CPU time 1168.09 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:32:31 PM PST 23
Peak memory 272440 kb
Host smart-ae4c0761-25ec-4281-8b5d-6fa170d09b3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59499760831557501748945791409351419349566455012757383351126424916718854330375 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.alert_handler_entropy.59499760831557501748945791409351419349566455012757383351126424916718854330375
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.55032654274986319750271195000438067184690544273845915976281297094106657548679
Short name T193
Test name
Test status
Simulation time 6994902141 ps
CPU time 230.05 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:16:54 PM PST 23
Peak memory 251060 kb
Host smart-218c7dad-d07b-49b3-af34-cb8fc44cae6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55032
654274986319750271195000438067184690544273845915976281297094106657548679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.alert_handler_esc_alert_accum.55032654274986319750271195000438067184690544273845915976281297094106657548679
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.13527669779373722499696583372734925643738758124568863258681650061860770060159
Short name T195
Test name
Test status
Simulation time 1449142936 ps
CPU time 50.11 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:48 PM PST 23
Peak memory 255488 kb
Host smart-b4ad09ba-4599-495b-b3e6-f95d2a5a59f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13527
669779373722499696583372734925643738758124568863258681650061860770060159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.alert_handler_esc_intr_timeout.13527669779373722499696583372734925643738758124568863258681650061860770060159
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.92329425311729142929175767505015834798047756827023416272242442294385530725738
Short name T243
Test name
Test status
Simulation time 58351884139 ps
CPU time 1858.05 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:44:03 PM PST 23
Peak memory 289124 kb
Host smart-2d14e01b-a36f-4ab5-b81a-60cc6d94e240
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92329425311729142929175767505015834798047756827023416272242442294385530725738 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.alert_handler_lpg.92329425311729142929175767505015834798047756827023416272242442294385530725738
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.72496032592153915251266182415358987331544065695303320393623480408883179838330
Short name T147
Test name
Test status
Simulation time 48172572717 ps
CPU time 1624.71 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:40:08 PM PST 23
Peak memory 272460 kb
Host smart-46b94d21-7c8c-4be4-9d1a-53390faf42e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72496032592153915251266182415358987331544065695303320393623480408883179838330 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.72496032592153915251266182415358987331544065695303320393623480408883179838330
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.101035478990544435219730027510556779580318695232594942028990679902258088976208
Short name T51
Test name
Test status
Simulation time 17273552054 ps
CPU time 408.64 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:19:52 PM PST 23
Peak memory 247496 kb
Host smart-4cf21a35-7175-4e8a-ba7c-5c8a5c67965d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101035478990544435219730027510556779580318695232594942028990679902258088976208 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.101035478990544435219730027510556779580318695232594942028990679902258088976208
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.106006090326815499399324351469933682910602436344167203142790989563237344844487
Short name T598
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.46 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:13:51 PM PST 23
Peak memory 255288 kb
Host smart-18233f16-23f7-4713-8ef6-7c39f5d4d92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10600
6090326815499399324351469933682910602436344167203142790989563237344844487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.alert_handler_random_alerts.106006090326815499399324351469933682910602436344167203142790989563237344844487
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.53398491341702648007595028603047117389530461698039391681883746021516395469825
Short name T76
Test name
Test status
Simulation time 1291269199 ps
CPU time 49.35 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:13:53 PM PST 23
Peak memory 254672 kb
Host smart-5244ee36-bbd2-451a-a0ef-b0cbc5389b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53398
491341702648007595028603047117389530461698039391681883746021516395469825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.alert_handler_random_classes.53398491341702648007595028603047117389530461698039391681883746021516395469825
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.105206701653342304230754716298019364058771458737432646738306725772648361550845
Short name T56
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.81 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:13:49 PM PST 23
Peak memory 255348 kb
Host smart-5dd318ce-4655-4d95-a04d-4035a8f1dcae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
6701653342304230754716298019364058771458737432646738306725772648361550845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.alert_handler_sig_int_fail.105206701653342304230754716298019364058771458737432646738306725772648361550845
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.40064373337546344644709660337364537312080825482243154950475885673871247946499
Short name T250
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.84 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:13:56 PM PST 23
Peak memory 248684 kb
Host smart-505e55af-be74-438e-95de-2b4e68296c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40064
373337546344644709660337364537312080825482243154950475885673871247946499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_h
andler_smoke.40064373337546344644709660337364537312080825482243154950475885673871247946499
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.77684470364232512850458190111266030066147880833931981960051938264832839457499
Short name T227
Test name
Test status
Simulation time 63383433172 ps
CPU time 2094.68 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:47:59 PM PST 23
Peak memory 289584 kb
Host smart-33aa1fb5-2620-48b4-b54e-832b3cced17e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77684470364232512850458190111266030066147880833931981960051938264832839457499 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.77684470364232512850458190111266030066147880833931981960051938
264832839457499
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.60784657605705816517071802124972943807255331903930123790841315102246583422900
Short name T168
Test name
Test status
Simulation time 79866015596 ps
CPU time 3008.24 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 02:03:10 PM PST 23
Peak memory 298144 kb
Host smart-08ec52ef-83a4-480f-8f43-58d2764e4702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607846576057058165170718021249729438072553319039
30123790841315102246583422900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.60784657
605705816517071802124972943807255331903930123790841315102246583422900
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3007216236311083844930924565936892060459484970140086924284871897352176935022
Short name T393
Test name
Test status
Simulation time 30823729350 ps
CPU time 1059.88 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:30:44 PM PST 23
Peak memory 272268 kb
Host smart-91ec2b7a-7d78-4d57-8336-374afc5691c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007216236311083844930924565936892060459484970140086924284871897352176935022 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.alert_handler_entropy.3007216236311083844930924565936892060459484970140086924284871897352176935022
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.78620598998674403492502597457940995006940108960776201010022742100469849351699
Short name T247
Test name
Test status
Simulation time 6994902141 ps
CPU time 224.8 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:16:43 PM PST 23
Peak memory 251068 kb
Host smart-e0e7b481-30a3-404b-9097-c87237cdfc63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78620
598998674403492502597457940995006940108960776201010022742100469849351699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.alert_handler_esc_alert_accum.78620598998674403492502597457940995006940108960776201010022742100469849351699
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.55940068223027404644019786074184946879919970321615462651796785834594027473484
Short name T524
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.84 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:13:53 PM PST 23
Peak memory 255472 kb
Host smart-32341f8b-ad6f-4d45-bc37-2ac103f69e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55940
068223027404644019786074184946879919970321615462651796785834594027473484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.alert_handler_esc_intr_timeout.55940068223027404644019786074184946879919970321615462651796785834594027473484
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.47434453110486459828099248961679710770552834178979172469982671127807484101683
Short name T530
Test name
Test status
Simulation time 58351884139 ps
CPU time 1817.5 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:43:22 PM PST 23
Peak memory 289132 kb
Host smart-6ae2eb8a-fe1a-4339-b997-3a851761e575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47434453110486459828099248961679710770552834178979172469982671127807484101683 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.alert_handler_lpg.47434453110486459828099248961679710770552834178979172469982671127807484101683
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.77835861910349758635920730810538527102520528093909818987361286138780674061987
Short name T107
Test name
Test status
Simulation time 48172572717 ps
CPU time 1610.45 seconds
Started Nov 22 01:12:55 PM PST 23
Finished Nov 22 01:39:50 PM PST 23
Peak memory 272472 kb
Host smart-8afc2dd5-30c4-4e0f-af88-189d52e8331c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77835861910349758635920730810538527102520528093909818987361286138780674061987 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.77835861910349758635920730810538527102520528093909818987361286138780674061987
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.27746091893485988680009130866425664622675054601334477830205684276743316140510
Short name T333
Test name
Test status
Simulation time 17273552054 ps
CPU time 388.94 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:19:33 PM PST 23
Peak memory 247372 kb
Host smart-a7e7ce0e-3b58-4c9f-83e3-0f6796d8c824
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27746091893485988680009130866425664622675054601334477830205684276743316140510 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.27746091893485988680009130866425664622675054601334477830205684276743316140510
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.20050417980599092549828236446286884981177660407836982501784519409259024440658
Short name T224
Test name
Test status
Simulation time 1399732617 ps
CPU time 46.5 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:13:48 PM PST 23
Peak memory 255296 kb
Host smart-d642ff19-db03-4be4-9061-52be299a4c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20050
417980599092549828236446286884981177660407836982501784519409259024440658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.alert_handler_random_alerts.20050417980599092549828236446286884981177660407836982501784519409259024440658
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.114869428214524305539565672703282430467924380263625914560591421736414227662935
Short name T320
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.67 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:13:50 PM PST 23
Peak memory 254688 kb
Host smart-e540aa3d-084a-41e0-a705-6786d3a3c13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11486
9428214524305539565672703282430467924380263625914560591421736414227662935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.alert_handler_random_classes.114869428214524305539565672703282430467924380263625914560591421736414227662935
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.89474002688488668386400233869884563498669650162506083676646490721410925322179
Short name T203
Test name
Test status
Simulation time 1261680150 ps
CPU time 48.11 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:13:51 PM PST 23
Peak memory 255340 kb
Host smart-2c703423-c89f-4e68-aa94-f621b62e78cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89474
002688488668386400233869884563498669650162506083676646490721410925322179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
alert_handler_sig_int_fail.89474002688488668386400233869884563498669650162506083676646490721410925322179
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.114395007448934182624278141248166750061032873000467828151651549351911987212282
Short name T504
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.8 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:13:54 PM PST 23
Peak memory 248648 kb
Host smart-3caed1e7-bb00-4201-b328-2df5dd1ad984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11439
5007448934182624278141248166750061032873000467828151651549351911987212282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_
handler_smoke.114395007448934182624278141248166750061032873000467828151651549351911987212282
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.92438574038339431448563402073377664432611238540404424566101959295120762414444
Short name T452
Test name
Test status
Simulation time 63383433172 ps
CPU time 2069.32 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:47:33 PM PST 23
Peak memory 289584 kb
Host smart-04cc1159-695f-4068-8a9a-ed64bab8e8a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92438574038339431448563402073377664432611238540404424566101959295120762414444 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.92438574038339431448563402073377664432611238540404424566101959
295120762414444
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.103330723412980658998253509457825368656351852022570664427884390321138546608456
Short name T387
Test name
Test status
Simulation time 79866015596 ps
CPU time 2746.89 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:58:50 PM PST 23
Peak memory 298036 kb
Host smart-22ad25f7-0064-4466-bbaa-3d1ca9efc083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103330723412980658998253509457825368656351852022
570664427884390321138546608456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1033307
23412980658998253509457825368656351852022570664427884390321138546608456
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.64219016832759681009639158320711729735953314520560206036335039073303642061165
Short name T338
Test name
Test status
Simulation time 30823729350 ps
CPU time 1063.25 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:30:47 PM PST 23
Peak memory 272320 kb
Host smart-9064d381-f20d-421c-9823-aadf357b1551
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64219016832759681009639158320711729735953314520560206036335039073303642061165 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.alert_handler_entropy.64219016832759681009639158320711729735953314520560206036335039073303642061165
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.5288889276156154479573781697111529697336802466452958574385971442060215502668
Short name T549
Test name
Test status
Simulation time 6994902141 ps
CPU time 241.05 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:17:04 PM PST 23
Peak memory 251192 kb
Host smart-df3af113-82ef-4925-81b1-8b350bbc0765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52888
89276156154479573781697111529697336802466452958574385971442060215502668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.alert_handler_esc_alert_accum.5288889276156154479573781697111529697336802466452958574385971442060215502668
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.110441594409393171998049402521506867723777530351701564071026264238211640054866
Short name T330
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.16 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:13:53 PM PST 23
Peak memory 256176 kb
Host smart-a9617f17-5842-4b07-800c-d051f4e4d069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
1594409393171998049402521506867723777530351701564071026264238211640054866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.alert_handler_esc_intr_timeout.110441594409393171998049402521506867723777530351701564071026264238211640054866
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.86779581252289278289622693198363229271022286349960107572448001982481629215418
Short name T181
Test name
Test status
Simulation time 58351884139 ps
CPU time 1928.26 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:45:06 PM PST 23
Peak memory 289160 kb
Host smart-780e0005-6c58-4172-9b28-e16fc3de11e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86779581252289278289622693198363229271022286349960107572448001982481629215418 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.alert_handler_lpg.86779581252289278289622693198363229271022286349960107572448001982481629215418
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.47128125266598101872147868752585666729079885264159850475919333017223149296860
Short name T447
Test name
Test status
Simulation time 48172572717 ps
CPU time 1469.3 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:37:33 PM PST 23
Peak memory 272340 kb
Host smart-4fc6da00-2d28-4dd8-bbe6-876c5bac5cbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47128125266598101872147868752585666729079885264159850475919333017223149296860 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.47128125266598101872147868752585666729079885264159850475919333017223149296860
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.53806560212420527035719368400519401143818575248499703568990550832288575285034
Short name T220
Test name
Test status
Simulation time 17273552054 ps
CPU time 380.69 seconds
Started Nov 22 01:12:57 PM PST 23
Finished Nov 22 01:19:21 PM PST 23
Peak memory 247564 kb
Host smart-71881adf-a73d-446e-bb60-42afc9a352a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53806560212420527035719368400519401143818575248499703568990550832288575285034 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.53806560212420527035719368400519401143818575248499703568990550832288575285034
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.29873748027952929295696529064029439850322557844368613344894403196081353550665
Short name T178
Test name
Test status
Simulation time 1399732617 ps
CPU time 50.11 seconds
Started Nov 22 01:13:00 PM PST 23
Finished Nov 22 01:13:52 PM PST 23
Peak memory 255296 kb
Host smart-9955dd6b-2bcd-490c-838a-ee5e14377196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29873
748027952929295696529064029439850322557844368613344894403196081353550665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.alert_handler_random_alerts.29873748027952929295696529064029439850322557844368613344894403196081353550665
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.85271228640138231662677860472148103901684969212878835237100278592362142235118
Short name T522
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.32 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:13:50 PM PST 23
Peak memory 254688 kb
Host smart-63d10707-49cf-4371-a227-5b9c3b271cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85271
228640138231662677860472148103901684969212878835237100278592362142235118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.alert_handler_random_classes.85271228640138231662677860472148103901684969212878835237100278592362142235118
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.27679553941427811093983048126773009973531871576039567859022768527585777332678
Short name T519
Test name
Test status
Simulation time 1261680150 ps
CPU time 50.14 seconds
Started Nov 22 01:13:01 PM PST 23
Finished Nov 22 01:13:53 PM PST 23
Peak memory 255344 kb
Host smart-eb950883-0147-4276-9124-873336545ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27679
553941427811093983048126773009973531871576039567859022768527585777332678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
alert_handler_sig_int_fail.27679553941427811093983048126773009973531871576039567859022768527585777332678
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.27222404509426647003619193462652185613459839946563465379095633618566551575934
Short name T584
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.69 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:13:58 PM PST 23
Peak memory 248636 kb
Host smart-f2ea29cb-fe7d-4e4a-82f6-9189e56258ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222
404509426647003619193462652185613459839946563465379095633618566551575934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_h
andler_smoke.27222404509426647003619193462652185613459839946563465379095633618566551575934
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.79054264006209269223055357503168798076530791736915671524590758923703869762760
Short name T253
Test name
Test status
Simulation time 63383433172 ps
CPU time 2156.19 seconds
Started Nov 22 01:12:46 PM PST 23
Finished Nov 22 01:48:46 PM PST 23
Peak memory 289784 kb
Host smart-9f4ded0c-45a5-4116-ba3e-c3c0de13a7fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79054264006209269223055357503168798076530791736915671524590758923703869762760 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.79054264006209269223055357503168798076530791736915671524590758
923703869762760
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.73866180395524825052877335462335492759731435250036458388467495182351975587422
Short name T60
Test name
Test status
Simulation time 79866015596 ps
CPU time 2805.93 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:59:43 PM PST 23
Peak memory 298148 kb
Host smart-390fbfd0-e0ec-423d-84bc-8b9da2211a2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738661803955248250528773354623354927597314352500
36458388467495182351975587422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.73866180
395524825052877335462335492759731435250036458388467495182351975587422
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.24581122763804308929268215881276735361129338199607098168146901200661606490126
Short name T142
Test name
Test status
Simulation time 30823729350 ps
CPU time 1136.36 seconds
Started Nov 22 01:12:47 PM PST 23
Finished Nov 22 01:31:47 PM PST 23
Peak memory 272488 kb
Host smart-4408d93d-8946-40d5-8be8-0736bc7461fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24581122763804308929268215881276735361129338199607098168146901200661606490126 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.alert_handler_entropy.24581122763804308929268215881276735361129338199607098168146901200661606490126
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.11425960881617737381543012922055521372227050303288409764310740892067444787235
Short name T517
Test name
Test status
Simulation time 6994902141 ps
CPU time 230.1 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:16:49 PM PST 23
Peak memory 251124 kb
Host smart-51c9ff3d-b5ae-48c1-91c7-6bb55ac20902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11425
960881617737381543012922055521372227050303288409764310740892067444787235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.alert_handler_esc_alert_accum.11425960881617737381543012922055521372227050303288409764310740892067444787235
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.32802368234786372597704950038488162324210400969359918821478062108398758501370
Short name T198
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.46 seconds
Started Nov 22 01:13:02 PM PST 23
Finished Nov 22 01:13:52 PM PST 23
Peak memory 255480 kb
Host smart-96ac7765-f100-4f0e-b866-038a723a07db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32802
368234786372597704950038488162324210400969359918821478062108398758501370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.alert_handler_esc_intr_timeout.32802368234786372597704950038488162324210400969359918821478062108398758501370
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.26754669787084983372109390675747360130170516164591772123953083716966984086171
Short name T400
Test name
Test status
Simulation time 58351884139 ps
CPU time 1808.57 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:42:58 PM PST 23
Peak memory 289320 kb
Host smart-e27abfe3-979c-4781-9f65-d9355429f80e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26754669787084983372109390675747360130170516164591772123953083716966984086171 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.alert_handler_lpg.26754669787084983372109390675747360130170516164591772123953083716966984086171
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.18655708045675626981811234496574088347958079749716391471730907187840333057244
Short name T654
Test name
Test status
Simulation time 48172572717 ps
CPU time 1509.31 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 272384 kb
Host smart-68d870e1-f75a-44da-84f5-f1f5c1143e0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18655708045675626981811234496574088347958079749716391471730907187840333057244 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.18655708045675626981811234496574088347958079749716391471730907187840333057244
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.89249202061353755294028709497249439755033276267677335859201273105258260644157
Short name T534
Test name
Test status
Simulation time 17273552054 ps
CPU time 385.34 seconds
Started Nov 22 01:12:57 PM PST 23
Finished Nov 22 01:19:25 PM PST 23
Peak memory 247324 kb
Host smart-5e61f792-69a2-4ee8-b369-ea71d7b679b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89249202061353755294028709497249439755033276267677335859201273105258260644157 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.89249202061353755294028709497249439755033276267677335859201273105258260644157
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.30656692712533469653800786559890381756673581168227364743194004586299229155161
Short name T80
Test name
Test status
Simulation time 1399732617 ps
CPU time 46.28 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:13:36 PM PST 23
Peak memory 255384 kb
Host smart-84c36355-1c11-4910-9df3-99a1747b72a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30656
692712533469653800786559890381756673581168227364743194004586299229155161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.alert_handler_random_alerts.30656692712533469653800786559890381756673581168227364743194004586299229155161
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.71544602329659577834268266734362594560313190326889223366265204282387747306375
Short name T324
Test name
Test status
Simulation time 1291269199 ps
CPU time 47.37 seconds
Started Nov 22 01:12:53 PM PST 23
Finished Nov 22 01:13:44 PM PST 23
Peak memory 254844 kb
Host smart-a2508b2f-a856-41d5-9fd7-01d9c57f91fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71544
602329659577834268266734362594560313190326889223366265204282387747306375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.alert_handler_random_classes.71544602329659577834268266734362594560313190326889223366265204282387747306375
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.53235502204734466391563292027978445755349546126651740330750499323244718057540
Short name T297
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.88 seconds
Started Nov 22 01:12:47 PM PST 23
Finished Nov 22 01:13:36 PM PST 23
Peak memory 255548 kb
Host smart-367f8e52-07a9-47cd-8d68-c60e2d5cf300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53235
502204734466391563292027978445755349546126651740330750499323244718057540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
alert_handler_sig_int_fail.53235502204734466391563292027978445755349546126651740330750499323244718057540
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.17292372862600575138633457194915419487066725081085427927982346204775601395164
Short name T597
Test name
Test status
Simulation time 1558784916 ps
CPU time 49.29 seconds
Started Nov 22 01:13:03 PM PST 23
Finished Nov 22 01:13:55 PM PST 23
Peak memory 248716 kb
Host smart-3f959c63-f802-4782-844e-226ed1aea4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17292
372862600575138633457194915419487066725081085427927982346204775601395164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_h
andler_smoke.17292372862600575138633457194915419487066725081085427927982346204775601395164
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.12764922323781888528842111313230263407782919328492936753658976460358483439678
Short name T365
Test name
Test status
Simulation time 63383433172 ps
CPU time 2168.06 seconds
Started Nov 22 01:12:55 PM PST 23
Finished Nov 22 01:49:08 PM PST 23
Peak memory 289564 kb
Host smart-cbff81d6-0e24-486d-85c7-2315d44b05c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12764922323781888528842111313230263407782919328492936753658976460358483439678 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.12764922323781888528842111313230263407782919328492936753658976
460358483439678
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.66928320016616998848793599876819263704487286815594481467315704926604772683321
Short name T71
Test name
Test status
Simulation time 79866015596 ps
CPU time 2837.58 seconds
Started Nov 22 01:12:47 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 298100 kb
Host smart-daa793f8-fe18-4e3a-bac9-7d4a6e452311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669283200166169988487935998768192637044872868155
94481467315704926604772683321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.66928320
016616998848793599876819263704487286815594481467315704926604772683321
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.59966061963408499708848306215397582014641297078750534942405794091910004785469
Short name T28
Test name
Test status
Simulation time 30823729350 ps
CPU time 1044.48 seconds
Started Nov 22 01:12:47 PM PST 23
Finished Nov 22 01:30:15 PM PST 23
Peak memory 272448 kb
Host smart-3a2f2602-d859-4b58-b744-aa2c0e6f17dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59966061963408499708848306215397582014641297078750534942405794091910004785469 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.alert_handler_entropy.59966061963408499708848306215397582014641297078750534942405794091910004785469
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.110257772202852997832299332984650938281949741167492713906783545903300680701254
Short name T315
Test name
Test status
Simulation time 6994902141 ps
CPU time 228.78 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:16:41 PM PST 23
Peak memory 251204 kb
Host smart-4d9d47fa-0b38-4f4b-b967-942ac69f1911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11025
7772202852997832299332984650938281949741167492713906783545903300680701254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.alert_handler_esc_alert_accum.110257772202852997832299332984650938281949741167492713906783545903300680701254
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.86565824189358031846055838867768891108119730555745245929827634080135213924392
Short name T343
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.62 seconds
Started Nov 22 01:12:48 PM PST 23
Finished Nov 22 01:13:38 PM PST 23
Peak memory 255596 kb
Host smart-a5b66442-b72e-4c35-a8cb-f786b4750a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86565
824189358031846055838867768891108119730555745245929827634080135213924392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.alert_handler_esc_intr_timeout.86565824189358031846055838867768891108119730555745245929827634080135213924392
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.96999881131151034807400796339464431069331737865162711990620866474013255676242
Short name T471
Test name
Test status
Simulation time 58351884139 ps
CPU time 1769.13 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:42:24 PM PST 23
Peak memory 289184 kb
Host smart-5dee1e59-c433-4c7b-b0fe-bbb339df57c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96999881131151034807400796339464431069331737865162711990620866474013255676242 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.alert_handler_lpg.96999881131151034807400796339464431069331737865162711990620866474013255676242
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.42015038684946560368135262295067920425006663361017411338512612124903836654417
Short name T268
Test name
Test status
Simulation time 48172572717 ps
CPU time 1606.09 seconds
Started Nov 22 01:12:56 PM PST 23
Finished Nov 22 01:39:46 PM PST 23
Peak memory 272292 kb
Host smart-56ba5edd-ced3-4a16-8827-93f9f4a80e50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42015038684946560368135262295067920425006663361017411338512612124903836654417 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.42015038684946560368135262295067920425006663361017411338512612124903836654417
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.85981151782554402054853946701939830048420212647346679841013696269647069519678
Short name T500
Test name
Test status
Simulation time 17273552054 ps
CPU time 388.19 seconds
Started Nov 22 01:12:51 PM PST 23
Finished Nov 22 01:19:22 PM PST 23
Peak memory 247416 kb
Host smart-e29ce955-8137-4b22-a4f8-fcb28ffaf272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85981151782554402054853946701939830048420212647346679841013696269647069519678 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.85981151782554402054853946701939830048420212647346679841013696269647069519678
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.9528651742807045724019472580515708136002493928728980273492154598434041317706
Short name T394
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.03 seconds
Started Nov 22 01:12:56 PM PST 23
Finished Nov 22 01:13:47 PM PST 23
Peak memory 255272 kb
Host smart-3ab7b6e0-4197-46c3-a8b5-b91eee2556d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95286
51742807045724019472580515708136002493928728980273492154598434041317706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
alert_handler_random_alerts.9528651742807045724019472580515708136002493928728980273492154598434041317706
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.75152829765503159187739230143409198234643878591053316291225402366277343584718
Short name T579
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.62 seconds
Started Nov 22 01:12:56 PM PST 23
Finished Nov 22 01:13:46 PM PST 23
Peak memory 254640 kb
Host smart-e57acba8-f870-4fd3-8507-2d5f42cfde11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75152
829765503159187739230143409198234643878591053316291225402366277343584718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.alert_handler_random_classes.75152829765503159187739230143409198234643878591053316291225402366277343584718
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.71489244470515397486005253273414506392756082992574760470556753104839137016376
Short name T304
Test name
Test status
Simulation time 1261680150 ps
CPU time 48.45 seconds
Started Nov 22 01:12:51 PM PST 23
Finished Nov 22 01:13:42 PM PST 23
Peak memory 255400 kb
Host smart-19a406f4-d521-4e6d-9fb6-1dd33dceca32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71489
244470515397486005253273414506392756082992574760470556753104839137016376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
alert_handler_sig_int_fail.71489244470515397486005253273414506392756082992574760470556753104839137016376
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.40753206487581621611898995665961789550889565675069193493103727760670853161342
Short name T485
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.08 seconds
Started Nov 22 01:12:56 PM PST 23
Finished Nov 22 01:13:51 PM PST 23
Peak memory 248636 kb
Host smart-128b0765-32cc-4a52-9337-ae649990f581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40753
206487581621611898995665961789550889565675069193493103727760670853161342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_h
andler_smoke.40753206487581621611898995665961789550889565675069193493103727760670853161342
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.21270282347088720208762752962069508382206064753657670978275498315939502967990
Short name T491
Test name
Test status
Simulation time 63383433172 ps
CPU time 2046.33 seconds
Started Nov 22 01:12:56 PM PST 23
Finished Nov 22 01:47:06 PM PST 23
Peak memory 289564 kb
Host smart-94cc5f68-8e40-4e8a-a693-2609f8d38cb2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21270282347088720208762752962069508382206064753657670978275498315939502967990 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.21270282347088720208762752962069508382206064753657670978275498
315939502967990
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.42154558504031451879291284497577376320245789830281779050900305622157450113332
Short name T277
Test name
Test status
Simulation time 79866015596 ps
CPU time 2783.5 seconds
Started Nov 22 01:12:47 PM PST 23
Finished Nov 22 01:59:14 PM PST 23
Peak memory 298168 kb
Host smart-dfe9f768-46f4-45a6-889a-f9bcad581c88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421545585040314518792912844975773763202457898302
81779050900305622157450113332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.42154558
504031451879291284497577376320245789830281779050900305622157450113332
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.45471918728794074397549251702669433740398172550627650717572876992809974709937
Short name T659
Test name
Test status
Simulation time 30823729350 ps
CPU time 1110.58 seconds
Started Nov 22 01:12:57 PM PST 23
Finished Nov 22 01:31:31 PM PST 23
Peak memory 272272 kb
Host smart-8a85a4e7-efc0-4a4b-938d-c6920355fb16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45471918728794074397549251702669433740398172550627650717572876992809974709937 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.alert_handler_entropy.45471918728794074397549251702669433740398172550627650717572876992809974709937
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.87471453763352587392900213210025272948441405987549731023838611033505404300766
Short name T314
Test name
Test status
Simulation time 6994902141 ps
CPU time 221.46 seconds
Started Nov 22 01:12:54 PM PST 23
Finished Nov 22 01:16:40 PM PST 23
Peak memory 251236 kb
Host smart-63ae4c97-149b-44c7-8d76-fed92b31842f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87471
453763352587392900213210025272948441405987549731023838611033505404300766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.alert_handler_esc_alert_accum.87471453763352587392900213210025272948441405987549731023838611033505404300766
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.17216409000562412348703877662296450355550227806282120160663131409940368166727
Short name T190
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.6 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:13:40 PM PST 23
Peak memory 255596 kb
Host smart-8decb8e6-e461-4d18-899c-4f50f5e62f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17216
409000562412348703877662296450355550227806282120160663131409940368166727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.alert_handler_esc_intr_timeout.17216409000562412348703877662296450355550227806282120160663131409940368166727
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.75831657463691863680057734874370268645859386446790381009674500055095376992912
Short name T249
Test name
Test status
Simulation time 58351884139 ps
CPU time 1871.17 seconds
Started Nov 22 01:12:52 PM PST 23
Finished Nov 22 01:44:07 PM PST 23
Peak memory 289300 kb
Host smart-4f1827ab-fb7c-43ea-b8c1-5811babce0fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75831657463691863680057734874370268645859386446790381009674500055095376992912 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.alert_handler_lpg.75831657463691863680057734874370268645859386446790381009674500055095376992912
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.90372760545067593739010917088286229795736940249531472344069188926491124592201
Short name T560
Test name
Test status
Simulation time 48172572717 ps
CPU time 1628.62 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 272460 kb
Host smart-20f27e4d-588b-4b6e-91b3-803002e4aae2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90372760545067593739010917088286229795736940249531472344069188926491124592201 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.90372760545067593739010917088286229795736940249531472344069188926491124592201
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.20933349155679313518604109462639890140895150596291139896250684512653188763954
Short name T415
Test name
Test status
Simulation time 17273552054 ps
CPU time 402.85 seconds
Started Nov 22 01:12:51 PM PST 23
Finished Nov 22 01:19:36 PM PST 23
Peak memory 247432 kb
Host smart-e77bb38c-8c1b-4ed5-ab61-504512561c5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20933349155679313518604109462639890140895150596291139896250684512653188763954 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.20933349155679313518604109462639890140895150596291139896250684512653188763954
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.26121165289605733605225282296498927209132449204556202583507162059280524436177
Short name T246
Test name
Test status
Simulation time 1399732617 ps
CPU time 48.31 seconds
Started Nov 22 01:12:55 PM PST 23
Finished Nov 22 01:13:47 PM PST 23
Peak memory 255468 kb
Host smart-60b545ed-e152-4e7c-b067-2a96588bcb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
165289605733605225282296498927209132449204556202583507162059280524436177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.alert_handler_random_alerts.26121165289605733605225282296498927209132449204556202583507162059280524436177
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.20827280100794590686457674327583099185252160525528720778040251049492680303561
Short name T275
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.41 seconds
Started Nov 22 01:12:48 PM PST 23
Finished Nov 22 01:13:37 PM PST 23
Peak memory 254844 kb
Host smart-c570269e-20c3-4775-b3b5-ca92b3c20966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20827
280100794590686457674327583099185252160525528720778040251049492680303561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.alert_handler_random_classes.20827280100794590686457674327583099185252160525528720778040251049492680303561
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.93061525757199344131385519935381706051427899161237662213730508669487763301916
Short name T665
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.37 seconds
Started Nov 22 01:12:49 PM PST 23
Finished Nov 22 01:13:36 PM PST 23
Peak memory 255436 kb
Host smart-38db9506-2443-4d7c-a660-f11246de66ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93061
525757199344131385519935381706051427899161237662213730508669487763301916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
alert_handler_sig_int_fail.93061525757199344131385519935381706051427899161237662213730508669487763301916
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.13608097170373389618957110398407599750877939765789266559267145399492625117841
Short name T165
Test name
Test status
Simulation time 1558784916 ps
CPU time 54.22 seconds
Started Nov 22 01:12:48 PM PST 23
Finished Nov 22 01:13:45 PM PST 23
Peak memory 248852 kb
Host smart-986b9478-0674-45b2-84bb-b3a397b08128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13608
097170373389618957110398407599750877939765789266559267145399492625117841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_h
andler_smoke.13608097170373389618957110398407599750877939765789266559267145399492625117841
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.66894661520076543610306238438086418305188795679042963982133784086957494838872
Short name T619
Test name
Test status
Simulation time 63383433172 ps
CPU time 2004.12 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:46:55 PM PST 23
Peak memory 289780 kb
Host smart-80eb6ff4-26d1-44e1-b564-2e73e31efde2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66894661520076543610306238438086418305188795679042963982133784086957494838872 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.66894661520076543610306238438086418305188795679042963982133784
086957494838872
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.78981157336606580790560031830831234175216940395355362248710075558396874325643
Short name T457
Test name
Test status
Simulation time 79866015596 ps
CPU time 2645.76 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:57:36 PM PST 23
Peak memory 298168 kb
Host smart-b71c8ff3-8204-4fe7-8925-b5932892d30b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789811573366065807905600318308312341752169403953
55362248710075558396874325643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.78981157
336606580790560031830831234175216940395355362248710075558396874325643
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.51025849801929018433382164548323570189735508610675724682648806727168384931269
Short name T429
Test name
Test status
Simulation time 30823729350 ps
CPU time 1088.1 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 272464 kb
Host smart-ff195418-18d0-4a48-bc0f-0fb9318c1d23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51025849801929018433382164548323570189735508610675724682648806727168384931269 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.alert_handler_entropy.51025849801929018433382164548323570189735508610675724682648806727168384931269
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.112921609121915263768346291213365271044597261798101370530359921855311328562243
Short name T197
Test name
Test status
Simulation time 6994902141 ps
CPU time 229.51 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:17:20 PM PST 23
Peak memory 251120 kb
Host smart-78d75016-9a57-4d4c-8a9c-c2a9930b8fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292
1609121915263768346291213365271044597261798101370530359921855311328562243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.alert_handler_esc_alert_accum.112921609121915263768346291213365271044597261798101370530359921855311328562243
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.94071410510876498902896657559591425886768507298279845345927572769019024916818
Short name T412
Test name
Test status
Simulation time 1449142936 ps
CPU time 50.86 seconds
Started Nov 22 01:13:21 PM PST 23
Finished Nov 22 01:14:19 PM PST 23
Peak memory 255628 kb
Host smart-a301855a-461e-40c8-9f8c-c206d088223e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94071
410510876498902896657559591425886768507298279845345927572769019024916818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.alert_handler_esc_intr_timeout.94071410510876498902896657559591425886768507298279845345927572769019024916818
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.35433734320972607176909284114508616956482540533569774729457717183884014869157
Short name T590
Test name
Test status
Simulation time 58351884139 ps
CPU time 1760.03 seconds
Started Nov 22 01:13:22 PM PST 23
Finished Nov 22 01:42:50 PM PST 23
Peak memory 289272 kb
Host smart-344da4f7-edd6-4c17-a129-6213d08bec4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35433734320972607176909284114508616956482540533569774729457717183884014869157 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.alert_handler_lpg.35433734320972607176909284114508616956482540533569774729457717183884014869157
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.11683319810792991489518676948625770086121890602552101336004227057878568005599
Short name T531
Test name
Test status
Simulation time 48172572717 ps
CPU time 1575.27 seconds
Started Nov 22 01:13:21 PM PST 23
Finished Nov 22 01:39:43 PM PST 23
Peak memory 272520 kb
Host smart-03fb912a-a58e-4803-a00b-37415c5054ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11683319810792991489518676948625770086121890602552101336004227057878568005599 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.11683319810792991489518676948625770086121890602552101336004227057878568005599
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.39677937048113903089045949888351611371549625888166188444432042159366067552595
Short name T451
Test name
Test status
Simulation time 17273552054 ps
CPU time 405.21 seconds
Started Nov 22 01:13:24 PM PST 23
Finished Nov 22 01:20:17 PM PST 23
Peak memory 247444 kb
Host smart-86e423de-a632-40e8-b255-e90b855c3bb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39677937048113903089045949888351611371549625888166188444432042159366067552595 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.39677937048113903089045949888351611371549625888166188444432042159366067552595
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.103795545197614679243095143833606055591136334324191534221788270082045550261360
Short name T302
Test name
Test status
Simulation time 1399732617 ps
CPU time 44.8 seconds
Started Nov 22 01:13:20 PM PST 23
Finished Nov 22 01:14:11 PM PST 23
Peak memory 255252 kb
Host smart-02d5cbf7-355e-48c9-8c54-b38b5e69957e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10379
5545197614679243095143833606055591136334324191534221788270082045550261360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.alert_handler_random_alerts.103795545197614679243095143833606055591136334324191534221788270082045550261360
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.35609999637029844976429709899371716840009267868098076141017893767625100180531
Short name T289
Test name
Test status
Simulation time 1291269199 ps
CPU time 42.42 seconds
Started Nov 22 01:13:18 PM PST 23
Finished Nov 22 01:14:05 PM PST 23
Peak memory 254672 kb
Host smart-da8e8cf9-d354-4979-a03e-4c7274e6337b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35609
999637029844976429709899371716840009267868098076141017893767625100180531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.alert_handler_random_classes.35609999637029844976429709899371716840009267868098076141017893767625100180531
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.110986636460893777136212747189983004963354991553367519405846361573954275921416
Short name T258
Test name
Test status
Simulation time 1261680150 ps
CPU time 46.48 seconds
Started Nov 22 01:13:22 PM PST 23
Finished Nov 22 01:14:16 PM PST 23
Peak memory 255536 kb
Host smart-57410186-9c86-4e55-8c23-81a4df8ef059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11098
6636460893777136212747189983004963354991553367519405846361573954275921416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.alert_handler_sig_int_fail.110986636460893777136212747189983004963354991553367519405846361573954275921416
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.67566849728436735358906514099671359560999814268789975767641165235502169978432
Short name T138
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.94 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:14:22 PM PST 23
Peak memory 248656 kb
Host smart-3cba222b-b67e-4c92-b7d4-8d2cfceeb27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67566
849728436735358906514099671359560999814268789975767641165235502169978432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_h
andler_smoke.67566849728436735358906514099671359560999814268789975767641165235502169978432
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.10593383470472208156306828672802541981967565367346716092057151940934352887001
Short name T465
Test name
Test status
Simulation time 63383433172 ps
CPU time 2117.1 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:48:47 PM PST 23
Peak memory 289788 kb
Host smart-8957ed99-f05c-465e-be0a-885f69dc742e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10593383470472208156306828672802541981967565367346716092057151940934352887001 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.10593383470472208156306828672802541981967565367346716092057151
940934352887001
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.20029514646205195559449330622305608501287537942985069928664454873231179649355
Short name T341
Test name
Test status
Simulation time 79866015596 ps
CPU time 2733.01 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:59:04 PM PST 23
Peak memory 298200 kb
Host smart-b5dc9679-8b6c-4490-a0e8-d32711c17490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200295146462051955594493306223056085012875379429
85069928664454873231179649355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.20029514
646205195559449330622305608501287537942985069928664454873231179649355
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.13773154262901148741695766353657744770883659667190821332850672125334376742012
Short name T585
Test name
Test status
Simulation time 30823729350 ps
CPU time 1134.99 seconds
Started Nov 22 01:13:33 PM PST 23
Finished Nov 22 01:32:34 PM PST 23
Peak memory 272452 kb
Host smart-080b7abc-7b9c-4b03-aec6-a2815c5f4b20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13773154262901148741695766353657744770883659667190821332850672125334376742012 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.alert_handler_entropy.13773154262901148741695766353657744770883659667190821332850672125334376742012
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.33531777964031322904923572478274202924473088641107511792515668193909693045012
Short name T252
Test name
Test status
Simulation time 6994902141 ps
CPU time 228.35 seconds
Started Nov 22 01:13:24 PM PST 23
Finished Nov 22 01:17:20 PM PST 23
Peak memory 251116 kb
Host smart-e052bdc0-d913-4053-9e3a-f6013bc9e342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
777964031322904923572478274202924473088641107511792515668193909693045012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.alert_handler_esc_alert_accum.33531777964031322904923572478274202924473088641107511792515668193909693045012
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.92176813779891130461950801398598049799357027696415356288973350367340305973254
Short name T296
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.08 seconds
Started Nov 22 01:13:22 PM PST 23
Finished Nov 22 01:14:17 PM PST 23
Peak memory 255456 kb
Host smart-b5af9f5b-35da-406c-a568-2f7ff9222166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92176
813779891130461950801398598049799357027696415356288973350367340305973254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.alert_handler_esc_intr_timeout.92176813779891130461950801398598049799357027696415356288973350367340305973254
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.71040029446166115947763062928676541322205238311432865621292430445105435451961
Short name T604
Test name
Test status
Simulation time 58351884139 ps
CPU time 1859.89 seconds
Started Nov 22 01:13:33 PM PST 23
Finished Nov 22 01:44:39 PM PST 23
Peak memory 289160 kb
Host smart-6a475c20-41dc-486a-a513-715850b1ade2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71040029446166115947763062928676541322205238311432865621292430445105435451961 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.alert_handler_lpg.71040029446166115947763062928676541322205238311432865621292430445105435451961
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.65918893175504072003895509398624460392603111197066372469605147531132148139086
Short name T271
Test name
Test status
Simulation time 48172572717 ps
CPU time 1549.27 seconds
Started Nov 22 01:13:32 PM PST 23
Finished Nov 22 01:39:27 PM PST 23
Peak memory 272512 kb
Host smart-58f0c93e-382e-4cc3-af01-667765e3687f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65918893175504072003895509398624460392603111197066372469605147531132148139086 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.65918893175504072003895509398624460392603111197066372469605147531132148139086
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.39880102955877254557960296347727913734224036097237252576863389846588512576454
Short name T424
Test name
Test status
Simulation time 17273552054 ps
CPU time 401.77 seconds
Started Nov 22 01:13:24 PM PST 23
Finished Nov 22 01:20:13 PM PST 23
Peak memory 247480 kb
Host smart-222db669-d97b-47af-a6ce-1a0fb541bc45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39880102955877254557960296347727913734224036097237252576863389846588512576454 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.39880102955877254557960296347727913734224036097237252576863389846588512576454
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.46101927586187385870883629208676084369772934419205003540361456931218659920143
Short name T141
Test name
Test status
Simulation time 1399732617 ps
CPU time 46.55 seconds
Started Nov 22 01:13:24 PM PST 23
Finished Nov 22 01:14:18 PM PST 23
Peak memory 255484 kb
Host smart-8be1b31f-f72b-4fcb-85c3-3d87ced167e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46101
927586187385870883629208676084369772934419205003540361456931218659920143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.alert_handler_random_alerts.46101927586187385870883629208676084369772934419205003540361456931218659920143
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.30971692846629106029628662849541611089576479696869625186491613483303728553403
Short name T391
Test name
Test status
Simulation time 1291269199 ps
CPU time 44.86 seconds
Started Nov 22 01:13:31 PM PST 23
Finished Nov 22 01:14:21 PM PST 23
Peak memory 254844 kb
Host smart-aa6395f5-cf31-49d6-81a0-51d86e50683a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30971
692846629106029628662849541611089576479696869625186491613483303728553403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.alert_handler_random_classes.30971692846629106029628662849541611089576479696869625186491613483303728553403
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.14550423231179205921857781214922166447924512732026046376314372958896614237446
Short name T244
Test name
Test status
Simulation time 1261680150 ps
CPU time 41.95 seconds
Started Nov 22 01:13:23 PM PST 23
Finished Nov 22 01:14:13 PM PST 23
Peak memory 255556 kb
Host smart-967188d9-30b7-4d9a-8a5e-db63312fdacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14550
423231179205921857781214922166447924512732026046376314372958896614237446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
alert_handler_sig_int_fail.14550423231179205921857781214922166447924512732026046376314372958896614237446
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.99004668395520445419633490769028950403044071190057241513858038495047306674587
Short name T596
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.02 seconds
Started Nov 22 01:13:33 PM PST 23
Finished Nov 22 01:14:29 PM PST 23
Peak memory 248864 kb
Host smart-4c338ce1-5798-4725-b017-02b4010d2024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99004
668395520445419633490769028950403044071190057241513858038495047306674587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_h
andler_smoke.99004668395520445419633490769028950403044071190057241513858038495047306674587
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.15176910538262760579180913706976600864629677271849372956329106016509004898573
Short name T657
Test name
Test status
Simulation time 63383433172 ps
CPU time 2100.4 seconds
Started Nov 22 01:13:40 PM PST 23
Finished Nov 22 01:48:52 PM PST 23
Peak memory 289576 kb
Host smart-3fa3f788-2b84-423a-81d6-19191dd30631
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15176910538262760579180913706976600864629677271849372956329106016509004898573 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.15176910538262760579180913706976600864629677271849372956329106
016509004898573
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.19852044479726719958242360423258521127189830218028773519560387476518592877115
Short name T450
Test name
Test status
Simulation time 79866015596 ps
CPU time 2823.99 seconds
Started Nov 22 01:13:32 PM PST 23
Finished Nov 22 02:00:42 PM PST 23
Peak memory 298172 kb
Host smart-de669078-4efb-4924-b884-e89f671b61f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198520444797267199582423604232585211271898302180
28773519560387476518592877115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.19852044
479726719958242360423258521127189830218028773519560387476518592877115
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.89296908829642742056688170336656914157091015960022062415744308160878442259865
Short name T43
Test name
Test status
Simulation time 30823729350 ps
CPU time 1056.12 seconds
Started Nov 22 01:13:40 PM PST 23
Finished Nov 22 01:31:26 PM PST 23
Peak memory 272468 kb
Host smart-4676b2be-4133-4449-a4cb-76cda65e923c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89296908829642742056688170336656914157091015960022062415744308160878442259865 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.alert_handler_entropy.89296908829642742056688170336656914157091015960022062415744308160878442259865
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.89940648190871552495077116916079833604035534805728845079389106717974203638090
Short name T662
Test name
Test status
Simulation time 6994902141 ps
CPU time 237.94 seconds
Started Nov 22 01:13:25 PM PST 23
Finished Nov 22 01:17:29 PM PST 23
Peak memory 251256 kb
Host smart-b3eecab9-550a-4bf4-8b92-d7d21df8fe84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89940
648190871552495077116916079833604035534805728845079389106717974203638090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.alert_handler_esc_alert_accum.89940648190871552495077116916079833604035534805728845079389106717974203638090
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3336911205876670618047648239790283025253688119672357033819225009948021326184
Short name T453
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.5 seconds
Started Nov 22 01:13:33 PM PST 23
Finished Nov 22 01:14:26 PM PST 23
Peak memory 255640 kb
Host smart-12be8111-9ba2-45f1-bec3-70043463866e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33369
11205876670618047648239790283025253688119672357033819225009948021326184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.alert_handler_esc_intr_timeout.3336911205876670618047648239790283025253688119672357033819225009948021326184
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.43945922370359404211221596026259797517672546331732249417759423450449204734697
Short name T655
Test name
Test status
Simulation time 58351884139 ps
CPU time 1827.5 seconds
Started Nov 22 01:13:38 PM PST 23
Finished Nov 22 01:44:15 PM PST 23
Peak memory 289284 kb
Host smart-168cea78-0aac-4df7-9a87-ed6b5bd90035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43945922370359404211221596026259797517672546331732249417759423450449204734697 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.alert_handler_lpg.43945922370359404211221596026259797517672546331732249417759423450449204734697
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.30463096616237344338563628902398033165925401815343812031994220702639228179538
Short name T600
Test name
Test status
Simulation time 48172572717 ps
CPU time 1504.84 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 01:38:56 PM PST 23
Peak memory 272516 kb
Host smart-dba78647-2ef5-43dd-8980-c8466ab0199c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30463096616237344338563628902398033165925401815343812031994220702639228179538 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.30463096616237344338563628902398033165925401815343812031994220702639228179538
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.25391680744603083259552930694823018909082605061484283450681871580670974952690
Short name T413
Test name
Test status
Simulation time 17273552054 ps
CPU time 407.52 seconds
Started Nov 22 01:13:40 PM PST 23
Finished Nov 22 01:20:38 PM PST 23
Peak memory 247548 kb
Host smart-7a1e4206-f8fc-482c-af12-c5c6d847de14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25391680744603083259552930694823018909082605061484283450681871580670974952690 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.25391680744603083259552930694823018909082605061484283450681871580670974952690
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.71394807010171542433364169109688122574926505257170126350138871661734804098388
Short name T162
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.27 seconds
Started Nov 22 01:13:34 PM PST 23
Finished Nov 22 01:14:27 PM PST 23
Peak memory 255496 kb
Host smart-adb37871-bfac-42d6-a03b-7efaa0d400ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71394
807010171542433364169109688122574926505257170126350138871661734804098388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.alert_handler_random_alerts.71394807010171542433364169109688122574926505257170126350138871661734804098388
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.68682208595445570620050975154398293316338624034350742218304540217128726961779
Short name T563
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.94 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 01:14:38 PM PST 23
Peak memory 254856 kb
Host smart-5cedee36-742a-42cc-b57d-5e0d8687f735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68682
208595445570620050975154398293316338624034350742218304540217128726961779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.alert_handler_random_classes.68682208595445570620050975154398293316338624034350742218304540217128726961779
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.12548066999455445935130805841591384974031764539377917475551550913001378235412
Short name T346
Test name
Test status
Simulation time 1261680150 ps
CPU time 49.12 seconds
Started Nov 22 01:13:39 PM PST 23
Finished Nov 22 01:14:38 PM PST 23
Peak memory 255496 kb
Host smart-c0f2098c-680e-49a9-af4c-203f7c9a0bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12548
066999455445935130805841591384974031764539377917475551550913001378235412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
alert_handler_sig_int_fail.12548066999455445935130805841591384974031764539377917475551550913001378235412
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.26530020448969498854110838358752628827662188839705065781026830130172627162843
Short name T463
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.37 seconds
Started Nov 22 01:13:27 PM PST 23
Finished Nov 22 01:14:25 PM PST 23
Peak memory 248792 kb
Host smart-2d6cb477-1eed-44db-96a2-02dcc0dda844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530
020448969498854110838358752628827662188839705065781026830130172627162843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_h
andler_smoke.26530020448969498854110838358752628827662188839705065781026830130172627162843
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.20717482731405041565325161137981676857468611541860472477141118110836989397489
Short name T294
Test name
Test status
Simulation time 63383433172 ps
CPU time 2005.39 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 01:47:17 PM PST 23
Peak memory 289632 kb
Host smart-758ff450-538c-413d-8e1a-021e11eb7b26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717482731405041565325161137981676857468611541860472477141118110836989397489 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.20717482731405041565325161137981676857468611541860472477141118
110836989397489
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.52830762504688164800019282862876314940333306444131371379837969451315184392030
Short name T216
Test name
Test status
Simulation time 79866015596 ps
CPU time 3028.67 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 02:04:20 PM PST 23
Peak memory 298088 kb
Host smart-944036ec-492e-4d2b-be97-df460a26caa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528307625046881648000192828628763149403333064441
31371379837969451315184392030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.52830762
504688164800019282862876314940333306444131371379837969451315184392030
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.112248498302025913115816075535449537633796485989347293552749316340759147142842
Short name T121
Test name
Test status
Simulation time 49707703 ps
CPU time 3.07 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 01:12:45 PM PST 23
Peak memory 248960 kb
Host smart-e8d6d272-0848-41f1-9e94-175dc4b1b122
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=112248498302025913115816075535449537633796485989347293552749316340759147142842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.alert_handler_alert_accum_saturation.112248498302025913115816075535449537633796485989347293552749316340759147142842
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.16462891549803441959214914714128926358192171127956787785021357068077032110021
Short name T647
Test name
Test status
Simulation time 30823729350 ps
CPU time 1029.12 seconds
Started Nov 22 01:12:17 PM PST 23
Finished Nov 22 01:29:28 PM PST 23
Peak memory 272416 kb
Host smart-4cab92dd-7c14-4ca9-88df-6fd07913869e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16462891549803441959214914714128926358192171127956787785021357068077032110021 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.alert_handler_entropy.16462891549803441959214914714128926358192171127956787785021357068077032110021
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.48525302936471291520589932404112631758491402497209868849141130708747008810853
Short name T460
Test name
Test status
Simulation time 1452482195 ps
CPU time 34.46 seconds
Started Nov 22 01:12:18 PM PST 23
Finished Nov 22 01:12:54 PM PST 23
Peak memory 240504 kb
Host smart-7df5204c-a4ea-4af0-a835-dca75c6a5332
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=48525302936471291520589932404112631758491402497209868849141130708747008810853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.alert_handler_entropy_stress.48525302936471291520589932404112631758491402497209868849141130708747008810853
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.79271975448618342553068852557942668826101764856614707578899676371001550181861
Short name T237
Test name
Test status
Simulation time 6994902141 ps
CPU time 230.95 seconds
Started Nov 22 01:12:14 PM PST 23
Finished Nov 22 01:16:07 PM PST 23
Peak memory 251256 kb
Host smart-150701c7-e15f-40c6-9f92-9402e6459631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79271
975448618342553068852557942668826101764856614707578899676371001550181861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.alert_handler_esc_alert_accum.79271975448618342553068852557942668826101764856614707578899676371001550181861
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.86278710624130367566712740338758784838893211504357816716602729237683616617304
Short name T83
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.75 seconds
Started Nov 22 01:12:15 PM PST 23
Finished Nov 22 01:13:07 PM PST 23
Peak memory 255604 kb
Host smart-9fa8728b-107e-4cf7-be0e-aa2f2528950d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86278
710624130367566712740338758784838893211504357816716602729237683616617304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.alert_handler_esc_intr_timeout.86278710624130367566712740338758784838893211504357816716602729237683616617304
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.9618976446235595741738694951901643671621984915950433263141107489083635904956
Short name T218
Test name
Test status
Simulation time 58351884139 ps
CPU time 1837.49 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:42:48 PM PST 23
Peak memory 289300 kb
Host smart-0f58e5fe-aa77-4861-8f48-5989bb882fe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9618976446235595741738694951901643671621984915950433263141107489083635904956 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.alert_handler_lpg.9618976446235595741738694951901643671621984915950433263141107489083635904956
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.11574921416991227703472959151663093760507075828033325940965784370321464153902
Short name T652
Test name
Test status
Simulation time 48172572717 ps
CPU time 1508.68 seconds
Started Nov 22 01:12:14 PM PST 23
Finished Nov 22 01:37:25 PM PST 23
Peak memory 272352 kb
Host smart-a626005b-da9e-4b62-98f5-113b30a591e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11574921416991227703472959151663093760507075828033325940965784370321464153902 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.11574921416991227703472959151663093760507075828033325940965784370321464153902
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.22641971752682665974734043283235241509607905585808945174033457459033462455708
Short name T505
Test name
Test status
Simulation time 17273552054 ps
CPU time 386.17 seconds
Started Nov 22 01:12:14 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 247368 kb
Host smart-beb00628-3b8e-4ddf-9651-123b990be250
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22641971752682665974734043283235241509607905585808945174033457459033462455708 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.22641971752682665974734043283235241509607905585808945174033457459033462455708
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.8814132928327357880284422112930415545682203983310526056532099330900893350466
Short name T236
Test name
Test status
Simulation time 1399732617 ps
CPU time 45.74 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 255444 kb
Host smart-e644f732-1418-483e-b0ef-4089d5a69438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88141
32928327357880284422112930415545682203983310526056532099330900893350466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
lert_handler_random_alerts.8814132928327357880284422112930415545682203983310526056532099330900893350466
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.16410617039629794647204346397498183163497793063036946317174728434138841956104
Short name T630
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.54 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 254852 kb
Host smart-0d9eb985-0056-412b-bc94-db2378bd5686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16410
617039629794647204346397498183163497793063036946317174728434138841956104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.alert_handler_random_classes.16410617039629794647204346397498183163497793063036946317174728434138841956104
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.77062513631518588998907853678095436002954821702059040075525913735660364702818
Short name T36
Test name
Test status
Simulation time 740845031 ps
CPU time 24.64 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 01:13:06 PM PST 23
Peak memory 274788 kb
Host smart-807f4fad-7188-4cbf-a7a8-b49b85f6e09a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=77062513631518588998907853678095436002954821702059040075525913735660364702818 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.alert_handler_sec_cm.77062513631518588998907853678095436002954821702059040075525913735660364702818
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.112397461096774901131449993010500109696216787694659964249109729726752486294455
Short name T454
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.31 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:56 PM PST 23
Peak memory 255536 kb
Host smart-f8fbe7f8-24a3-41ac-a3dc-8ed49440bf24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11239
7461096774901131449993010500109696216787694659964249109729726752486294455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
alert_handler_sig_int_fail.112397461096774901131449993010500109696216787694659964249109729726752486294455
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.42947408470904566011451512544848398416823937974410572063505476922699531998965
Short name T514
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.64 seconds
Started Nov 22 01:12:11 PM PST 23
Finished Nov 22 01:13:05 PM PST 23
Peak memory 248832 kb
Host smart-cddde875-b4b6-41fc-97d2-dde30ef84fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42947
408470904566011451512544848398416823937974410572063505476922699531998965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_ha
ndler_smoke.42947408470904566011451512544848398416823937974410572063505476922699531998965
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.8358071898035660911747685614450450619176818929851207029400507964858104430723
Short name T206
Test name
Test status
Simulation time 63383433172 ps
CPU time 2209.73 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 01:49:31 PM PST 23
Peak memory 289736 kb
Host smart-9ab9e97b-4982-4e38-9c19-cccc6472037d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8358071898035660911747685614450450619176818929851207029400507964858104430723 -assert nopos
tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.8358071898035660911747685614450450619176818929851207029400507964858104430723
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.86271823182052928771101086586691571775725937198083862500895477437149932285674
Short name T508
Test name
Test status
Simulation time 79866015596 ps
CPU time 2662.31 seconds
Started Nov 22 01:12:12 PM PST 23
Finished Nov 22 01:56:37 PM PST 23
Peak memory 297988 kb
Host smart-43a4b372-8037-4942-b869-024a4e089000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862718231820529287711010865866915717757259371980
83862500895477437149932285674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.862718231
82052928771101086586691571775725937198083862500895477437149932285674
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.37003156847895385011468150187663235206847763188264915921622657567416688894552
Short name T658
Test name
Test status
Simulation time 30823729350 ps
CPU time 1086.21 seconds
Started Nov 22 01:13:44 PM PST 23
Finished Nov 22 01:32:00 PM PST 23
Peak memory 272364 kb
Host smart-af41e2d5-7bba-4154-b968-26114dc5c0f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37003156847895385011468150187663235206847763188264915921622657567416688894552 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.alert_handler_entropy.37003156847895385011468150187663235206847763188264915921622657567416688894552
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.39537528794052351321566145146780779579640242979415844516750955726130711074590
Short name T689
Test name
Test status
Simulation time 6994902141 ps
CPU time 226.9 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 01:17:38 PM PST 23
Peak memory 251268 kb
Host smart-7c9b89ee-27d7-4f2d-a308-5bced1031393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
528794052351321566145146780779579640242979415844516750955726130711074590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.alert_handler_esc_alert_accum.39537528794052351321566145146780779579640242979415844516750955726130711074590
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.59459028567765363472405455807769729489832728823493188649894302526247593091809
Short name T145
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.86 seconds
Started Nov 22 01:13:45 PM PST 23
Finished Nov 22 01:14:42 PM PST 23
Peak memory 255612 kb
Host smart-84fc8f7b-e10b-4834-b85e-8dae69449d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59459
028567765363472405455807769729489832728823493188649894302526247593091809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.alert_handler_esc_intr_timeout.59459028567765363472405455807769729489832728823493188649894302526247593091809
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.100386807646742958022273644413873193222395742222152767403785145993586990315402
Short name T525
Test name
Test status
Simulation time 58351884139 ps
CPU time 1936.53 seconds
Started Nov 22 01:13:43 PM PST 23
Finished Nov 22 01:46:10 PM PST 23
Peak memory 289264 kb
Host smart-4fe941ef-24b3-48c7-870f-3611d10d69e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100386807646742958022273644413873193222395742222152767403785145993586990315402 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.alert_handler_lpg.100386807646742958022273644413873193222395742222152767403785145993586990315402
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.91005234581095005689139002175222112362456900046118390491615741866857737332517
Short name T603
Test name
Test status
Simulation time 48172572717 ps
CPU time 1585.81 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 272484 kb
Host smart-81bd5986-1aa8-4650-be77-9752f2c72714
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91005234581095005689139002175222112362456900046118390491615741866857737332517 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.91005234581095005689139002175222112362456900046118390491615741866857737332517
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.74604919207121911364861886039746238591285571807126391343345378360535962691753
Short name T200
Test name
Test status
Simulation time 17273552054 ps
CPU time 398.89 seconds
Started Nov 22 01:13:42 PM PST 23
Finished Nov 22 01:20:30 PM PST 23
Peak memory 247536 kb
Host smart-a68599f4-bb71-41e0-bdb8-b10717efef42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74604919207121911364861886039746238591285571807126391343345378360535962691753 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.74604919207121911364861886039746238591285571807126391343345378360535962691753
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.33679601762376485674745285377295922065393934710889301155574877357960457415503
Short name T48
Test name
Test status
Simulation time 1399732617 ps
CPU time 45.32 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 01:14:37 PM PST 23
Peak memory 255468 kb
Host smart-48eebac5-40a9-4d9b-a907-cfa14e834dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33679
601762376485674745285377295922065393934710889301155574877357960457415503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.alert_handler_random_alerts.33679601762376485674745285377295922065393934710889301155574877357960457415503
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.65253458848662893775583633690470889855240008646935589340000072138551386864663
Short name T384
Test name
Test status
Simulation time 1291269199 ps
CPU time 44.14 seconds
Started Nov 22 01:13:40 PM PST 23
Finished Nov 22 01:14:36 PM PST 23
Peak memory 254816 kb
Host smart-4ec25f26-6244-4c54-a0d4-be95991c440b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65253
458848662893775583633690470889855240008646935589340000072138551386864663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.alert_handler_random_classes.65253458848662893775583633690470889855240008646935589340000072138551386864663
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.38603064665839916160606081098258163859340088695770007807272838084228499112311
Short name T187
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.03 seconds
Started Nov 22 01:13:40 PM PST 23
Finished Nov 22 01:14:35 PM PST 23
Peak memory 255516 kb
Host smart-a1559e06-e7e7-4ab4-ac39-3bf2d19a9155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
064665839916160606081098258163859340088695770007807272838084228499112311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
alert_handler_sig_int_fail.38603064665839916160606081098258163859340088695770007807272838084228499112311
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.50414154043422790021558082294252424662560984736759115293960993922124191301472
Short name T84
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.74 seconds
Started Nov 22 01:13:42 PM PST 23
Finished Nov 22 01:14:47 PM PST 23
Peak memory 248840 kb
Host smart-b74b8f35-7263-4b6f-96ea-835e3991cf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50414
154043422790021558082294252424662560984736759115293960993922124191301472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_h
andler_smoke.50414154043422790021558082294252424662560984736759115293960993922124191301472
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.112978514987450254326841357556511835535821253939857896134127865743338673297624
Short name T445
Test name
Test status
Simulation time 63383433172 ps
CPU time 2113.29 seconds
Started Nov 22 01:13:41 PM PST 23
Finished Nov 22 01:49:05 PM PST 23
Peak memory 289756 kb
Host smart-310188a1-9d36-48ac-bdce-39048d9385ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112978514987450254326841357556511835535821253939857896134127865743338673297624 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.1129785149874502543268413575565118355358212539398578961341278
65743338673297624
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.25743021618776138651438144407523719485968321506901382543276271120512349491050
Short name T538
Test name
Test status
Simulation time 79866015596 ps
CPU time 2864.62 seconds
Started Nov 22 01:13:45 PM PST 23
Finished Nov 22 02:01:39 PM PST 23
Peak memory 298200 kb
Host smart-93af2e11-0408-4ced-826b-5c6703d08b93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257430216187761386514381444075237194859683215069
01382543276271120512349491050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.25743021
618776138651438144407523719485968321506901382543276271120512349491050
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.21074898185392853551517718572559461567958697469245318713753581520211009187606
Short name T687
Test name
Test status
Simulation time 30823729350 ps
CPU time 1108.89 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:32:26 PM PST 23
Peak memory 272448 kb
Host smart-3d02c702-563b-4c61-b913-a0a5e428168f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21074898185392853551517718572559461567958697469245318713753581520211009187606 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.alert_handler_entropy.21074898185392853551517718572559461567958697469245318713753581520211009187606
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.114236118042420777394824535027735498715899542136913735962930469996132594265855
Short name T31
Test name
Test status
Simulation time 6994902141 ps
CPU time 265.64 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 251184 kb
Host smart-4f6dceed-697e-4e30-9eca-39349ded8e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11423
6118042420777394824535027735498715899542136913735962930469996132594265855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.alert_handler_esc_alert_accum.114236118042420777394824535027735498715899542136913735962930469996132594265855
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.42943531662528245687078684647677990325560314315283872519778674296179966690078
Short name T376
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.23 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:14:46 PM PST 23
Peak memory 255632 kb
Host smart-7d712108-c089-400e-886a-45fa3d619107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42943
531662528245687078684647677990325560314315283872519778674296179966690078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.alert_handler_esc_intr_timeout.42943531662528245687078684647677990325560314315283872519778674296179966690078
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.74709511659403128997348461085164221622893360048082669169030108337086168434222
Short name T279
Test name
Test status
Simulation time 58351884139 ps
CPU time 1802.55 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:43:59 PM PST 23
Peak memory 289304 kb
Host smart-81186839-800c-455d-8b5a-22e1d8689f8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74709511659403128997348461085164221622893360048082669169030108337086168434222 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.alert_handler_lpg.74709511659403128997348461085164221622893360048082669169030108337086168434222
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.113323459831276323114527353702432626210415015068040498998055519197445056665274
Short name T171
Test name
Test status
Simulation time 48172572717 ps
CPU time 1446.91 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 272400 kb
Host smart-9eaf6748-0269-4f32-ac40-c7d2f32e5d51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113323459831276323114527353702432626210415015068040498998055519197445056665274 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.113323459831276323114527353702432626210415015068040498998055519197445056665274
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.104163541150425864939718454766625636773542417694514652373396084854356797522584
Short name T591
Test name
Test status
Simulation time 17273552054 ps
CPU time 406.25 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:20:43 PM PST 23
Peak memory 247392 kb
Host smart-f89d51f0-193f-4811-add2-75eadd6b64d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104163541150425864939718454766625636773542417694514652373396084854356797522584 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.104163541150425864939718454766625636773542417694514652373396084854356797522584
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.102445880424657431536609409657927277353734120012350234719244666652863615413896
Short name T636
Test name
Test status
Simulation time 1399732617 ps
CPU time 49.73 seconds
Started Nov 22 01:13:47 PM PST 23
Finished Nov 22 01:14:45 PM PST 23
Peak memory 255452 kb
Host smart-98c32e70-cd54-40a6-8a7a-2384f7f207ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10244
5880424657431536609409657927277353734120012350234719244666652863615413896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.alert_handler_random_alerts.102445880424657431536609409657927277353734120012350234719244666652863615413896
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.56166386630233519302124338749124186746852312917447517259506446879104122543087
Short name T396
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.32 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:14:41 PM PST 23
Peak memory 254688 kb
Host smart-61b5792d-9b14-429f-9e28-9462c879627e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56166
386630233519302124338749124186746852312917447517259506446879104122543087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.alert_handler_random_classes.56166386630233519302124338749124186746852312917447517259506446879104122543087
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.16603944299973086891952390188793811695487605081741145661340470512651324780133
Short name T232
Test name
Test status
Simulation time 1261680150 ps
CPU time 46.41 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:14:44 PM PST 23
Peak memory 255540 kb
Host smart-70135055-fc52-4796-bf1f-073169ca06c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16603
944299973086891952390188793811695487605081741145661340470512651324780133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
alert_handler_sig_int_fail.16603944299973086891952390188793811695487605081741145661340470512651324780133
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2653479043767787627710392972554278100395660829411905489900503637461734531978
Short name T205
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.67 seconds
Started Nov 22 01:13:46 PM PST 23
Finished Nov 22 01:14:49 PM PST 23
Peak memory 248860 kb
Host smart-d0cf5005-f934-4ff1-82e0-3da921671daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26534
79043767787627710392972554278100395660829411905489900503637461734531978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_smoke.2653479043767787627710392972554278100395660829411905489900503637461734531978
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.25101761590321269838857898888776212782843422939526293264449835843894646081625
Short name T440
Test name
Test status
Simulation time 63383433172 ps
CPU time 2168.77 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:50:06 PM PST 23
Peak memory 289568 kb
Host smart-f7987f0c-7e20-41ea-a845-fa48bca7d4e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25101761590321269838857898888776212782843422939526293264449835843894646081625 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.25101761590321269838857898888776212782843422939526293264449835
843894646081625
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.28269309327595595953684050622651952313252745418124494492778178650807272844736
Short name T68
Test name
Test status
Simulation time 79866015596 ps
CPU time 2654.19 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:58:12 PM PST 23
Peak memory 298088 kb
Host smart-6b6c0a80-e329-4721-a972-3f7ad1248d52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282693093275955959536840506226519523132527454181
24494492778178650807272844736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.28269309
327595595953684050622651952313252745418124494492778178650807272844736
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.6497142046266226845479672495226780331007045181845551060452715581781602395613
Short name T464
Test name
Test status
Simulation time 30823729350 ps
CPU time 1134.74 seconds
Started Nov 22 01:13:51 PM PST 23
Finished Nov 22 01:32:53 PM PST 23
Peak memory 272412 kb
Host smart-a9abceac-f69e-46d7-baa6-9726c380de5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6497142046266226845479672495226780331007045181845551060452715581781602395613 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.alert_handler_entropy.6497142046266226845479672495226780331007045181845551060452715581781602395613
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.89674510274192475867914527741974540169093200274785234963935044123000256171297
Short name T272
Test name
Test status
Simulation time 6994902141 ps
CPU time 246.87 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 251248 kb
Host smart-5e733881-1a8b-48a9-a3a3-7c9fdf8ecb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89674
510274192475867914527741974540169093200274785234963935044123000256171297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.alert_handler_esc_alert_accum.89674510274192475867914527741974540169093200274785234963935044123000256171297
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.69558546290376413030702936013420687162017658159441600882533346973889394155467
Short name T24
Test name
Test status
Simulation time 1449142936 ps
CPU time 46.1 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:14:43 PM PST 23
Peak memory 255644 kb
Host smart-9a07101f-d82b-4527-9a2d-cea52da10841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69558
546290376413030702936013420687162017658159441600882533346973889394155467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.alert_handler_esc_intr_timeout.69558546290376413030702936013420687162017658159441600882533346973889394155467
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.70554801036926699571238178921474902789623643665742979511838324044049138177351
Short name T210
Test name
Test status
Simulation time 58351884139 ps
CPU time 1898.13 seconds
Started Nov 22 01:13:52 PM PST 23
Finished Nov 22 01:45:37 PM PST 23
Peak memory 289120 kb
Host smart-7b2e1d6f-6348-460f-8944-65e48a4b2f64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70554801036926699571238178921474902789623643665742979511838324044049138177351 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.alert_handler_lpg.70554801036926699571238178921474902789623643665742979511838324044049138177351
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.83367324116473206988334510141536068337595405557037717085286258172666883381516
Short name T497
Test name
Test status
Simulation time 48172572717 ps
CPU time 1591.86 seconds
Started Nov 22 01:13:52 PM PST 23
Finished Nov 22 01:40:30 PM PST 23
Peak memory 272272 kb
Host smart-7705f6fc-d8a8-4c51-895c-323a45570ceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83367324116473206988334510141536068337595405557037717085286258172666883381516 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.83367324116473206988334510141536068337595405557037717085286258172666883381516
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.114475634468465440111536899717512921042634655888934597431563289369216256600681
Short name T18
Test name
Test status
Simulation time 17273552054 ps
CPU time 378.22 seconds
Started Nov 22 01:13:55 PM PST 23
Finished Nov 22 01:20:17 PM PST 23
Peak memory 247492 kb
Host smart-f632b7dd-8183-49ac-bdc7-f2f43a7cc467
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114475634468465440111536899717512921042634655888934597431563289369216256600681 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.114475634468465440111536899717512921042634655888934597431563289369216256600681
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.82563576969087478746768055785738708536628854435803065212945117651931865169293
Short name T688
Test name
Test status
Simulation time 1399732617 ps
CPU time 52.11 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:14:49 PM PST 23
Peak memory 255492 kb
Host smart-e58d73b7-3c0a-4b89-bb02-776a1dace1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82563
576969087478746768055785738708536628854435803065212945117651931865169293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.alert_handler_random_alerts.82563576969087478746768055785738708536628854435803065212945117651931865169293
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.110878378656476028413149771245583844343783679394139613762434543535300989500193
Short name T321
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.58 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:14:41 PM PST 23
Peak memory 254732 kb
Host smart-ee68bbf0-df8d-4673-92b0-deb202a5c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11087
8378656476028413149771245583844343783679394139613762434543535300989500193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.alert_handler_random_classes.110878378656476028413149771245583844343783679394139613762434543535300989500193
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.54258843840531027916241287397952827162084507366644888466534424309502432178017
Short name T509
Test name
Test status
Simulation time 1261680150 ps
CPU time 46.35 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:14:43 PM PST 23
Peak memory 255380 kb
Host smart-93ec64c2-1dd1-4472-94eb-6ca81042881f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54258
843840531027916241287397952827162084507366644888466534424309502432178017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
alert_handler_sig_int_fail.54258843840531027916241287397952827162084507366644888466534424309502432178017
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.84192272413397382569910863463032164977881140276923082240444871800843325566825
Short name T260
Test name
Test status
Simulation time 1558784916 ps
CPU time 57.43 seconds
Started Nov 22 01:13:47 PM PST 23
Finished Nov 22 01:14:53 PM PST 23
Peak memory 248816 kb
Host smart-209731c1-3d36-4341-ae6d-da9d866c1d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84192
272413397382569910863463032164977881140276923082240444871800843325566825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_h
andler_smoke.84192272413397382569910863463032164977881140276923082240444871800843325566825
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.27466427289253510362495757177802735992662020887636797744858126104043451543929
Short name T381
Test name
Test status
Simulation time 63383433172 ps
CPU time 2184.76 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:50:22 PM PST 23
Peak memory 289780 kb
Host smart-25f31991-11d5-4dd9-8da0-e4244b0da936
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27466427289253510362495757177802735992662020887636797744858126104043451543929 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.27466427289253510362495757177802735992662020887636797744858126
104043451543929
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.28946313797384004461032589441470982506084388734551958899911465319225490648589
Short name T256
Test name
Test status
Simulation time 79866015596 ps
CPU time 2938.64 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 02:02:56 PM PST 23
Peak memory 298184 kb
Host smart-e8345d62-0bd0-463d-aa1a-c9efc285e800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289463137973840044610325894414709825060843887345
51958899911465319225490648589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.28946313
797384004461032589441470982506084388734551958899911465319225490648589
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.28445867361509831239842689207757451749242813387637614719005850313976344761419
Short name T510
Test name
Test status
Simulation time 30823729350 ps
CPU time 1086.03 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:32:03 PM PST 23
Peak memory 272284 kb
Host smart-81f66f9a-d12b-4aca-817d-10b5546fbcd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28445867361509831239842689207757451749242813387637614719005850313976344761419 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.alert_handler_entropy.28445867361509831239842689207757451749242813387637614719005850313976344761419
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.106476380511303437060595718710857473319322844198415830641534135496373712583804
Short name T521
Test name
Test status
Simulation time 6994902141 ps
CPU time 252.76 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:18:09 PM PST 23
Peak memory 251224 kb
Host smart-08125fc8-c5f9-41d8-83b1-0f0771ba1432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10647
6380511303437060595718710857473319322844198415830641534135496373712583804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.alert_handler_esc_alert_accum.106476380511303437060595718710857473319322844198415830641534135496373712583804
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.49665577123538727109019479080700891084669391558139990648662501134160512626516
Short name T389
Test name
Test status
Simulation time 1449142936 ps
CPU time 51.87 seconds
Started Nov 22 01:13:46 PM PST 23
Finished Nov 22 01:14:47 PM PST 23
Peak memory 255600 kb
Host smart-c145c5f8-7f92-4dbb-b71a-db854fbfb18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49665
577123538727109019479080700891084669391558139990648662501134160512626516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.alert_handler_esc_intr_timeout.49665577123538727109019479080700891084669391558139990648662501134160512626516
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4251728943501335593880484012041313734694610906986512264625494174536195563367
Short name T38
Test name
Test status
Simulation time 58351884139 ps
CPU time 1828.65 seconds
Started Nov 22 01:13:47 PM PST 23
Finished Nov 22 01:44:25 PM PST 23
Peak memory 289264 kb
Host smart-847876e4-6090-4ceb-b752-7b2e840499d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251728943501335593880484012041313734694610906986512264625494174536195563367 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.alert_handler_lpg.4251728943501335593880484012041313734694610906986512264625494174536195563367
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.43164638271427228834069018653744973426527706114137628633828666688211270401897
Short name T553
Test name
Test status
Simulation time 48172572717 ps
CPU time 1596.72 seconds
Started Nov 22 01:13:57 PM PST 23
Finished Nov 22 01:40:37 PM PST 23
Peak memory 272500 kb
Host smart-9cfc232d-6008-426d-8c49-335dff1538c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43164638271427228834069018653744973426527706114137628633828666688211270401897 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.43164638271427228834069018653744973426527706114137628633828666688211270401897
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.59349532640491129936716922728462358302030208797296117615321401661396947441558
Short name T617
Test name
Test status
Simulation time 17273552054 ps
CPU time 387.1 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:20:24 PM PST 23
Peak memory 247548 kb
Host smart-9bc7c39c-a70f-42e9-b10a-7f11fb649713
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59349532640491129936716922728462358302030208797296117615321401661396947441558 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.59349532640491129936716922728462358302030208797296117615321401661396947441558
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.69369781709866255053880299925947825748682095775972789830694339290566018728906
Short name T73
Test name
Test status
Simulation time 1399732617 ps
CPU time 52.17 seconds
Started Nov 22 01:13:51 PM PST 23
Finished Nov 22 01:14:50 PM PST 23
Peak memory 255408 kb
Host smart-4bee452f-f644-41ab-8e76-4a66111cd50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69369
781709866255053880299925947825748682095775972789830694339290566018728906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.alert_handler_random_alerts.69369781709866255053880299925947825748682095775972789830694339290566018728906
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.11370828675254765845691227775924838812358485538226853330103797812246559119998
Short name T274
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.85 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:14:41 PM PST 23
Peak memory 254820 kb
Host smart-6d039a5f-506c-4aaa-a62d-35d5fc4252cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11370
828675254765845691227775924838812358485538226853330103797812246559119998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.alert_handler_random_classes.11370828675254765845691227775924838812358485538226853330103797812246559119998
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.11235376464072592201105203484265162198440120145425295053460473025084092634750
Short name T427
Test name
Test status
Simulation time 1261680150 ps
CPU time 47.45 seconds
Started Nov 22 01:13:46 PM PST 23
Finished Nov 22 01:14:42 PM PST 23
Peak memory 255472 kb
Host smart-b3acac9d-d1a5-4781-a793-fd3324d7722f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
376464072592201105203484265162198440120145425295053460473025084092634750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
alert_handler_sig_int_fail.11235376464072592201105203484265162198440120145425295053460473025084092634750
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.25381740376546875906846785115747152027342321389476352359391880271621551407572
Short name T474
Test name
Test status
Simulation time 1558784916 ps
CPU time 49.21 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:14:47 PM PST 23
Peak memory 248660 kb
Host smart-af9bfd6c-b9c8-4dd7-b52d-067ec0466463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381
740376546875906846785115747152027342321389476352359391880271621551407572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_h
andler_smoke.25381740376546875906846785115747152027342321389476352359391880271621551407572
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.105031473074278003654592485165269634127861564605360436654420709834133776944472
Short name T379
Test name
Test status
Simulation time 63383433172 ps
CPU time 2074.77 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:48:32 PM PST 23
Peak memory 289660 kb
Host smart-e7fc6bea-211d-4c9f-b4ab-8c7b5feeb4a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105031473074278003654592485165269634127861564605360436654420709834133776944472 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.1050314730742780036545924851652696341278615646053604366544207
09834133776944472
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.63952849419324331288002726943457618151881301971935963665863408990036217829029
Short name T388
Test name
Test status
Simulation time 79866015596 ps
CPU time 2919.66 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 02:02:37 PM PST 23
Peak memory 298184 kb
Host smart-a2d2d07b-aef7-4c0d-8d9e-0380690d5e84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639528494193243312880027269434576181518813019719
35963665863408990036217829029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.63952849
419324331288002726943457618151881301971935963665863408990036217829029
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.93109944374285307086321621999645086393544616709120103790365933100636720048263
Short name T684
Test name
Test status
Simulation time 30823729350 ps
CPU time 1040.18 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:31:17 PM PST 23
Peak memory 272484 kb
Host smart-b9f0c040-01d9-4763-9b44-282fc5263d15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93109944374285307086321621999645086393544616709120103790365933100636720048263 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.alert_handler_entropy.93109944374285307086321621999645086393544616709120103790365933100636720048263
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.78032726855401669811877636980644251298758511902616009655359293602618287524259
Short name T692
Test name
Test status
Simulation time 6994902141 ps
CPU time 244.66 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:18:01 PM PST 23
Peak memory 251224 kb
Host smart-18c3afb2-f97f-45b5-bc40-7911a5893934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78032
726855401669811877636980644251298758511902616009655359293602618287524259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.alert_handler_esc_alert_accum.78032726855401669811877636980644251298758511902616009655359293602618287524259
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.73071405826471777216043118404847426294124367961210585928548267352407030963320
Short name T399
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.81 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:14:45 PM PST 23
Peak memory 255544 kb
Host smart-ce693b72-72a4-4d30-a77b-fa4c5dd2436d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73071
405826471777216043118404847426294124367961210585928548267352407030963320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.alert_handler_esc_intr_timeout.73071405826471777216043118404847426294124367961210585928548267352407030963320
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.41738097287176093703273032221901219075281064842865330762476880244801822969481
Short name T599
Test name
Test status
Simulation time 58351884139 ps
CPU time 1846 seconds
Started Nov 22 01:13:47 PM PST 23
Finished Nov 22 01:44:42 PM PST 23
Peak memory 288996 kb
Host smart-db48f930-7943-4ed4-b929-a373d941e85c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41738097287176093703273032221901219075281064842865330762476880244801822969481 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.alert_handler_lpg.41738097287176093703273032221901219075281064842865330762476880244801822969481
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.78368431323678175475671971265739306794150353822359340873108320408115262326101
Short name T623
Test name
Test status
Simulation time 48172572717 ps
CPU time 1564.47 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 272404 kb
Host smart-89fd063f-738a-42a2-a014-da0642562863
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78368431323678175475671971265739306794150353822359340873108320408115262326101 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.78368431323678175475671971265739306794150353822359340873108320408115262326101
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.82289215866872992180844672736970735146514289093353024189410611058049523052658
Short name T653
Test name
Test status
Simulation time 17273552054 ps
CPU time 420.84 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:20:58 PM PST 23
Peak memory 247540 kb
Host smart-b6fadb2b-8fcb-4bb9-a5da-b44dd4743d7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82289215866872992180844672736970735146514289093353024189410611058049523052658 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.82289215866872992180844672736970735146514289093353024189410611058049523052658
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.98847615667878446512531881922066918061640608050401741279932509693230399824846
Short name T555
Test name
Test status
Simulation time 1399732617 ps
CPU time 45.67 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:14:42 PM PST 23
Peak memory 255492 kb
Host smart-b1a4ffd2-e340-4846-a0cd-f6a8f3fab184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98847
615667878446512531881922066918061640608050401741279932509693230399824846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.alert_handler_random_alerts.98847615667878446512531881922066918061640608050401741279932509693230399824846
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.28598966416695391208606805833829535964141443820944498244576016538678676649024
Short name T331
Test name
Test status
Simulation time 1291269199 ps
CPU time 49.8 seconds
Started Nov 22 01:13:49 PM PST 23
Finished Nov 22 01:14:47 PM PST 23
Peak memory 254872 kb
Host smart-d57575d5-c782-43c7-91c5-dcb2dac2f848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28598
966416695391208606805833829535964141443820944498244576016538678676649024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.alert_handler_random_classes.28598966416695391208606805833829535964141443820944498244576016538678676649024
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.38711867993975820861438258605630965911464891455188904078742103871386753724236
Short name T354
Test name
Test status
Simulation time 1261680150 ps
CPU time 42.86 seconds
Started Nov 22 01:13:47 PM PST 23
Finished Nov 22 01:14:38 PM PST 23
Peak memory 255420 kb
Host smart-08ef6b00-31ab-47e7-b603-7bca775ec5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
867993975820861438258605630965911464891455188904078742103871386753724236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
alert_handler_sig_int_fail.38711867993975820861438258605630965911464891455188904078742103871386753724236
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.98975728953498088056452036800539685930855241413875590824643646827012148744734
Short name T573
Test name
Test status
Simulation time 1558784916 ps
CPU time 49.3 seconds
Started Nov 22 01:13:53 PM PST 23
Finished Nov 22 01:14:48 PM PST 23
Peak memory 248848 kb
Host smart-d99ca56f-7dae-415a-a0af-73b61f4f32af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98975
728953498088056452036800539685930855241413875590824643646827012148744734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_h
andler_smoke.98975728953498088056452036800539685930855241413875590824643646827012148744734
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.109189211617293384508054299185299387363765228442058584647317619265113096563047
Short name T194
Test name
Test status
Simulation time 79866015596 ps
CPU time 2637.31 seconds
Started Nov 22 01:13:53 PM PST 23
Finished Nov 22 01:57:56 PM PST 23
Peak memory 298200 kb
Host smart-0c060331-b392-42b0-830c-57d257001e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109189211617293384508054299185299387363765228442
058584647317619265113096563047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1091892
11617293384508054299185299387363765228442058584647317619265113096563047
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.7939060685328408232980731842360815426546693192121866335140941616280877848461
Short name T416
Test name
Test status
Simulation time 30823729350 ps
CPU time 1018.1 seconds
Started Nov 22 01:13:58 PM PST 23
Finished Nov 22 01:30:59 PM PST 23
Peak memory 272432 kb
Host smart-ba41cfde-6e98-49f5-9cf6-8989ce6dcfec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7939060685328408232980731842360815426546693192121866335140941616280877848461 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.alert_handler_entropy.7939060685328408232980731842360815426546693192121866335140941616280877848461
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.45273600993221267162611758428519681162926642363975409579500772596868361526686
Short name T674
Test name
Test status
Simulation time 6994902141 ps
CPU time 239.52 seconds
Started Nov 22 01:13:58 PM PST 23
Finished Nov 22 01:18:00 PM PST 23
Peak memory 251184 kb
Host smart-88f3e83a-7323-4dfe-a697-36c8e69060df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45273
600993221267162611758428519681162926642363975409579500772596868361526686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.alert_handler_esc_alert_accum.45273600993221267162611758428519681162926642363975409579500772596868361526686
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.25558698633416902260224353544002937092437273410679657066003937425510887858452
Short name T148
Test name
Test status
Simulation time 1449142936 ps
CPU time 51.46 seconds
Started Nov 22 01:13:52 PM PST 23
Finished Nov 22 01:14:50 PM PST 23
Peak memory 255412 kb
Host smart-5e5d7d86-11d0-4e9b-bdd6-84cdebcf10ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25558
698633416902260224353544002937092437273410679657066003937425510887858452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.alert_handler_esc_intr_timeout.25558698633416902260224353544002937092437273410679657066003937425510887858452
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.40985862517340918445123861160339297589926919514398135058714588139398832574372
Short name T556
Test name
Test status
Simulation time 58351884139 ps
CPU time 1868.42 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:45:06 PM PST 23
Peak memory 289316 kb
Host smart-bfa5ba0d-5789-4fb5-b8bf-66286a7c774a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40985862517340918445123861160339297589926919514398135058714588139398832574372 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.alert_handler_lpg.40985862517340918445123861160339297589926919514398135058714588139398832574372
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.31291077867145255592384251385291525307884103619182171260330397136455586970228
Short name T512
Test name
Test status
Simulation time 48172572717 ps
CPU time 1679.01 seconds
Started Nov 22 01:14:00 PM PST 23
Finished Nov 22 01:42:01 PM PST 23
Peak memory 272292 kb
Host smart-77ba7d06-0221-49b3-9ddb-90aa015a7e0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31291077867145255592384251385291525307884103619182171260330397136455586970228 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.31291077867145255592384251385291525307884103619182171260330397136455586970228
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.83328470955906618079611506331782078960913101894533533250290914279395595714000
Short name T571
Test name
Test status
Simulation time 17273552054 ps
CPU time 403.12 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:20:41 PM PST 23
Peak memory 247340 kb
Host smart-24f1d457-6a7f-40c9-b3a5-073d676e7759
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83328470955906618079611506331782078960913101894533533250290914279395595714000 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.83328470955906618079611506331782078960913101894533533250290914279395595714000
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.104278931397616732908141834825003852825217641019415316309106169764179111308981
Short name T35
Test name
Test status
Simulation time 1399732617 ps
CPU time 48.95 seconds
Started Nov 22 01:13:59 PM PST 23
Finished Nov 22 01:14:50 PM PST 23
Peak memory 255360 kb
Host smart-34dc58a3-98f9-41fd-b77a-0a30b8bdf6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10427
8931397616732908141834825003852825217641019415316309106169764179111308981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.alert_handler_random_alerts.104278931397616732908141834825003852825217641019415316309106169764179111308981
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.113994357087804278350803047576995236473214843152885547139692080717908378795887
Short name T437
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.67 seconds
Started Nov 22 01:13:56 PM PST 23
Finished Nov 22 01:14:45 PM PST 23
Peak memory 254772 kb
Host smart-d0dbd8b3-e0c0-4a0f-ac03-0541cc6d0070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11399
4357087804278350803047576995236473214843152885547139692080717908378795887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.alert_handler_random_classes.113994357087804278350803047576995236473214843152885547139692080717908378795887
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.12898677354621398591121283534338411437220355060451442824896385423550904426166
Short name T170
Test name
Test status
Simulation time 1261680150 ps
CPU time 47.63 seconds
Started Nov 22 01:13:57 PM PST 23
Finished Nov 22 01:14:48 PM PST 23
Peak memory 255488 kb
Host smart-272bb5cf-508f-4420-b8d4-63b9e481fd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
677354621398591121283534338411437220355060451442824896385423550904426166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
alert_handler_sig_int_fail.12898677354621398591121283534338411437220355060451442824896385423550904426166
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.94273053410623262158086133149162182886375080786189761684162890340901081644358
Short name T221
Test name
Test status
Simulation time 1558784916 ps
CPU time 52.07 seconds
Started Nov 22 01:13:52 PM PST 23
Finished Nov 22 01:14:50 PM PST 23
Peak memory 248652 kb
Host smart-d5606e66-42bf-4151-960e-bb55ac72da4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94273
053410623262158086133149162182886375080786189761684162890340901081644358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_h
andler_smoke.94273053410623262158086133149162182886375080786189761684162890340901081644358
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.29620103920405175704518270851086223761936321342171361811057140499515296506429
Short name T283
Test name
Test status
Simulation time 63383433172 ps
CPU time 2092.41 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 01:48:49 PM PST 23
Peak memory 289784 kb
Host smart-0d68341f-33cf-4b3b-906d-1ddb3a2ffbad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29620103920405175704518270851086223761936321342171361811057140499515296506429 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.29620103920405175704518270851086223761936321342171361811057140
499515296506429
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.59422823375730789793990404501063846985159233945819163261512347698336151302732
Short name T680
Test name
Test status
Simulation time 79866015596 ps
CPU time 2852.79 seconds
Started Nov 22 01:13:48 PM PST 23
Finished Nov 22 02:01:30 PM PST 23
Peak memory 298192 kb
Host smart-eee2662d-346f-4013-b800-6e3628807e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594228233757307897939904045010638469851592339458
19163261512347698336151302732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.59422823
375730789793990404501063846985159233945819163261512347698336151302732
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.20118985443976056885648065922872578647520310860129164741532060061330178404981
Short name T153
Test name
Test status
Simulation time 30823729350 ps
CPU time 1227.83 seconds
Started Nov 22 01:14:00 PM PST 23
Finished Nov 22 01:34:30 PM PST 23
Peak memory 272272 kb
Host smart-9fae0de6-99f2-4287-961f-43af5b2c6465
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20118985443976056885648065922872578647520310860129164741532060061330178404981 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.alert_handler_entropy.20118985443976056885648065922872578647520310860129164741532060061330178404981
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.80478741404449567342273315528113273934320383389302824535473700440592824264326
Short name T593
Test name
Test status
Simulation time 6994902141 ps
CPU time 232.8 seconds
Started Nov 22 01:13:51 PM PST 23
Finished Nov 22 01:17:51 PM PST 23
Peak memory 251204 kb
Host smart-713cb51a-3b88-4adf-961c-8c19f45f6dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80478
741404449567342273315528113273934320383389302824535473700440592824264326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.alert_handler_esc_alert_accum.80478741404449567342273315528113273934320383389302824535473700440592824264326
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.99076652178516406233189992214800350562383382777947435123505870836606923725522
Short name T621
Test name
Test status
Simulation time 1449142936 ps
CPU time 52.47 seconds
Started Nov 22 01:13:54 PM PST 23
Finished Nov 22 01:14:51 PM PST 23
Peak memory 255624 kb
Host smart-fb9cf81a-8250-4dff-98b9-e7b814d7d4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99076
652178516406233189992214800350562383382777947435123505870836606923725522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.alert_handler_esc_intr_timeout.99076652178516406233189992214800350562383382777947435123505870836606923725522
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.71566294384902032233239122092661339129881165121354524488227401276137525637221
Short name T86
Test name
Test status
Simulation time 58351884139 ps
CPU time 1898.52 seconds
Started Nov 22 01:14:00 PM PST 23
Finished Nov 22 01:45:40 PM PST 23
Peak memory 289240 kb
Host smart-070cb991-e169-47d3-85bf-1299aad227d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71566294384902032233239122092661339129881165121354524488227401276137525637221 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.alert_handler_lpg.71566294384902032233239122092661339129881165121354524488227401276137525637221
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.14728634502543734085956636883815457994595381036225998753808573080554233768074
Short name T367
Test name
Test status
Simulation time 48172572717 ps
CPU time 1608.2 seconds
Started Nov 22 01:14:00 PM PST 23
Finished Nov 22 01:40:50 PM PST 23
Peak memory 272292 kb
Host smart-e9b87904-ddae-467c-91f6-72f470fd1897
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14728634502543734085956636883815457994595381036225998753808573080554233768074 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.14728634502543734085956636883815457994595381036225998753808573080554233768074
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3852258575505624453315404608182688596625287334837699798061800107757402959055
Short name T140
Test name
Test status
Simulation time 17273552054 ps
CPU time 409.31 seconds
Started Nov 22 01:13:52 PM PST 23
Finished Nov 22 01:20:48 PM PST 23
Peak memory 247384 kb
Host smart-19693649-a100-4222-9d04-00432a117f1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852258575505624453315404608182688596625287334837699798061800107757402959055 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3852258575505624453315404608182688596625287334837699798061800107757402959055
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.95682288539560975706384129293882195204420638411143488253515876954338814053185
Short name T223
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.14 seconds
Started Nov 22 01:13:51 PM PST 23
Finished Nov 22 01:14:45 PM PST 23
Peak memory 255436 kb
Host smart-b17fed0d-49c5-4ba4-b9c1-eb82a121c99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95682
288539560975706384129293882195204420638411143488253515876954338814053185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.alert_handler_random_alerts.95682288539560975706384129293882195204420638411143488253515876954338814053185
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.8798233188979226995444773041213095139773444389753453970371351358466966825053
Short name T59
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.05 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:14:40 PM PST 23
Peak memory 254816 kb
Host smart-8055c6f0-e7b5-41b2-b761-290836d356c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87982
33188979226995444773041213095139773444389753453970371351358466966825053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.alert_handler_random_classes.8798233188979226995444773041213095139773444389753453970371351358466966825053
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.56067867012881883556202813318611685118789706494340419656831490532679807535636
Short name T377
Test name
Test status
Simulation time 1261680150 ps
CPU time 47.82 seconds
Started Nov 22 01:13:50 PM PST 23
Finished Nov 22 01:14:45 PM PST 23
Peak memory 255552 kb
Host smart-4a01d399-a8c1-4487-905c-cbc65271f9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56067
867012881883556202813318611685118789706494340419656831490532679807535636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
alert_handler_sig_int_fail.56067867012881883556202813318611685118789706494340419656831490532679807535636
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.41818200804215483347149825721157272769326200095000639589624366106911154390217
Short name T323
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.08 seconds
Started Nov 22 01:13:51 PM PST 23
Finished Nov 22 01:14:48 PM PST 23
Peak memory 248780 kb
Host smart-9d8698a4-adf1-490c-af13-2cfff8d07980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41818
200804215483347149825721157272769326200095000639589624366106911154390217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_h
andler_smoke.41818200804215483347149825721157272769326200095000639589624366106911154390217
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.58948612693599717349086750570612733903869702457647233689866581055531477576041
Short name T300
Test name
Test status
Simulation time 63383433172 ps
CPU time 1965.13 seconds
Started Nov 22 01:13:58 PM PST 23
Finished Nov 22 01:46:46 PM PST 23
Peak memory 289724 kb
Host smart-5200402b-c878-48b5-b5c3-754bd4010679
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58948612693599717349086750570612733903869702457647233689866581055531477576041 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.58948612693599717349086750570612733903869702457647233689866581
055531477576041
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.5231831261119415497361026145517475888551837547628130456656651234506325817788
Short name T642
Test name
Test status
Simulation time 79866015596 ps
CPU time 2818.29 seconds
Started Nov 22 01:14:01 PM PST 23
Finished Nov 22 02:01:01 PM PST 23
Peak memory 298128 kb
Host smart-29a403e7-c72e-458e-a714-f2b331ab4c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523183126111941549736102614551747588855183754762
8130456656651234506325817788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.523183126
1119415497361026145517475888551837547628130456656651234506325817788
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.102491247705432008621522019803736015445268460298777546259968167608294821514752
Short name T695
Test name
Test status
Simulation time 30823729350 ps
CPU time 1015.16 seconds
Started Nov 22 01:13:58 PM PST 23
Finished Nov 22 01:30:56 PM PST 23
Peak memory 272432 kb
Host smart-03bc4abe-9ea1-47a5-a365-3f532afee2a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102491247705432008621522019803736015445268460298777546259968167608294821514752 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.alert_handler_entropy.102491247705432008621522019803736015445268460298777546259968167608294821514752
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.105307766028205010847391102317568259764194431904942474258814104130288993710953
Short name T583
Test name
Test status
Simulation time 6994902141 ps
CPU time 233.49 seconds
Started Nov 22 01:13:58 PM PST 23
Finished Nov 22 01:17:54 PM PST 23
Peak memory 251184 kb
Host smart-1068fb78-a187-4949-8c0c-df3b2875a99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10530
7766028205010847391102317568259764194431904942474258814104130288993710953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.alert_handler_esc_alert_accum.105307766028205010847391102317568259764194431904942474258814104130288993710953
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.5614026971980489021924490674874131336639950560280091026983730787118999879388
Short name T255
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.17 seconds
Started Nov 22 01:14:01 PM PST 23
Finished Nov 22 01:14:50 PM PST 23
Peak memory 255604 kb
Host smart-4bc88f9f-2e48-47ad-a310-0d00e0d418b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56140
26971980489021924490674874131336639950560280091026983730787118999879388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.alert_handler_esc_intr_timeout.5614026971980489021924490674874131336639950560280091026983730787118999879388
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.97706912690848526091051753892405371208560013665054796744650938962175884198553
Short name T676
Test name
Test status
Simulation time 58351884139 ps
CPU time 1884.25 seconds
Started Nov 22 01:14:07 PM PST 23
Finished Nov 22 01:45:33 PM PST 23
Peak memory 289196 kb
Host smart-b7431642-b698-4961-93c3-fbace1427b89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97706912690848526091051753892405371208560013665054796744650938962175884198553 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.alert_handler_lpg.97706912690848526091051753892405371208560013665054796744650938962175884198553
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.104814602803554283151792047093768103273188979670333700403861545854939054896601
Short name T53
Test name
Test status
Simulation time 48172572717 ps
CPU time 1547.08 seconds
Started Nov 22 01:14:13 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 272356 kb
Host smart-6336cbcc-d3e3-4a41-9dc9-23816f3aa22b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104814602803554283151792047093768103273188979670333700403861545854939054896601 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.104814602803554283151792047093768103273188979670333700403861545854939054896601
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.37913569613852504809346811524787366358132129816265124799736828049486930807263
Short name T523
Test name
Test status
Simulation time 17273552054 ps
CPU time 394.74 seconds
Started Nov 22 01:14:00 PM PST 23
Finished Nov 22 01:20:37 PM PST 23
Peak memory 247472 kb
Host smart-024d2e1e-8b2a-4429-a0d9-8c7e29b5d369
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37913569613852504809346811524787366358132129816265124799736828049486930807263 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.37913569613852504809346811524787366358132129816265124799736828049486930807263
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.112538856527381025674478763821396677338623848272846426369319436993518536467369
Short name T434
Test name
Test status
Simulation time 1399732617 ps
CPU time 49.92 seconds
Started Nov 22 01:13:59 PM PST 23
Finished Nov 22 01:14:51 PM PST 23
Peak memory 255432 kb
Host smart-0b11600e-84b1-4322-b802-5e536af9cf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11253
8856527381025674478763821396677338623848272846426369319436993518536467369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.alert_handler_random_alerts.112538856527381025674478763821396677338623848272846426369319436993518536467369
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.113750981407786126343213967921868769205485645402566296226527901749469723887163
Short name T290
Test name
Test status
Simulation time 1291269199 ps
CPU time 42.01 seconds
Started Nov 22 01:13:56 PM PST 23
Finished Nov 22 01:14:41 PM PST 23
Peak memory 254812 kb
Host smart-c07434ce-2d41-45ac-bc94-f981efe0c464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11375
0981407786126343213967921868769205485645402566296226527901749469723887163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.alert_handler_random_classes.113750981407786126343213967921868769205485645402566296226527901749469723887163
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.37215945801220253400424917011391916718662112479309996562915551434839065256667
Short name T615
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.96 seconds
Started Nov 22 01:13:57 PM PST 23
Finished Nov 22 01:14:45 PM PST 23
Peak memory 255476 kb
Host smart-2b3814b6-69e8-4eb6-b3f4-498230f15ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37215
945801220253400424917011391916718662112479309996562915551434839065256667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
alert_handler_sig_int_fail.37215945801220253400424917011391916718662112479309996562915551434839065256667
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.72164068781057666921450550288214475523078857941027358300110928382658457009476
Short name T172
Test name
Test status
Simulation time 1558784916 ps
CPU time 49.58 seconds
Started Nov 22 01:13:59 PM PST 23
Finished Nov 22 01:14:51 PM PST 23
Peak memory 248796 kb
Host smart-2eac073b-6059-4935-9e43-bc7108612773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72164
068781057666921450550288214475523078857941027358300110928382658457009476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_h
andler_smoke.72164068781057666921450550288214475523078857941027358300110928382658457009476
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.17809725621805358852849808715394250530945274227858673117647763523292535263926
Short name T488
Test name
Test status
Simulation time 63383433172 ps
CPU time 2048.51 seconds
Started Nov 22 01:14:13 PM PST 23
Finished Nov 22 01:48:22 PM PST 23
Peak memory 289624 kb
Host smart-a36b143b-673a-424f-9986-8946892914a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17809725621805358852849808715394250530945274227858673117647763523292535263926 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.17809725621805358852849808715394250530945274227858673117647763
523292535263926
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.45287798787410724546799963840991534222116281695785556227853735949235077398540
Short name T169
Test name
Test status
Simulation time 79866015596 ps
CPU time 2798.77 seconds
Started Nov 22 01:14:06 PM PST 23
Finished Nov 22 02:00:46 PM PST 23
Peak memory 298192 kb
Host smart-0ede3567-74bc-4745-b303-299ce1fc1c25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452877987874107245467999638409915342221162816957
85556227853735949235077398540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.45287798
787410724546799963840991534222116281695785556227853735949235077398540
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.108557324316152648225575625818975913245002381772405035417173696402196304780723
Short name T155
Test name
Test status
Simulation time 30823729350 ps
CPU time 1166.93 seconds
Started Nov 22 01:14:10 PM PST 23
Finished Nov 22 01:33:38 PM PST 23
Peak memory 272464 kb
Host smart-600f5ee9-6c35-4330-b3b6-305811a5481a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108557324316152648225575625818975913245002381772405035417173696402196304780723 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.alert_handler_entropy.108557324316152648225575625818975913245002381772405035417173696402196304780723
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.84269494811960976232278730383036664183178149222496762550402549577447235666358
Short name T134
Test name
Test status
Simulation time 6994902141 ps
CPU time 233.97 seconds
Started Nov 22 01:14:07 PM PST 23
Finished Nov 22 01:18:02 PM PST 23
Peak memory 251208 kb
Host smart-77fb2265-37b9-45e1-a599-05934a6b1436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84269
494811960976232278730383036664183178149222496762550402549577447235666358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.alert_handler_esc_alert_accum.84269494811960976232278730383036664183178149222496762550402549577447235666358
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.58873218131142192097990686900301691880663633128783970487294641711798400889241
Short name T351
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.01 seconds
Started Nov 22 01:14:04 PM PST 23
Finished Nov 22 01:14:54 PM PST 23
Peak memory 255624 kb
Host smart-fd30eb87-6980-4e01-ac81-82d20a973e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58873
218131142192097990686900301691880663633128783970487294641711798400889241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.alert_handler_esc_intr_timeout.58873218131142192097990686900301691880663633128783970487294641711798400889241
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.71569327236449445635698786668110925476829038751821708419364887425375093412164
Short name T581
Test name
Test status
Simulation time 58351884139 ps
CPU time 1810.57 seconds
Started Nov 22 01:14:11 PM PST 23
Finished Nov 22 01:44:22 PM PST 23
Peak memory 289220 kb
Host smart-da48fd27-8b30-4c2a-aaaa-70fc7fef8c09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71569327236449445635698786668110925476829038751821708419364887425375093412164 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.alert_handler_lpg.71569327236449445635698786668110925476829038751821708419364887425375093412164
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.16691232063030088961438443516599254987050126093285792494164605365792626141994
Short name T160
Test name
Test status
Simulation time 48172572717 ps
CPU time 1690.92 seconds
Started Nov 22 01:14:09 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 272520 kb
Host smart-1c76cee7-ee14-4609-a845-a609be80ecce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16691232063030088961438443516599254987050126093285792494164605365792626141994 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.16691232063030088961438443516599254987050126093285792494164605365792626141994
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.11286489943082770289678200180967889454978769484516766798655452952301286348874
Short name T361
Test name
Test status
Simulation time 17273552054 ps
CPU time 389.04 seconds
Started Nov 22 01:14:06 PM PST 23
Finished Nov 22 01:20:36 PM PST 23
Peak memory 247420 kb
Host smart-add5f864-7649-41e9-a9a6-1de71f916bcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11286489943082770289678200180967889454978769484516766798655452952301286348874 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.11286489943082770289678200180967889454978769484516766798655452952301286348874
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.45705368703579558440469674882774760609059569557958715958681915354966896095145
Short name T368
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.53 seconds
Started Nov 22 01:14:06 PM PST 23
Finished Nov 22 01:14:54 PM PST 23
Peak memory 255468 kb
Host smart-4368e60e-e788-40fe-8333-e2e5489088a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45705
368703579558440469674882774760609059569557958715958681915354966896095145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.alert_handler_random_alerts.45705368703579558440469674882774760609059569557958715958681915354966896095145
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.36500853039366115341087734653276813620367956569226503225244989474503309979338
Short name T409
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.54 seconds
Started Nov 22 01:14:04 PM PST 23
Finished Nov 22 01:14:51 PM PST 23
Peak memory 254864 kb
Host smart-5a27b549-e819-4226-9761-f52342227d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500
853039366115341087734653276813620367956569226503225244989474503309979338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.alert_handler_random_classes.36500853039366115341087734653276813620367956569226503225244989474503309979338
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.74409804098307287823360835961530519720688948924471036332668015191677250815046
Short name T226
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.56 seconds
Started Nov 22 01:14:08 PM PST 23
Finished Nov 22 01:14:53 PM PST 23
Peak memory 255420 kb
Host smart-b9e1b43a-fa99-406d-b178-3af89b5ee106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74409
804098307287823360835961530519720688948924471036332668015191677250815046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
alert_handler_sig_int_fail.74409804098307287823360835961530519720688948924471036332668015191677250815046
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.55389315880526342633543827035583740700817061972989853003848301224318014970298
Short name T385
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.46 seconds
Started Nov 22 01:14:08 PM PST 23
Finished Nov 22 01:15:00 PM PST 23
Peak memory 248836 kb
Host smart-52c9fd82-b9f3-4680-8961-e4dca2c15777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55389
315880526342633543827035583740700817061972989853003848301224318014970298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_h
andler_smoke.55389315880526342633543827035583740700817061972989853003848301224318014970298
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.21040299659719542146691642717327861494399722792544109681192254688537126828387
Short name T299
Test name
Test status
Simulation time 63383433172 ps
CPU time 2028.63 seconds
Started Nov 22 01:14:08 PM PST 23
Finished Nov 22 01:47:57 PM PST 23
Peak memory 289780 kb
Host smart-9d02787d-a3df-47fc-9305-dc2794f86986
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21040299659719542146691642717327861494399722792544109681192254688537126828387 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.21040299659719542146691642717327861494399722792544109681192254
688537126828387
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.87659690450904454646416569912390825539684330344892273001334872200832940170765
Short name T378
Test name
Test status
Simulation time 79866015596 ps
CPU time 2784.79 seconds
Started Nov 22 01:14:05 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 298196 kb
Host smart-86ac38ea-bd21-476c-9bc3-a6eeef34e325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876596904509044546464165699123908255396843303448
92273001334872200832940170765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.87659690
450904454646416569912390825539684330344892273001334872200832940170765
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.48332866648581834961681440992931058006173877512175315520033078269662877553766
Short name T276
Test name
Test status
Simulation time 30823729350 ps
CPU time 1002.72 seconds
Started Nov 22 01:14:10 PM PST 23
Finished Nov 22 01:30:54 PM PST 23
Peak memory 272356 kb
Host smart-6a28a809-2c3f-4a55-a813-6e8bbd4d098d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48332866648581834961681440992931058006173877512175315520033078269662877553766 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.alert_handler_entropy.48332866648581834961681440992931058006173877512175315520033078269662877553766
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.111766971683427073362180771057191505493254005935384088826722025729303746333556
Short name T634
Test name
Test status
Simulation time 6994902141 ps
CPU time 240.2 seconds
Started Nov 22 01:14:05 PM PST 23
Finished Nov 22 01:18:06 PM PST 23
Peak memory 251220 kb
Host smart-0bd028d0-1855-4a05-b1f2-0cab17d910d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
6971683427073362180771057191505493254005935384088826722025729303746333556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.alert_handler_esc_alert_accum.111766971683427073362180771057191505493254005935384088826722025729303746333556
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.69039004968254110684967209991658511730783380749212000395498826501480533951746
Short name T307
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.84 seconds
Started Nov 22 01:14:11 PM PST 23
Finished Nov 22 01:15:00 PM PST 23
Peak memory 255636 kb
Host smart-43ccc103-38b6-454b-9fcf-b4a80fe41114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69039
004968254110684967209991658511730783380749212000395498826501480533951746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.alert_handler_esc_intr_timeout.69039004968254110684967209991658511730783380749212000395498826501480533951746
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.14083033549659338625644109267109520828523408896460671183618033405701817829809
Short name T241
Test name
Test status
Simulation time 58351884139 ps
CPU time 1841.77 seconds
Started Nov 22 01:14:06 PM PST 23
Finished Nov 22 01:44:49 PM PST 23
Peak memory 289332 kb
Host smart-f379b7ff-1ef9-4c5f-95b1-af7af7c1fe47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14083033549659338625644109267109520828523408896460671183618033405701817829809 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.alert_handler_lpg.14083033549659338625644109267109520828523408896460671183618033405701817829809
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.89591537828314339831629059218087726152315440896519854843341887192630008290851
Short name T369
Test name
Test status
Simulation time 48172572717 ps
CPU time 1544.58 seconds
Started Nov 22 01:14:04 PM PST 23
Finished Nov 22 01:39:51 PM PST 23
Peak memory 272488 kb
Host smart-74a3d105-a86a-4192-a9d5-d3c65e182b00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89591537828314339831629059218087726152315440896519854843341887192630008290851 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.89591537828314339831629059218087726152315440896519854843341887192630008290851
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.75810742611810356814716280230302375809750069312674822748484265786806629413303
Short name T575
Test name
Test status
Simulation time 17273552054 ps
CPU time 392.49 seconds
Started Nov 22 01:14:12 PM PST 23
Finished Nov 22 01:20:45 PM PST 23
Peak memory 247532 kb
Host smart-bca9bdf8-f80f-49ba-a446-f222a4cad62d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75810742611810356814716280230302375809750069312674822748484265786806629413303 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.75810742611810356814716280230302375809750069312674822748484265786806629413303
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.81450889445341269674110357197655277080957714185183375234883046927538034515549
Short name T328
Test name
Test status
Simulation time 1399732617 ps
CPU time 51.81 seconds
Started Nov 22 01:14:05 PM PST 23
Finished Nov 22 01:14:58 PM PST 23
Peak memory 255456 kb
Host smart-14e1c894-3a08-47c4-bb27-6a866027b92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81450
889445341269674110357197655277080957714185183375234883046927538034515549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.alert_handler_random_alerts.81450889445341269674110357197655277080957714185183375234883046927538034515549
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.20658300797051597577193040088771158811029052361655319217537660811150757623989
Short name T77
Test name
Test status
Simulation time 1291269199 ps
CPU time 44.08 seconds
Started Nov 22 01:14:12 PM PST 23
Finished Nov 22 01:14:57 PM PST 23
Peak memory 254768 kb
Host smart-17d9a4cf-033f-4167-b506-cdd83d0e6a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658
300797051597577193040088771158811029052361655319217537660811150757623989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.alert_handler_random_classes.20658300797051597577193040088771158811029052361655319217537660811150757623989
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2790190843854365724627739231209829016295385764588818176718005682202039171661
Short name T436
Test name
Test status
Simulation time 1261680150 ps
CPU time 46.31 seconds
Started Nov 22 01:14:05 PM PST 23
Finished Nov 22 01:14:52 PM PST 23
Peak memory 255540 kb
Host smart-6f84fab1-a007-4e59-95bc-630cf3a546da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
90843854365724627739231209829016295385764588818176718005682202039171661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.a
lert_handler_sig_int_fail.2790190843854365724627739231209829016295385764588818176718005682202039171661
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.59239099740565989646286550832501001839261488694884161015327643774495439157354
Short name T229
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.33 seconds
Started Nov 22 01:14:07 PM PST 23
Finished Nov 22 01:14:58 PM PST 23
Peak memory 248808 kb
Host smart-7e1de51c-21ae-409a-b701-10deab0873ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59239
099740565989646286550832501001839261488694884161015327643774495439157354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_h
andler_smoke.59239099740565989646286550832501001839261488694884161015327643774495439157354
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.52743198635464440787549556019276957424535824730209916147837766430837146424556
Short name T475
Test name
Test status
Simulation time 63383433172 ps
CPU time 2078.26 seconds
Started Nov 22 01:14:12 PM PST 23
Finished Nov 22 01:48:52 PM PST 23
Peak memory 289780 kb
Host smart-ec58798f-8170-4a06-bad2-70e313dfd7ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52743198635464440787549556019276957424535824730209916147837766430837146424556 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.52743198635464440787549556019276957424535824730209916147837766
430837146424556
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.10417918320148042126241729507899487039162826876661053930030375442484501181287
Short name T473
Test name
Test status
Simulation time 79866015596 ps
CPU time 2686.24 seconds
Started Nov 22 01:14:06 PM PST 23
Finished Nov 22 01:58:54 PM PST 23
Peak memory 297976 kb
Host smart-82df0fe6-10c2-462d-90ad-d49e2a64d85d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104179183201480421262417295078994870391628268766
61053930030375442484501181287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.10417918
320148042126241729507899487039162826876661053930030375442484501181287
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2064235466933381547623334736900552799076627906446952529253463663056336732462
Short name T118
Test name
Test status
Simulation time 49707703 ps
CPU time 2.81 seconds
Started Nov 22 01:12:39 PM PST 23
Finished Nov 22 01:12:48 PM PST 23
Peak memory 249036 kb
Host smart-21c8d776-1a35-4df9-ad75-449062371cce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2064235466933381547623334736900552799076627906446952529253463663056336732462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.alert_handler_alert_accum_saturation.2064235466933381547623334736900552799076627906446952529253463663056336732462
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.10337226092457193652069505910469454159705255004351790004080452436779612408735
Short name T572
Test name
Test status
Simulation time 30823729350 ps
CPU time 1091.09 seconds
Started Nov 22 01:12:29 PM PST 23
Finished Nov 22 01:30:47 PM PST 23
Peak memory 272456 kb
Host smart-876b80a3-c41c-4e2b-a48f-7ed603d35edd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10337226092457193652069505910469454159705255004351790004080452436779612408735 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.alert_handler_entropy.10337226092457193652069505910469454159705255004351790004080452436779612408735
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.60497368005277246654197857519008146967805170842680530728010222205058999171782
Short name T292
Test name
Test status
Simulation time 1452482195 ps
CPU time 35.74 seconds
Started Nov 22 01:12:32 PM PST 23
Finished Nov 22 01:13:14 PM PST 23
Peak memory 240624 kb
Host smart-e0c4a2c1-8dd2-4a97-9072-e43e7034fb3a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=60497368005277246654197857519008146967805170842680530728010222205058999171782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.alert_handler_entropy_stress.60497368005277246654197857519008146967805170842680530728010222205058999171782
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.62112263187785493613096468733946441154532150106568063587358241797860142244517
Short name T222
Test name
Test status
Simulation time 6994902141 ps
CPU time 238.58 seconds
Started Nov 22 01:12:12 PM PST 23
Finished Nov 22 01:16:13 PM PST 23
Peak memory 251224 kb
Host smart-581ff2ef-113d-48b1-8ca8-5acab63ad45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62112
263187785493613096468733946441154532150106568063587358241797860142244517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.alert_handler_esc_alert_accum.62112263187785493613096468733946441154532150106568063587358241797860142244517
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.98507978788598762740261054537865095418374827998385086308040749892714208135893
Short name T418
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.56 seconds
Started Nov 22 01:12:18 PM PST 23
Finished Nov 22 01:13:08 PM PST 23
Peak memory 255636 kb
Host smart-80884832-b722-45cd-8872-b2c6590aad7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98507
978788598762740261054537865095418374827998385086308040749892714208135893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.alert_handler_esc_intr_timeout.98507978788598762740261054537865095418374827998385086308040749892714208135893
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.18762721433009506430470952895728125051714849798773659366212739255351637518857
Short name T188
Test name
Test status
Simulation time 58351884139 ps
CPU time 1794.48 seconds
Started Nov 22 01:12:19 PM PST 23
Finished Nov 22 01:42:15 PM PST 23
Peak memory 289328 kb
Host smart-5f9e5665-2bda-43a3-aa95-65cd1dbc0859
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18762721433009506430470952895728125051714849798773659366212739255351637518857 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.alert_handler_lpg.18762721433009506430470952895728125051714849798773659366212739255351637518857
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.62784463320922857785686654900681597848321300658559688669032074811270963501345
Short name T363
Test name
Test status
Simulation time 48172572717 ps
CPU time 1497.31 seconds
Started Nov 22 01:12:29 PM PST 23
Finished Nov 22 01:37:33 PM PST 23
Peak memory 272536 kb
Host smart-c009c227-d8eb-478e-aeb2-254e1a7908ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62784463320922857785686654900681597848321300658559688669032074811270963501345 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.62784463320922857785686654900681597848321300658559688669032074811270963501345
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.90488445095488270434395592801770804849359861588714812021593559329208267100104
Short name T682
Test name
Test status
Simulation time 17273552054 ps
CPU time 373.34 seconds
Started Nov 22 01:12:29 PM PST 23
Finished Nov 22 01:18:49 PM PST 23
Peak memory 247516 kb
Host smart-a2ce77e2-b04e-4abd-be8d-7bb5d6503546
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90488445095488270434395592801770804849359861588714812021593559329208267100104 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.90488445095488270434395592801770804849359861588714812021593559329208267100104
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.54040358829080855061927431041007922348845102442582428822301649232396314317765
Short name T295
Test name
Test status
Simulation time 1399732617 ps
CPU time 44.9 seconds
Started Nov 22 01:12:34 PM PST 23
Finished Nov 22 01:13:28 PM PST 23
Peak memory 255460 kb
Host smart-051fe564-d832-4e12-80b7-8a036db465be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54040
358829080855061927431041007922348845102442582428822301649232396314317765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
alert_handler_random_alerts.54040358829080855061927431041007922348845102442582428822301649232396314317765
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.115145517869803312765995655893827042457392299374771525809543349865552428857717
Short name T557
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.79 seconds
Started Nov 22 01:12:13 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 254816 kb
Host smart-c4e2580b-2b25-47f4-b058-fbfc7759cbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11514
5517869803312765995655893827042457392299374771525809543349865552428857717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.alert_handler_random_classes.115145517869803312765995655893827042457392299374771525809543349865552428857717
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.113912011525026760595554139065278848674198985569785286622275445390975956048449
Short name T22
Test name
Test status
Simulation time 740845031 ps
CPU time 23.41 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:13:12 PM PST 23
Peak memory 274804 kb
Host smart-345bd752-fa66-40c3-90cc-8c53230426fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=113912011525026760595554139065278848674198985569785286622275445390975956048449 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.alert_handler_sec_cm.113912011525026760595554139065278848674198985569785286622275445390975956048449
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.43936819282822556100360075384234570036963827257259369719841744676691434724920
Short name T406
Test name
Test status
Simulation time 1261680150 ps
CPU time 42.71 seconds
Started Nov 22 01:12:23 PM PST 23
Finished Nov 22 01:13:11 PM PST 23
Peak memory 255516 kb
Host smart-5343f28d-f807-4545-9516-5075d773b120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43936
819282822556100360075384234570036963827257259369719841744676691434724920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
lert_handler_sig_int_fail.43936819282822556100360075384234570036963827257259369719841744676691434724920
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3683775683319697358114430515737311856405970360064069938540207777929307616989
Short name T482
Test name
Test status
Simulation time 1558784916 ps
CPU time 52.57 seconds
Started Nov 22 01:12:24 PM PST 23
Finished Nov 22 01:13:24 PM PST 23
Peak memory 248848 kb
Host smart-51033b81-718e-4c23-b8ab-a199dcdabdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36837
75683319697358114430515737311856405970360064069938540207777929307616989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_smoke.3683775683319697358114430515737311856405970360064069938540207777929307616989
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.40262202544179273708404161306192772922472267958539054350567362396882582207424
Short name T189
Test name
Test status
Simulation time 63383433172 ps
CPU time 2077.02 seconds
Started Nov 22 01:12:26 PM PST 23
Finished Nov 22 01:47:12 PM PST 23
Peak memory 289748 kb
Host smart-c832bc7b-1eb6-4d68-805d-18fa01b4b4f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40262202544179273708404161306192772922472267958539054350567362396882582207424 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.402622025441792737084041613061927729224722679585390543505673623
96882582207424
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.44515516350803499651875370835079012354507114940181454223663219319125424026453
Short name T63
Test name
Test status
Simulation time 79866015596 ps
CPU time 2865.31 seconds
Started Nov 22 01:12:23 PM PST 23
Finished Nov 22 02:00:16 PM PST 23
Peak memory 298172 kb
Host smart-03436605-27d2-4db7-9ffa-ae8ef1209a88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445155163508034996518753708350790123545071149401
81454223663219319125424026453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.445155163
50803499651875370835079012354507114940181454223663219319125424026453
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.84273637013845372932798328914238258992426545239364670386235977916615876118611
Short name T461
Test name
Test status
Simulation time 30823729350 ps
CPU time 1102.93 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:32:47 PM PST 23
Peak memory 272392 kb
Host smart-8960181c-69f9-40b1-ba75-1fed60d5ad2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84273637013845372932798328914238258992426545239364670386235977916615876118611 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.alert_handler_entropy.84273637013845372932798328914238258992426545239364670386235977916615876118611
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.76750979058479555275447126167673541588021336910262671814803220224975259051616
Short name T174
Test name
Test status
Simulation time 6994902141 ps
CPU time 239.14 seconds
Started Nov 22 01:14:05 PM PST 23
Finished Nov 22 01:18:05 PM PST 23
Peak memory 251244 kb
Host smart-054cfae5-796c-4578-87be-628cc3e2e9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76750
979058479555275447126167673541588021336910262671814803220224975259051616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.alert_handler_esc_alert_accum.76750979058479555275447126167673541588021336910262671814803220224975259051616
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.78704212962698446861323151632578146743635254876522083392746127343203897115813
Short name T548
Test name
Test status
Simulation time 1449142936 ps
CPU time 53.6 seconds
Started Nov 22 01:14:04 PM PST 23
Finished Nov 22 01:14:59 PM PST 23
Peak memory 255656 kb
Host smart-9a959fa9-d88b-422d-a358-b4f64fb128e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78704
212962698446861323151632578146743635254876522083392746127343203897115813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.alert_handler_esc_intr_timeout.78704212962698446861323151632578146743635254876522083392746127343203897115813
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.61951324617515255088075909098970400982644680105735462401804230187272743363570
Short name T507
Test name
Test status
Simulation time 58351884139 ps
CPU time 1780.68 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:44:19 PM PST 23
Peak memory 289152 kb
Host smart-51d82ed3-d1a7-4869-bf7e-1787bd7186ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61951324617515255088075909098970400982644680105735462401804230187272743363570 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.alert_handler_lpg.61951324617515255088075909098970400982644680105735462401804230187272743363570
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.46582556720191572062493731466184503611439484109561741707571234682154899798660
Short name T362
Test name
Test status
Simulation time 48172572717 ps
CPU time 1701.74 seconds
Started Nov 22 01:14:21 PM PST 23
Finished Nov 22 01:42:45 PM PST 23
Peak memory 272308 kb
Host smart-3584d8fa-b7ab-430d-8ae9-2e48d257d4c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46582556720191572062493731466184503611439484109561741707571234682154899798660 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.46582556720191572062493731466184503611439484109561741707571234682154899798660
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.58008711196252667910324281304564220931031195568288762933147236537635015303771
Short name T559
Test name
Test status
Simulation time 17273552054 ps
CPU time 394.53 seconds
Started Nov 22 01:14:21 PM PST 23
Finished Nov 22 01:20:57 PM PST 23
Peak memory 247528 kb
Host smart-95d37b8b-569b-4237-8301-cacb6d650fd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58008711196252667910324281304564220931031195568288762933147236537635015303771 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.58008711196252667910324281304564220931031195568288762933147236537635015303771
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.66882567674788025713647309089097008204402215667693906633837342917131712347050
Short name T137
Test name
Test status
Simulation time 1399732617 ps
CPU time 46.55 seconds
Started Nov 22 01:14:07 PM PST 23
Finished Nov 22 01:14:55 PM PST 23
Peak memory 255468 kb
Host smart-a8ac6c21-af4e-4177-ad05-db462c622fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66882
567674788025713647309089097008204402215667693906633837342917131712347050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.alert_handler_random_alerts.66882567674788025713647309089097008204402215667693906633837342917131712347050
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.43056075196389211981810908486202437570643460800229397026594372464144772693415
Short name T58
Test name
Test status
Simulation time 1291269199 ps
CPU time 47.34 seconds
Started Nov 22 01:14:12 PM PST 23
Finished Nov 22 01:15:00 PM PST 23
Peak memory 254856 kb
Host smart-7d3c7b5e-22cd-4c88-9879-aacbac331506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43056
075196389211981810908486202437570643460800229397026594372464144772693415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.alert_handler_random_classes.43056075196389211981810908486202437570643460800229397026594372464144772693415
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.49347101858199102997350029392090760505228015694009148897369024240705145848326
Short name T350
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.09 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:15:10 PM PST 23
Peak memory 255532 kb
Host smart-44042de7-094c-4e15-91a8-82b7cb84ebef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49347
101858199102997350029392090760505228015694009148897369024240705145848326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
alert_handler_sig_int_fail.49347101858199102997350029392090760505228015694009148897369024240705145848326
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.51964280538713511468678819860639779610222861750882881956535730879057832215017
Short name T492
Test name
Test status
Simulation time 1558784916 ps
CPU time 52.93 seconds
Started Nov 22 01:14:05 PM PST 23
Finished Nov 22 01:14:59 PM PST 23
Peak memory 248840 kb
Host smart-2ef25bff-6cd2-48a4-83ef-f7c804d4478c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51964
280538713511468678819860639779610222861750882881956535730879057832215017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_h
andler_smoke.51964280538713511468678819860639779610222861750882881956535730879057832215017
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.41190469841396905847514239142870924847192770493800855454772490129165367352564
Short name T481
Test name
Test status
Simulation time 63383433172 ps
CPU time 2071.31 seconds
Started Nov 22 01:14:34 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 289780 kb
Host smart-0323fc07-45d1-4629-a4d6-fb2537f40a67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41190469841396905847514239142870924847192770493800855454772490129165367352564 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.41190469841396905847514239142870924847192770493800855454772490
129165367352564
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.50194865665733653864638437676074384385128484244941666137121307455848761424557
Short name T259
Test name
Test status
Simulation time 79866015596 ps
CPU time 2803.53 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 02:01:07 PM PST 23
Peak memory 298104 kb
Host smart-8d13f35a-eb5e-4122-a718-c865152658f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501948656657336538646384376760743843851284842449
41666137121307455848761424557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.50194865
665733653864638437676074384385128484244941666137121307455848761424557
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2091661613143377028096472111551984589692096655310275483509233607824228951432
Short name T230
Test name
Test status
Simulation time 30823729350 ps
CPU time 1068.7 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:32:14 PM PST 23
Peak memory 272500 kb
Host smart-449528f9-0958-4356-9719-8654aa7d6d27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091661613143377028096472111551984589692096655310275483509233607824228951432 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.alert_handler_entropy.2091661613143377028096472111551984589692096655310275483509233607824228951432
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.109805246027606165637387455718083888970983719608730820254897444970118576915564
Short name T403
Test name
Test status
Simulation time 6994902141 ps
CPU time 237.56 seconds
Started Nov 22 01:14:26 PM PST 23
Finished Nov 22 01:18:25 PM PST 23
Peak memory 251216 kb
Host smart-9dc54743-2f28-45e8-9134-74e2f8629b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10980
5246027606165637387455718083888970983719608730820254897444970118576915564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.alert_handler_esc_alert_accum.109805246027606165637387455718083888970983719608730820254897444970118576915564
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.84051669956187334940309191920632921571286208870578965806037498874433064491573
Short name T334
Test name
Test status
Simulation time 1449142936 ps
CPU time 51.31 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:15:14 PM PST 23
Peak memory 255648 kb
Host smart-e1c9fac4-9b91-41db-9953-f9a3475507a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84051
669956187334940309191920632921571286208870578965806037498874433064491573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.alert_handler_esc_intr_timeout.84051669956187334940309191920632921571286208870578965806037498874433064491573
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.95634511396865280518964351632662439274776749011774424107428856809632526799147
Short name T144
Test name
Test status
Simulation time 58351884139 ps
CPU time 1839.26 seconds
Started Nov 22 01:14:26 PM PST 23
Finished Nov 22 01:45:07 PM PST 23
Peak memory 289316 kb
Host smart-c86346d8-1f7b-43e2-b709-806ca57c7d7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95634511396865280518964351632662439274776749011774424107428856809632526799147 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.alert_handler_lpg.95634511396865280518964351632662439274776749011774424107428856809632526799147
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.78165038748009792882742373475372300129080914238828431818714878801251102133383
Short name T355
Test name
Test status
Simulation time 48172572717 ps
CPU time 1587.72 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:40:53 PM PST 23
Peak memory 272512 kb
Host smart-d3388314-1a9a-4182-adc2-9f3359dee249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78165038748009792882742373475372300129080914238828431818714878801251102133383 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.78165038748009792882742373475372300129080914238828431818714878801251102133383
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.115211131565429989368545833207010093471059777902789584833499639461810830128419
Short name T303
Test name
Test status
Simulation time 17273552054 ps
CPU time 412.4 seconds
Started Nov 22 01:14:24 PM PST 23
Finished Nov 22 01:21:19 PM PST 23
Peak memory 247556 kb
Host smart-239d044e-8f1e-434d-80f2-d4c52b3f7614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115211131565429989368545833207010093471059777902789584833499639461810830128419 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.115211131565429989368545833207010093471059777902789584833499639461810830128419
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.41040718657641379151006963980997938490006545293006102117468763949649936419531
Short name T656
Test name
Test status
Simulation time 1399732617 ps
CPU time 49.1 seconds
Started Nov 22 01:14:27 PM PST 23
Finished Nov 22 01:15:18 PM PST 23
Peak memory 255452 kb
Host smart-daed3ca4-a8f3-4590-8857-a4beba78845c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41040
718657641379151006963980997938490006545293006102117468763949649936419531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.alert_handler_random_alerts.41040718657641379151006963980997938490006545293006102117468763949649936419531
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.79889551880282452951056735254453904352021422966911504549020593678361475642811
Short name T685
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.38 seconds
Started Nov 22 01:14:26 PM PST 23
Finished Nov 22 01:15:13 PM PST 23
Peak memory 254832 kb
Host smart-0110afdc-b577-4186-823c-609246fc5bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79889
551880282452951056735254453904352021422966911504549020593678361475642811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.alert_handler_random_classes.79889551880282452951056735254453904352021422966911504549020593678361475642811
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.107858398381218014628024869626492585373238868005944478973625030192077309732962
Short name T375
Test name
Test status
Simulation time 1261680150 ps
CPU time 48.63 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:15:14 PM PST 23
Peak memory 255524 kb
Host smart-b483fbc4-9c5a-4ae2-9441-125d68675f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10785
8398381218014628024869626492585373238868005944478973625030192077309732962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.alert_handler_sig_int_fail.107858398381218014628024869626492585373238868005944478973625030192077309732962
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.61687225708795242591880320254193635286373722583176456984821562352109056505504
Short name T562
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.43 seconds
Started Nov 22 01:14:21 PM PST 23
Finished Nov 22 01:15:13 PM PST 23
Peak memory 248852 kb
Host smart-2d483931-10dd-46b9-8515-4b1cdcb6c07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61687
225708795242591880320254193635286373722583176456984821562352109056505504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_h
andler_smoke.61687225708795242591880320254193635286373722583176456984821562352109056505504
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.51972736932368024772287454872826391829246669061699908449523050313632271079078
Short name T239
Test name
Test status
Simulation time 63383433172 ps
CPU time 2009.53 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:47:53 PM PST 23
Peak memory 289732 kb
Host smart-9ad23015-9b95-45a3-88d1-650698d0ea68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51972736932368024772287454872826391829246669061699908449523050313632271079078 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.51972736932368024772287454872826391829246669061699908449523050
313632271079078
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.76363921511460020215205423815413592289928751245437501428940588868485598664016
Short name T668
Test name
Test status
Simulation time 79866015596 ps
CPU time 2648.25 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 298180 kb
Host smart-a883da99-e90f-41b2-8991-e0c06a9a7394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763639215114600202152054238154135922899287512454
37501428940588868485598664016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.76363921
511460020215205423815413592289928751245437501428940588868485598664016
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2186502439144657264639370297321965905108797205960851861908369369868079694501
Short name T27
Test name
Test status
Simulation time 30823729350 ps
CPU time 1060.83 seconds
Started Nov 22 01:14:24 PM PST 23
Finished Nov 22 01:32:07 PM PST 23
Peak memory 272484 kb
Host smart-09276bea-f1b7-429d-a306-69ee086c5417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186502439144657264639370297321965905108797205960851861908369369868079694501 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.alert_handler_entropy.2186502439144657264639370297321965905108797205960851861908369369868079694501
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.60326319663545398012769502683987696824511956189464018885862288037019774100595
Short name T677
Test name
Test status
Simulation time 6994902141 ps
CPU time 245.08 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:18:29 PM PST 23
Peak memory 251076 kb
Host smart-8d628236-3ea7-4f50-a258-fc35129cdebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60326
319663545398012769502683987696824511956189464018885862288037019774100595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.alert_handler_esc_alert_accum.60326319663545398012769502683987696824511956189464018885862288037019774100595
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.78565479322455215596415893646489265642186144073865352252173276322011467419071
Short name T611
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.87 seconds
Started Nov 22 01:14:28 PM PST 23
Finished Nov 22 01:15:18 PM PST 23
Peak memory 255660 kb
Host smart-d999ddd8-05a0-4e9d-8b09-6a25bb87953a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78565
479322455215596415893646489265642186144073865352252173276322011467419071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.alert_handler_esc_intr_timeout.78565479322455215596415893646489265642186144073865352252173276322011467419071
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.68407064320751681750494308086478498195209295314138457069688452899519903719611
Short name T395
Test name
Test status
Simulation time 58351884139 ps
CPU time 1804.73 seconds
Started Nov 22 01:14:29 PM PST 23
Finished Nov 22 01:44:36 PM PST 23
Peak memory 289304 kb
Host smart-ab3dd619-e7fe-443f-b5d1-5c6ee493d56b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68407064320751681750494308086478498195209295314138457069688452899519903719611 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.alert_handler_lpg.68407064320751681750494308086478498195209295314138457069688452899519903719611
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.23211025852043948215139672931759620189434036653894241688762817121901238344280
Short name T358
Test name
Test status
Simulation time 48172572717 ps
CPU time 1559.29 seconds
Started Nov 22 01:14:28 PM PST 23
Finished Nov 22 01:40:30 PM PST 23
Peak memory 272520 kb
Host smart-ec2deccf-497d-405d-8f71-3977c9943cd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23211025852043948215139672931759620189434036653894241688762817121901238344280 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.23211025852043948215139672931759620189434036653894241688762817121901238344280
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.79769947459316864716420110636949017727856670922877097009739062874113226339578
Short name T420
Test name
Test status
Simulation time 17273552054 ps
CPU time 408.74 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:21:14 PM PST 23
Peak memory 247540 kb
Host smart-e352c3e2-d87a-450c-b637-dd6eb8ee073e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79769947459316864716420110636949017727856670922877097009739062874113226339578 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.79769947459316864716420110636949017727856670922877097009739062874113226339578
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.109867468485379791183697763896215082469249581888514278581298861193301165605117
Short name T421
Test name
Test status
Simulation time 1399732617 ps
CPU time 49.06 seconds
Started Nov 22 01:14:31 PM PST 23
Finished Nov 22 01:15:21 PM PST 23
Peak memory 255492 kb
Host smart-64e57d3b-6c6b-4730-8cd6-6a5c3d8475f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10986
7468485379791183697763896215082469249581888514278581298861193301165605117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.alert_handler_random_alerts.109867468485379791183697763896215082469249581888514278581298861193301165605117
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.73114059694829068839933981715162068785665732763041808476923961129754244272096
Short name T233
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.7 seconds
Started Nov 22 01:14:21 PM PST 23
Finished Nov 22 01:15:09 PM PST 23
Peak memory 254672 kb
Host smart-af454fdb-9a42-4250-8636-554d15f82250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73114
059694829068839933981715162068785665732763041808476923961129754244272096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.alert_handler_random_classes.73114059694829068839933981715162068785665732763041808476923961129754244272096
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.97102185491544370585780243539369658348889021353822719056635521820611200669646
Short name T219
Test name
Test status
Simulation time 1261680150 ps
CPU time 46.77 seconds
Started Nov 22 01:14:24 PM PST 23
Finished Nov 22 01:15:13 PM PST 23
Peak memory 255548 kb
Host smart-e798748e-14d2-4c52-9650-50673b13c2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97102
185491544370585780243539369658348889021353822719056635521820611200669646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
alert_handler_sig_int_fail.97102185491544370585780243539369658348889021353822719056635521820611200669646
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.112872865728555781735936627508578395195593802785862006716419744644499348989728
Short name T357
Test name
Test status
Simulation time 1558784916 ps
CPU time 55.13 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:15:19 PM PST 23
Peak memory 248784 kb
Host smart-91ab156d-5694-433e-84dc-4db2040a9792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11287
2865728555781735936627508578395195593802785862006716419744644499348989728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_
handler_smoke.112872865728555781735936627508578395195593802785862006716419744644499348989728
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.52982902187346439708144222526816993934019293043074719568699099048137648762108
Short name T691
Test name
Test status
Simulation time 63383433172 ps
CPU time 2051.34 seconds
Started Nov 22 01:14:32 PM PST 23
Finished Nov 22 01:48:45 PM PST 23
Peak memory 289616 kb
Host smart-e0ded299-5c7c-4a29-bcf0-8765867fd96d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52982902187346439708144222526816993934019293043074719568699099048137648762108 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.52982902187346439708144222526816993934019293043074719568699099
048137648762108
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.17161161309689198000800220689392346831967568299150819699087545750965907793082
Short name T666
Test name
Test status
Simulation time 79866015596 ps
CPU time 2827.95 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 02:01:34 PM PST 23
Peak memory 298076 kb
Host smart-e4a077ab-5ae2-4c92-8a39-a23c647d1d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171611613096891980008002206893923468319675682991
50819699087545750965907793082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.17161161
309689198000800220689392346831967568299150819699087545750965907793082
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.24272079386161821396593950077247691641745250724298972602750244733867581676723
Short name T264
Test name
Test status
Simulation time 30823729350 ps
CPU time 1012.26 seconds
Started Nov 22 01:14:25 PM PST 23
Finished Nov 22 01:31:19 PM PST 23
Peak memory 272436 kb
Host smart-ddaceb9a-8d95-40eb-8506-edcc3f566827
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24272079386161821396593950077247691641745250724298972602750244733867581676723 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.alert_handler_entropy.24272079386161821396593950077247691641745250724298972602750244733867581676723
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.20345164697292810648563548896646316986414147423636445307350466387034166141043
Short name T439
Test name
Test status
Simulation time 6994902141 ps
CPU time 244.6 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:18:30 PM PST 23
Peak memory 251260 kb
Host smart-9dce73f9-70a6-4f8a-bc8a-95a702b02cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20345
164697292810648563548896646316986414147423636445307350466387034166141043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.alert_handler_esc_alert_accum.20345164697292810648563548896646316986414147423636445307350466387034166141043
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.25558516801718221242181053513329581178256286111060667786575738762437620613375
Short name T566
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.12 seconds
Started Nov 22 01:14:24 PM PST 23
Finished Nov 22 01:15:15 PM PST 23
Peak memory 255528 kb
Host smart-515672cf-04e2-4203-8f51-ff6594796b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25558
516801718221242181053513329581178256286111060667786575738762437620613375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.alert_handler_esc_intr_timeout.25558516801718221242181053513329581178256286111060667786575738762437620613375
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.32946720393732061299545876070458916673257758506917441521251110644199916690484
Short name T183
Test name
Test status
Simulation time 58351884139 ps
CPU time 1838.79 seconds
Started Nov 22 01:14:21 PM PST 23
Finished Nov 22 01:45:01 PM PST 23
Peak memory 289284 kb
Host smart-3a6d27c1-7cd2-4180-b53f-6f49d49c811c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32946720393732061299545876070458916673257758506917441521251110644199916690484 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.alert_handler_lpg.32946720393732061299545876070458916673257758506917441521251110644199916690484
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.67464358236400618384619001952053263026536642899474608006873607815440754348922
Short name T390
Test name
Test status
Simulation time 48172572717 ps
CPU time 1572.51 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:40:35 PM PST 23
Peak memory 272460 kb
Host smart-9f681a2d-61b6-4630-938c-3089fe52871e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67464358236400618384619001952053263026536642899474608006873607815440754348922 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.67464358236400618384619001952053263026536642899474608006873607815440754348922
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.25208076834966683802205615068019200747612418842495493135552830856864167178673
Short name T620
Test name
Test status
Simulation time 17273552054 ps
CPU time 392.78 seconds
Started Nov 22 01:14:29 PM PST 23
Finished Nov 22 01:21:04 PM PST 23
Peak memory 247552 kb
Host smart-27454105-fc4c-473a-87da-9772c902b1f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25208076834966683802205615068019200747612418842495493135552830856864167178673 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.25208076834966683802205615068019200747612418842495493135552830856864167178673
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.113184606594955791077674208692682548646097136743000478196033968982507899792714
Short name T157
Test name
Test status
Simulation time 1399732617 ps
CPU time 44.94 seconds
Started Nov 22 01:14:20 PM PST 23
Finished Nov 22 01:15:06 PM PST 23
Peak memory 255484 kb
Host smart-d6bc1185-a907-4040-8ae2-ccce4eb4bff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11318
4606594955791077674208692682548646097136743000478196033968982507899792714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.alert_handler_random_alerts.113184606594955791077674208692682548646097136743000478196033968982507899792714
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.92170493875439197769534353370768377429464250961688006932541382508687029015850
Short name T79
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.07 seconds
Started Nov 22 01:14:24 PM PST 23
Finished Nov 22 01:15:11 PM PST 23
Peak memory 254732 kb
Host smart-8252d775-d21a-4dd7-9333-069b5a8e5142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92170
493875439197769534353370768377429464250961688006932541382508687029015850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.alert_handler_random_classes.92170493875439197769534353370768377429464250961688006932541382508687029015850
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.85457014917957102464486283449037120515031743529198023551780263984945351425131
Short name T364
Test name
Test status
Simulation time 1261680150 ps
CPU time 42.83 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:15:08 PM PST 23
Peak memory 255436 kb
Host smart-a57f2e20-1457-4cb6-bb80-9c4807b52835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85457
014917957102464486283449037120515031743529198023551780263984945351425131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
alert_handler_sig_int_fail.85457014917957102464486283449037120515031743529198023551780263984945351425131
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.108245062359235537170173975357745424901984857409106429192702239135661360206882
Short name T469
Test name
Test status
Simulation time 1558784916 ps
CPU time 54.73 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:15:20 PM PST 23
Peak memory 248708 kb
Host smart-bad803ed-359f-4c81-934c-c475df8ea665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10824
5062359235537170173975357745424901984857409106429192702239135661360206882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_
handler_smoke.108245062359235537170173975357745424901984857409106429192702239135661360206882
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3712944967178942686050824149518213816263715960977329236627703888538055017397
Short name T606
Test name
Test status
Simulation time 63383433172 ps
CPU time 2128.66 seconds
Started Nov 22 01:14:21 PM PST 23
Finished Nov 22 01:49:51 PM PST 23
Peak memory 289776 kb
Host smart-bf15e5eb-1ce8-45d8-96d0-2ab73e1a890a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712944967178942686050824149518213816263715960977329236627703888538055017397 -assert nopos
tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.371294496717894268605082414951821381626371596097732923662770388
8538055017397
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.65634994522218829458195572564289535435854390176371254625381723402654977988796
Short name T564
Test name
Test status
Simulation time 79866015596 ps
CPU time 2852.5 seconds
Started Nov 22 01:14:25 PM PST 23
Finished Nov 22 02:02:00 PM PST 23
Peak memory 298040 kb
Host smart-5fabf7b0-1974-4dce-b8a0-2b1d8be7287a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656349945222188294581955725642895354358543901763
71254625381723402654977988796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.65634994
522218829458195572564289535435854390176371254625381723402654977988796
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.105824520656636769675076485791164305909343149745192081982305969937490928929992
Short name T511
Test name
Test status
Simulation time 30823729350 ps
CPU time 1059.47 seconds
Started Nov 22 01:14:27 PM PST 23
Finished Nov 22 01:32:08 PM PST 23
Peak memory 272328 kb
Host smart-6d718b28-dc37-4f83-a571-2167a95691a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105824520656636769675076485791164305909343149745192081982305969937490928929992 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.alert_handler_entropy.105824520656636769675076485791164305909343149745192081982305969937490928929992
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1022142326710241101769154968503996622433787604961358548339813078196648018213
Short name T651
Test name
Test status
Simulation time 6994902141 ps
CPU time 220.45 seconds
Started Nov 22 01:14:21 PM PST 23
Finished Nov 22 01:18:02 PM PST 23
Peak memory 251056 kb
Host smart-e89202a6-d99a-4407-aaa5-e300aa1ee7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10221
42326710241101769154968503996622433787604961358548339813078196648018213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.alert_handler_esc_alert_accum.1022142326710241101769154968503996622433787604961358548339813078196648018213
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.27310266761027435715421885615740470435050376969069034226227398417638998648681
Short name T546
Test name
Test status
Simulation time 1449142936 ps
CPU time 49.63 seconds
Started Nov 22 01:14:24 PM PST 23
Finished Nov 22 01:15:15 PM PST 23
Peak memory 255488 kb
Host smart-a34e1cd3-32ab-4d15-b6a4-b62082a5a9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
266761027435715421885615740470435050376969069034226227398417638998648681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.alert_handler_esc_intr_timeout.27310266761027435715421885615740470435050376969069034226227398417638998648681
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.31537835514400571301655056989560226568462910231259762782055746823449833764363
Short name T640
Test name
Test status
Simulation time 58351884139 ps
CPU time 1815.28 seconds
Started Nov 22 01:14:32 PM PST 23
Finished Nov 22 01:44:48 PM PST 23
Peak memory 289144 kb
Host smart-1eed3220-ede0-404e-a2af-5ea36e2478a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31537835514400571301655056989560226568462910231259762782055746823449833764363 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.alert_handler_lpg.31537835514400571301655056989560226568462910231259762782055746823449833764363
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.63686078107724445576095376725083029584712476227057044065667620838540112642521
Short name T518
Test name
Test status
Simulation time 48172572717 ps
CPU time 1496.14 seconds
Started Nov 22 01:14:32 PM PST 23
Finished Nov 22 01:39:29 PM PST 23
Peak memory 272316 kb
Host smart-07c46219-ab5f-40ed-a78e-c1e309d73ea5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63686078107724445576095376725083029584712476227057044065667620838540112642521 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.63686078107724445576095376725083029584712476227057044065667620838540112642521
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.84830725502132121753005636173456401048078233153277342912238575958727927460855
Short name T327
Test name
Test status
Simulation time 17273552054 ps
CPU time 404.94 seconds
Started Nov 22 01:14:23 PM PST 23
Finished Nov 22 01:21:10 PM PST 23
Peak memory 247488 kb
Host smart-5d4367d6-6bd2-45e7-9981-e06d26240bf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84830725502132121753005636173456401048078233153277342912238575958727927460855 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.84830725502132121753005636173456401048078233153277342912238575958727927460855
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.19725768186658723272049238784268157642325172428750798054059042994778999950362
Short name T284
Test name
Test status
Simulation time 1399732617 ps
CPU time 49.29 seconds
Started Nov 22 01:14:29 PM PST 23
Finished Nov 22 01:15:20 PM PST 23
Peak memory 255488 kb
Host smart-ae400f42-e115-4f2e-8f2e-e24700d4fba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
768186658723272049238784268157642325172428750798054059042994778999950362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.alert_handler_random_alerts.19725768186658723272049238784268157642325172428750798054059042994778999950362
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.67654106044564180752196006461129231552285088957646590123904074861927735368023
Short name T308
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.52 seconds
Started Nov 22 01:14:26 PM PST 23
Finished Nov 22 01:15:13 PM PST 23
Peak memory 254696 kb
Host smart-61a2ff21-0f5e-4505-8227-56d00d431d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67654
106044564180752196006461129231552285088957646590123904074861927735368023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.alert_handler_random_classes.67654106044564180752196006461129231552285088957646590123904074861927735368023
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.52092567430040074492811881953883040825474431585020371143121266245320799063044
Short name T442
Test name
Test status
Simulation time 1261680150 ps
CPU time 50.17 seconds
Started Nov 22 01:14:31 PM PST 23
Finished Nov 22 01:15:22 PM PST 23
Peak memory 255328 kb
Host smart-7ec68973-4e64-4be1-aab1-97d8f3ac11d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52092
567430040074492811881953883040825474431585020371143121266245320799063044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
alert_handler_sig_int_fail.52092567430040074492811881953883040825474431585020371143121266245320799063044
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.37902576397913262897789202684807711765509918555211147813935446003786596176522
Short name T208
Test name
Test status
Simulation time 1558784916 ps
CPU time 49.05 seconds
Started Nov 22 01:14:22 PM PST 23
Finished Nov 22 01:15:13 PM PST 23
Peak memory 248748 kb
Host smart-ad1a463c-48ef-4e72-9936-23d81f03210c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37902
576397913262897789202684807711765509918555211147813935446003786596176522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_h
andler_smoke.37902576397913262897789202684807711765509918555211147813935446003786596176522
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.60133547951423678266382595095145447523964219413555866101415248364897949719623
Short name T164
Test name
Test status
Simulation time 63383433172 ps
CPU time 1985.02 seconds
Started Nov 22 01:14:30 PM PST 23
Finished Nov 22 01:47:37 PM PST 23
Peak memory 289576 kb
Host smart-d0781c2f-e7dc-4b54-afcc-b127e8eaf334
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60133547951423678266382595095145447523964219413555866101415248364897949719623 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.60133547951423678266382595095145447523964219413555866101415248
364897949719623
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.102433556389924174282732567321070097834189667407315139155197876183578272537700
Short name T366
Test name
Test status
Simulation time 79866015596 ps
CPU time 2694.66 seconds
Started Nov 22 01:14:35 PM PST 23
Finished Nov 22 01:59:31 PM PST 23
Peak memory 297992 kb
Host smart-b8c52402-98d1-462e-973b-5417a49e4110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102433556389924174282732567321070097834189667407
315139155197876183578272537700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1024335
56389924174282732567321070097834189667407315139155197876183578272537700
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.48911290984081019276247970361191507728956265280822941838622896855805310749133
Short name T614
Test name
Test status
Simulation time 30823729350 ps
CPU time 1023.04 seconds
Started Nov 22 01:14:41 PM PST 23
Finished Nov 22 01:31:45 PM PST 23
Peak memory 272284 kb
Host smart-793a5af4-5924-430e-a1bf-8e3262e45e03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48911290984081019276247970361191507728956265280822941838622896855805310749133 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.alert_handler_entropy.48911290984081019276247970361191507728956265280822941838622896855805310749133
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.12089622725380104613302557946435256915278696894595116337117666649667043548651
Short name T690
Test name
Test status
Simulation time 6994902141 ps
CPU time 241.02 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:18:39 PM PST 23
Peak memory 251252 kb
Host smart-d7d359cf-5df6-4176-8ef6-7cfdea1dbb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12089
622725380104613302557946435256915278696894595116337117666649667043548651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.alert_handler_esc_alert_accum.12089622725380104613302557946435256915278696894595116337117666649667043548651
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.71109088615306970507219045344251150593014379619612729102925905672395352719911
Short name T550
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.44 seconds
Started Nov 22 01:14:45 PM PST 23
Finished Nov 22 01:15:34 PM PST 23
Peak memory 255592 kb
Host smart-986943a4-ab20-448c-b642-6a830afcff79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71109
088615306970507219045344251150593014379619612729102925905672395352719911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.alert_handler_esc_intr_timeout.71109088615306970507219045344251150593014379619612729102925905672395352719911
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.113640108436671853741882509523141187484484670404449789729901832972420824278458
Short name T672
Test name
Test status
Simulation time 58351884139 ps
CPU time 1897.82 seconds
Started Nov 22 01:14:45 PM PST 23
Finished Nov 22 01:46:25 PM PST 23
Peak memory 289316 kb
Host smart-0c8fbba7-b6b4-4b44-8302-1f075175c4d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113640108436671853741882509523141187484484670404449789729901832972420824278458 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.alert_handler_lpg.113640108436671853741882509523141187484484670404449789729901832972420824278458
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.43147980779416148400049479135592497889163650392386956209269142891882845185652
Short name T631
Test name
Test status
Simulation time 48172572717 ps
CPU time 1536.19 seconds
Started Nov 22 01:14:35 PM PST 23
Finished Nov 22 01:40:12 PM PST 23
Peak memory 272472 kb
Host smart-6f1c0c35-e846-4e25-b5c1-b2650a782dd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43147980779416148400049479135592497889163650392386956209269142891882845185652 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.43147980779416148400049479135592497889163650392386956209269142891882845185652
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3696270766202900170965026801662671036297335254200240118326793544518861979033
Short name T175
Test name
Test status
Simulation time 17273552054 ps
CPU time 393.85 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:21:11 PM PST 23
Peak memory 247488 kb
Host smart-f12229b4-437e-435d-b876-27198d1a24ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696270766202900170965026801662671036297335254200240118326793544518861979033 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3696270766202900170965026801662671036297335254200240118326793544518861979033
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.110133767980381405288694565708094136770252485163835652922624356535479105599931
Short name T29
Test name
Test status
Simulation time 1399732617 ps
CPU time 50.81 seconds
Started Nov 22 01:14:38 PM PST 23
Finished Nov 22 01:15:30 PM PST 23
Peak memory 255296 kb
Host smart-c3e703e3-6478-4387-859b-764a74462f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11013
3767980381405288694565708094136770252485163835652922624356535479105599931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.alert_handler_random_alerts.110133767980381405288694565708094136770252485163835652922624356535479105599931
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.80721165031844449474926201338817996154431416919031857747189251355994432739368
Short name T528
Test name
Test status
Simulation time 1291269199 ps
CPU time 49.98 seconds
Started Nov 22 01:14:44 PM PST 23
Finished Nov 22 01:15:35 PM PST 23
Peak memory 254856 kb
Host smart-8c9f8143-e2d9-482f-8cd1-805adaf08ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80721
165031844449474926201338817996154431416919031857747189251355994432739368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.alert_handler_random_classes.80721165031844449474926201338817996154431416919031857747189251355994432739368
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.750234901746160588683453718956775163732539177889346691397213884247859058133
Short name T561
Test name
Test status
Simulation time 1261680150 ps
CPU time 49.47 seconds
Started Nov 22 01:15:09 PM PST 23
Finished Nov 22 01:16:00 PM PST 23
Peak memory 256824 kb
Host smart-edaa0a73-5c54-40a6-867a-fb71183cd43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75023
4901746160588683453718956775163732539177889346691397213884247859058133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=aler
t_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.al
ert_handler_sig_int_fail.750234901746160588683453718956775163732539177889346691397213884247859058133
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.62060836487073747141757712055912973091540954673499996120087893339195957084114
Short name T661
Test name
Test status
Simulation time 1558784916 ps
CPU time 54.37 seconds
Started Nov 22 01:14:39 PM PST 23
Finished Nov 22 01:15:35 PM PST 23
Peak memory 248628 kb
Host smart-40fa9975-ff2d-44fe-b97a-6fb01509252a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62060
836487073747141757712055912973091540954673499996120087893339195957084114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_h
andler_smoke.62060836487073747141757712055912973091540954673499996120087893339195957084114
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3768997982615357545070743731295346045985874550290269159812208982913212974807
Short name T270
Test name
Test status
Simulation time 63383433172 ps
CPU time 2074.75 seconds
Started Nov 22 01:14:45 PM PST 23
Finished Nov 22 01:49:21 PM PST 23
Peak memory 289792 kb
Host smart-22962117-49b1-4fed-a8b8-a91d2d9fb0da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768997982615357545070743731295346045985874550290269159812208982913212974807 -assert nopos
tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.376899798261535754507074373129534604598587455029026915981220898
2913212974807
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.112165670097197363330481954210040072253643657304274138615847738622559267870991
Short name T182
Test name
Test status
Simulation time 79866015596 ps
CPU time 2728.47 seconds
Started Nov 22 01:14:37 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 298012 kb
Host smart-19664be1-29da-49c6-8dd3-16bb009db0a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112165670097197363330481954210040072253643657304
274138615847738622559267870991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1121656
70097197363330481954210040072253643657304274138615847738622559267870991
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.48947164270780757842890586761890455792642225860527483360940467063760397786437
Short name T204
Test name
Test status
Simulation time 30823729350 ps
CPU time 1002.12 seconds
Started Nov 22 01:14:48 PM PST 23
Finished Nov 22 01:31:31 PM PST 23
Peak memory 272320 kb
Host smart-09ebab01-9c4f-4c8d-803b-15e0c2e61ad9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48947164270780757842890586761890455792642225860527483360940467063760397786437 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.alert_handler_entropy.48947164270780757842890586761890455792642225860527483360940467063760397786437
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.91501826214339365209655776449100775795727448727230308268943539313364497029792
Short name T663
Test name
Test status
Simulation time 6994902141 ps
CPU time 234.55 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:18:32 PM PST 23
Peak memory 251084 kb
Host smart-144a02f5-71e5-4126-8277-0d50a624e865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91501
826214339365209655776449100775795727448727230308268943539313364497029792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.alert_handler_esc_alert_accum.91501826214339365209655776449100775795727448727230308268943539313364497029792
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.109523072146748310055741886697081368130614445945164882097430796318367131961176
Short name T605
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.76 seconds
Started Nov 22 01:14:44 PM PST 23
Finished Nov 22 01:15:34 PM PST 23
Peak memory 256308 kb
Host smart-cc03f5ab-cdc7-4140-9c10-18a99ad56c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952
3072146748310055741886697081368130614445945164882097430796318367131961176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.alert_handler_esc_intr_timeout.109523072146748310055741886697081368130614445945164882097430796318367131961176
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.20314958162565126894019658976899786025527038105278937286257483694358746897071
Short name T578
Test name
Test status
Simulation time 58351884139 ps
CPU time 1871.78 seconds
Started Nov 22 01:14:37 PM PST 23
Finished Nov 22 01:45:51 PM PST 23
Peak memory 289240 kb
Host smart-a3beee17-8060-42c4-84a8-f6d165e47067
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20314958162565126894019658976899786025527038105278937286257483694358746897071 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.alert_handler_lpg.20314958162565126894019658976899786025527038105278937286257483694358746897071
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.27493989648328152353575464473325462837025796085607160760706653672155048482038
Short name T588
Test name
Test status
Simulation time 48172572717 ps
CPU time 1537.08 seconds
Started Nov 22 01:14:41 PM PST 23
Finished Nov 22 01:40:20 PM PST 23
Peak memory 272348 kb
Host smart-a8fd7240-8316-48c9-91a1-25b1d8d59bbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27493989648328152353575464473325462837025796085607160760706653672155048482038 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.27493989648328152353575464473325462837025796085607160760706653672155048482038
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.53183808848539894282480357817996354377505717565719087619714967882205323953816
Short name T278
Test name
Test status
Simulation time 17273552054 ps
CPU time 408.4 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:21:26 PM PST 23
Peak memory 247552 kb
Host smart-1b51bdb4-86cd-4ebc-a07b-7d9b44f0b980
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53183808848539894282480357817996354377505717565719087619714967882205323953816 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.53183808848539894282480357817996354377505717565719087619714967882205323953816
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.51243269253325497862474614838557810788089447832607329674903503885663731721386
Short name T238
Test name
Test status
Simulation time 1399732617 ps
CPU time 53.12 seconds
Started Nov 22 01:14:45 PM PST 23
Finished Nov 22 01:15:40 PM PST 23
Peak memory 255484 kb
Host smart-50c79dc7-5c89-48c3-ba31-91409bcd7d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51243
269253325497862474614838557810788089447832607329674903503885663731721386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.alert_handler_random_alerts.51243269253325497862474614838557810788089447832607329674903503885663731721386
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.60268260291984495119799187599592663323659550752406404551757602944075985981407
Short name T468
Test name
Test status
Simulation time 1291269199 ps
CPU time 47.1 seconds
Started Nov 22 01:14:40 PM PST 23
Finished Nov 22 01:15:29 PM PST 23
Peak memory 254696 kb
Host smart-9be5da6c-90db-439e-b181-f17e5d256f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60268
260291984495119799187599592663323659550752406404551757602944075985981407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.alert_handler_random_classes.60268260291984495119799187599592663323659550752406404551757602944075985981407
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.29639222775242371489620184302534855993769294980758923510399784868798049622728
Short name T163
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.55 seconds
Started Nov 22 01:14:32 PM PST 23
Finished Nov 22 01:15:18 PM PST 23
Peak memory 255516 kb
Host smart-6c9a0fdf-af2e-4c4e-aab0-9628bdfda1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29639
222775242371489620184302534855993769294980758923510399784868798049622728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
alert_handler_sig_int_fail.29639222775242371489620184302534855993769294980758923510399784868798049622728
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.38389525189671057084013420132349869079098673023088991970048288792606961061913
Short name T332
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.91 seconds
Started Nov 22 01:14:49 PM PST 23
Finished Nov 22 01:15:43 PM PST 23
Peak memory 248380 kb
Host smart-076b8ea1-08bc-4cee-9a88-21e58fc66631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38389
525189671057084013420132349869079098673023088991970048288792606961061913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_h
andler_smoke.38389525189671057084013420132349869079098673023088991970048288792606961061913
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.36102160196299459745709970107392117734206704117234539675980981648538242536451
Short name T455
Test name
Test status
Simulation time 63383433172 ps
CPU time 2195.26 seconds
Started Nov 22 01:14:32 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 289760 kb
Host smart-b592a454-2acf-465b-9859-a7fef4221b06
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36102160196299459745709970107392117734206704117234539675980981648538242536451 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.36102160196299459745709970107392117734206704117234539675980981
648538242536451
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.18668484474653382766998721014607185129928353914931076386763851519830437750308
Short name T479
Test name
Test status
Simulation time 79866015596 ps
CPU time 2738.76 seconds
Started Nov 22 01:14:39 PM PST 23
Finished Nov 22 02:00:20 PM PST 23
Peak memory 297988 kb
Host smart-070e9bc5-c499-4480-9e9a-b2df7847a71f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186684844746533827669987210146071851299283539149
31076386763851519830437750308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.18668484
474653382766998721014607185129928353914931076386763851519830437750308
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.13267495929632562602278301212315648726851411954541839736361339967580623228338
Short name T209
Test name
Test status
Simulation time 30823729350 ps
CPU time 1093.58 seconds
Started Nov 22 01:14:35 PM PST 23
Finished Nov 22 01:32:49 PM PST 23
Peak memory 272272 kb
Host smart-9c521c32-7337-43f3-919c-0ff88236dc92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13267495929632562602278301212315648726851411954541839736361339967580623228338 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.alert_handler_entropy.13267495929632562602278301212315648726851411954541839736361339967580623228338
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.72303119278839644135639384681797172636454421646737726598032552440057064899364
Short name T404
Test name
Test status
Simulation time 6994902141 ps
CPU time 247.28 seconds
Started Nov 22 01:14:39 PM PST 23
Finished Nov 22 01:18:48 PM PST 23
Peak memory 251060 kb
Host smart-064dfe80-4007-49ae-a63e-cff7d0c3223e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72303
119278839644135639384681797172636454421646737726598032552440057064899364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.alert_handler_esc_alert_accum.72303119278839644135639384681797172636454421646737726598032552440057064899364
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.5863003568695201219207685752834922878746799617312864294475540395624476654886
Short name T335
Test name
Test status
Simulation time 1449142936 ps
CPU time 52.16 seconds
Started Nov 22 01:14:44 PM PST 23
Finished Nov 22 01:15:38 PM PST 23
Peak memory 255652 kb
Host smart-31ea6798-866b-4228-809b-c238d5350dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58630
03568695201219207685752834922878746799617312864294475540395624476654886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.alert_handler_esc_intr_timeout.5863003568695201219207685752834922878746799617312864294475540395624476654886
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.104429806607609752881860337174172878717309131185954727689323548724819233042778
Short name T417
Test name
Test status
Simulation time 58351884139 ps
CPU time 1934.55 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:46:53 PM PST 23
Peak memory 289320 kb
Host smart-55d3cc95-1f99-4211-a4b3-3092529a9b6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104429806607609752881860337174172878717309131185954727689323548724819233042778 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.alert_handler_lpg.104429806607609752881860337174172878717309131185954727689323548724819233042778
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.109822019702258657087203944439434731726626780452528962717592227674544101834218
Short name T570
Test name
Test status
Simulation time 48172572717 ps
CPU time 1535.99 seconds
Started Nov 22 01:14:41 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 272348 kb
Host smart-b341fc41-5ebe-4b08-8074-f0709862acb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109822019702258657087203944439434731726626780452528962717592227674544101834218 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.109822019702258657087203944439434731726626780452528962717592227674544101834218
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.5369794436802125114726149780913135588780326197871230491875484618287883534958
Short name T82
Test name
Test status
Simulation time 17273552054 ps
CPU time 386.03 seconds
Started Nov 22 01:14:34 PM PST 23
Finished Nov 22 01:21:01 PM PST 23
Peak memory 247324 kb
Host smart-3f740bf4-2403-4e3a-a25a-f5668f17b0fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5369794436802125114726149780913135588780326197871230491875484618287883534958 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.5369794436802125114726149780913135588780326197871230491875484618287883534958
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.83410569224774455880401547269177253617537483210041568410137532062246829925135
Short name T407
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.52 seconds
Started Nov 22 01:14:32 PM PST 23
Finished Nov 22 01:15:21 PM PST 23
Peak memory 255352 kb
Host smart-b27a81c1-d4bd-4b8f-8fad-a34e439e2c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83410
569224774455880401547269177253617537483210041568410137532062246829925135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.alert_handler_random_alerts.83410569224774455880401547269177253617537483210041568410137532062246829925135
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.15404742220126108881186691374122248510517737564224891130869380077612440241334
Short name T478
Test name
Test status
Simulation time 1291269199 ps
CPU time 46.73 seconds
Started Nov 22 01:14:32 PM PST 23
Finished Nov 22 01:15:21 PM PST 23
Peak memory 254732 kb
Host smart-8aaaab9b-86cd-4eb5-935a-f138458740d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
742220126108881186691374122248510517737564224891130869380077612440241334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.alert_handler_random_classes.15404742220126108881186691374122248510517737564224891130869380077612440241334
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.17510676831167150445508936367944089293115063555200791460355403050082763166983
Short name T425
Test name
Test status
Simulation time 1261680150 ps
CPU time 42.8 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:15:20 PM PST 23
Peak memory 255376 kb
Host smart-3d44438f-df4c-4009-8a0e-216e96290707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17510
676831167150445508936367944089293115063555200791460355403050082763166983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
alert_handler_sig_int_fail.17510676831167150445508936367944089293115063555200791460355403050082763166983
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.11833464365331693578717769095092425333514691388257535824822437294776328301
Short name T201
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.38 seconds
Started Nov 22 01:14:43 PM PST 23
Finished Nov 22 01:15:36 PM PST 23
Peak memory 248800 kb
Host smart-fdbe8c04-c382-4e18-87bb-26e2a2c1ef57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11833
464365331693578717769095092425333514691388257535824822437294776328301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_hand
ler_smoke.11833464365331693578717769095092425333514691388257535824822437294776328301
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.41289461645959704866146885914405914774047646295569914762343179775512606955384
Short name T577
Test name
Test status
Simulation time 63383433172 ps
CPU time 2064.33 seconds
Started Nov 22 01:14:39 PM PST 23
Finished Nov 22 01:49:05 PM PST 23
Peak memory 289568 kb
Host smart-fb8fbda4-4141-4c62-bfaf-9da3be3b9cb2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41289461645959704866146885914405914774047646295569914762343179775512606955384 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.41289461645959704866146885914405914774047646295569914762343179
775512606955384
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.103111341865757428112790482696482019362725184915340981286373508191994820153992
Short name T257
Test name
Test status
Simulation time 79866015596 ps
CPU time 2775.83 seconds
Started Nov 22 01:14:44 PM PST 23
Finished Nov 22 02:01:01 PM PST 23
Peak memory 298212 kb
Host smart-75399356-8e8a-4432-9d7a-a4f8907a92f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103111341865757428112790482696482019362725184915
340981286373508191994820153992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1031113
41865757428112790482696482019362725184915340981286373508191994820153992
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.48428750367255169280802689018988519967037076268874436656101235933901250975200
Short name T594
Test name
Test status
Simulation time 30823729350 ps
CPU time 1070.83 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:32:29 PM PST 23
Peak memory 272260 kb
Host smart-8cfe105b-a839-4e82-8ad6-120807577b4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48428750367255169280802689018988519967037076268874436656101235933901250975200 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.alert_handler_entropy.48428750367255169280802689018988519967037076268874436656101235933901250975200
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.108886753233938920955744969611973913836580629643174739141287459069286315065002
Short name T301
Test name
Test status
Simulation time 6994902141 ps
CPU time 238.65 seconds
Started Nov 22 01:14:38 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 251056 kb
Host smart-be7cc1ea-b8a1-4e29-84ce-bc87acc26598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10888
6753233938920955744969611973913836580629643174739141287459069286315065002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.alert_handler_esc_alert_accum.108886753233938920955744969611973913836580629643174739141287459069286315065002
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.113528060399986252471266296299760852037447955275158224287959769248330245676749
Short name T261
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.05 seconds
Started Nov 22 01:14:49 PM PST 23
Finished Nov 22 01:15:39 PM PST 23
Peak memory 256200 kb
Host smart-9a3baf1b-d05e-4c08-a72e-4700cfb2f256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
8060399986252471266296299760852037447955275158224287959769248330245676749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.alert_handler_esc_intr_timeout.113528060399986252471266296299760852037447955275158224287959769248330245676749
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.47902502157065690264329550570256038238879113362817095036781825642509928320621
Short name T372
Test name
Test status
Simulation time 58351884139 ps
CPU time 1862.25 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:45:40 PM PST 23
Peak memory 289248 kb
Host smart-cc2909cf-169a-43d8-9dba-37a681d7f142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47902502157065690264329550570256038238879113362817095036781825642509928320621 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.alert_handler_lpg.47902502157065690264329550570256038238879113362817095036781825642509928320621
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.16374955049390721527815494318439380636489672464324095772300307790577342994824
Short name T143
Test name
Test status
Simulation time 48172572717 ps
CPU time 1519.64 seconds
Started Nov 22 01:14:34 PM PST 23
Finished Nov 22 01:39:55 PM PST 23
Peak memory 272472 kb
Host smart-2de13395-a2d1-450e-88f5-5868ce42b425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16374955049390721527815494318439380636489672464324095772300307790577342994824 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.16374955049390721527815494318439380636489672464324095772300307790577342994824
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.5447434636533399119959502395202396258350323629860424419044521724788982091509
Short name T345
Test name
Test status
Simulation time 17273552054 ps
CPU time 385.67 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:21:03 PM PST 23
Peak memory 247372 kb
Host smart-74103627-f15b-4137-b561-d5506b85c93d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5447434636533399119959502395202396258350323629860424419044521724788982091509 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.5447434636533399119959502395202396258350323629860424419044521724788982091509
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.12117328259401677667909489535958448418723667723057660503401987483605081799723
Short name T287
Test name
Test status
Simulation time 1399732617 ps
CPU time 45.85 seconds
Started Nov 22 01:14:50 PM PST 23
Finished Nov 22 01:15:38 PM PST 23
Peak memory 255320 kb
Host smart-7f255651-4546-4ee0-8617-c561881d2e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12117
328259401677667909489535958448418723667723057660503401987483605081799723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.alert_handler_random_alerts.12117328259401677667909489535958448418723667723057660503401987483605081799723
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.114604113966567917544530689514377384142307538768053966719308331023338195307154
Short name T305
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.87 seconds
Started Nov 22 01:14:38 PM PST 23
Finished Nov 22 01:15:23 PM PST 23
Peak memory 254660 kb
Host smart-00c077f4-cfb0-44fe-ac63-b4b80329c3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11460
4113966567917544530689514377384142307538768053966719308331023338195307154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.alert_handler_random_classes.114604113966567917544530689514377384142307538768053966719308331023338195307154
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.39627241464503630576572490439762763710263194993543443677197541352878289453210
Short name T646
Test name
Test status
Simulation time 1261680150 ps
CPU time 45.52 seconds
Started Nov 22 01:14:42 PM PST 23
Finished Nov 22 01:15:29 PM PST 23
Peak memory 255340 kb
Host smart-da731924-e665-43a4-96dd-50ec9a72d2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
241464503630576572490439762763710263194993543443677197541352878289453210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
alert_handler_sig_int_fail.39627241464503630576572490439762763710263194993543443677197541352878289453210
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4127138911564057639632939317045799566480476370166586197010059042016697037740
Short name T686
Test name
Test status
Simulation time 1558784916 ps
CPU time 51.52 seconds
Started Nov 22 01:14:37 PM PST 23
Finished Nov 22 01:15:30 PM PST 23
Peak memory 248788 kb
Host smart-46213fe2-23dd-4a38-9de3-634b8538674c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41271
38911564057639632939317045799566480476370166586197010059042016697037740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_smoke.4127138911564057639632939317045799566480476370166586197010059042016697037740
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.75234912839948416438857682443843278052659200134080676078760768358504807525703
Short name T313
Test name
Test status
Simulation time 63383433172 ps
CPU time 2076.36 seconds
Started Nov 22 01:14:44 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 289788 kb
Host smart-f48aa81f-1278-4273-9151-b96cd0341626
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75234912839948416438857682443843278052659200134080676078760768358504807525703 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.75234912839948416438857682443843278052659200134080676078760768
358504807525703
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.14815317952206025827746107325348761167783519280641055984440699393537525053483
Short name T217
Test name
Test status
Simulation time 79866015596 ps
CPU time 2715.42 seconds
Started Nov 22 01:14:38 PM PST 23
Finished Nov 22 01:59:55 PM PST 23
Peak memory 298120 kb
Host smart-e1de66c1-0770-4de1-8b57-c8bca9d03c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148153179522060258277461073253487611677835192806
41055984440699393537525053483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.14815317
952206025827746107325348761167783519280641055984440699393537525053483
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.32985976886639891432726877743765010331138976676249908012375562082752050506474
Short name T490
Test name
Test status
Simulation time 30823729350 ps
CPU time 1002.93 seconds
Started Nov 22 01:14:49 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 272324 kb
Host smart-51219754-af04-494b-b95d-fc38a5ec477e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32985976886639891432726877743765010331138976676249908012375562082752050506474 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.alert_handler_entropy.32985976886639891432726877743765010331138976676249908012375562082752050506474
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.28116430263308014313645246748147447467150056876925963362026457689136883226166
Short name T254
Test name
Test status
Simulation time 6994902141 ps
CPU time 221.83 seconds
Started Nov 22 01:14:49 PM PST 23
Finished Nov 22 01:18:31 PM PST 23
Peak memory 251076 kb
Host smart-84afdd20-e1ab-4a24-a26d-384989e56101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28116
430263308014313645246748147447467150056876925963362026457689136883226166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.alert_handler_esc_alert_accum.28116430263308014313645246748147447467150056876925963362026457689136883226166
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.15704684144666644524272999358155094508644100942179081514386615599481020068686
Short name T19
Test name
Test status
Simulation time 1449142936 ps
CPU time 48 seconds
Started Nov 22 01:14:38 PM PST 23
Finished Nov 22 01:15:28 PM PST 23
Peak memory 255472 kb
Host smart-53ca098e-7646-4cc7-9963-86912b0e0a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
684144666644524272999358155094508644100942179081514386615599481020068686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.alert_handler_esc_intr_timeout.15704684144666644524272999358155094508644100942179081514386615599481020068686
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.22614848834114543571718573779930882151010252243991957113964920156496751303217
Short name T382
Test name
Test status
Simulation time 58351884139 ps
CPU time 1901.28 seconds
Started Nov 22 01:14:38 PM PST 23
Finished Nov 22 01:46:21 PM PST 23
Peak memory 289196 kb
Host smart-bf03398a-7548-4d50-a9ad-8ab71e5deea4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22614848834114543571718573779930882151010252243991957113964920156496751303217 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.alert_handler_lpg.22614848834114543571718573779930882151010252243991957113964920156496751303217
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.38956338393504711087384496342715029497948562396812114612174107569523657407435
Short name T108
Test name
Test status
Simulation time 48172572717 ps
CPU time 1585.28 seconds
Started Nov 22 01:15:21 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 272472 kb
Host smart-d78c4294-e546-4868-952e-6ec9e174af48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38956338393504711087384496342715029497948562396812114612174107569523657407435 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.38956338393504711087384496342715029497948562396812114612174107569523657407435
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.11363774030322475585218749989714750706733378149095848978760834785995194164892
Short name T150
Test name
Test status
Simulation time 17273552054 ps
CPU time 378.58 seconds
Started Nov 22 01:14:49 PM PST 23
Finished Nov 22 01:21:11 PM PST 23
Peak memory 247104 kb
Host smart-13222e80-4920-40b5-9b35-431231ee771a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11363774030322475585218749989714750706733378149095848978760834785995194164892 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.11363774030322475585218749989714750706733378149095848978760834785995194164892
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.81171929482099701950142876080847482023483584346715830415237269249204298695719
Short name T49
Test name
Test status
Simulation time 1399732617 ps
CPU time 48.36 seconds
Started Nov 22 01:15:22 PM PST 23
Finished Nov 22 01:16:10 PM PST 23
Peak memory 255440 kb
Host smart-c49a1257-f279-44b9-a110-115ae38c289c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81171
929482099701950142876080847482023483584346715830415237269249204298695719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.alert_handler_random_alerts.81171929482099701950142876080847482023483584346715830415237269249204298695719
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.86568722428982699060432593184592541069420495563143398695148936355232515624567
Short name T467
Test name
Test status
Simulation time 1291269199 ps
CPU time 44.73 seconds
Started Nov 22 01:14:38 PM PST 23
Finished Nov 22 01:15:24 PM PST 23
Peak memory 254680 kb
Host smart-bb2665bc-606b-4220-abbd-f4611bf2ce9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86568
722428982699060432593184592541069420495563143398695148936355232515624567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.alert_handler_random_classes.86568722428982699060432593184592541069420495563143398695148936355232515624567
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.68945201225801344519024715955674836922468355419122224196653366111753206742885
Short name T580
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.95 seconds
Started Nov 22 01:15:20 PM PST 23
Finished Nov 22 01:16:06 PM PST 23
Peak memory 255476 kb
Host smart-0db70ffa-72b0-421f-8b6d-6cf51f598617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68945
201225801344519024715955674836922468355419122224196653366111753206742885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
alert_handler_sig_int_fail.68945201225801344519024715955674836922468355419122224196653366111753206742885
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.4396469089423344171294405248174901073489400646495016959123385287677365839117
Short name T392
Test name
Test status
Simulation time 1558784916 ps
CPU time 52.9 seconds
Started Nov 22 01:14:36 PM PST 23
Finished Nov 22 01:15:31 PM PST 23
Peak memory 248796 kb
Host smart-f36c214f-4307-4033-8d66-7a0909fc1580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43964
69089423344171294405248174901073489400646495016959123385287677365839117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_smoke.4396469089423344171294405248174901073489400646495016959123385287677365839117
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.51873244508113554629677019191374661349306655094516635356825773015493976698999
Short name T65
Test name
Test status
Simulation time 63383433172 ps
CPU time 2065.43 seconds
Started Nov 22 01:15:23 PM PST 23
Finished Nov 22 01:49:49 PM PST 23
Peak memory 289584 kb
Host smart-8cf3056a-a308-40f3-89a7-8c607542723c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51873244508113554629677019191374661349306655094516635356825773015493976698999 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.51873244508113554629677019191374661349306655094516635356825773
015493976698999
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.113392713944199300948190221234576125768229547177402107501573547184361559793259
Short name T359
Test name
Test status
Simulation time 79866015596 ps
CPU time 2760.05 seconds
Started Nov 22 01:15:23 PM PST 23
Finished Nov 22 02:01:24 PM PST 23
Peak memory 298004 kb
Host smart-a1137a6e-9419-4c68-a94a-68365c276e90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113392713944199300948190221234576125768229547177
402107501573547184361559793259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1133927
13944199300948190221234576125768229547177402107501573547184361559793259
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.72944481503524050686213487859749103404741650624668320504687328856834075115807
Short name T122
Test name
Test status
Simulation time 49707703 ps
CPU time 3.06 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 248988 kb
Host smart-7bdb366d-4bab-40cc-a240-edc305ef1862
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=72944481503524050686213487859749103404741650624668320504687328856834075115807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.alert_handler_alert_accum_saturation.72944481503524050686213487859749103404741650624668320504687328856834075115807
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.113587308271000470219782872890305879924078279173920553278373608904615503072590
Short name T349
Test name
Test status
Simulation time 30823729350 ps
CPU time 1098.05 seconds
Started Nov 22 01:12:42 PM PST 23
Finished Nov 22 01:31:06 PM PST 23
Peak memory 271684 kb
Host smart-82f73ab8-6859-4272-b3d5-c7da0a487fea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113587308271000470219782872890305879924078279173920553278373608904615503072590 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.alert_handler_entropy.113587308271000470219782872890305879924078279173920553278373608904615503072590
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.55253821770899655423968000805843099702729493430663935443607315699278787915848
Short name T352
Test name
Test status
Simulation time 1452482195 ps
CPU time 36.54 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:12:49 PM PST 23
Peak memory 240644 kb
Host smart-aa8384cb-e81c-4676-8e80-402b44a74e11
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=55253821770899655423968000805843099702729493430663935443607315699278787915848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.alert_handler_entropy_stress.55253821770899655423968000805843099702729493430663935443607315699278787915848
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.111733214826315713427326908304564311251253647027037922991151380362460935082270
Short name T159
Test name
Test status
Simulation time 6994902141 ps
CPU time 234.67 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:16:07 PM PST 23
Peak memory 251208 kb
Host smart-7e2e473d-08d6-47fa-9da2-d5422f22d50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
3214826315713427326908304564311251253647027037922991151380362460935082270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.alert_handler_esc_alert_accum.111733214826315713427326908304564311251253647027037922991151380362460935082270
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.31475235475552312303767942240912563714452194973272193620797222330152359008059
Short name T419
Test name
Test status
Simulation time 1449142936 ps
CPU time 48.52 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 255548 kb
Host smart-bc35074b-9b4e-4afd-91e3-c18ded5af89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31475
235475552312303767942240912563714452194973272193620797222330152359008059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.alert_handler_esc_intr_timeout.31475235475552312303767942240912563714452194973272193620797222330152359008059
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.34040355393233933787735234024099847683568632145322001665014031882063827472835
Short name T443
Test name
Test status
Simulation time 48172572717 ps
CPU time 1531.1 seconds
Started Nov 22 01:12:14 PM PST 23
Finished Nov 22 01:37:47 PM PST 23
Peak memory 272536 kb
Host smart-0c7bbb96-45e2-4b81-ab07-c35c3b13439f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34040355393233933787735234024099847683568632145322001665014031882063827472835 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.34040355393233933787735234024099847683568632145322001665014031882063827472835
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3846925474785115321244141405559385678534399013961290388150463885109032995261
Short name T441
Test name
Test status
Simulation time 17273552054 ps
CPU time 382.76 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:18:36 PM PST 23
Peak memory 247328 kb
Host smart-ab308027-f60f-44e1-a11c-9a32a07cc00e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846925474785115321244141405559385678534399013961290388150463885109032995261 -assert nopostproc +UVM_TESTNAME=alert_hand
ler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3846925474785115321244141405559385678534399013961290388150463885109032995261
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.52266485280032897380180017900018751185284155484722453655836431606034493661059
Short name T214
Test name
Test status
Simulation time 1399732617 ps
CPU time 48.64 seconds
Started Nov 22 01:12:44 PM PST 23
Finished Nov 22 01:13:38 PM PST 23
Peak memory 255444 kb
Host smart-5c25b506-bf2e-4e66-9de5-5b71eda57134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52266
485280032897380180017900018751185284155484722453655836431606034493661059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
alert_handler_random_alerts.52266485280032897380180017900018751185284155484722453655836431606034493661059
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.75832937241323520302048499815582451092325165337273594170079074363541733469814
Short name T78
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.77 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:13:34 PM PST 23
Peak memory 254832 kb
Host smart-90982d93-3a52-4eb4-87e9-3491285f87fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75832
937241323520302048499815582451092325165337273594170079074363541733469814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.alert_handler_random_classes.75832937241323520302048499815582451092325165337273594170079074363541733469814
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.9961233546664618790045580476842889759648039697585458720160484754738840149373
Short name T269
Test name
Test status
Simulation time 1261680150 ps
CPU time 42.87 seconds
Started Nov 22 01:12:40 PM PST 23
Finished Nov 22 01:13:28 PM PST 23
Peak memory 255536 kb
Host smart-3491738d-7cd8-4c6f-8802-fca509ea8bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99612
33546664618790045580476842889759648039697585458720160484754738840149373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.al
ert_handler_sig_int_fail.9961233546664618790045580476842889759648039697585458720160484754738840149373
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.60930624515869396681265513399977727415173413404125538787856516341422241543983
Short name T213
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.97 seconds
Started Nov 22 01:12:28 PM PST 23
Finished Nov 22 01:13:26 PM PST 23
Peak memory 248724 kb
Host smart-9a3c9a1a-2bc5-424d-87e9-339046fef965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60930
624515869396681265513399977727415173413404125538787856516341422241543983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_ha
ndler_smoke.60930624515869396681265513399977727415173413404125538787856516341422241543983
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.6148873806735253602836841299663050815761331961605471481591716318348215576674
Short name T326
Test name
Test status
Simulation time 63383433172 ps
CPU time 2046.64 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:46:15 PM PST 23
Peak memory 289588 kb
Host smart-cd3a6cdc-6d35-46fe-ac28-0bd4e0df2041
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6148873806735253602836841299663050815761331961605471481591716318348215576674 -assert nopos
tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.6148873806735253602836841299663050815761331961605471481591716318348215576674
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.18370274836666455210857809835242006381711733630454016490526379829003060951538
Short name T245
Test name
Test status
Simulation time 79866015596 ps
CPU time 2938.17 seconds
Started Nov 22 01:12:20 PM PST 23
Finished Nov 22 02:01:21 PM PST 23
Peak memory 298076 kb
Host smart-1235ad05-06a6-4852-8b1e-15a6a91460ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183702748366664552108578098352420063817117336304
54016490526379829003060951538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.183702748
36666455210857809835242006381711733630454016490526379829003060951538
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.41111556482727783237704141807613670108054610440062755748622691715045666498427
Short name T459
Test name
Test status
Simulation time 49707703 ps
CPU time 3.1 seconds
Started Nov 22 01:12:15 PM PST 23
Finished Nov 22 01:12:20 PM PST 23
Peak memory 248304 kb
Host smart-7e11d05e-ee5d-47db-8e78-ad0effd12450
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=41111556482727783237704141807613670108054610440062755748622691715045666498427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.alert_handler_alert_accum_saturation.41111556482727783237704141807613670108054610440062755748622691715045666498427
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.75615708347085257848622616089363607393622015164431738799132148997897146590953
Short name T291
Test name
Test status
Simulation time 30823729350 ps
CPU time 1085.36 seconds
Started Nov 22 01:12:20 PM PST 23
Finished Nov 22 01:30:28 PM PST 23
Peak memory 272332 kb
Host smart-a85609b2-c87c-443f-8343-d2082ff0c114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75615708347085257848622616089363607393622015164431738799132148997897146590953 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.alert_handler_entropy.75615708347085257848622616089363607393622015164431738799132148997897146590953
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.45016210429412163349870575219359258038406966531772131112418785809653713335504
Short name T558
Test name
Test status
Simulation time 1452482195 ps
CPU time 37.42 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:49 PM PST 23
Peak memory 240656 kb
Host smart-0dfdf175-3d41-46a6-a0a9-46e2690600b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=45016210429412163349870575219359258038406966531772131112418785809653713335504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.alert_handler_entropy_stress.45016210429412163349870575219359258038406966531772131112418785809653713335504
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.53344648703455243862547866942401462023804395771912875235479875931322728393120
Short name T629
Test name
Test status
Simulation time 6994902141 ps
CPU time 249.5 seconds
Started Nov 22 01:12:20 PM PST 23
Finished Nov 22 01:16:32 PM PST 23
Peak memory 251012 kb
Host smart-4e4df322-60de-452c-aeb5-bcb4c9574186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53344
648703455243862547866942401462023804395771912875235479875931322728393120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.alert_handler_esc_alert_accum.53344648703455243862547866942401462023804395771912875235479875931322728393120
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.35774761266714543004018036394765042394534514423909240900475008817988279561137
Short name T180
Test name
Test status
Simulation time 1449142936 ps
CPU time 45.51 seconds
Started Nov 22 01:12:14 PM PST 23
Finished Nov 22 01:13:01 PM PST 23
Peak memory 255668 kb
Host smart-1e34bd2a-98aa-4fe7-a0a8-73957526d3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35774
761266714543004018036394765042394534514423909240900475008817988279561137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.alert_handler_esc_intr_timeout.35774761266714543004018036394765042394534514423909240900475008817988279561137
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.43333369645515569647097095976072947520443442814972348757173196969432078269872
Short name T149
Test name
Test status
Simulation time 58351884139 ps
CPU time 1829.65 seconds
Started Nov 22 01:12:34 PM PST 23
Finished Nov 22 01:43:12 PM PST 23
Peak memory 289316 kb
Host smart-12253e83-801a-4330-9c6a-20ff34290f2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43333369645515569647097095976072947520443442814972348757173196969432078269872 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.alert_handler_lpg.43333369645515569647097095976072947520443442814972348757173196969432078269872
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.62044857244236588588272934581492043473836616389412615850074458324450450220782
Short name T312
Test name
Test status
Simulation time 48172572717 ps
CPU time 1695.06 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:40:27 PM PST 23
Peak memory 272504 kb
Host smart-e2718b15-84e1-4a83-b841-389ce335b88e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62044857244236588588272934581492043473836616389412615850074458324450450220782 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.62044857244236588588272934581492043473836616389412615850074458324450450220782
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.78336949068528420420989403551850643691720876843146520140163021058477349694506
Short name T639
Test name
Test status
Simulation time 17273552054 ps
CPU time 404.55 seconds
Started Nov 22 01:12:12 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 247528 kb
Host smart-8d028d22-f72e-4bad-a838-4bf1935abec8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78336949068528420420989403551850643691720876843146520140163021058477349694506 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.78336949068528420420989403551850643691720876843146520140163021058477349694506
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.89577516977620507339438241767601650882393488372133033354869426057710886750950
Short name T41
Test name
Test status
Simulation time 1399732617 ps
CPU time 46.11 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:12:56 PM PST 23
Peak memory 255436 kb
Host smart-dee9c36b-eeb4-4ad4-8549-919eed6f409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89577
516977620507339438241767601650882393488372133033354869426057710886750950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
alert_handler_random_alerts.89577516977620507339438241767601650882393488372133033354869426057710886750950
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.53889118638357531560662134602567905775379546395940120807825716397030234804696
Short name T673
Test name
Test status
Simulation time 1291269199 ps
CPU time 45.92 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 254868 kb
Host smart-66bc7936-1c17-4c72-9bbc-b446c669dbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53889
118638357531560662134602567905775379546395940120807825716397030234804696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.alert_handler_random_classes.53889118638357531560662134602567905775379546395940120807825716397030234804696
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.66693968841446473364086813850036503635567665212157333197000578398095699242471
Short name T430
Test name
Test status
Simulation time 1261680150 ps
CPU time 48.18 seconds
Started Nov 22 01:12:20 PM PST 23
Finished Nov 22 01:13:10 PM PST 23
Peak memory 255244 kb
Host smart-88ce493d-6e34-4f14-a53f-7f4219a2efe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66693
968841446473364086813850036503635567665212157333197000578398095699242471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
lert_handler_sig_int_fail.66693968841446473364086813850036503635567665212157333197000578398095699242471
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.101923197301611684741477255429950637231725646973585418241106283816942964894442
Short name T448
Test name
Test status
Simulation time 1558784916 ps
CPU time 52.09 seconds
Started Nov 22 01:12:11 PM PST 23
Finished Nov 22 01:13:06 PM PST 23
Peak memory 248832 kb
Host smart-469eb14b-903a-4119-80f0-2eee31558721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10192
3197301611684741477255429950637231725646973585418241106283816942964894442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_h
andler_smoke.101923197301611684741477255429950637231725646973585418241106283816942964894442
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2154275947519127173783674278967169828549987507780451209205601587491555856888
Short name T501
Test name
Test status
Simulation time 63383433172 ps
CPU time 2117.41 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:47:30 PM PST 23
Peak memory 289772 kb
Host smart-64ebeab1-0d09-41f5-82ca-6e505b9d7b8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154275947519127173783674278967169828549987507780451209205601587491555856888 -assert nopos
tproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.2154275947519127173783674278967169828549987507780451209205601587491555856888
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.90463361314885187849301496393044401388862908351292726329148765306652749672380
Short name T637
Test name
Test status
Simulation time 79866015596 ps
CPU time 2679.24 seconds
Started Nov 22 01:12:24 PM PST 23
Finished Nov 22 01:57:12 PM PST 23
Peak memory 298180 kb
Host smart-750d425d-11f3-4c9f-b6b3-792c2f758fd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904633613148851878493014963930444013888629083512
92726329148765306652749672380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.904633613
14885187849301496393044401388862908351292726329148765306652749672380
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.87548847920082367511255771762217644001747165664747786091865630262596133400115
Short name T513
Test name
Test status
Simulation time 49707703 ps
CPU time 2.94 seconds
Started Nov 22 01:12:19 PM PST 23
Finished Nov 22 01:12:24 PM PST 23
Peak memory 248988 kb
Host smart-4b4aecac-eb54-405b-a59b-feb3f83ba4a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=87548847920082367511255771762217644001747165664747786091865630262596133400115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.alert_handler_alert_accum_saturation.87548847920082367511255771762217644001747165664747786091865630262596133400115
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.11987936060254383181262260280949069300455059470235901573456754613583830744705
Short name T373
Test name
Test status
Simulation time 30823729350 ps
CPU time 1074.2 seconds
Started Nov 22 01:12:19 PM PST 23
Finished Nov 22 01:30:15 PM PST 23
Peak memory 272420 kb
Host smart-c8e54441-a03d-4769-9d76-a965a4f9a3e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11987936060254383181262260280949069300455059470235901573456754613583830744705 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.alert_handler_entropy.11987936060254383181262260280949069300455059470235901573456754613583830744705
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.105175553575961662596921421940866445318656318691494840639218862776423396632964
Short name T426
Test name
Test status
Simulation time 1452482195 ps
CPU time 35.63 seconds
Started Nov 22 01:12:21 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 240640 kb
Host smart-49c83503-bfa8-4666-959b-b7c6ae68d86c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=105175553575961662596921421940866445318656318691494840639218862776423396632964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.alert_handler_entropy_stress.105175553575961662596921421940866445318656318691494840639218862776423396632964
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.14165232189060953592352744521080994156461185416567913155868607805826146909114
Short name T535
Test name
Test status
Simulation time 6994902141 ps
CPU time 222.21 seconds
Started Nov 22 01:12:17 PM PST 23
Finished Nov 22 01:16:01 PM PST 23
Peak memory 251184 kb
Host smart-c8fb025e-2840-4ae4-a96c-df1e50d878d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14165
232189060953592352744521080994156461185416567913155868607805826146909114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.alert_handler_esc_alert_accum.14165232189060953592352744521080994156461185416567913155868607805826146909114
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.39014166198377177225757298049283103065508877056823305094442709146829939196546
Short name T212
Test name
Test status
Simulation time 1449142936 ps
CPU time 50.42 seconds
Started Nov 22 01:12:50 PM PST 23
Finished Nov 22 01:13:43 PM PST 23
Peak memory 255532 kb
Host smart-0cc124d8-ab28-4ad0-ac8e-f2412eb2e617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39014
166198377177225757298049283103065508877056823305094442709146829939196546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.alert_handler_esc_intr_timeout.39014166198377177225757298049283103065508877056823305094442709146829939196546
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.10823316247868686186662721552141404545798040244280200020246539926749778926332
Short name T146
Test name
Test status
Simulation time 58351884139 ps
CPU time 1985.07 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 01:45:46 PM PST 23
Peak memory 289256 kb
Host smart-979aff56-1606-4d85-8f4e-d69861803e9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10823316247868686186662721552141404545798040244280200020246539926749778926332 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.alert_handler_lpg.10823316247868686186662721552141404545798040244280200020246539926749778926332
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.75273937186189823718626238849975852684932082148063585940381262158304692196685
Short name T192
Test name
Test status
Simulation time 48172572717 ps
CPU time 1557.24 seconds
Started Nov 22 01:12:27 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 272528 kb
Host smart-419af909-bf0c-48fb-babd-69e3f7b11af1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75273937186189823718626238849975852684932082148063585940381262158304692196685 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.75273937186189823718626238849975852684932082148063585940381262158304692196685
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.102871370109623079616625669518179081535255237418945112814824384309344732550137
Short name T470
Test name
Test status
Simulation time 17273552054 ps
CPU time 415.77 seconds
Started Nov 22 01:12:32 PM PST 23
Finished Nov 22 01:19:36 PM PST 23
Peak memory 247484 kb
Host smart-42487531-11d8-448e-a147-34827206469a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102871370109623079616625669518179081535255237418945112814824384309344732550137 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.102871370109623079616625669518179081535255237418945112814824384309344732550137
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.62454425845771814403668053900673837512944686270904611115971170225137962121691
Short name T136
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.58 seconds
Started Nov 22 01:12:19 PM PST 23
Finished Nov 22 01:13:08 PM PST 23
Peak memory 255456 kb
Host smart-c7d026cc-0b7b-43e0-8c74-863e83a67f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62454
425845771814403668053900673837512944686270904611115971170225137962121691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
alert_handler_random_alerts.62454425845771814403668053900673837512944686270904611115971170225137962121691
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.76866844146842264977092122719794088188549002142805548788489835913698170918855
Short name T483
Test name
Test status
Simulation time 1291269199 ps
CPU time 41.37 seconds
Started Nov 22 01:12:15 PM PST 23
Finished Nov 22 01:12:58 PM PST 23
Peak memory 254144 kb
Host smart-a345a681-7051-40b6-a471-f23daa100a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76866
844146842264977092122719794088188549002142805548788489835913698170918855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.alert_handler_random_classes.76866844146842264977092122719794088188549002142805548788489835913698170918855
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.14403581047101651503557219464495541775037285655170886825148350114995064568884
Short name T251
Test name
Test status
Simulation time 1261680150 ps
CPU time 43.67 seconds
Started Nov 22 01:12:15 PM PST 23
Finished Nov 22 01:13:01 PM PST 23
Peak memory 255548 kb
Host smart-c7de82ef-27d8-4ce3-befd-93b5735bae36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14403
581047101651503557219464495541775037285655170886825148350114995064568884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
lert_handler_sig_int_fail.14403581047101651503557219464495541775037285655170886825148350114995064568884
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.68703968372634470379578950528915909502974906467659767016905834549102103692528
Short name T458
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.02 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:13:00 PM PST 23
Peak memory 248532 kb
Host smart-48b45b90-775b-4ca3-9afa-ec6c9fabb44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68703
968372634470379578950528915909502974906467659767016905834549102103692528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_ha
ndler_smoke.68703968372634470379578950528915909502974906467659767016905834549102103692528
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.23079726257438872107233775101815686165617139064734062748830478310754326027387
Short name T622
Test name
Test status
Simulation time 63383433172 ps
CPU time 2060.72 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:46:33 PM PST 23
Peak memory 289592 kb
Host smart-faf6174a-8d5e-4394-b1a3-d86a5153075b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23079726257438872107233775101815686165617139064734062748830478310754326027387 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.230797262574388721072337751018156861656171390647340627488304783
10754326027387
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.56561174616970072765460467706055960921123613658894181752988035123581932592536
Short name T626
Test name
Test status
Simulation time 79866015596 ps
CPU time 2988.95 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 02:02:31 PM PST 23
Peak memory 298140 kb
Host smart-58b699e6-a302-4eba-9967-be7a92069b92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565611746169700727654604677060559609211236136588
94181752988035123581932592536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.565611746
16970072765460467706055960921123613658894181752988035123581932592536
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.60945321638254438305857036396480040732575545668592607209566946381393947340544
Short name T551
Test name
Test status
Simulation time 49707703 ps
CPU time 2.99 seconds
Started Nov 22 01:12:43 PM PST 23
Finished Nov 22 01:12:51 PM PST 23
Peak memory 249000 kb
Host smart-482ccc15-9f83-436f-909c-de72a9624f0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=60945321638254438305857036396480040732575545668592607209566946381393947340544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.alert_handler_alert_accum_saturation.60945321638254438305857036396480040732575545668592607209566946381393947340544
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.34324439610685034752251864725469086791910420320077466888837192705569394269947
Short name T541
Test name
Test status
Simulation time 30823729350 ps
CPU time 1131.14 seconds
Started Nov 22 01:12:28 PM PST 23
Finished Nov 22 01:31:27 PM PST 23
Peak memory 272384 kb
Host smart-e8241cc1-7d10-40e8-944f-358571b7207a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34324439610685034752251864725469086791910420320077466888837192705569394269947 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.alert_handler_entropy.34324439610685034752251864725469086791910420320077466888837192705569394269947
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.106419860707144744370720859247812553161344028949956949781471976987687673770346
Short name T408
Test name
Test status
Simulation time 1452482195 ps
CPU time 34.88 seconds
Started Nov 22 01:12:40 PM PST 23
Finished Nov 22 01:13:21 PM PST 23
Peak memory 240640 kb
Host smart-a2cb0b58-1efc-4377-9047-4ec8cbfb284a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=106419860707144744370720859247812553161344028949956949781471976987687673770346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.alert_handler_entropy_stress.106419860707144744370720859247812553161344028949956949781471976987687673770346
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.37144364625596110844900252154917258188405330745310917295691782823944327152938
Short name T432
Test name
Test status
Simulation time 6994902141 ps
CPU time 234.76 seconds
Started Nov 22 01:12:23 PM PST 23
Finished Nov 22 01:16:24 PM PST 23
Peak memory 251084 kb
Host smart-1c2abdd3-ae0e-4346-bc1a-ec990f7ec7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37144
364625596110844900252154917258188405330745310917295691782823944327152938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.alert_handler_esc_alert_accum.37144364625596110844900252154917258188405330745310917295691782823944327152938
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.91756966794432409005114131307172112304661043489546576651228410888539701957727
Short name T380
Test name
Test status
Simulation time 1449142936 ps
CPU time 47.89 seconds
Started Nov 22 01:12:35 PM PST 23
Finished Nov 22 01:13:31 PM PST 23
Peak memory 255640 kb
Host smart-637808cd-afcb-4ca8-b2fb-865e828898a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91756
966794432409005114131307172112304661043489546576651228410888539701957727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.alert_handler_esc_intr_timeout.91756966794432409005114131307172112304661043489546576651228410888539701957727
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.48046375668373458723980797437584131784240455667563936251411902797833153934730
Short name T265
Test name
Test status
Simulation time 58351884139 ps
CPU time 1860.53 seconds
Started Nov 22 01:12:36 PM PST 23
Finished Nov 22 01:43:44 PM PST 23
Peak memory 289304 kb
Host smart-a988ec93-1545-4e4c-bfe2-80c3217f1b24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48046375668373458723980797437584131784240455667563936251411902797833153934730 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.alert_handler_lpg.48046375668373458723980797437584131784240455667563936251411902797833153934730
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.112743743398198133192543080442792234086133917539087563010884030461647120311602
Short name T520
Test name
Test status
Simulation time 48172572717 ps
CPU time 1513.9 seconds
Started Nov 22 01:12:41 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 272192 kb
Host smart-34fdf1b0-b122-4361-8460-72010c5e9b2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112743743398198133192543080442792234086133917539087563010884030461647120311602 -assert nopostproc +UVM_TESTNAME=alert_ha
ndler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.112743743398198133192543080442792234086133917539087563010884030461647120311602
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.19999784911770205568343496044636767398085433354515995042418690838583846542284
Short name T516
Test name
Test status
Simulation time 17273552054 ps
CPU time 422.85 seconds
Started Nov 22 01:12:28 PM PST 23
Finished Nov 22 01:19:38 PM PST 23
Peak memory 247528 kb
Host smart-87136d87-3c2d-4717-83c7-42f80a4f37df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19999784911770205568343496044636767398085433354515995042418690838583846542284 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.19999784911770205568343496044636767398085433354515995042418690838583846542284
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.18943590085967671242085096952435594280694365107843299744141387171930438985088
Short name T644
Test name
Test status
Simulation time 1399732617 ps
CPU time 48.99 seconds
Started Nov 22 01:12:27 PM PST 23
Finished Nov 22 01:13:24 PM PST 23
Peak memory 255348 kb
Host smart-cfca1276-0671-499e-9109-b2895a6f361c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18943
590085967671242085096952435594280694365107843299744141387171930438985088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
alert_handler_random_alerts.18943590085967671242085096952435594280694365107843299744141387171930438985088
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.96303779043455690482362996626903086920043515773992082629441987557665036282519
Short name T61
Test name
Test status
Simulation time 1291269199 ps
CPU time 44.26 seconds
Started Nov 22 01:12:34 PM PST 23
Finished Nov 22 01:13:27 PM PST 23
Peak memory 254848 kb
Host smart-fc0f0e26-4006-4842-ad34-21dfd3c61e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96303
779043455690482362996626903086920043515773992082629441987557665036282519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.alert_handler_random_classes.96303779043455690482362996626903086920043515773992082629441987557665036282519
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.108525915261206417571128204686580683269313404869565998845375213530818060358162
Short name T645
Test name
Test status
Simulation time 1261680150 ps
CPU time 44.58 seconds
Started Nov 22 01:12:33 PM PST 23
Finished Nov 22 01:13:26 PM PST 23
Peak memory 255348 kb
Host smart-ff35d122-1f4b-4a2a-8edc-caac8abdc84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10852
5915261206417571128204686580683269313404869565998845375213530818060358162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
alert_handler_sig_int_fail.108525915261206417571128204686580683269313404869565998845375213530818060358162
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.93923368467776095433462476518188435593172623771804205415372277426867451385617
Short name T72
Test name
Test status
Simulation time 1558784916 ps
CPU time 53.31 seconds
Started Nov 22 01:12:27 PM PST 23
Finished Nov 22 01:13:28 PM PST 23
Peak memory 248832 kb
Host smart-cd8ee4b1-b58c-4743-bb86-ff183e1561a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93923
368467776095433462476518188435593172623771804205415372277426867451385617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_ha
ndler_smoke.93923368467776095433462476518188435593172623771804205415372277426867451385617
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.113807062251928315569550052262707098996418033250452155004369497278233029904758
Short name T85
Test name
Test status
Simulation time 63383433172 ps
CPU time 1959.04 seconds
Started Nov 22 01:12:35 PM PST 23
Finished Nov 22 01:45:22 PM PST 23
Peak memory 289636 kb
Host smart-5243e359-c233-4f37-a9ee-5dd0c6906065
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113807062251928315569550052262707098996418033250452155004369497278233029904758 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.11380706225192831556955005226270709899641803325045215500436949
7278233029904758
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.67245496462700938411566093774102897084113422324656608340374657540196833631107
Short name T537
Test name
Test status
Simulation time 49707703 ps
CPU time 2.98 seconds
Started Nov 22 01:12:07 PM PST 23
Finished Nov 22 01:12:12 PM PST 23
Peak memory 248964 kb
Host smart-22a3728a-a1cf-41ad-a39b-53fa28f3e429
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=67245496462700938411566093774102897084113422324656608340374657540196833631107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.alert_handler_alert_accum_saturation.67245496462700938411566093774102897084113422324656608340374657540196833631107
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.29590055324131084300341755243164679173213610858728929883234883895241360353886
Short name T565
Test name
Test status
Simulation time 30823729350 ps
CPU time 1100.51 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:30:33 PM PST 23
Peak memory 272468 kb
Host smart-9109f5e0-e8e2-4b09-b2d6-ad133d1f05f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29590055324131084300341755243164679173213610858728929883234883895241360353886 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.alert_handler_entropy.29590055324131084300341755243164679173213610858728929883234883895241360353886
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.29564910515412668398191774104179033795456935381200538304142802156774026503421
Short name T493
Test name
Test status
Simulation time 1452482195 ps
CPU time 37.36 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:12:47 PM PST 23
Peak memory 240628 kb
Host smart-723de6ce-935d-4869-a42b-6c8f704a2149
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=29564910515412668398191774104179033795456935381200538304142802156774026503421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.alert_handler_entropy_stress.29564910515412668398191774104179033795456935381200538304142802156774026503421
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.61102305117639069701885590296857623386733957425301004177898445835457517781590
Short name T607
Test name
Test status
Simulation time 6994902141 ps
CPU time 237.34 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:16:10 PM PST 23
Peak memory 251236 kb
Host smart-7fff18ab-efac-417c-8c89-b7afd388786a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61102
305117639069701885590296857623386733957425301004177898445835457517781590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.alert_handler_esc_alert_accum.61102305117639069701885590296857623386733957425301004177898445835457517781590
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.15694991169227106300376485317027922249444540995815203638159436562475223728661
Short name T582
Test name
Test status
Simulation time 1449142936 ps
CPU time 45.82 seconds
Started Nov 22 01:12:11 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 255440 kb
Host smart-539cbeea-c3cc-4f4f-9417-fcc1c6b4b348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15694
991169227106300376485317027922249444540995815203638159436562475223728661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.alert_handler_esc_intr_timeout.15694991169227106300376485317027922249444540995815203638159436562475223728661
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.84921226638931063159689118028807354018962689191320598304981630587335217402836
Short name T678
Test name
Test status
Simulation time 58351884139 ps
CPU time 1837.29 seconds
Started Nov 22 01:12:08 PM PST 23
Finished Nov 22 01:42:47 PM PST 23
Peak memory 289264 kb
Host smart-437684df-fc7e-4297-8be4-008ae68c01dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84921226638931063159689118028807354018962689191320598304981630587335217402836 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.alert_handler_lpg.84921226638931063159689118028807354018962689191320598304981630587335217402836
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.27415644515526844006547010908259159453911178300976349957719691599978311769256
Short name T46
Test name
Test status
Simulation time 48172572717 ps
CPU time 1514.72 seconds
Started Nov 22 01:12:06 PM PST 23
Finished Nov 22 01:37:23 PM PST 23
Peak memory 272516 kb
Host smart-7a83458a-11ca-4caf-99b6-55be51d85b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27415644515526844006547010908259159453911178300976349957719691599978311769256 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.27415644515526844006547010908259159453911178300976349957719691599978311769256
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.97960855697711203772312849622774129803085527719270090828301996319216587406141
Short name T506
Test name
Test status
Simulation time 17273552054 ps
CPU time 390.12 seconds
Started Nov 22 01:12:10 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 247568 kb
Host smart-235208c2-05d3-411a-8b0c-c41ce900f43a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97960855697711203772312849622774129803085527719270090828301996319216587406141 -assert nopostproc +UVM_TESTNAME=alert_han
dler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.97960855697711203772312849622774129803085527719270090828301996319216587406141
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.29081642999276091964398629642206499600671119243870487692751271276286522582612
Short name T667
Test name
Test status
Simulation time 1399732617 ps
CPU time 47.68 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:59 PM PST 23
Peak memory 255444 kb
Host smart-82a1ada9-e877-4c0d-b534-83baa99d077b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29081
642999276091964398629642206499600671119243870487692751271276286522582612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
alert_handler_random_alerts.29081642999276091964398629642206499600671119243870487692751271276286522582612
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.77859060072826096565586509325717359020889235337670772886266785305250560411177
Short name T608
Test name
Test status
Simulation time 1291269199 ps
CPU time 43.85 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:12:55 PM PST 23
Peak memory 254820 kb
Host smart-2e76e899-c5f1-45f9-aff8-bf2e178e2c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77859
060072826096565586509325717359020889235337670772886266785305250560411177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.alert_handler_random_classes.77859060072826096565586509325717359020889235337670772886266785305250560411177
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.42024720264544531313666983878035740719483459904072261134987734820374159310067
Short name T431
Test name
Test status
Simulation time 1261680150 ps
CPU time 47.14 seconds
Started Nov 22 01:12:20 PM PST 23
Finished Nov 22 01:13:09 PM PST 23
Peak memory 255408 kb
Host smart-365f337c-24d8-4d9b-b13a-ae152d291b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42024
720264544531313666983878035740719483459904072261134987734820374159310067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
lert_handler_sig_int_fail.42024720264544531313666983878035740719483459904072261134987734820374159310067
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.115575855679101409588714968277185531553950538424208188667795936393366260865293
Short name T694
Test name
Test status
Simulation time 1558784916 ps
CPU time 50.09 seconds
Started Nov 22 01:12:51 PM PST 23
Finished Nov 22 01:13:43 PM PST 23
Peak memory 248704 kb
Host smart-d49b5fe3-27d4-4ed2-9d79-0e3d28ab99b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11557
5855679101409588714968277185531553950538424208188667795936393366260865293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_h
andler_smoke.115575855679101409588714968277185531553950538424208188667795936393366260865293
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.69070963944980053343427659939325650822819401658631944442180920028476376289846
Short name T285
Test name
Test status
Simulation time 63383433172 ps
CPU time 2032.17 seconds
Started Nov 22 01:12:09 PM PST 23
Finished Nov 22 01:46:03 PM PST 23
Peak memory 289668 kb
Host smart-bd9e231d-657a-405e-ac3c-131664b5da07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69070963944980053343427659939325650822819401658631944442180920028476376289846 -assert nopo
stproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.690709639449800533434276599393256508228194016586319444421809200
28476376289846
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.15153506389520462871725122521729883908034002473111567285696613254721298155004
Short name T449
Test name
Test status
Simulation time 79866015596 ps
CPU time 2847.99 seconds
Started Nov 22 01:12:13 PM PST 23
Finished Nov 22 01:59:43 PM PST 23
Peak memory 298184 kb
Host smart-e9242e70-6daf-428e-ab50-72744bf4dfa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151535063895204628717251225217298839080340024731
11567285696613254721298155004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.151535063
89520462871725122521729883908034002473111567285696613254721298155004
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%