Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	77039	1			T4	9		T14	13		T77	1
class_i[0x1]	67154	1			T8	1		T7	8		T14	18
class_i[0x2]	74267	1			T8	6		T14	13		T34	891
class_i[0x3]	76953	1			T8	1		T7	2		T14	5226

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	73023	1			T4	3		T7	1		T14	1437
alert[0x1]	74019	1			T4	1		T8	4		T7	1
alert[0x2]	70502	1			T4	2		T8	3		T7	2
alert[0x3]	77869	1			T4	3		T8	1		T7	6

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

295140

1

T8

6

T7

10

T14

5270

esc_ping_fail

273

1

T4

9

T8

2

T9

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	72946	1			T7	1		T14	1437		T34	515
esc_integrity_fail	alert[0x1]	73946	1			T8	4		T7	1		T14	1306
esc_integrity_fail	alert[0x2]	70444	1			T8	2		T7	2		T14	1370
esc_integrity_fail	alert[0x3]	77804	1			T7	6		T14	1157		T34	475
esc_ping_fail	alert[0x0]	77	1			T4	3		T9	1		T124	2
esc_ping_fail	alert[0x1]	73	1			T4	1		T9	2		T86	1
esc_ping_fail	alert[0x2]	58	1			T4	2		T8	1		T124	1
esc_ping_fail	alert[0x3]	65	1			T4	3		T8	1		T9	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	76998	1			T14	13		T77	1		T81	3
esc_integrity_fail	class_i[0x1]	67084	1			T7	8		T14	18		T34	492
esc_integrity_fail	class_i[0x2]	74174	1			T8	6		T14	13		T34	891
esc_integrity_fail	class_i[0x3]	76884	1			T7	2		T14	5226		T75	25
esc_ping_fail	class_i[0x0]	41	1			T4	9		T44	6		T271	2
esc_ping_fail	class_i[0x1]	70	1			T8	1		T86	1		T124	5
esc_ping_fail	class_i[0x2]	93	1			T9	1		T86	1		T264	5
esc_ping_fail	class_i[0x3]	69	1			T8	1		T9	3		T273	3