Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	0	40	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	0	40	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	76	1			T33	1		T34	3		T78	1
class_index[0x1]	89	1			T31	1		T34	3		T77	1
class_index[0x2]	74	1			T34	2		T80	1		T92	3
class_index[0x3]	79	1			T34	2		T77	1		T35	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	88	1			T31	1		T34	2		T78	1
intr_timeout_cnt[1]	61	1			T33	1		T34	2		T36	1
intr_timeout_cnt[2]	57	1			T34	2		T77	1		T93	1
intr_timeout_cnt[3]	19	1			T35	1		T36	1		T60	1
intr_timeout_cnt[4]	17	1			T34	2		T35	1		T93	1
intr_timeout_cnt[5]	16	1			T34	1		T77	1		T92	1
intr_timeout_cnt[6]	22	1			T101	1		T102	1		T289	1
intr_timeout_cnt[7]	15	1			T101	1		T104	3		T249	1
intr_timeout_cnt[8]	14	1			T34	1		T92	2		T102	1
intr_timeout_cnt[9]	9	1			T66	3		T48	1		T290	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	0	40	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	26	1			T34	2		T78	1		T92	1
class_index[0x0]	intr_timeout_cnt[1]	18	1			T33	1		T100	1		T62	1
class_index[0x0]	intr_timeout_cnt[2]	12	1			T131	1		T48	1		T117	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T60	1		T291	1		T223	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T34	1		T292	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T102	1		T126	2		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T293	1		T294	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	4	1			T295	1		T296	1		T37	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T52	1		T119	1		T297	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T298	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	27	1			T31	1		T92	1		T93	1
class_index[0x1]	intr_timeout_cnt[1]	11	1			T34	1		T52	2		T116	1
class_index[0x1]	intr_timeout_cnt[2]	21	1			T77	1		T93	1		T101	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T72	2		T299	1		T230	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T93	1		T62	1		T102	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T34	1		T114	1		T300	2
class_index[0x1]	intr_timeout_cnt[6]	6	1			T125	1		T117	1		T291	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T101	1		T48	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	6	1			T34	1		T63	1		T116	1
class_index[0x1]	intr_timeout_cnt[9]	3	1			T66	1		T48	1		T290	1
class_index[0x2]	intr_timeout_cnt[0]	12	1			T80	1		T42	1		T61	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T36	1		T60	1		T62	1
class_index[0x2]	intr_timeout_cnt[2]	15	1			T34	1		T102	1		T72	8
class_index[0x2]	intr_timeout_cnt[3]	5	1			T35	1		T36	1		T301	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T34	1		T112	1		T116	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T92	1		T70	1		T231	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T101	1		T289	1		T298	2
class_index[0x2]	intr_timeout_cnt[7]	6	1			T104	3		T249	1		T72	1
class_index[0x2]	intr_timeout_cnt[8]	4	1			T92	2		T102	1		T49	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T66	1		T302	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	23	1			T125	1		T49	2		T117	1
class_index[0x3]	intr_timeout_cnt[1]	16	1			T34	1		T93	1		T100	2
class_index[0x3]	intr_timeout_cnt[2]	9	1			T34	1		T300	1		T115	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T48	1		T73	1		T119	1
class_index[0x3]	intr_timeout_cnt[4]	6	1			T35	1		T101	1		T52	2
class_index[0x3]	intr_timeout_cnt[5]	4	1			T77	1		T114	1		T303	1
class_index[0x3]	intr_timeout_cnt[6]	9	1			T102	1		T53	1		T117	1
class_index[0x3]	intr_timeout_cnt[7]	3	1			T30	2		T296	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T304	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T66	1		T305	1		-	-