Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	372764	1			T22	5		T27	1		T29	1
all_values[1]	372764	1			T22	5		T27	1		T29	1
all_values[2]	372764	1			T22	5		T27	1		T29	1
all_values[3]	372764	1			T22	5		T27	1		T29	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

742471

1

T22

10

T27

4

T29

4

auto[1]

748585

1

T22

10

T169

16

T170

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

895474

1

T22

14

T27

4

T29

4

auto[1]

595582

1

T22

6

T169

8

T170

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106553	1			T22	4		T27	1		T29	1
all_values[0]	auto[0]	auto[1]	79472	1			T169	2		T170	1		T225	1
all_values[0]	auto[1]	auto[0]	107676	1			T169	1		T170	2		T323	4
all_values[0]	auto[1]	auto[1]	79063	1			T22	1		T169	2		T170	2
all_values[1]	auto[0]	auto[0]	112961	1			T22	2		T27	1		T29	1
all_values[1]	auto[0]	auto[1]	72498	1			T22	3		T170	1		T229	1
all_values[1]	auto[1]	auto[0]	114390	1			T169	3		T170	5		T225	2
all_values[1]	auto[1]	auto[1]	72915	1			T169	1		T225	2		T229	3
all_values[2]	auto[0]	auto[0]	112654	1			T27	1		T29	1		T169	2
all_values[2]	auto[0]	auto[1]	73074	1			T170	2		T324	2		T325	3
all_values[2]	auto[1]	auto[0]	113924	1			T22	3		T169	5		T170	1
all_values[2]	auto[1]	auto[1]	73112	1			T22	2		T169	1		T170	3
all_values[3]	auto[0]	auto[0]	112803	1			T22	1		T27	1		T29	1
all_values[3]	auto[0]	auto[1]	72456	1			T169	2		T170	2		T225	2
all_values[3]	auto[1]	auto[0]	114513	1			T22	4		T169	3		T170	1
all_values[3]	auto[1]	auto[1]	72992	1			T170	3		T225	2		T229	2