Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	372764	1			T22	5		T27	1		T29	1
all_pins[1]	372764	1			T22	5		T27	1		T29	1
all_pins[2]	372764	1			T22	5		T27	1		T29	1
all_pins[3]	372764	1			T22	5		T27	1		T29	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1192974	1			T22	17		T27	4		T29	4
values[0x1]	298082	1			T22	3		T169	4		T170	8
transitions[0x0=>0x1]	199644	1			T22	2		T169	2		T170	3
transitions[0x1=>0x0]	199888	1			T22	3		T169	3		T170	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	293701	1			T22	4		T27	1		T29	1
all_pins[0]	values[0x1]	79063	1			T22	1		T169	2		T170	2
all_pins[0]	transitions[0x0=>0x1]	78351	1			T169	1		T323	3		T326	1
all_pins[0]	transitions[0x1=>0x0]	72524	1			T170	1		T225	1		T229	1
all_pins[1]	values[0x0]	299849	1			T22	5		T27	1		T29	1
all_pins[1]	values[0x1]	72915	1			T169	1		T225	2		T229	3
all_pins[1]	transitions[0x0=>0x1]	40593	1			T225	2		T229	2		T323	1
all_pins[1]	transitions[0x1=>0x0]	46741	1			T22	1		T169	1		T170	2
all_pins[2]	values[0x0]	299652	1			T22	3		T27	1		T29	1
all_pins[2]	values[0x1]	73112	1			T22	2		T169	1		T170	3
all_pins[2]	transitions[0x0=>0x1]	40415	1			T22	2		T169	1		T170	3
all_pins[2]	transitions[0x1=>0x0]	40218	1			T169	1		T229	2		T323	3
all_pins[3]	values[0x0]	299772	1			T22	5		T27	1		T29	1
all_pins[3]	values[0x1]	72992	1			T170	3		T225	2		T229	2
all_pins[3]	transitions[0x0=>0x1]	40285	1			T225	1		T229	1		T326	1
all_pins[3]	transitions[0x1=>0x0]	40405	1			T22	2		T169	1		T225	2