Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T22	4		T169	7		T170	7
all_values[1]	269	1			T22	4		T169	7		T170	7
all_values[2]	269	1			T22	4		T169	7		T170	7
all_values[3]	269	1			T22	4		T169	7		T170	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

561

1

T22

9

T169

11

T170

19

auto[1]

515

1

T22

7

T169

17

T170

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400

1

T22

8

T169

13

T170

8

auto[1]

676

1

T22

8

T169

15

T170

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T22

11

T169

17

T170

13

auto[1]

453

1

T22

5

T169

11

T170

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

56

1

T22

2

T169

1

T170

3

all_values[0]

auto[0]

auto[0]

auto[1]

30

1

T169

1

T229

1

T326

1

all_values[0]

auto[0]

auto[1]

auto[0]

45

1

T169

1

T225

1

T323

1

all_values[0]

auto[0]

auto[1]

auto[1]

25

1

T22

1

T169

1

T170

1

all_values[0]

auto[1]

auto[0]

auto[1]

60

1

T22

1

T169

2

T170

3

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T169

1

T229

1

T323

4

all_values[1]

auto[0]

auto[0]

auto[0]

60

1

T22

1

T169

3

T225

2

all_values[1]

auto[0]

auto[0]

auto[1]

26

1

T22

1

T326

1

T324

1

all_values[1]

auto[0]

auto[1]

auto[0]

38

1

T169

2

T170

3

T324

1

all_values[1]

auto[0]

auto[1]

auto[1]

40

1

T225

1

T229

1

T323

1

all_values[1]

auto[1]

auto[0]

auto[1]

58

1

T22

2

T169

1

T170

3

all_values[1]

auto[1]

auto[1]

auto[1]

47

1

T169

1

T170

1

T225

1

all_values[2]

auto[0]

auto[0]

auto[0]

54

1

T169

1

T170

2

T323

4

all_values[2]

auto[0]

auto[0]

auto[1]

18

1

T170

1

T325

1

T327

2

all_values[2]

auto[0]

auto[1]

auto[0]

52

1

T22

1

T169

3

T225

1

all_values[2]

auto[0]

auto[1]

auto[1]

33

1

T22

1

T169

1

T170

1

all_values[2]

auto[1]

auto[0]

auto[1]

59

1

T22

1

T170

2

T225

1

all_values[2]

auto[1]

auto[1]

auto[1]

53

1

T22

1

T169

2

T170

1

all_values[3]

auto[0]

auto[0]

auto[0]

46

1

T22

1

T323

3

T326

1

all_values[3]

auto[0]

auto[0]

auto[1]

27

1

T169

1

T170

1

T225

1

all_values[3]

auto[0]

auto[1]

auto[0]

49

1

T22

3

T169

2

T323

3

all_values[3]

auto[0]

auto[1]

auto[1]

24

1

T170

1

T229

1

T324

1

all_values[3]

auto[1]

auto[0]

auto[1]

67

1

T169

1

T170

4

T326

1

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T169

3

T170

1

T225

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal