Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91460	1			T5	44		T7	1308		T14	1212
accum_cnt_1000	243632	1			T2	24		T3	918		T5	1121
accum_cnt_100	28082	1			T2	29		T3	144		T5	59
accum_cnt_50	72325	1			T2	26		T3	100		T4	5
accum_cnt_10	194697	1			T1	4		T2	9		T3	25
accum_cnt_0	429838	1			T1	64		T2	112		T3	3561

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	275858	1			T1	17		T2	50		T3	1187
class_index[0x1]	275858	1			T1	17		T2	50		T3	1187
class_index[0x2]	275857	1			T1	17		T2	50		T3	1187
class_index[0x3]	275857	1			T1	17		T2	50		T3	1187

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26842	1			T6	448		T36	219		T88	563
class_index[0x0]	accum_cnt_1000	70837	1			T2	12		T19	54		T20	29
class_index[0x0]	accum_cnt_100	8149	1			T2	16		T19	17		T20	18
class_index[0x0]	accum_cnt_50	18447	1			T2	11		T19	13		T20	13
class_index[0x0]	accum_cnt_10	56137	1			T1	4		T2	5		T5	650
class_index[0x0]	accum_cnt_0	81996	1			T1	13		T2	6		T3	1187
class_index[0x1]	accum_cnt_2000	24494	1			T7	721		T14	591		T6	556
class_index[0x1]	accum_cnt_1000	58992	1			T2	12		T7	659		T20	20
class_index[0x1]	accum_cnt_100	6877	1			T2	13		T7	38		T20	22
class_index[0x1]	accum_cnt_50	15725	1			T2	15		T19	84		T7	31
class_index[0x1]	accum_cnt_10	44369	1			T2	4		T5	4		T19	7
class_index[0x1]	accum_cnt_0	114777	1			T1	17		T2	6		T3	1187
class_index[0x2]	accum_cnt_2000	18043	1			T5	9		T7	587		T14	621
class_index[0x2]	accum_cnt_1000	56967	1			T5	578		T7	504		T14	576
class_index[0x2]	accum_cnt_100	6936	1			T5	30		T7	29		T14	30
class_index[0x2]	accum_cnt_50	23514	1			T4	5		T5	24		T7	23
class_index[0x2]	accum_cnt_10	48696	1			T4	24		T5	10		T8	1
class_index[0x2]	accum_cnt_0	110268	1			T1	17		T2	50		T3	1187
class_index[0x3]	accum_cnt_2000	22081	1			T5	35		T16	88		T81	43
class_index[0x3]	accum_cnt_1000	56836	1			T3	918		T5	543		T16	608
class_index[0x3]	accum_cnt_100	6120	1			T3	144		T5	29		T16	31
class_index[0x3]	accum_cnt_50	14639	1			T3	100		T5	25		T19	80
class_index[0x3]	accum_cnt_10	45495	1			T3	25		T18	5		T5	16
class_index[0x3]	accum_cnt_0	122797	1			T1	17		T2	50		T4	38