Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5439	1			T57	32		T124	1		T93	2
alert[0x1]	9040	1			T8	1		T75	1		T101	13
alert[0x2]	4264	1			T81	1		T36	10		T95	1
alert[0x3]	7528	1			T8	1		T57	10		T9	1
alert[0x4]	5055	1			T4	1		T9	1		T36	1
alert[0x5]	11974	1			T4	1		T9	1		T92	10
alert[0x6]	4634	1			T92	16		T36	11		T60	3
alert[0x7]	2460	1			T57	2		T92	9		T86	1
alert[0x8]	10962	1			T8	1		T9	2		T124	2
alert[0x9]	5269	1			T4	1		T75	2		T9	1
alert[0xa]	7666	1			T57	13		T77	2		T92	12
alert[0xb]	15979	1			T8	1		T57	1		T9	1
alert[0xc]	19263	1			T4	1		T18	3		T57	6
alert[0xd]	4971	1			T81	14		T92	1		T60	17
alert[0xe]	1271	1			T4	2		T81	1		T35	1
alert[0xf]	3742	1			T86	1		T101	269		T62	842
alert[0x10]	7526	1			T60	1		T95	17		T39	76
alert[0x11]	4412	1			T4	1		T57	2		T81	2
alert[0x12]	5427	1			T35	3		T95	14		T106	5
alert[0x13]	14052	1			T77	7		T60	15		T96	8
alert[0x14]	5024	1			T81	1		T92	7		T36	2
alert[0x15]	9530	1			T92	3		T36	21		T86	1
alert[0x16]	5120	1			T4	1		T41	12		T60	2
alert[0x17]	4699	1			T4	1		T75	2		T9	1
alert[0x18]	18380	1			T8	1		T57	3		T9	1
alert[0x19]	8224	1			T36	3		T124	1		T95	916
alert[0x1a]	4600	1			T4	1		T9	1		T93	9
alert[0x1b]	13752	1			T4	2		T57	16		T92	1
alert[0x1c]	2539	1			T36	4		T93	2		T95	2
alert[0x1d]	7161	1			T81	4		T106	3		T62	21
alert[0x1e]	9055	1			T81	1		T93	1		T263	2
alert[0x1f]	13320	1			T3	1		T4	2		T18	27
alert[0x20]	7307	1			T8	1		T35	5		T36	11
alert[0x21]	3269	1			T9	2		T81	1		T92	26
alert[0x22]	14749	1			T8	1		T17	1		T9	1
alert[0x23]	9362	1			T9	1		T81	17		T88	3
alert[0x24]	3732	1			T8	1		T36	14		T44	1
alert[0x25]	3508	1			T4	1		T81	1		T39	174
alert[0x26]	3362	1			T57	3		T36	17		T93	2
alert[0x27]	2911	1			T75	64		T77	2		T86	1
alert[0x28]	6101	1			T76	1		T36	168		T93	7
alert[0x29]	6338	1			T36	8		T86	1		T124	1
alert[0x2a]	3796	1			T57	6		T86	1		T93	3
alert[0x2b]	5515	1			T92	1		T36	4		T60	49
alert[0x2c]	4441	1			T36	274		T101	1		T106	7
alert[0x2d]	4661	1			T3	1		T81	45		T92	9
alert[0x2e]	4247	1			T81	20		T124	1		T44	1
alert[0x2f]	4786	1			T75	2		T81	4		T36	2
alert[0x30]	5675	1			T4	1		T92	9		T36	66
alert[0x31]	11518	1			T57	5		T9	1		T92	31
alert[0x32]	6332	1			T75	11		T36	2		T124	1
alert[0x33]	5756	1			T60	1		T95	171		T96	5
alert[0x34]	3774	1			T18	3		T8	1		T92	40
alert[0x35]	2399	1			T81	1		T60	3		T95	6
alert[0x36]	5678	1			T4	1		T77	7		T81	1
alert[0x37]	3056	1			T57	3		T35	12		T93	29
alert[0x38]	4110	1			T77	1		T92	7		T36	49
alert[0x39]	7878	1			T81	2		T39	673		T61	933
alert[0x3a]	3885	1			T81	4		T36	1		T59	3
alert[0x3b]	3664	1			T57	28		T92	13		T36	14
alert[0x3c]	3486	1			T81	3		T36	3		T39	1015
alert[0x3d]	2877	1			T92	14		T95	18		T39	6
alert[0x3e]	8371	1			T8	1		T81	1		T92	31
alert[0x3f]	17680	1			T93	11		T101	46		T106	4
alert[0x40]	4067	1			T57	6		T263	1		T39	8

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	102992	1			T4	2		T8	9		T57	133
class_i[0x1]	133719	1			T3	2		T57	3		T75	2
class_i[0x2]	117172	1			T4	14		T18	33		T8	1
class_i[0x3]	86746	1			T4	1		T75	11		T76	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

439944

1

T18

33

T57

136

T75

82

alert_ping_fail

685

1

T3

2

T4

17

T8

10

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5427	1			T57	32		T93	2		T60	2
alert_integrity_fail	alert[0x1]	9032	1			T75	1		T101	13		T62	71
alert_integrity_fail	alert[0x2]	4251	1			T81	1		T36	10		T95	1
alert_integrity_fail	alert[0x3]	7520	1			T57	10		T81	3		T59	1
alert_integrity_fail	alert[0x4]	5048	1			T36	1		T60	14		T96	2
alert_integrity_fail	alert[0x5]	11957	1			T92	10		T36	1		T101	3
alert_integrity_fail	alert[0x6]	4617	1			T92	16		T36	11		T60	3
alert_integrity_fail	alert[0x7]	2451	1			T57	2		T92	9		T93	60
alert_integrity_fail	alert[0x8]	10946	1			T93	153		T60	16		T39	635
alert_integrity_fail	alert[0x9]	5260	1			T75	2		T81	1		T36	11
alert_integrity_fail	alert[0xa]	7649	1			T57	13		T77	2		T92	12
alert_integrity_fail	alert[0xb]	15971	1			T57	1		T81	45		T39	509
alert_integrity_fail	alert[0xc]	19254	1			T18	3		T57	6		T92	2
alert_integrity_fail	alert[0xd]	4962	1			T81	14		T92	1		T60	17
alert_integrity_fail	alert[0xe]	1258	1			T81	1		T35	1		T60	18
alert_integrity_fail	alert[0xf]	3735	1			T101	269		T62	842		T66	139
alert_integrity_fail	alert[0x10]	7517	1			T60	1		T95	17		T39	76
alert_integrity_fail	alert[0x11]	4403	1			T57	2		T81	2		T92	2
alert_integrity_fail	alert[0x12]	5419	1			T35	3		T95	14		T106	5
alert_integrity_fail	alert[0x13]	14038	1			T77	7		T60	15		T96	8
alert_integrity_fail	alert[0x14]	5011	1			T81	1		T92	7		T36	2
alert_integrity_fail	alert[0x15]	9515	1			T92	3		T36	21		T39	34
alert_integrity_fail	alert[0x16]	5112	1			T41	12		T60	2		T95	5
alert_integrity_fail	alert[0x17]	4689	1			T75	2		T93	6		T60	3
alert_integrity_fail	alert[0x18]	18375	1			T57	3		T92	33		T95	958
alert_integrity_fail	alert[0x19]	8219	1			T36	3		T95	916		T102	39
alert_integrity_fail	alert[0x1a]	4590	1			T93	9		T101	1531		T106	51
alert_integrity_fail	alert[0x1b]	13741	1			T57	16		T92	1		T93	10
alert_integrity_fail	alert[0x1c]	2524	1			T36	4		T93	2		T95	2
alert_integrity_fail	alert[0x1d]	7151	1			T81	4		T106	3		T62	21
alert_integrity_fail	alert[0x1e]	9048	1			T81	1		T93	1		T101	5
alert_integrity_fail	alert[0x1f]	13308	1			T18	27		T92	4		T36	144
alert_integrity_fail	alert[0x20]	7293	1			T35	5		T36	11		T39	36
alert_integrity_fail	alert[0x21]	3253	1			T81	1		T92	26		T36	14
alert_integrity_fail	alert[0x22]	14736	1			T81	1		T36	5		T95	10
alert_integrity_fail	alert[0x23]	9356	1			T81	17		T88	3		T93	5
alert_integrity_fail	alert[0x24]	3725	1			T36	14		T106	8		T62	5
alert_integrity_fail	alert[0x25]	3499	1			T81	1		T39	174		T61	88
alert_integrity_fail	alert[0x26]	3355	1			T57	3		T36	17		T93	2
alert_integrity_fail	alert[0x27]	2899	1			T75	64		T77	2		T95	11
alert_integrity_fail	alert[0x28]	6085	1			T76	1		T36	168		T93	7
alert_integrity_fail	alert[0x29]	6325	1			T36	8		T93	31		T106	1437
alert_integrity_fail	alert[0x2a]	3778	1			T57	6		T93	3		T95	33
alert_integrity_fail	alert[0x2b]	5504	1			T92	1		T36	4		T60	49
alert_integrity_fail	alert[0x2c]	4432	1			T36	274		T101	1		T106	7
alert_integrity_fail	alert[0x2d]	4653	1			T81	45		T92	9		T36	1
alert_integrity_fail	alert[0x2e]	4225	1			T81	20		T106	39		T62	554
alert_integrity_fail	alert[0x2f]	4769	1			T75	2		T81	4		T36	2
alert_integrity_fail	alert[0x30]	5668	1			T92	9		T36	66		T93	1
alert_integrity_fail	alert[0x31]	11504	1			T57	5		T92	31		T36	1
alert_integrity_fail	alert[0x32]	6321	1			T75	11		T36	2		T106	4
alert_integrity_fail	alert[0x33]	5746	1			T60	1		T95	171		T96	5
alert_integrity_fail	alert[0x34]	3765	1			T18	3		T92	40		T93	73
alert_integrity_fail	alert[0x35]	2390	1			T81	1		T60	3		T95	6
alert_integrity_fail	alert[0x36]	5667	1			T77	7		T81	1		T92	2
alert_integrity_fail	alert[0x37]	3042	1			T57	3		T35	12		T93	29
alert_integrity_fail	alert[0x38]	4102	1			T77	1		T92	7		T36	49
alert_integrity_fail	alert[0x39]	7872	1			T81	2		T39	673		T61	933
alert_integrity_fail	alert[0x3a]	3875	1			T81	4		T36	1		T59	3
alert_integrity_fail	alert[0x3b]	3656	1			T57	28		T92	13		T36	14
alert_integrity_fail	alert[0x3c]	3479	1			T81	3		T36	3		T39	1015
alert_integrity_fail	alert[0x3d]	2870	1			T92	14		T95	18		T39	6
alert_integrity_fail	alert[0x3e]	8363	1			T81	1		T92	31		T36	7
alert_integrity_fail	alert[0x3f]	17677	1			T93	11		T101	46		T106	4
alert_integrity_fail	alert[0x40]	4062	1			T57	6		T39	8		T61	293
alert_ping_fail	alert[0x0]	12	1			T124	1		T263	1		T264	1
alert_ping_fail	alert[0x1]	8	1			T8	1		T264	1		T265	1
alert_ping_fail	alert[0x2]	13	1			T266	2		T267	1		T268	1
alert_ping_fail	alert[0x3]	8	1			T8	1		T9	1		T124	1
alert_ping_fail	alert[0x4]	7	1			T4	1		T9	1		T269	1
alert_ping_fail	alert[0x5]	17	1			T4	1		T9	1		T264	1
alert_ping_fail	alert[0x6]	17	1			T44	1		T264	1		T261	2
alert_ping_fail	alert[0x7]	9	1			T86	1		T264	1		T270	1
alert_ping_fail	alert[0x8]	16	1			T8	1		T9	2		T124	2
alert_ping_fail	alert[0x9]	9	1			T4	1		T9	1		T86	1
alert_ping_fail	alert[0xa]	17	1			T44	1		T248	2		T271	1
alert_ping_fail	alert[0xb]	8	1			T8	1		T9	1		T266	1
alert_ping_fail	alert[0xc]	9	1			T4	1		T86	1		T44	1
alert_ping_fail	alert[0xd]	9	1			T263	1		T268	1		T272	1
alert_ping_fail	alert[0xe]	13	1			T4	2		T124	1		T273	1
alert_ping_fail	alert[0xf]	7	1			T86	1		T271	1		T274	1
alert_ping_fail	alert[0x10]	9	1			T264	1		T267	1		T270	1
alert_ping_fail	alert[0x11]	9	1			T4	1		T264	1		T275	1
alert_ping_fail	alert[0x12]	8	1			T273	2		T274	1		T270	1
alert_ping_fail	alert[0x13]	14	1			T44	1		T265	1		T271	1
alert_ping_fail	alert[0x14]	13	1			T262	1		T271	1		T276	1
alert_ping_fail	alert[0x15]	15	1			T86	1		T256	1		T271	1
alert_ping_fail	alert[0x16]	8	1			T4	1		T273	1		T277	1
alert_ping_fail	alert[0x17]	10	1			T4	1		T9	1		T266	1
alert_ping_fail	alert[0x18]	5	1			T8	1		T9	1		T278	1
alert_ping_fail	alert[0x19]	5	1			T124	1		T275	1		T274	1
alert_ping_fail	alert[0x1a]	10	1			T4	1		T9	1		T278	1
alert_ping_fail	alert[0x1b]	11	1			T4	2		T278	1		T217	1
alert_ping_fail	alert[0x1c]	15	1			T263	1		T44	2		T273	1
alert_ping_fail	alert[0x1d]	10	1			T265	1		T273	2		T279	1
alert_ping_fail	alert[0x1e]	7	1			T263	2		T271	1		T268	1
alert_ping_fail	alert[0x1f]	12	1			T3	1		T4	2		T44	1
alert_ping_fail	alert[0x20]	14	1			T8	1		T124	1		T44	1
alert_ping_fail	alert[0x21]	16	1			T9	2		T271	1		T267	2
alert_ping_fail	alert[0x22]	13	1			T8	1		T17	1		T9	1
alert_ping_fail	alert[0x23]	6	1			T9	1		T266	2		T280	1
alert_ping_fail	alert[0x24]	7	1			T8	1		T44	1		T217	1
alert_ping_fail	alert[0x25]	9	1			T4	1		T266	2		T267	1
alert_ping_fail	alert[0x26]	7	1			T267	1		T274	1		T281	1
alert_ping_fail	alert[0x27]	12	1			T86	1		T263	1		T264	2
alert_ping_fail	alert[0x28]	16	1			T276	1		T267	1		T274	1
alert_ping_fail	alert[0x29]	13	1			T86	1		T124	1		T264	1
alert_ping_fail	alert[0x2a]	18	1			T86	1		T264	3		T261	1
alert_ping_fail	alert[0x2b]	11	1			T264	1		T242	1		T279	1
alert_ping_fail	alert[0x2c]	9	1			T265	1		T274	1		T221	1
alert_ping_fail	alert[0x2d]	8	1			T3	1		T273	1		T275	1
alert_ping_fail	alert[0x2e]	22	1			T124	1		T44	1		T264	2
alert_ping_fail	alert[0x2f]	17	1			T264	1		T265	1		T257	1
alert_ping_fail	alert[0x30]	7	1			T4	1		T263	1		T266	1
alert_ping_fail	alert[0x31]	14	1			T9	1		T86	1		T44	1
alert_ping_fail	alert[0x32]	11	1			T124	1		T271	1		T266	1
alert_ping_fail	alert[0x33]	10	1			T272	1		T282	1		T283	1
alert_ping_fail	alert[0x34]	9	1			T8	1		T273	2		T272	2
alert_ping_fail	alert[0x35]	9	1			T273	2		T278	1		T284	1
alert_ping_fail	alert[0x36]	11	1			T4	1		T274	1		T272	2
alert_ping_fail	alert[0x37]	14	1			T44	1		T273	1		T266	2
alert_ping_fail	alert[0x38]	8	1			T217	1		T275	1		T274	1
alert_ping_fail	alert[0x39]	6	1			T217	1		T283	1		T280	1
alert_ping_fail	alert[0x3a]	10	1			T44	1		T264	2		T265	1
alert_ping_fail	alert[0x3b]	8	1			T266	1		T267	1		T285	1
alert_ping_fail	alert[0x3c]	7	1			T266	1		T286	1		T287	1
alert_ping_fail	alert[0x3d]	7	1			T285	2		T280	1		T288	1
alert_ping_fail	alert[0x3e]	8	1			T8	1		T273	1		T217	1
alert_ping_fail	alert[0x3f]	3	1			T271	1		T273	1		T287	1
alert_ping_fail	alert[0x40]	5	1			T263	1		T284	1		T282	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	102875	1			T57	133		T75	69		T77	12
alert_integrity_fail	class_i[0x1]	133526	1			T57	3		T75	2		T77	1
alert_integrity_fail	class_i[0x2]	116955	1			T18	33		T77	6		T92	113
alert_integrity_fail	class_i[0x3]	86588	1			T75	11		T76	1		T81	30
alert_ping_fail	class_i[0x0]	117	1			T4	2		T8	9		T9	13
alert_ping_fail	class_i[0x1]	193	1			T3	2		T9	1		T86	2
alert_ping_fail	class_i[0x2]	217	1			T4	14		T8	1		T17	1
alert_ping_fail	class_i[0x3]	158	1			T4	1		T86	4		T44	12