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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.69 99.99 98.72 100.00 100.00 100.00 99.38 99.72


Total test records in report: 848
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T774 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3916421268 Dec 24 12:33:04 PM PST 23 Dec 24 12:33:56 PM PST 23 91765741 ps
T187 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1573936334 Dec 24 12:32:43 PM PST 23 Dec 24 12:34:29 PM PST 23 5175056869 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3785064204 Dec 24 12:32:42 PM PST 23 Dec 24 12:33:12 PM PST 23 64811182 ps
T776 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2794718908 Dec 24 12:33:30 PM PST 23 Dec 24 12:34:06 PM PST 23 28708798 ps
T777 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2518149133 Dec 24 12:33:24 PM PST 23 Dec 24 12:34:02 PM PST 23 9210169 ps
T778 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4119271089 Dec 24 12:33:19 PM PST 23 Dec 24 12:34:09 PM PST 23 432000954 ps
T779 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.527133476 Dec 24 12:33:11 PM PST 23 Dec 24 12:33:55 PM PST 23 383819058 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1000708420 Dec 24 12:33:05 PM PST 23 Dec 24 12:33:53 PM PST 23 95318201 ps
T781 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3620435349 Dec 24 12:33:43 PM PST 23 Dec 24 12:34:21 PM PST 23 9294111 ps
T188 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4002309458 Dec 24 12:33:18 PM PST 23 Dec 24 12:34:00 PM PST 23 113388643 ps
T163 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3059781876 Dec 24 12:32:47 PM PST 23 Dec 24 12:41:13 PM PST 23 23540158628 ps
T782 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1509484963 Dec 24 12:33:10 PM PST 23 Dec 24 12:33:56 PM PST 23 35334031 ps
T186 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1163850562 Dec 24 12:32:50 PM PST 23 Dec 24 12:33:25 PM PST 23 61060994 ps
T783 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1440619570 Dec 24 12:32:56 PM PST 23 Dec 24 12:34:00 PM PST 23 664758349 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1000890175 Dec 24 12:33:51 PM PST 23 Dec 24 12:34:46 PM PST 23 258270477 ps
T183 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4267838360 Dec 24 12:32:55 PM PST 23 Dec 24 12:34:34 PM PST 23 1889545588 ps
T181 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.274581854 Dec 24 12:32:55 PM PST 23 Dec 24 12:33:38 PM PST 23 104742704 ps
T785 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3681164643 Dec 24 12:33:13 PM PST 23 Dec 24 12:33:54 PM PST 23 9300402 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.960643002 Dec 24 12:32:56 PM PST 23 Dec 24 12:33:47 PM PST 23 235913896 ps
T157 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3417616674 Dec 24 12:33:06 PM PST 23 Dec 24 12:43:29 PM PST 23 17694662415 ps
T787 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.100004992 Dec 24 12:33:49 PM PST 23 Dec 24 12:34:27 PM PST 23 10328605 ps
T788 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1824830496 Dec 24 12:32:56 PM PST 23 Dec 24 12:33:42 PM PST 23 49479961 ps
T789 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.535880985 Dec 24 12:33:51 PM PST 23 Dec 24 12:34:29 PM PST 23 9121787 ps
T790 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2279343724 Dec 24 12:32:51 PM PST 23 Dec 24 12:33:28 PM PST 23 7295753 ps
T149 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4253208798 Dec 24 12:33:34 PM PST 23 Dec 24 12:50:45 PM PST 23 74000049598 ps
T159 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3714092154 Dec 24 12:32:55 PM PST 23 Dec 24 12:42:58 PM PST 23 38424333089 ps
T791 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3325053897 Dec 24 12:33:35 PM PST 23 Dec 24 12:34:11 PM PST 23 10284705 ps
T792 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3391261012 Dec 24 12:33:02 PM PST 23 Dec 24 12:33:49 PM PST 23 272596812 ps
T158 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1622271008 Dec 24 12:32:53 PM PST 23 Dec 24 12:35:27 PM PST 23 1387890663 ps
T793 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.807522628 Dec 24 12:33:24 PM PST 23 Dec 24 12:34:04 PM PST 23 27487583 ps
T155 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1037735364 Dec 24 12:32:44 PM PST 23 Dec 24 12:36:11 PM PST 23 21845408950 ps
T185 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.584674199 Dec 24 12:33:28 PM PST 23 Dec 24 12:34:23 PM PST 23 634204062 ps
T794 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1160090680 Dec 24 12:32:57 PM PST 23 Dec 24 12:37:29 PM PST 23 7067997336 ps
T795 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1633279481 Dec 24 12:33:06 PM PST 23 Dec 24 12:33:52 PM PST 23 33451967 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.540058468 Dec 24 12:32:51 PM PST 23 Dec 24 12:33:33 PM PST 23 230181921 ps
T797 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2722167834 Dec 24 12:32:58 PM PST 23 Dec 24 12:35:13 PM PST 23 4581082621 ps
T798 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.339401592 Dec 24 12:33:14 PM PST 23 Dec 24 12:34:00 PM PST 23 79755900 ps
T799 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1448423069 Dec 24 12:33:25 PM PST 23 Dec 24 12:34:08 PM PST 23 213591321 ps
T178 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2267338736 Dec 24 12:32:56 PM PST 23 Dec 24 12:33:40 PM PST 23 113382511 ps
T800 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4248855086 Dec 24 12:32:51 PM PST 23 Dec 24 12:33:44 PM PST 23 1391329810 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.148045610 Dec 24 12:33:02 PM PST 23 Dec 24 12:33:49 PM PST 23 34440603 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1302041670 Dec 24 12:33:05 PM PST 23 Dec 24 12:34:05 PM PST 23 588353716 ps
T161 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4108106436 Dec 24 12:33:24 PM PST 23 Dec 24 12:51:40 PM PST 23 56937487820 ps
T803 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2048024143 Dec 24 12:33:20 PM PST 23 Dec 24 12:34:00 PM PST 23 23215685 ps
T164 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4205317431 Dec 24 12:33:35 PM PST 23 Dec 24 12:37:30 PM PST 23 25781890574 ps
T804 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1392150516 Dec 24 12:33:33 PM PST 23 Dec 24 12:34:09 PM PST 23 9998946 ps
T167 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.580116654 Dec 24 12:33:15 PM PST 23 Dec 24 12:39:14 PM PST 23 20677881652 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1168127557 Dec 24 12:33:28 PM PST 23 Dec 24 12:34:11 PM PST 23 151844293 ps
T180 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3592434575 Dec 24 12:33:15 PM PST 23 Dec 24 12:33:57 PM PST 23 159808371 ps
T182 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2727473955 Dec 24 12:33:26 PM PST 23 Dec 24 12:34:05 PM PST 23 30049178 ps
T806 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2119950670 Dec 24 12:32:43 PM PST 23 Dec 24 12:33:12 PM PST 23 7026524 ps
T807 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.319901087 Dec 24 12:33:03 PM PST 23 Dec 24 12:35:52 PM PST 23 4218219725 ps
T808 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.821643225 Dec 24 12:33:13 PM PST 23 Dec 24 12:34:01 PM PST 23 215699149 ps
T809 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1012284174 Dec 24 12:32:38 PM PST 23 Dec 24 12:33:14 PM PST 23 35179647 ps
T810 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1760566525 Dec 24 12:32:47 PM PST 23 Dec 24 12:33:16 PM PST 23 11886272 ps
T811 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2554402539 Dec 24 12:33:07 PM PST 23 Dec 24 12:33:56 PM PST 23 78899991 ps
T812 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1601257018 Dec 24 12:33:32 PM PST 23 Dec 24 12:34:14 PM PST 23 29196867 ps
T813 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1256114229 Dec 24 12:33:34 PM PST 23 Dec 24 12:34:11 PM PST 23 6129859 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2623466940 Dec 24 12:33:06 PM PST 23 Dec 24 12:33:59 PM PST 23 317345305 ps
T815 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2192870245 Dec 24 12:32:54 PM PST 23 Dec 24 12:33:37 PM PST 23 22362947 ps
T816 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.296293499 Dec 24 12:33:08 PM PST 23 Dec 24 12:33:58 PM PST 23 1348332028 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.299822992 Dec 24 12:33:08 PM PST 23 Dec 24 12:38:51 PM PST 23 4681574652 ps
T818 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3681558573 Dec 24 12:33:24 PM PST 23 Dec 24 12:34:02 PM PST 23 8654933 ps
T819 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.274387322 Dec 24 12:32:52 PM PST 23 Dec 24 12:33:31 PM PST 23 20137275 ps
T820 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1169815771 Dec 24 12:32:53 PM PST 23 Dec 24 12:33:43 PM PST 23 314298428 ps
T821 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2735383139 Dec 24 12:33:03 PM PST 23 Dec 24 12:33:45 PM PST 23 63473246 ps
T822 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2731511338 Dec 24 12:32:56 PM PST 23 Dec 24 12:33:40 PM PST 23 161131107 ps
T823 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2296656924 Dec 24 12:33:18 PM PST 23 Dec 24 12:34:33 PM PST 23 4508514303 ps
T824 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3942219155 Dec 24 12:33:14 PM PST 23 Dec 24 12:33:56 PM PST 23 42357661 ps
T166 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.177897735 Dec 24 12:33:00 PM PST 23 Dec 24 12:38:57 PM PST 23 2360972203 ps
T825 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.675936395 Dec 24 12:33:25 PM PST 23 Dec 24 12:34:32 PM PST 23 1860623698 ps
T826 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2365435398 Dec 24 12:33:16 PM PST 23 Dec 24 12:33:57 PM PST 23 10799280 ps
T827 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3202853188 Dec 24 12:32:59 PM PST 23 Dec 24 12:36:35 PM PST 23 2426883734 ps
T329 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3882426113 Dec 24 12:33:20 PM PST 23 Dec 24 12:38:50 PM PST 23 35357459877 ps
T828 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3722405285 Dec 24 12:33:29 PM PST 23 Dec 24 12:34:06 PM PST 23 28433137 ps
T829 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.851442128 Dec 24 12:32:43 PM PST 23 Dec 24 12:34:47 PM PST 23 824037586 ps
T830 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3176368734 Dec 24 12:32:51 PM PST 23 Dec 24 12:33:32 PM PST 23 52859999 ps
T831 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1731715609 Dec 24 12:33:13 PM PST 23 Dec 24 12:33:57 PM PST 23 51693155 ps
T832 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.522075706 Dec 24 12:33:30 PM PST 23 Dec 24 12:34:07 PM PST 23 6668302 ps
T833 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.902630388 Dec 24 12:32:58 PM PST 23 Dec 24 12:36:00 PM PST 23 8803732203 ps
T834 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.468703702 Dec 24 12:33:33 PM PST 23 Dec 24 12:34:14 PM PST 23 345233981 ps
T835 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1626927224 Dec 24 12:32:58 PM PST 23 Dec 24 12:39:06 PM PST 23 5772146252 ps
T836 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2031049333 Dec 24 12:32:51 PM PST 23 Dec 24 12:33:29 PM PST 23 27365066 ps
T184 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3913596489 Dec 24 12:33:15 PM PST 23 Dec 24 12:35:08 PM PST 23 2403246953 ps
T837 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4202019956 Dec 24 12:32:35 PM PST 23 Dec 24 12:33:05 PM PST 23 36213198 ps
T838 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1053516237 Dec 24 12:33:43 PM PST 23 Dec 24 12:34:20 PM PST 23 10797764 ps
T839 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1855281411 Dec 24 12:33:22 PM PST 23 Dec 24 12:34:01 PM PST 23 14265477 ps
T840 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2075830581 Dec 24 12:33:04 PM PST 23 Dec 24 12:34:54 PM PST 23 587925558 ps
T841 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3105573837 Dec 24 12:33:45 PM PST 23 Dec 24 12:34:23 PM PST 23 27199277 ps
T328 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.909418766 Dec 24 12:32:51 PM PST 23 Dec 24 12:51:57 PM PST 23 17555235612 ps
T842 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1638118992 Dec 24 12:33:23 PM PST 23 Dec 24 12:37:05 PM PST 23 13282299192 ps
T843 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1811314429 Dec 24 12:32:57 PM PST 23 Dec 24 12:34:13 PM PST 23 524318346 ps
T844 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3811123144 Dec 24 12:33:46 PM PST 23 Dec 24 12:34:24 PM PST 23 10162196 ps
T168 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2652408795 Dec 24 12:32:40 PM PST 23 Dec 24 12:44:35 PM PST 23 5788360526 ps
T845 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1255334680 Dec 24 12:32:59 PM PST 23 Dec 24 12:33:47 PM PST 23 759828316 ps
T846 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3545361770 Dec 24 12:32:54 PM PST 23 Dec 24 12:33:53 PM PST 23 260253809 ps
T847 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1790351537 Dec 24 12:33:19 PM PST 23 Dec 24 12:33:59 PM PST 23 15078720 ps
T848 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3268613073 Dec 24 12:33:42 PM PST 23 Dec 24 12:34:23 PM PST 23 296218276 ps

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2640790980
Short name T13
Test name
Test status
Simulation time 2728348245 ps
CPU time 250.22 seconds
Started Dec 24 12:33:35 PM PST 23
Finished Dec 24 12:38:21 PM PST 23
Peak memory 265576 kb
Host smart-c78e3004-79a1-4133-a98b-f09b34ff9da8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2640790980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2640790980
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2361447517
Short name T5
Test name
Test status
Simulation time 102201037740 ps
CPU time 1412.25 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:54:17 PM PST 23
Peak memory 272008 kb
Host smart-0eb65427-3c81-4927-a03a-be3db206b1cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361447517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2361447517
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3986684349
Short name T162
Test name
Test status
Simulation time 2531974091 ps
CPU time 74.46 seconds
Started Dec 24 12:32:45 PM PST 23
Finished Dec 24 12:34:27 PM PST 23
Peak memory 236604 kb
Host smart-af5f9153-73cb-4029-b40a-1a0804501bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3986684349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3986684349
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.805081892
Short name T36
Test name
Test status
Simulation time 249617267268 ps
CPU time 4629.86 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 02:46:28 PM PST 23
Peak memory 322568 kb
Host smart-4ebc3e0a-d2ef-41b5-a7d6-7f9e5722282c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805081892 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.805081892
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1209191545
Short name T46
Test name
Test status
Simulation time 1873369161 ps
CPU time 25.68 seconds
Started Dec 24 01:28:05 PM PST 23
Finished Dec 24 01:28:41 PM PST 23
Peak memory 269384 kb
Host smart-c9f5cb9a-8c32-462c-9369-2f2558efb9df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1209191545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1209191545
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1713051275
Short name T3
Test name
Test status
Simulation time 65168897683 ps
CPU time 1180.82 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:50:19 PM PST 23
Peak memory 284716 kb
Host smart-85643efe-108a-4f4f-b49c-d2fb8cdf1a1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713051275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1713051275
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1155445096
Short name T7
Test name
Test status
Simulation time 38572754067 ps
CPU time 2471.43 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 02:09:27 PM PST 23
Peak memory 288948 kb
Host smart-664f98a5-dbd8-447b-9fd5-e2444d03e022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155445096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1155445096
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.336459251
Short name T62
Test name
Test status
Simulation time 120612355933 ps
CPU time 10315.4 seconds
Started Dec 24 01:28:39 PM PST 23
Finished Dec 24 04:20:37 PM PST 23
Peak memory 394620 kb
Host smart-79cbb988-524b-4b5e-9e22-e16f8e211420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336459251 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.336459251
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.925183832
Short name T133
Test name
Test status
Simulation time 15315569126 ps
CPU time 173.5 seconds
Started Dec 24 12:32:48 PM PST 23
Finished Dec 24 12:36:09 PM PST 23
Peak memory 265396 kb
Host smart-f3be2c04-38bf-4213-bf84-25e5e8cd2113
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=925183832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.925183832
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.4185090780
Short name T34
Test name
Test status
Simulation time 254671760770 ps
CPU time 3642.76 seconds
Started Dec 24 01:28:26 PM PST 23
Finished Dec 24 02:29:11 PM PST 23
Peak memory 281640 kb
Host smart-8c1a3abe-02d0-4333-8012-eb09b622e9e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185090780 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.4185090780
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3461448920
Short name T169
Test name
Test status
Simulation time 8186691 ps
CPU time 1.33 seconds
Started Dec 24 12:33:17 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 235636 kb
Host smart-e710d61d-838c-42f8-afaa-0578bda31373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3461448920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3461448920
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2557995115
Short name T136
Test name
Test status
Simulation time 30921729840 ps
CPU time 549.52 seconds
Started Dec 24 12:33:03 PM PST 23
Finished Dec 24 12:42:54 PM PST 23
Peak memory 269952 kb
Host smart-8bb071d9-40c2-4c03-bf46-52fd49c4993e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557995115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2557995115
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3278929484
Short name T139
Test name
Test status
Simulation time 4544798421 ps
CPU time 624.25 seconds
Started Dec 24 12:33:16 PM PST 23
Finished Dec 24 12:44:20 PM PST 23
Peak memory 265404 kb
Host smart-465bd27e-6d32-4a3b-90c4-1a42dc78c171
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278929484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3278929484
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.901153241
Short name T95
Test name
Test status
Simulation time 416290875530 ps
CPU time 6279.28 seconds
Started Dec 24 01:31:53 PM PST 23
Finished Dec 24 03:16:34 PM PST 23
Peak memory 338760 kb
Host smart-65670201-8ad4-43ed-8f2f-c0a1894653f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901153241 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.901153241
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2691984846
Short name T242
Test name
Test status
Simulation time 440745100755 ps
CPU time 3330.93 seconds
Started Dec 24 01:29:17 PM PST 23
Finished Dec 24 02:24:50 PM PST 23
Peak memory 288584 kb
Host smart-a8369caa-d62f-4568-b591-7a6c05680c4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691984846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2691984846
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2878555421
Short name T264
Test name
Test status
Simulation time 98219516832 ps
CPU time 687.61 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 01:41:03 PM PST 23
Peak memory 247508 kb
Host smart-cb51e3a8-d570-4ba2-8c78-0b1652e03eb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878555421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2878555421
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.132161216
Short name T51
Test name
Test status
Simulation time 220064972418 ps
CPU time 3428.41 seconds
Started Dec 24 01:30:38 PM PST 23
Finished Dec 24 02:27:48 PM PST 23
Peak memory 288856 kb
Host smart-bd2e2552-f9b1-4e0d-97d7-04da70197c12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132161216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.132161216
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2548260295
Short name T140
Test name
Test status
Simulation time 4432946924 ps
CPU time 611.71 seconds
Started Dec 24 12:33:07 PM PST 23
Finished Dec 24 12:44:00 PM PST 23
Peak memory 265340 kb
Host smart-f01716ab-ccaf-40ac-8327-51459b34fabb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548260295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2548260295
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3729775393
Short name T175
Test name
Test status
Simulation time 90621808 ps
CPU time 2.5 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:11 PM PST 23
Peak memory 236604 kb
Host smart-2c65e854-1e17-4ec0-b1ba-b6e08c190db4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3729775393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3729775393
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2438000460
Short name T14
Test name
Test status
Simulation time 34361883853 ps
CPU time 2269.88 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 289156 kb
Host smart-6d638cae-a6be-46e7-b371-3e887de7dcf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438000460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2438000460
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3185787063
Short name T148
Test name
Test status
Simulation time 23950415876 ps
CPU time 311.55 seconds
Started Dec 24 12:32:40 PM PST 23
Finished Dec 24 12:38:17 PM PST 23
Peak memory 265500 kb
Host smart-b56f3c68-44cc-4a46-8bbd-17809691b8a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3185787063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3185787063
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3987155994
Short name T66
Test name
Test status
Simulation time 218063785793 ps
CPU time 3216.84 seconds
Started Dec 24 01:30:05 PM PST 23
Finished Dec 24 02:23:44 PM PST 23
Peak memory 298040 kb
Host smart-63484ac3-93cf-4ac8-abe2-1f2e542ce269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987155994 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3987155994
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1812646766
Short name T283
Test name
Test status
Simulation time 9753768139 ps
CPU time 420.56 seconds
Started Dec 24 01:31:22 PM PST 23
Finished Dec 24 01:38:24 PM PST 23
Peak memory 247284 kb
Host smart-81a9c128-7a99-4fb2-8af3-f61abeeeaacb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812646766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1812646766
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2918910781
Short name T72
Test name
Test status
Simulation time 341568693443 ps
CPU time 5424.16 seconds
Started Dec 24 01:28:20 PM PST 23
Finished Dec 24 02:58:49 PM PST 23
Peak memory 322056 kb
Host smart-c6eaf679-dbdc-4e7a-a909-96eef95c74b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918910781 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2918910781
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3748348637
Short name T221
Test name
Test status
Simulation time 92940403222 ps
CPU time 2670.31 seconds
Started Dec 24 01:30:52 PM PST 23
Finished Dec 24 02:15:23 PM PST 23
Peak memory 281396 kb
Host smart-6ba1ce81-dc36-470b-bfbc-cb6bba1cd2e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748348637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3748348637
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2521970806
Short name T137
Test name
Test status
Simulation time 22925990560 ps
CPU time 354.78 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:39:19 PM PST 23
Peak memory 265092 kb
Host smart-9b3c02ac-c7fb-4b37-8885-61a00978110d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2521970806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2521970806
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2972406361
Short name T4
Test name
Test status
Simulation time 9715369458 ps
CPU time 414.75 seconds
Started Dec 24 01:29:40 PM PST 23
Finished Dec 24 01:36:36 PM PST 23
Peak memory 246944 kb
Host smart-848a7eb6-abe6-4612-8942-62b57ba41db4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972406361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2972406361
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.488915003
Short name T17
Test name
Test status
Simulation time 179352754640 ps
CPU time 1804.6 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 281904 kb
Host smart-c5fc23bd-f692-46a4-8a2d-df21937d0963
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488915003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.488915003
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3699759232
Short name T285
Test name
Test status
Simulation time 215895947725 ps
CPU time 557.94 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:37:43 PM PST 23
Peak memory 247492 kb
Host smart-cd212899-f1ca-4cb2-af57-96bf4b205fcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699759232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3699759232
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3417616674
Short name T157
Test name
Test status
Simulation time 17694662415 ps
CPU time 580.47 seconds
Started Dec 24 12:33:06 PM PST 23
Finished Dec 24 12:43:29 PM PST 23
Peak memory 265352 kb
Host smart-e26e044d-6db7-4761-9224-b7dfa087f30e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417616674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3417616674
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.786562846
Short name T92
Test name
Test status
Simulation time 89163350571 ps
CPU time 1911.59 seconds
Started Dec 24 01:31:31 PM PST 23
Finished Dec 24 02:03:24 PM PST 23
Peak memory 281708 kb
Host smart-1f6094e5-95f3-48bd-89cd-cecf46afe857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786562846 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.786562846
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2778424143
Short name T306
Test name
Test status
Simulation time 176427506229 ps
CPU time 2570.02 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 02:12:24 PM PST 23
Peak memory 289472 kb
Host smart-a5429bed-e52a-4ccc-b2f7-8b76705e67cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778424143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2778424143
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4207404585
Short name T101
Test name
Test status
Simulation time 122173958314 ps
CPU time 2418.98 seconds
Started Dec 24 01:30:58 PM PST 23
Finished Dec 24 02:11:28 PM PST 23
Peak memory 289220 kb
Host smart-d2336831-55d9-4a1a-98cf-81ca2b0a3efb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207404585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4207404585
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2484665455
Short name T274
Test name
Test status
Simulation time 18955581090 ps
CPU time 378.71 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:37:01 PM PST 23
Peak memory 254936 kb
Host smart-81347153-fc26-4b1c-a7a6-85bcfc9c46b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484665455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2484665455
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4093311798
Short name T223
Test name
Test status
Simulation time 17357205360 ps
CPU time 1522.37 seconds
Started Dec 24 01:30:17 PM PST 23
Finished Dec 24 01:55:41 PM PST 23
Peak memory 289612 kb
Host smart-66249225-e88f-48c0-9dc5-8ed7fa51fb21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093311798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4093311798
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3420977855
Short name T117
Test name
Test status
Simulation time 875190784 ps
CPU time 22.7 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:30:56 PM PST 23
Peak memory 248660 kb
Host smart-7430a16e-6e87-4800-b57e-1b6c798a50b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34209
77855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3420977855
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4205317431
Short name T164
Test name
Test status
Simulation time 25781890574 ps
CPU time 200.51 seconds
Started Dec 24 12:33:35 PM PST 23
Finished Dec 24 12:37:30 PM PST 23
Peak memory 271072 kb
Host smart-93779fd3-9509-49c2-97e4-28f50dffc220
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4205317431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.4205317431
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1020693636
Short name T324
Test name
Test status
Simulation time 19587969 ps
CPU time 1.33 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:11 PM PST 23
Peak memory 236388 kb
Host smart-3361de98-b9f4-486b-b760-292b90b19321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1020693636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1020693636
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1068265075
Short name T276
Test name
Test status
Simulation time 19414292875 ps
CPU time 1374.94 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 289120 kb
Host smart-5dc451b2-390e-4a81-a371-35edd284eedb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068265075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1068265075
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.272804198
Short name T239
Test name
Test status
Simulation time 19243863778 ps
CPU time 1287.04 seconds
Started Dec 24 01:28:42 PM PST 23
Finished Dec 24 01:50:11 PM PST 23
Peak memory 285772 kb
Host smart-470b62ba-138c-40d4-8d5c-c739ef548386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272804198 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.272804198
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3892641889
Short name T23
Test name
Test status
Simulation time 594983005 ps
CPU time 33.38 seconds
Started Dec 24 12:32:50 PM PST 23
Finished Dec 24 12:33:55 PM PST 23
Peak memory 239304 kb
Host smart-ab7f6183-c51b-4a0d-9e5a-65ded022ad78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3892641889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3892641889
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2616255261
Short name T250
Test name
Test status
Simulation time 136591619698 ps
CPU time 3874.5 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 02:33:50 PM PST 23
Peak memory 300836 kb
Host smart-cdeb7936-7673-48cf-b3c2-2f7827035189
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616255261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2616255261
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2297612192
Short name T114
Test name
Test status
Simulation time 42976287248 ps
CPU time 2752.1 seconds
Started Dec 24 01:29:05 PM PST 23
Finished Dec 24 02:15:00 PM PST 23
Peak memory 289028 kb
Host smart-928ad08c-3676-4ec4-9a1d-bd941dd188d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297612192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2297612192
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3059781876
Short name T163
Test name
Test status
Simulation time 23540158628 ps
CPU time 477.75 seconds
Started Dec 24 12:32:47 PM PST 23
Finished Dec 24 12:41:13 PM PST 23
Peak memory 265164 kb
Host smart-e3228589-e1a7-436e-98db-9bd049b450ab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059781876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3059781876
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2855100683
Short name T268
Test name
Test status
Simulation time 5903621320 ps
CPU time 238.81 seconds
Started Dec 24 01:29:12 PM PST 23
Finished Dec 24 01:33:12 PM PST 23
Peak memory 247724 kb
Host smart-6bcc8c05-a71b-4f7b-8a1c-696d873bc4a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855100683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2855100683
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.153477385
Short name T56
Test name
Test status
Simulation time 339072022 ps
CPU time 19.99 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:29:35 PM PST 23
Peak memory 253600 kb
Host smart-1d77c2ca-4ab1-4479-8b54-e1353e417877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
7385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.153477385
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1485097942
Short name T37
Test name
Test status
Simulation time 58480003364 ps
CPU time 3509.86 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 02:26:54 PM PST 23
Peak memory 289336 kb
Host smart-5169c775-7365-4cb7-891a-7285ec870bab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485097942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1485097942
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3329233351
Short name T201
Test name
Test status
Simulation time 91165992 ps
CPU time 3.97 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:28:19 PM PST 23
Peak memory 248812 kb
Host smart-ef7d956a-6349-4d8a-a2ce-b797d8df36c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3329233351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3329233351
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2876140991
Short name T205
Test name
Test status
Simulation time 23579652 ps
CPU time 2.44 seconds
Started Dec 24 01:27:56 PM PST 23
Finished Dec 24 01:27:59 PM PST 23
Peak memory 248864 kb
Host smart-fa1dc821-1c58-46f5-900a-2226ad0bf9f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2876140991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2876140991
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1278898015
Short name T199
Test name
Test status
Simulation time 34666127 ps
CPU time 3.18 seconds
Started Dec 24 01:28:37 PM PST 23
Finished Dec 24 01:28:42 PM PST 23
Peak memory 248896 kb
Host smart-42bd07f8-c0f8-45fe-a6af-d9e6123266aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1278898015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1278898015
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3204454936
Short name T203
Test name
Test status
Simulation time 145853200 ps
CPU time 3.61 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:29:20 PM PST 23
Peak memory 248732 kb
Host smart-f33aa5bc-ea58-4132-8fcd-034648897be7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3204454936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3204454936
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1382797304
Short name T327
Test name
Test status
Simulation time 11075187 ps
CPU time 1.59 seconds
Started Dec 24 12:33:38 PM PST 23
Finished Dec 24 12:34:16 PM PST 23
Peak memory 235456 kb
Host smart-eae84c19-1502-4865-b97d-31bb1c28c892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1382797304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1382797304
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3945734916
Short name T309
Test name
Test status
Simulation time 685542983825 ps
CPU time 2822.03 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 02:15:41 PM PST 23
Peak memory 284012 kb
Host smart-a20bbe54-e3b5-43e3-aa5f-0c826f92b6d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945734916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3945734916
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1727554275
Short name T273
Test name
Test status
Simulation time 35062300520 ps
CPU time 349.63 seconds
Started Dec 24 01:30:23 PM PST 23
Finished Dec 24 01:36:14 PM PST 23
Peak memory 248632 kb
Host smart-1327c003-d95b-4f48-b13b-e9f4e827c18a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727554275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1727554275
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2463819017
Short name T9
Test name
Test status
Simulation time 6938658437 ps
CPU time 282 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:35:25 PM PST 23
Peak memory 248644 kb
Host smart-41315ad9-ced1-456f-9904-58f4048ed394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463819017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2463819017
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2110593079
Short name T119
Test name
Test status
Simulation time 29653622651 ps
CPU time 1870.15 seconds
Started Dec 24 01:31:53 PM PST 23
Finished Dec 24 02:03:04 PM PST 23
Peak memory 288192 kb
Host smart-a2511d57-d7e8-439d-8d60-bd3bf2770760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110593079 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2110593079
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2488720933
Short name T235
Test name
Test status
Simulation time 242849918489 ps
CPU time 10412.3 seconds
Started Dec 24 01:29:47 PM PST 23
Finished Dec 24 04:23:21 PM PST 23
Peak memory 393100 kb
Host smart-6c978706-85cd-45fc-a5e4-6eb99222c1ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488720933 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2488720933
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1687432867
Short name T126
Test name
Test status
Simulation time 565498405 ps
CPU time 42.18 seconds
Started Dec 24 01:28:20 PM PST 23
Finished Dec 24 01:29:06 PM PST 23
Peak memory 254596 kb
Host smart-e7b88f9e-cbae-4123-a62b-f489b6b05f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16874
32867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1687432867
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2801328640
Short name T153
Test name
Test status
Simulation time 9036403975 ps
CPU time 521.51 seconds
Started Dec 24 12:32:52 PM PST 23
Finished Dec 24 12:42:11 PM PST 23
Peak memory 265360 kb
Host smart-45df1459-a3d6-4372-bd0f-3c0aa036acb9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801328640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2801328640
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2267338736
Short name T178
Test name
Test status
Simulation time 113382511 ps
CPU time 2.54 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:40 PM PST 23
Peak memory 236456 kb
Host smart-48672b18-22fe-48a0-a66b-34ff1a85525b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2267338736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2267338736
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1775716050
Short name T151
Test name
Test status
Simulation time 6895693569 ps
CPU time 209.19 seconds
Started Dec 24 12:32:41 PM PST 23
Finished Dec 24 12:36:37 PM PST 23
Peak memory 265256 kb
Host smart-f046abe2-2b1c-46ea-b7a3-84ddc0e92211
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1775716050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1775716050
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2727473955
Short name T182
Test name
Test status
Simulation time 30049178 ps
CPU time 2.58 seconds
Started Dec 24 12:33:26 PM PST 23
Finished Dec 24 12:34:05 PM PST 23
Peak memory 235580 kb
Host smart-01d0d2b2-3c72-4276-a3c5-86d92111447b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2727473955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2727473955
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1168738369
Short name T30
Test name
Test status
Simulation time 241811792331 ps
CPU time 3933.36 seconds
Started Dec 24 01:30:38 PM PST 23
Finished Dec 24 02:36:14 PM PST 23
Peak memory 305740 kb
Host smart-1ea947c5-1019-4b92-b5aa-41808240a044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168738369 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1168738369
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1159461389
Short name T174
Test name
Test status
Simulation time 86255590 ps
CPU time 2.98 seconds
Started Dec 24 12:33:00 PM PST 23
Finished Dec 24 12:33:46 PM PST 23
Peak memory 235272 kb
Host smart-26889bee-c802-452e-9b92-970069c56ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1159461389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1159461389
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.4006083587
Short name T321
Test name
Test status
Simulation time 30292502792 ps
CPU time 1294.77 seconds
Started Dec 24 01:28:40 PM PST 23
Finished Dec 24 01:50:17 PM PST 23
Peak memory 285344 kb
Host smart-10a08d5d-2bfb-4a75-a4a4-3f8d8c299661
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006083587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.4006083587
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.171588581
Short name T240
Test name
Test status
Simulation time 1424124339 ps
CPU time 31.56 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:29:47 PM PST 23
Peak memory 248100 kb
Host smart-ef04de73-b0aa-4a9f-982e-bf73f3a5bba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17158
8581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.171588581
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.359832350
Short name T304
Test name
Test status
Simulation time 13754898357 ps
CPU time 892.84 seconds
Started Dec 24 01:29:22 PM PST 23
Finished Dec 24 01:44:16 PM PST 23
Peak memory 273284 kb
Host smart-787a1781-147c-4a38-aff9-b30dea09bbf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359832350 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.359832350
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2541298329
Short name T70
Test name
Test status
Simulation time 14212714542 ps
CPU time 1397.52 seconds
Started Dec 24 01:29:29 PM PST 23
Finished Dec 24 01:52:49 PM PST 23
Peak memory 287996 kb
Host smart-1861d00d-321c-4230-8ed1-afa195f89d1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541298329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2541298329
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2441231398
Short name T255
Test name
Test status
Simulation time 28436312422 ps
CPU time 1273.31 seconds
Started Dec 24 01:29:36 PM PST 23
Finished Dec 24 01:50:51 PM PST 23
Peak memory 289352 kb
Host smart-93f2035c-0793-4bb7-a454-9171391ce045
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441231398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2441231398
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1382947664
Short name T125
Test name
Test status
Simulation time 3092636369 ps
CPU time 47.16 seconds
Started Dec 24 01:30:01 PM PST 23
Finished Dec 24 01:30:49 PM PST 23
Peak memory 248264 kb
Host smart-468a88c8-a345-4a67-8dad-0f9a1eb04d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
47664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1382947664
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3264632526
Short name T293
Test name
Test status
Simulation time 2581001478 ps
CPU time 91.52 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 01:32:12 PM PST 23
Peak memory 256620 kb
Host smart-658c00b9-393e-4e83-a014-b441e82c477c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264632526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3264632526
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1022325940
Short name T298
Test name
Test status
Simulation time 434583265 ps
CPU time 44.01 seconds
Started Dec 24 01:31:50 PM PST 23
Finished Dec 24 01:32:35 PM PST 23
Peak memory 256636 kb
Host smart-e2b8fd54-56d2-4949-8cdd-036ed09d4513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10223
25940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1022325940
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2061849990
Short name T246
Test name
Test status
Simulation time 47513388481 ps
CPU time 732.91 seconds
Started Dec 24 01:28:22 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 273144 kb
Host smart-6aea04d6-0e6c-40da-83d2-6dab5ac661c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061849990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2061849990
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.663494586
Short name T16
Test name
Test status
Simulation time 50908662916 ps
CPU time 1491.86 seconds
Started Dec 24 01:29:05 PM PST 23
Finished Dec 24 01:53:59 PM PST 23
Peak memory 272220 kb
Host smart-7ca2f2bc-3ba6-47e9-ad07-1dcd7293f308
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663494586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.663494586
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3715066057
Short name T111
Test name
Test status
Simulation time 430505543 ps
CPU time 21.65 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 01:29:55 PM PST 23
Peak memory 255024 kb
Host smart-80e6254a-caed-42b9-8d32-a06ba6030c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37150
66057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3715066057
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3202853188
Short name T827
Test name
Test status
Simulation time 2426883734 ps
CPU time 173.82 seconds
Started Dec 24 12:32:59 PM PST 23
Finished Dec 24 12:36:35 PM PST 23
Peak memory 271408 kb
Host smart-61caab18-a1aa-4cfe-a083-97783a3125b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3202853188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3202853188
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3913596489
Short name T184
Test name
Test status
Simulation time 2403246953 ps
CPU time 73.75 seconds
Started Dec 24 12:33:15 PM PST 23
Finished Dec 24 12:35:08 PM PST 23
Peak memory 236628 kb
Host smart-ab4253f0-a010-4cad-ad3a-4df338760eae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3913596489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3913596489
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1611492588
Short name T176
Test name
Test status
Simulation time 180604011 ps
CPU time 3.49 seconds
Started Dec 24 12:33:18 PM PST 23
Finished Dec 24 12:34:00 PM PST 23
Peak memory 236808 kb
Host smart-f0c0cb69-9897-4a0b-aa4c-06d3b7243e35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1611492588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1611492588
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2021829804
Short name T145
Test name
Test status
Simulation time 63845174084 ps
CPU time 1246.91 seconds
Started Dec 24 12:33:04 PM PST 23
Finished Dec 24 12:54:32 PM PST 23
Peak memory 265368 kb
Host smart-f1960aeb-bc7d-4bb2-bc48-405e546e11f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021829804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2021829804
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2665026834
Short name T177
Test name
Test status
Simulation time 51358574 ps
CPU time 2.33 seconds
Started Dec 24 12:33:01 PM PST 23
Finished Dec 24 12:33:45 PM PST 23
Peak memory 237360 kb
Host smart-47174715-2667-49b8-849d-fb145e350d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2665026834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2665026834
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3592434575
Short name T180
Test name
Test status
Simulation time 159808371 ps
CPU time 3.37 seconds
Started Dec 24 12:33:15 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 236700 kb
Host smart-ed6c4bbd-4f7f-4504-b2b6-42759986a7de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3592434575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3592434575
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1163850562
Short name T186
Test name
Test status
Simulation time 61060994 ps
CPU time 3.04 seconds
Started Dec 24 12:32:50 PM PST 23
Finished Dec 24 12:33:25 PM PST 23
Peak memory 236888 kb
Host smart-f7c54d4a-1cf1-40d9-af73-9199518c1b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1163850562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1163850562
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.274581854
Short name T181
Test name
Test status
Simulation time 104742704 ps
CPU time 2.41 seconds
Started Dec 24 12:32:55 PM PST 23
Finished Dec 24 12:33:38 PM PST 23
Peak memory 235584 kb
Host smart-2931f76f-4d5f-446d-a20e-1723117ad34f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=274581854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.274581854
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.301526083
Short name T165
Test name
Test status
Simulation time 77439058 ps
CPU time 2.05 seconds
Started Dec 24 12:32:55 PM PST 23
Finished Dec 24 12:33:38 PM PST 23
Peak memory 236620 kb
Host smart-efa83cf1-f2fe-45b2-8220-e4b8dea5cade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=301526083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.301526083
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4002309458
Short name T188
Test name
Test status
Simulation time 113388643 ps
CPU time 2.69 seconds
Started Dec 24 12:33:18 PM PST 23
Finished Dec 24 12:34:00 PM PST 23
Peak memory 236756 kb
Host smart-b8c75a6c-0cd8-4a0e-af5f-22f5deb39526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4002309458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4002309458
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.584674199
Short name T185
Test name
Test status
Simulation time 634204062 ps
CPU time 19.98 seconds
Started Dec 24 12:33:28 PM PST 23
Finished Dec 24 12:34:23 PM PST 23
Peak memory 236424 kb
Host smart-1f7c3b02-f205-417c-825e-6949b7b34c95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=584674199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.584674199
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1573936334
Short name T187
Test name
Test status
Simulation time 5175056869 ps
CPU time 77.36 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:34:29 PM PST 23
Peak memory 239184 kb
Host smart-be6ab0c3-9a12-4832-a1d0-42ac89f55bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1573936334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1573936334
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2075830581
Short name T840
Test name
Test status
Simulation time 587925558 ps
CPU time 68.72 seconds
Started Dec 24 12:33:04 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 236132 kb
Host smart-0e13c9f8-48a1-4208-a764-a18efc8ee265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2075830581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2075830581
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.872106557
Short name T192
Test name
Test status
Simulation time 53016071378 ps
CPU time 438.43 seconds
Started Dec 24 12:33:08 PM PST 23
Finished Dec 24 12:41:08 PM PST 23
Peak memory 235524 kb
Host smart-d4da2259-2d8e-4037-a5e1-7d11145502a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=872106557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.872106557
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1328286964
Short name T746
Test name
Test status
Simulation time 71034182 ps
CPU time 5.66 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:33:21 PM PST 23
Peak memory 240340 kb
Host smart-68ee97b7-5db9-4cb2-96d0-29fdcaad4213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1328286964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1328286964
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1813080154
Short name T727
Test name
Test status
Simulation time 267187442 ps
CPU time 6.54 seconds
Started Dec 24 12:32:39 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 243860 kb
Host smart-e795195d-b99d-49f5-904a-84e875b5abae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813080154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1813080154
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3785064204
Short name T775
Test name
Test status
Simulation time 64811182 ps
CPU time 3.26 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 236332 kb
Host smart-d15e66af-57c4-4706-b660-ae6496f11277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3785064204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3785064204
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2735383139
Short name T821
Test name
Test status
Simulation time 63473246 ps
CPU time 1.37 seconds
Started Dec 24 12:33:03 PM PST 23
Finished Dec 24 12:33:45 PM PST 23
Peak memory 234632 kb
Host smart-a2f3c62a-a55c-4c12-afc5-08f5ca1b7031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2735383139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2735383139
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2623466940
Short name T814
Test name
Test status
Simulation time 317345305 ps
CPU time 11.45 seconds
Started Dec 24 12:33:06 PM PST 23
Finished Dec 24 12:33:59 PM PST 23
Peak memory 244536 kb
Host smart-ab742c6f-59e7-49dd-b195-cd5f4356dc3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2623466940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2623466940
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2722167834
Short name T797
Test name
Test status
Simulation time 4581082621 ps
CPU time 93.2 seconds
Started Dec 24 12:32:58 PM PST 23
Finished Dec 24 12:35:13 PM PST 23
Peak memory 256936 kb
Host smart-d2949fec-0fce-4e69-9d57-adcc8114ecde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2722167834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2722167834
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1436769367
Short name T135
Test name
Test status
Simulation time 747422184 ps
CPU time 10.07 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:37 PM PST 23
Peak memory 248652 kb
Host smart-ef755c02-21b9-47ec-8bb2-336c95f309d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1436769367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1436769367
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.849175539
Short name T728
Test name
Test status
Simulation time 1735184317 ps
CPU time 103.04 seconds
Started Dec 24 12:33:00 PM PST 23
Finished Dec 24 12:35:25 PM PST 23
Peak memory 236160 kb
Host smart-225a908a-ed91-4200-9a9e-ade6d40fb6cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=849175539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.849175539
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4095837581
Short name T228
Test name
Test status
Simulation time 7735311554 ps
CPU time 412.16 seconds
Started Dec 24 12:32:52 PM PST 23
Finished Dec 24 12:40:20 PM PST 23
Peak memory 235552 kb
Host smart-72a3c6c0-fece-446d-8060-4480c9a2578d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4095837581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4095837581
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3882578756
Short name T739
Test name
Test status
Simulation time 419381450 ps
CPU time 8.73 seconds
Started Dec 24 12:32:41 PM PST 23
Finished Dec 24 12:33:17 PM PST 23
Peak memory 240404 kb
Host smart-e61ee43f-b07d-49dc-822a-236a93993e6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3882578756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3882578756
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.540058468
Short name T796
Test name
Test status
Simulation time 230181921 ps
CPU time 6.48 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:33 PM PST 23
Peak memory 243812 kb
Host smart-567c8d07-ff9f-4b3c-b48c-32caafe3ebca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540058468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.540058468
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.136810544
Short name T738
Test name
Test status
Simulation time 120900159 ps
CPU time 9.08 seconds
Started Dec 24 12:33:01 PM PST 23
Finished Dec 24 12:33:52 PM PST 23
Peak memory 236364 kb
Host smart-5cdaed94-3de4-4703-95df-88e074f0cd29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=136810544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.136810544
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2119950670
Short name T806
Test name
Test status
Simulation time 7026524 ps
CPU time 1.27 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 236320 kb
Host smart-f98c5cfa-29fc-4679-b346-95754a35721e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2119950670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2119950670
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.30309968
Short name T749
Test name
Test status
Simulation time 358000179 ps
CPU time 22.46 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:34:04 PM PST 23
Peak memory 244564 kb
Host smart-ba168407-ce05-4a85-bf17-4b862a45a91e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=30309968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outst
anding.30309968
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2748448533
Short name T154
Test name
Test status
Simulation time 16944464960 ps
CPU time 287.29 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:37:58 PM PST 23
Peak memory 266432 kb
Host smart-89e08f5c-ef14-4f83-b848-b128a53020a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748448533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2748448533
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.960643002
Short name T786
Test name
Test status
Simulation time 235913896 ps
CPU time 10.81 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:47 PM PST 23
Peak memory 247076 kb
Host smart-5410fe1f-b016-455d-a91b-742f4505af44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=960643002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.960643002
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.148045610
Short name T801
Test name
Test status
Simulation time 34440603 ps
CPU time 5.02 seconds
Started Dec 24 12:33:02 PM PST 23
Finished Dec 24 12:33:49 PM PST 23
Peak memory 251632 kb
Host smart-78f91117-4f13-41dd-9d7e-5730e310e32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148045610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.148045610
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1720846142
Short name T28
Test name
Test status
Simulation time 182014235 ps
CPU time 7.17 seconds
Started Dec 24 12:33:05 PM PST 23
Finished Dec 24 12:33:55 PM PST 23
Peak memory 235464 kb
Host smart-7f15681a-566e-494b-aee6-4592783f6070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1720846142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1720846142
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.854791345
Short name T771
Test name
Test status
Simulation time 12052149 ps
CPU time 1.34 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:11 PM PST 23
Peak memory 234668 kb
Host smart-448369b4-96e6-4137-895a-8ea9ad70d8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=854791345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.854791345
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3545361770
Short name T846
Test name
Test status
Simulation time 260253809 ps
CPU time 17.34 seconds
Started Dec 24 12:32:54 PM PST 23
Finished Dec 24 12:33:53 PM PST 23
Peak memory 240260 kb
Host smart-9580264e-193a-4849-a212-380114ab9061
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3545361770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3545361770
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.581063449
Short name T146
Test name
Test status
Simulation time 2423147462 ps
CPU time 105.45 seconds
Started Dec 24 12:32:54 PM PST 23
Finished Dec 24 12:35:24 PM PST 23
Peak memory 266604 kb
Host smart-24271c8e-6e6a-4b59-9e91-019dbab095a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=581063449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.581063449
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.177897735
Short name T166
Test name
Test status
Simulation time 2360972203 ps
CPU time 314.95 seconds
Started Dec 24 12:33:00 PM PST 23
Finished Dec 24 12:38:57 PM PST 23
Peak memory 268884 kb
Host smart-9a7b2af8-9801-4a87-bc5e-062d4fe370bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177897735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.177897735
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2285674187
Short name T758
Test name
Test status
Simulation time 222123955 ps
CPU time 7.99 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:33:20 PM PST 23
Peak memory 247476 kb
Host smart-d9ced359-6cee-49e3-b0c2-1c4965a362a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2285674187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2285674187
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4267838360
Short name T183
Test name
Test status
Simulation time 1889545588 ps
CPU time 58.39 seconds
Started Dec 24 12:32:55 PM PST 23
Finished Dec 24 12:34:34 PM PST 23
Peak memory 244956 kb
Host smart-d279c3d3-8fbf-4a55-b7a9-3020f718f839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4267838360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4267838360
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3792560464
Short name T179
Test name
Test status
Simulation time 760436212 ps
CPU time 6.38 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:33:18 PM PST 23
Peak memory 253812 kb
Host smart-80f0a80f-5981-4213-937b-e1c16bdd35d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792560464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3792560464
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.527133476
Short name T779
Test name
Test status
Simulation time 383819058 ps
CPU time 4.6 seconds
Started Dec 24 12:33:11 PM PST 23
Finished Dec 24 12:33:55 PM PST 23
Peak memory 238308 kb
Host smart-192c540c-bccc-435b-80f3-1ea4ac042236
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=527133476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.527133476
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4122995708
Short name T331
Test name
Test status
Simulation time 88648750 ps
CPU time 11.67 seconds
Started Dec 24 12:33:01 PM PST 23
Finished Dec 24 12:33:55 PM PST 23
Peak memory 244544 kb
Host smart-f1c4cce4-afaf-4692-8e1e-7675ae35a2f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4122995708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4122995708
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.299822992
Short name T817
Test name
Test status
Simulation time 4681574652 ps
CPU time 302.35 seconds
Started Dec 24 12:33:08 PM PST 23
Finished Dec 24 12:38:51 PM PST 23
Peak memory 265384 kb
Host smart-18549556-4a34-49b2-b3b3-4419888c643d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=299822992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.299822992
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2518749249
Short name T743
Test name
Test status
Simulation time 270505764 ps
CPU time 8.12 seconds
Started Dec 24 12:33:17 PM PST 23
Finished Dec 24 12:34:05 PM PST 23
Peak memory 252872 kb
Host smart-a0d2d58a-070b-429a-a01f-51371c901275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2518749249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2518749249
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1282876769
Short name T734
Test name
Test status
Simulation time 139799449 ps
CPU time 6.97 seconds
Started Dec 24 12:32:45 PM PST 23
Finished Dec 24 12:33:20 PM PST 23
Peak memory 253716 kb
Host smart-8318a4f7-8d75-43aa-aeb2-cabe2446dab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282876769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1282876769
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1731715609
Short name T831
Test name
Test status
Simulation time 51693155 ps
CPU time 4.45 seconds
Started Dec 24 12:33:13 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 236340 kb
Host smart-a9e34821-134c-4378-be37-134a193c2898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1731715609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1731715609
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1655445788
Short name T229
Test name
Test status
Simulation time 50548799 ps
CPU time 1.25 seconds
Started Dec 24 12:33:26 PM PST 23
Finished Dec 24 12:34:04 PM PST 23
Peak memory 236172 kb
Host smart-d6b4de15-6793-4ded-9cd6-a9a7b43110c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1655445788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1655445788
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2894389990
Short name T21
Test name
Test status
Simulation time 474607241 ps
CPU time 21.22 seconds
Started Dec 24 12:32:52 PM PST 23
Finished Dec 24 12:33:49 PM PST 23
Peak memory 248556 kb
Host smart-7c1f741b-789d-4732-a7ec-64c4228cb5e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2894389990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2894389990
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4253208798
Short name T149
Test name
Test status
Simulation time 74000049598 ps
CPU time 995.73 seconds
Started Dec 24 12:33:34 PM PST 23
Finished Dec 24 12:50:45 PM PST 23
Peak memory 265196 kb
Host smart-01c336bd-fe49-4377-8e70-276732d2b71b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253208798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4253208798
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.468703702
Short name T834
Test name
Test status
Simulation time 345233981 ps
CPU time 5.09 seconds
Started Dec 24 12:33:33 PM PST 23
Finished Dec 24 12:34:14 PM PST 23
Peak memory 248520 kb
Host smart-b68bf025-889b-4361-a55b-2e458b2aecdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=468703702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.468703702
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1633279481
Short name T795
Test name
Test status
Simulation time 33451967 ps
CPU time 3.94 seconds
Started Dec 24 12:33:06 PM PST 23
Finished Dec 24 12:33:52 PM PST 23
Peak memory 240320 kb
Host smart-26ba0e6a-3393-4a02-92ac-6bd3af57a39c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633279481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1633279481
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1683124081
Short name T25
Test name
Test status
Simulation time 122455624 ps
CPU time 5.03 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:43 PM PST 23
Peak memory 236404 kb
Host smart-e4cb3417-bda9-43cc-9403-0990bda795cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1683124081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1683124081
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2456103832
Short name T737
Test name
Test status
Simulation time 9851034 ps
CPU time 1.55 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 235740 kb
Host smart-159ee95b-a9b8-4b1d-9b54-2c127c317029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2456103832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2456103832
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2273279490
Short name T191
Test name
Test status
Simulation time 178108620 ps
CPU time 21.93 seconds
Started Dec 24 12:33:16 PM PST 23
Finished Dec 24 12:34:18 PM PST 23
Peak memory 244624 kb
Host smart-86c4ff3f-91b9-4b99-ab4b-2b2f043be69c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2273279490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2273279490
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.580116654
Short name T167
Test name
Test status
Simulation time 20677881652 ps
CPU time 320.08 seconds
Started Dec 24 12:33:15 PM PST 23
Finished Dec 24 12:39:14 PM PST 23
Peak memory 265288 kb
Host smart-b717ee10-3b04-454e-95df-e1625fff7c57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=580116654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.580116654
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3882426113
Short name T329
Test name
Test status
Simulation time 35357459877 ps
CPU time 291.59 seconds
Started Dec 24 12:33:20 PM PST 23
Finished Dec 24 12:38:50 PM PST 23
Peak memory 265388 kb
Host smart-7de38ba3-7ece-42c2-a161-e4928789a574
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882426113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3882426113
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2616356623
Short name T171
Test name
Test status
Simulation time 985236040 ps
CPU time 15.62 seconds
Started Dec 24 12:33:12 PM PST 23
Finished Dec 24 12:34:07 PM PST 23
Peak memory 248588 kb
Host smart-08d8ead9-6e40-483b-891a-f3e6a7d1180a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2616356623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2616356623
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.807522628
Short name T793
Test name
Test status
Simulation time 27487583 ps
CPU time 3.17 seconds
Started Dec 24 12:33:24 PM PST 23
Finished Dec 24 12:34:04 PM PST 23
Peak memory 239244 kb
Host smart-3865f769-2708-415a-930c-5dd38bd3b013
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807522628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.807522628
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2967087929
Short name T741
Test name
Test status
Simulation time 92910813 ps
CPU time 7.27 seconds
Started Dec 24 12:32:54 PM PST 23
Finished Dec 24 12:33:45 PM PST 23
Peak memory 235452 kb
Host smart-d79274b4-152b-4adf-b019-1a3bd0f33fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2967087929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2967087929
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.961050398
Short name T744
Test name
Test status
Simulation time 8039420 ps
CPU time 1.32 seconds
Started Dec 24 12:33:17 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 235592 kb
Host smart-19c5fd21-eb59-44e9-9f94-0b2d04081cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=961050398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.961050398
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3796983679
Short name T193
Test name
Test status
Simulation time 749721694 ps
CPU time 22.88 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:59 PM PST 23
Peak memory 244632 kb
Host smart-675b613a-e752-4687-9a2e-4a59ad978596
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3796983679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3796983679
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.319901087
Short name T807
Test name
Test status
Simulation time 4218219725 ps
CPU time 127.88 seconds
Started Dec 24 12:33:03 PM PST 23
Finished Dec 24 12:35:52 PM PST 23
Peak memory 265212 kb
Host smart-c11c2b34-5115-4e89-9353-4e7c44f0dc70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=319901087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.319901087
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3151756039
Short name T141
Test name
Test status
Simulation time 12306292249 ps
CPU time 916.88 seconds
Started Dec 24 12:33:09 PM PST 23
Finished Dec 24 12:49:07 PM PST 23
Peak memory 270096 kb
Host smart-6d3d3b41-b71d-4292-ad60-fc43e48e43a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151756039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3151756039
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4045403618
Short name T27
Test name
Test status
Simulation time 42360023 ps
CPU time 5.22 seconds
Started Dec 24 12:33:15 PM PST 23
Finished Dec 24 12:33:59 PM PST 23
Peak memory 248140 kb
Host smart-a1c1a118-ec04-451b-83b4-e3f9b6f0b9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4045403618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4045403618
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1646308000
Short name T742
Test name
Test status
Simulation time 38958037 ps
CPU time 6.41 seconds
Started Dec 24 12:33:34 PM PST 23
Finished Dec 24 12:34:15 PM PST 23
Peak memory 255880 kb
Host smart-f8cd1441-8869-446e-bed2-60f149a8b868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646308000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1646308000
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.73634890
Short name T731
Test name
Test status
Simulation time 34751933 ps
CPU time 3.14 seconds
Started Dec 24 12:33:36 PM PST 23
Finished Dec 24 12:34:15 PM PST 23
Peak memory 235488 kb
Host smart-7d8efc54-163f-402a-9ca7-5c811e992657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=73634890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.73634890
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.464872679
Short name T767
Test name
Test status
Simulation time 14793775 ps
CPU time 1.25 seconds
Started Dec 24 12:33:22 PM PST 23
Finished Dec 24 12:34:00 PM PST 23
Peak memory 235556 kb
Host smart-716db6c5-2ec2-4968-b8fa-40f568cc1a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=464872679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.464872679
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.633801063
Short name T763
Test name
Test status
Simulation time 2283431657 ps
CPU time 18.97 seconds
Started Dec 24 12:33:22 PM PST 23
Finished Dec 24 12:34:19 PM PST 23
Peak memory 240408 kb
Host smart-9cb22ecf-6e62-4b41-9edf-d7328dbc6039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=633801063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.633801063
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3616293475
Short name T143
Test name
Test status
Simulation time 34691595242 ps
CPU time 1248.36 seconds
Started Dec 24 12:33:17 PM PST 23
Finished Dec 24 12:54:45 PM PST 23
Peak memory 265352 kb
Host smart-ef2e9d30-386c-4ef9-9010-ec90cf7d0ef0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616293475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3616293475
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3332745009
Short name T762
Test name
Test status
Simulation time 486030419 ps
CPU time 8.18 seconds
Started Dec 24 12:33:36 PM PST 23
Finished Dec 24 12:34:20 PM PST 23
Peak memory 247860 kb
Host smart-563db251-839f-49c7-9657-2c7d31d0e37a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3332745009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3332745009
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1448423069
Short name T799
Test name
Test status
Simulation time 213591321 ps
CPU time 6.02 seconds
Started Dec 24 12:33:25 PM PST 23
Finished Dec 24 12:34:08 PM PST 23
Peak memory 243432 kb
Host smart-30ac723e-8e48-4b67-af7a-ab1d73d82346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448423069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1448423069
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1168127557
Short name T805
Test name
Test status
Simulation time 151844293 ps
CPU time 7.47 seconds
Started Dec 24 12:33:28 PM PST 23
Finished Dec 24 12:34:11 PM PST 23
Peak memory 236324 kb
Host smart-19ab3094-3c0a-49a3-9224-fc7cd6b58b04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1168127557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1168127557
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2296656924
Short name T823
Test name
Test status
Simulation time 4508514303 ps
CPU time 34.88 seconds
Started Dec 24 12:33:18 PM PST 23
Finished Dec 24 12:34:33 PM PST 23
Peak memory 248668 kb
Host smart-77845913-2fd5-41b8-afb9-397c74fb2316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2296656924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2296656924
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4119271089
Short name T778
Test name
Test status
Simulation time 432000954 ps
CPU time 11.24 seconds
Started Dec 24 12:33:19 PM PST 23
Finished Dec 24 12:34:09 PM PST 23
Peak memory 248124 kb
Host smart-4eef5573-9fb1-4ffb-874a-31197221b682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4119271089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4119271089
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3268613073
Short name T848
Test name
Test status
Simulation time 296218276 ps
CPU time 6.06 seconds
Started Dec 24 12:33:42 PM PST 23
Finished Dec 24 12:34:23 PM PST 23
Peak memory 252764 kb
Host smart-4a274133-ab61-4b90-92bc-02dcf10a9a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268613073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3268613073
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1509484963
Short name T782
Test name
Test status
Simulation time 35334031 ps
CPU time 5.11 seconds
Started Dec 24 12:33:10 PM PST 23
Finished Dec 24 12:33:56 PM PST 23
Peak memory 240372 kb
Host smart-a9e648b0-7f0a-44c8-a609-d626cd7a9b60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1509484963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1509484963
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3523249125
Short name T22
Test name
Test status
Simulation time 11441864 ps
CPU time 1.24 seconds
Started Dec 24 12:33:24 PM PST 23
Finished Dec 24 12:34:02 PM PST 23
Peak memory 236388 kb
Host smart-3973c2ab-c048-4873-862d-b2852e1f0367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3523249125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3523249125
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1456817142
Short name T733
Test name
Test status
Simulation time 515716398 ps
CPU time 30.81 seconds
Started Dec 24 12:33:35 PM PST 23
Finished Dec 24 12:34:41 PM PST 23
Peak memory 243616 kb
Host smart-67096d90-9fc7-4dc4-8199-c714484036b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1456817142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1456817142
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3183369184
Short name T134
Test name
Test status
Simulation time 2346375396 ps
CPU time 151.3 seconds
Started Dec 24 12:33:27 PM PST 23
Finished Dec 24 12:36:34 PM PST 23
Peak memory 257144 kb
Host smart-741009f8-e698-4a49-bd7c-b43ea1b3ce59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3183369184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3183369184
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2504370979
Short name T144
Test name
Test status
Simulation time 2343840091 ps
CPU time 265.21 seconds
Started Dec 24 12:33:41 PM PST 23
Finished Dec 24 12:38:42 PM PST 23
Peak memory 268212 kb
Host smart-6a3abfdd-6b0c-4801-90f2-771a40692a3a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504370979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2504370979
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.339401592
Short name T798
Test name
Test status
Simulation time 79755900 ps
CPU time 6.24 seconds
Started Dec 24 12:33:14 PM PST 23
Finished Dec 24 12:34:00 PM PST 23
Peak memory 250284 kb
Host smart-918eb778-5978-428d-ada9-c18476876b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=339401592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.339401592
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3826581398
Short name T735
Test name
Test status
Simulation time 47905326 ps
CPU time 5.47 seconds
Started Dec 24 12:33:35 PM PST 23
Finished Dec 24 12:34:15 PM PST 23
Peak memory 248548 kb
Host smart-fcf788e9-032e-483d-a1bb-cbca0059617a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826581398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3826581398
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.821643225
Short name T808
Test name
Test status
Simulation time 215699149 ps
CPU time 8.08 seconds
Started Dec 24 12:33:13 PM PST 23
Finished Dec 24 12:34:01 PM PST 23
Peak memory 240412 kb
Host smart-baccf6b3-8c03-4e7d-a588-f8aed9b4560e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=821643225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.821643225
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2794718908
Short name T776
Test name
Test status
Simulation time 28708798 ps
CPU time 1.23 seconds
Started Dec 24 12:33:30 PM PST 23
Finished Dec 24 12:34:06 PM PST 23
Peak memory 235316 kb
Host smart-11741c3e-e190-4927-b1e3-93d30da53975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2794718908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2794718908
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1000890175
Short name T784
Test name
Test status
Simulation time 258270477 ps
CPU time 19.39 seconds
Started Dec 24 12:33:51 PM PST 23
Finished Dec 24 12:34:46 PM PST 23
Peak memory 239408 kb
Host smart-811c15dc-18a2-4e3e-8124-0422b735c895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1000890175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1000890175
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4253357416
Short name T147
Test name
Test status
Simulation time 5274117453 ps
CPU time 98.55 seconds
Started Dec 24 12:33:25 PM PST 23
Finished Dec 24 12:35:41 PM PST 23
Peak memory 265328 kb
Host smart-8d226a18-cd75-4a35-bb9d-6beb31bb11ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4253357416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4253357416
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1175321572
Short name T156
Test name
Test status
Simulation time 4492335120 ps
CPU time 553.08 seconds
Started Dec 24 12:33:31 PM PST 23
Finished Dec 24 12:43:19 PM PST 23
Peak memory 272652 kb
Host smart-452364c1-4db2-4de0-8722-c494091c1c19
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175321572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1175321572
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2220642336
Short name T29
Test name
Test status
Simulation time 558480843 ps
CPU time 12.62 seconds
Started Dec 24 12:33:28 PM PST 23
Finished Dec 24 12:34:16 PM PST 23
Peak memory 248596 kb
Host smart-fbf5a0cb-8331-4915-95aa-1146531c8003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220642336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2220642336
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.166593555
Short name T764
Test name
Test status
Simulation time 266547588 ps
CPU time 6.21 seconds
Started Dec 24 12:33:28 PM PST 23
Finished Dec 24 12:34:10 PM PST 23
Peak memory 248516 kb
Host smart-20b44050-cf6f-4e87-a443-801f0f608bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166593555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.166593555
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2150108736
Short name T748
Test name
Test status
Simulation time 126100202 ps
CPU time 7.88 seconds
Started Dec 24 12:33:34 PM PST 23
Finished Dec 24 12:34:17 PM PST 23
Peak memory 236436 kb
Host smart-30ac3508-f92e-4511-922a-9d969986cce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2150108736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2150108736
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1053516237
Short name T838
Test name
Test status
Simulation time 10797764 ps
CPU time 1.21 seconds
Started Dec 24 12:33:43 PM PST 23
Finished Dec 24 12:34:20 PM PST 23
Peak memory 234528 kb
Host smart-ad3851b1-78e5-478e-851f-e467e56d7a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1053516237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1053516237
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.118144551
Short name T769
Test name
Test status
Simulation time 670166527 ps
CPU time 38.16 seconds
Started Dec 24 12:33:24 PM PST 23
Finished Dec 24 12:34:40 PM PST 23
Peak memory 244536 kb
Host smart-0cf6dbc1-e760-474a-b28a-9f6fc573b22d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=118144551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.118144551
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1638118992
Short name T842
Test name
Test status
Simulation time 13282299192 ps
CPU time 184.24 seconds
Started Dec 24 12:33:23 PM PST 23
Finished Dec 24 12:37:05 PM PST 23
Peak memory 265240 kb
Host smart-36598a29-4729-4946-91a3-a50e3b6d4831
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1638118992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1638118992
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4108106436
Short name T161
Test name
Test status
Simulation time 56937487820 ps
CPU time 1059.12 seconds
Started Dec 24 12:33:24 PM PST 23
Finished Dec 24 12:51:40 PM PST 23
Peak memory 265412 kb
Host smart-e655f8c8-6f1f-4464-9bab-cb0846585887
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108106436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4108106436
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.296293499
Short name T816
Test name
Test status
Simulation time 1348332028 ps
CPU time 8.22 seconds
Started Dec 24 12:33:08 PM PST 23
Finished Dec 24 12:33:58 PM PST 23
Peak memory 247980 kb
Host smart-887b5710-0e5b-49f9-bb14-5d93699b6fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=296293499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.296293499
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.675936395
Short name T825
Test name
Test status
Simulation time 1860623698 ps
CPU time 30.68 seconds
Started Dec 24 12:33:25 PM PST 23
Finished Dec 24 12:34:32 PM PST 23
Peak memory 239336 kb
Host smart-2a75b902-183d-471d-8d49-7860c22c2a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=675936395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.675936395
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1038944580
Short name T745
Test name
Test status
Simulation time 4618168540 ps
CPU time 265.59 seconds
Started Dec 24 12:32:50 PM PST 23
Finished Dec 24 12:37:48 PM PST 23
Peak memory 238168 kb
Host smart-ca220f0c-e808-4120-9e38-8d4219542b97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1038944580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1038944580
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3599825457
Short name T729
Test name
Test status
Simulation time 25940854675 ps
CPU time 353.2 seconds
Started Dec 24 12:33:07 PM PST 23
Finished Dec 24 12:39:42 PM PST 23
Peak memory 240384 kb
Host smart-9fdc526a-d410-4c39-8943-53166b119ba6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3599825457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3599825457
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3307170870
Short name T172
Test name
Test status
Simulation time 215819469 ps
CPU time 4.94 seconds
Started Dec 24 12:33:17 PM PST 23
Finished Dec 24 12:34:01 PM PST 23
Peak memory 240384 kb
Host smart-7f31a558-585a-488a-9669-90580995de24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3307170870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3307170870
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3321986368
Short name T760
Test name
Test status
Simulation time 63129127 ps
CPU time 3.3 seconds
Started Dec 24 12:32:49 PM PST 23
Finished Dec 24 12:33:24 PM PST 23
Peak memory 255608 kb
Host smart-9e498add-9a49-4827-811e-b0624e6af0bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321986368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3321986368
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2497758145
Short name T755
Test name
Test status
Simulation time 109615027 ps
CPU time 4.18 seconds
Started Dec 24 12:32:46 PM PST 23
Finished Dec 24 12:33:19 PM PST 23
Peak memory 239296 kb
Host smart-c3d6b3a5-4f7a-4765-ae09-f3d5b849b130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2497758145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2497758145
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.274387322
Short name T819
Test name
Test status
Simulation time 20137275 ps
CPU time 1.3 seconds
Started Dec 24 12:32:52 PM PST 23
Finished Dec 24 12:33:31 PM PST 23
Peak memory 235584 kb
Host smart-330cf446-01bc-4b91-99ec-673ca197828e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=274387322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.274387322
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1257131583
Short name T757
Test name
Test status
Simulation time 1170720916 ps
CPU time 23.91 seconds
Started Dec 24 12:33:07 PM PST 23
Finished Dec 24 12:34:12 PM PST 23
Peak memory 244524 kb
Host smart-c9281a8d-f35f-4b98-92e2-e72e23aa3b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1257131583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1257131583
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1622271008
Short name T158
Test name
Test status
Simulation time 1387890663 ps
CPU time 115.73 seconds
Started Dec 24 12:32:53 PM PST 23
Finished Dec 24 12:35:27 PM PST 23
Peak memory 265516 kb
Host smart-45c2b9d9-2bae-4780-9d10-41a5e3daeda9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1622271008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1622271008
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2805134072
Short name T756
Test name
Test status
Simulation time 225057431 ps
CPU time 13.4 seconds
Started Dec 24 12:32:50 PM PST 23
Finished Dec 24 12:33:37 PM PST 23
Peak memory 248576 kb
Host smart-2c121c14-2f49-4723-b4a0-558b57d3dabf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2805134072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2805134072
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3620435349
Short name T781
Test name
Test status
Simulation time 9294111 ps
CPU time 1.31 seconds
Started Dec 24 12:33:43 PM PST 23
Finished Dec 24 12:34:21 PM PST 23
Peak memory 235444 kb
Host smart-2e6f8f0e-7c2a-4c98-ad5e-cbfae4f64741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3620435349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3620435349
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3370063757
Short name T766
Test name
Test status
Simulation time 10792809 ps
CPU time 1.22 seconds
Started Dec 24 12:33:46 PM PST 23
Finished Dec 24 12:34:24 PM PST 23
Peak memory 236336 kb
Host smart-72adc841-118c-44b4-a377-043bf546c57c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3370063757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3370063757
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3681558573
Short name T818
Test name
Test status
Simulation time 8654933 ps
CPU time 1.44 seconds
Started Dec 24 12:33:24 PM PST 23
Finished Dec 24 12:34:02 PM PST 23
Peak memory 234608 kb
Host smart-bda7062b-f46e-4ee0-8da7-9d7d8583da14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3681558573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3681558573
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3722405285
Short name T828
Test name
Test status
Simulation time 28433137 ps
CPU time 1.44 seconds
Started Dec 24 12:33:29 PM PST 23
Finished Dec 24 12:34:06 PM PST 23
Peak memory 236360 kb
Host smart-65e6344e-0302-433c-9e52-c231fca96573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3722405285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3722405285
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1855281411
Short name T839
Test name
Test status
Simulation time 14265477 ps
CPU time 1.4 seconds
Started Dec 24 12:33:22 PM PST 23
Finished Dec 24 12:34:01 PM PST 23
Peak memory 236448 kb
Host smart-503784d0-0d46-435e-a2d4-17917bdcf446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1855281411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1855281411
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3325053897
Short name T791
Test name
Test status
Simulation time 10284705 ps
CPU time 1.22 seconds
Started Dec 24 12:33:35 PM PST 23
Finished Dec 24 12:34:11 PM PST 23
Peak memory 236468 kb
Host smart-19ceff7b-a9da-4ad3-aaf5-45e2319435b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3325053897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3325053897
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1042642169
Short name T323
Test name
Test status
Simulation time 12207163 ps
CPU time 1.28 seconds
Started Dec 24 12:33:30 PM PST 23
Finished Dec 24 12:34:06 PM PST 23
Peak memory 235528 kb
Host smart-8bff9d61-9150-4ad3-b2eb-186bc8cf20ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1042642169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1042642169
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2451440498
Short name T759
Test name
Test status
Simulation time 8219515 ps
CPU time 1.45 seconds
Started Dec 24 12:33:35 PM PST 23
Finished Dec 24 12:34:12 PM PST 23
Peak memory 235636 kb
Host smart-3fbe7ec0-e6c0-4758-8c36-acbb8ca96d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2451440498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2451440498
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3681164643
Short name T785
Test name
Test status
Simulation time 9300402 ps
CPU time 1.17 seconds
Started Dec 24 12:33:13 PM PST 23
Finished Dec 24 12:33:54 PM PST 23
Peak memory 235620 kb
Host smart-9c8a3d1b-7725-463e-a28a-ff7bb98827ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3681164643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3681164643
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2048024143
Short name T803
Test name
Test status
Simulation time 23215685 ps
CPU time 1.37 seconds
Started Dec 24 12:33:20 PM PST 23
Finished Dec 24 12:34:00 PM PST 23
Peak memory 236348 kb
Host smart-fd904baa-f8b8-4654-aaeb-83650c0d86a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2048024143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2048024143
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1160090680
Short name T794
Test name
Test status
Simulation time 7067997336 ps
CPU time 229.66 seconds
Started Dec 24 12:32:57 PM PST 23
Finished Dec 24 12:37:29 PM PST 23
Peak memory 240456 kb
Host smart-3641af07-067f-47ca-967d-7094ec2b4b2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1160090680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1160090680
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.851442128
Short name T829
Test name
Test status
Simulation time 824037586 ps
CPU time 96.51 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:34:47 PM PST 23
Peak memory 240244 kb
Host smart-10930d0b-e5fa-421b-9426-209007a3b494
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=851442128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.851442128
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2341358100
Short name T736
Test name
Test status
Simulation time 58540413 ps
CPU time 6.82 seconds
Started Dec 24 12:33:05 PM PST 23
Finished Dec 24 12:33:53 PM PST 23
Peak memory 240376 kb
Host smart-f1f7b084-2bc0-4932-baa2-375bae25eee0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2341358100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2341358100
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1091854269
Short name T770
Test name
Test status
Simulation time 63457215 ps
CPU time 6.34 seconds
Started Dec 24 12:32:55 PM PST 23
Finished Dec 24 12:33:42 PM PST 23
Peak memory 251684 kb
Host smart-15c94bd4-2d1d-47aa-a5af-41d0c0acec6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091854269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1091854269
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.799176974
Short name T194
Test name
Test status
Simulation time 122553422 ps
CPU time 4.89 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:41 PM PST 23
Peak memory 236372 kb
Host smart-6526b55a-1a92-482e-a034-dea6597db2f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=799176974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.799176974
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2031049333
Short name T836
Test name
Test status
Simulation time 27365066 ps
CPU time 1.31 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:29 PM PST 23
Peak memory 235592 kb
Host smart-efa9bee0-f9bc-4d9d-b68a-03bbc3f2fa6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2031049333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2031049333
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1440619570
Short name T783
Test name
Test status
Simulation time 664758349 ps
CPU time 22.47 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:34:00 PM PST 23
Peak memory 248588 kb
Host smart-e4781b50-e8bf-433e-9708-04bb74e39a47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1440619570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1440619570
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3176368734
Short name T830
Test name
Test status
Simulation time 52859999 ps
CPU time 3.87 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:32 PM PST 23
Peak memory 240192 kb
Host smart-e6cd3107-a2c6-4f4b-8a23-e3af4928a175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3176368734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3176368734
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3127979611
Short name T325
Test name
Test status
Simulation time 10278145 ps
CPU time 1.52 seconds
Started Dec 24 12:33:36 PM PST 23
Finished Dec 24 12:34:13 PM PST 23
Peak memory 236376 kb
Host smart-cd12b5f6-f915-4203-9c4f-a33d3430d8ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3127979611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3127979611
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1790351537
Short name T847
Test name
Test status
Simulation time 15078720 ps
CPU time 1.28 seconds
Started Dec 24 12:33:19 PM PST 23
Finished Dec 24 12:33:59 PM PST 23
Peak memory 234604 kb
Host smart-6653e84f-634f-4986-8fb9-4d311d09b691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1790351537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1790351537
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.100004992
Short name T787
Test name
Test status
Simulation time 10328605 ps
CPU time 1.54 seconds
Started Dec 24 12:33:49 PM PST 23
Finished Dec 24 12:34:27 PM PST 23
Peak memory 236416 kb
Host smart-62bbf46c-8ae0-4869-a8dc-3208c4791b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=100004992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.100004992
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.522075706
Short name T832
Test name
Test status
Simulation time 6668302 ps
CPU time 1.36 seconds
Started Dec 24 12:33:30 PM PST 23
Finished Dec 24 12:34:07 PM PST 23
Peak memory 235480 kb
Host smart-71956f65-9e62-4794-8ddf-9f3342056a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=522075706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.522075706
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1150195128
Short name T225
Test name
Test status
Simulation time 16708193 ps
CPU time 1.2 seconds
Started Dec 24 12:33:17 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 236356 kb
Host smart-2aa7ead0-abc5-474f-828b-f93a464af8b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1150195128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1150195128
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.150088127
Short name T730
Test name
Test status
Simulation time 9319667 ps
CPU time 1.64 seconds
Started Dec 24 12:33:36 PM PST 23
Finished Dec 24 12:34:12 PM PST 23
Peak memory 235620 kb
Host smart-04e06986-5f47-4c6e-b40d-94ea395a2005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=150088127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.150088127
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1256114229
Short name T813
Test name
Test status
Simulation time 6129859 ps
CPU time 1.4 seconds
Started Dec 24 12:33:34 PM PST 23
Finished Dec 24 12:34:11 PM PST 23
Peak memory 236448 kb
Host smart-9020541b-b37d-4fb8-9c96-54dd775afae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1256114229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1256114229
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3105573837
Short name T841
Test name
Test status
Simulation time 27199277 ps
CPU time 1.33 seconds
Started Dec 24 12:33:45 PM PST 23
Finished Dec 24 12:34:23 PM PST 23
Peak memory 234496 kb
Host smart-76cd6f81-cafa-42bc-a8ee-0782d721f2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3105573837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3105573837
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.535880985
Short name T789
Test name
Test status
Simulation time 9121787 ps
CPU time 1.47 seconds
Started Dec 24 12:33:51 PM PST 23
Finished Dec 24 12:34:29 PM PST 23
Peak memory 235436 kb
Host smart-7fc97eef-7b2b-4296-b66f-bc4183273aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=535880985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.535880985
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.902630388
Short name T833
Test name
Test status
Simulation time 8803732203 ps
CPU time 131.12 seconds
Started Dec 24 12:32:58 PM PST 23
Finished Dec 24 12:36:00 PM PST 23
Peak memory 240360 kb
Host smart-0988c91d-7b9b-40c0-9287-199130b02b6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=902630388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.902630388
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1626927224
Short name T835
Test name
Test status
Simulation time 5772146252 ps
CPU time 326.7 seconds
Started Dec 24 12:32:58 PM PST 23
Finished Dec 24 12:39:06 PM PST 23
Peak memory 240360 kb
Host smart-bd646b69-0eec-4d94-84e1-56c89a334672
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1626927224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1626927224
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2192870245
Short name T815
Test name
Test status
Simulation time 22362947 ps
CPU time 3.82 seconds
Started Dec 24 12:32:54 PM PST 23
Finished Dec 24 12:33:37 PM PST 23
Peak memory 240348 kb
Host smart-33abc969-fa25-4ec2-855f-3412f9acc440
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2192870245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2192870245
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1255334680
Short name T845
Test name
Test status
Simulation time 759828316 ps
CPU time 6.41 seconds
Started Dec 24 12:32:59 PM PST 23
Finished Dec 24 12:33:47 PM PST 23
Peak memory 243552 kb
Host smart-b64e6e66-34c6-4099-9b89-3532d886d1e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255334680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1255334680
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1000708420
Short name T780
Test name
Test status
Simulation time 95318201 ps
CPU time 7.14 seconds
Started Dec 24 12:33:05 PM PST 23
Finished Dec 24 12:33:53 PM PST 23
Peak memory 240284 kb
Host smart-00aa23e0-caf5-4df6-9237-88c6f1ed884b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1000708420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1000708420
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1227968826
Short name T747
Test name
Test status
Simulation time 8326283 ps
CPU time 1.54 seconds
Started Dec 24 12:32:59 PM PST 23
Finished Dec 24 12:33:42 PM PST 23
Peak memory 235692 kb
Host smart-0329deb3-692f-460f-9a91-b737f8a783d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1227968826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1227968826
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1169815771
Short name T820
Test name
Test status
Simulation time 314298428 ps
CPU time 11.44 seconds
Started Dec 24 12:32:53 PM PST 23
Finished Dec 24 12:33:43 PM PST 23
Peak memory 244408 kb
Host smart-26123eaf-33f8-4da6-8419-a7aa53c04c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1169815771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1169815771
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1287912738
Short name T150
Test name
Test status
Simulation time 4760071255 ps
CPU time 299.1 seconds
Started Dec 24 12:33:05 PM PST 23
Finished Dec 24 12:38:45 PM PST 23
Peak memory 265360 kb
Host smart-25893bcd-c5ee-4587-8eb0-567fe68c31e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287912738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1287912738
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4248855086
Short name T800
Test name
Test status
Simulation time 1391329810 ps
CPU time 17.15 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:44 PM PST 23
Peak memory 248684 kb
Host smart-af56888d-9a7b-4823-b05e-3605b7883ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4248855086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4248855086
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3743746556
Short name T753
Test name
Test status
Simulation time 8193830 ps
CPU time 1.28 seconds
Started Dec 24 12:33:32 PM PST 23
Finished Dec 24 12:34:08 PM PST 23
Peak memory 236316 kb
Host smart-0c8b8993-e719-458e-862c-764df78ce5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3743746556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3743746556
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2723429066
Short name T772
Test name
Test status
Simulation time 11476387 ps
CPU time 1.23 seconds
Started Dec 24 12:33:55 PM PST 23
Finished Dec 24 12:34:34 PM PST 23
Peak memory 236336 kb
Host smart-970d4c53-9d72-4fdc-ab3f-5780b09d931d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2723429066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2723429066
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2380313239
Short name T752
Test name
Test status
Simulation time 24831320 ps
CPU time 1.45 seconds
Started Dec 24 12:33:30 PM PST 23
Finished Dec 24 12:34:06 PM PST 23
Peak memory 236448 kb
Host smart-10a9ae27-6504-4db7-9126-b8ff299d0a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2380313239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2380313239
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1392150516
Short name T804
Test name
Test status
Simulation time 9998946 ps
CPU time 1.3 seconds
Started Dec 24 12:33:33 PM PST 23
Finished Dec 24 12:34:09 PM PST 23
Peak memory 234552 kb
Host smart-ad55de3d-c146-4bf9-8302-8b4c903770fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1392150516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1392150516
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2518149133
Short name T777
Test name
Test status
Simulation time 9210169 ps
CPU time 1.28 seconds
Started Dec 24 12:33:24 PM PST 23
Finished Dec 24 12:34:02 PM PST 23
Peak memory 234584 kb
Host smart-9187ea51-28a4-4ec3-b0cc-b730392b1d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2518149133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2518149133
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.847365743
Short name T170
Test name
Test status
Simulation time 26220676 ps
CPU time 1.36 seconds
Started Dec 24 12:33:18 PM PST 23
Finished Dec 24 12:33:58 PM PST 23
Peak memory 235604 kb
Host smart-973e78c8-cb75-4466-80bd-d1b1fdc63ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=847365743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.847365743
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2365435398
Short name T826
Test name
Test status
Simulation time 10799280 ps
CPU time 1.5 seconds
Started Dec 24 12:33:16 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 235712 kb
Host smart-66fcd700-b67e-410d-aa85-f448677c9b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2365435398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2365435398
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1920949888
Short name T326
Test name
Test status
Simulation time 12217224 ps
CPU time 1.26 seconds
Started Dec 24 12:33:18 PM PST 23
Finished Dec 24 12:33:59 PM PST 23
Peak memory 236340 kb
Host smart-895f9652-db81-480e-a873-0a046a82047b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1920949888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1920949888
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1601257018
Short name T812
Test name
Test status
Simulation time 29196867 ps
CPU time 1.32 seconds
Started Dec 24 12:33:32 PM PST 23
Finished Dec 24 12:34:14 PM PST 23
Peak memory 235592 kb
Host smart-7ad9325c-679b-4bf1-9c40-9ad3a3a6ce2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1601257018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1601257018
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3811123144
Short name T844
Test name
Test status
Simulation time 10162196 ps
CPU time 1.53 seconds
Started Dec 24 12:33:46 PM PST 23
Finished Dec 24 12:34:24 PM PST 23
Peak memory 236396 kb
Host smart-98ebfeeb-473c-4835-b16c-77e329eea3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3811123144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3811123144
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3331972222
Short name T751
Test name
Test status
Simulation time 35922346 ps
CPU time 4.08 seconds
Started Dec 24 12:33:07 PM PST 23
Finished Dec 24 12:33:53 PM PST 23
Peak memory 237540 kb
Host smart-c5ecf377-6e37-49cf-bd2e-6e11d5c2f3f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331972222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3331972222
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.325088191
Short name T26
Test name
Test status
Simulation time 126183272 ps
CPU time 5.22 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:33:17 PM PST 23
Peak memory 238452 kb
Host smart-a74b99d6-cd32-4242-bcc8-56894b4e7036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=325088191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.325088191
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2800694493
Short name T768
Test name
Test status
Simulation time 13351858 ps
CPU time 1.33 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 234544 kb
Host smart-5f38ce1e-7142-4c01-9aef-40931e7e9908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2800694493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2800694493
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3916421268
Short name T774
Test name
Test status
Simulation time 91765741 ps
CPU time 11.21 seconds
Started Dec 24 12:33:04 PM PST 23
Finished Dec 24 12:33:56 PM PST 23
Peak memory 244336 kb
Host smart-ece6ef50-2aac-4409-95da-a152761af88f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3916421268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3916421268
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1037735364
Short name T155
Test name
Test status
Simulation time 21845408950 ps
CPU time 179.06 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:36:11 PM PST 23
Peak memory 271320 kb
Host smart-5da3013a-cc1f-4c9b-a793-ea99268ac12b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1037735364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1037735364
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3386110927
Short name T761
Test name
Test status
Simulation time 1119829226 ps
CPU time 18.84 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 248672 kb
Host smart-8d6da1e6-0ae7-4de2-b403-67e90e5c47b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3386110927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3386110927
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3942219155
Short name T824
Test name
Test status
Simulation time 42357661 ps
CPU time 2.95 seconds
Started Dec 24 12:33:14 PM PST 23
Finished Dec 24 12:33:56 PM PST 23
Peak memory 235484 kb
Host smart-1fdb8e39-3a55-4654-8167-07e8a7654d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3942219155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3942219155
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2673686847
Short name T24
Test name
Test status
Simulation time 113855315 ps
CPU time 6.25 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:33:18 PM PST 23
Peak memory 251748 kb
Host smart-ac600e65-5c65-444a-9633-d940dfac3c9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673686847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2673686847
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1824830496
Short name T788
Test name
Test status
Simulation time 49479961 ps
CPU time 4.27 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:42 PM PST 23
Peak memory 236256 kb
Host smart-e0972442-6315-4640-a6c3-105a0024d9fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1824830496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1824830496
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1760566525
Short name T810
Test name
Test status
Simulation time 11886272 ps
CPU time 1.25 seconds
Started Dec 24 12:32:47 PM PST 23
Finished Dec 24 12:33:16 PM PST 23
Peak memory 236392 kb
Host smart-87c39649-4043-4acf-9865-c94f60bb136f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1760566525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1760566525
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1110389934
Short name T754
Test name
Test status
Simulation time 332335361 ps
CPU time 21.39 seconds
Started Dec 24 12:32:52 PM PST 23
Finished Dec 24 12:33:51 PM PST 23
Peak memory 240612 kb
Host smart-d12813dd-d7b9-408d-9c3c-538233b82609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1110389934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1110389934
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1041907274
Short name T152
Test name
Test status
Simulation time 3493042159 ps
CPU time 195.37 seconds
Started Dec 24 12:32:53 PM PST 23
Finished Dec 24 12:36:47 PM PST 23
Peak memory 265468 kb
Host smart-982b44f0-8e5e-4b9c-af65-25288a0a1c42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1041907274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1041907274
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1012284174
Short name T809
Test name
Test status
Simulation time 35179647 ps
CPU time 2.7 seconds
Started Dec 24 12:32:38 PM PST 23
Finished Dec 24 12:33:14 PM PST 23
Peak memory 240432 kb
Host smart-3109b138-92dc-4241-80f7-8a0aba0dfbd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1012284174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1012284174
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2731511338
Short name T822
Test name
Test status
Simulation time 161131107 ps
CPU time 3.45 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:40 PM PST 23
Peak memory 238356 kb
Host smart-5d8e4529-955d-4052-a1b5-26d3ed959c10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731511338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2731511338
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4202019956
Short name T837
Test name
Test status
Simulation time 36213198 ps
CPU time 4.48 seconds
Started Dec 24 12:32:35 PM PST 23
Finished Dec 24 12:33:05 PM PST 23
Peak memory 240276 kb
Host smart-7a64a3d5-d3d2-4229-8314-bf2af2d1f339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4202019956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4202019956
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3668042821
Short name T765
Test name
Test status
Simulation time 16444374 ps
CPU time 1.31 seconds
Started Dec 24 12:33:28 PM PST 23
Finished Dec 24 12:34:10 PM PST 23
Peak memory 236484 kb
Host smart-2a30c754-8a23-4eb5-b951-0c9f030f1c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3668042821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3668042821
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1811314429
Short name T843
Test name
Test status
Simulation time 524318346 ps
CPU time 35.4 seconds
Started Dec 24 12:32:57 PM PST 23
Finished Dec 24 12:34:13 PM PST 23
Peak memory 244664 kb
Host smart-88660268-8c47-4538-96a4-c272aa9d1388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811314429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1811314429
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.481495338
Short name T138
Test name
Test status
Simulation time 5221155345 ps
CPU time 311.34 seconds
Started Dec 24 12:32:35 PM PST 23
Finished Dec 24 12:38:12 PM PST 23
Peak memory 265244 kb
Host smart-51c2c455-5e99-49e7-9c00-97ee9f73ea2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=481495338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.481495338
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.909418766
Short name T328
Test name
Test status
Simulation time 17555235612 ps
CPU time 1111.01 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:51:57 PM PST 23
Peak memory 273080 kb
Host smart-236c0305-f951-431a-b02e-5c492b9cf2ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909418766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.909418766
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2686968787
Short name T732
Test name
Test status
Simulation time 247630182 ps
CPU time 9.27 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:35 PM PST 23
Peak memory 248320 kb
Host smart-4ec60681-719f-4b49-bad5-593b041017b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2686968787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2686968787
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2554402539
Short name T811
Test name
Test status
Simulation time 78899991 ps
CPU time 7.07 seconds
Started Dec 24 12:33:07 PM PST 23
Finished Dec 24 12:33:56 PM PST 23
Peak memory 243456 kb
Host smart-cb9469b4-116f-4ecd-9d76-145c686d2e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554402539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2554402539
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3391261012
Short name T792
Test name
Test status
Simulation time 272596812 ps
CPU time 5.06 seconds
Started Dec 24 12:33:02 PM PST 23
Finished Dec 24 12:33:49 PM PST 23
Peak memory 236408 kb
Host smart-bb8d0260-3d71-48d4-bc47-1c352d608df2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3391261012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3391261012
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2279343724
Short name T790
Test name
Test status
Simulation time 7295753 ps
CPU time 1.46 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:28 PM PST 23
Peak memory 236368 kb
Host smart-e9b254e0-436d-4e62-9261-5cd7a3a3f03b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2279343724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2279343724
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2783867801
Short name T773
Test name
Test status
Simulation time 2038002060 ps
CPU time 35.59 seconds
Started Dec 24 12:32:54 PM PST 23
Finished Dec 24 12:34:11 PM PST 23
Peak memory 244536 kb
Host smart-0d770251-531c-4201-b778-cc59d45b16c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2783867801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2783867801
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3714092154
Short name T159
Test name
Test status
Simulation time 38424333089 ps
CPU time 562.27 seconds
Started Dec 24 12:32:55 PM PST 23
Finished Dec 24 12:42:58 PM PST 23
Peak memory 273008 kb
Host smart-e31b6baa-3e60-4656-baa0-975f01513fd3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714092154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3714092154
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2913890810
Short name T740
Test name
Test status
Simulation time 341974145 ps
CPU time 10.85 seconds
Started Dec 24 12:32:55 PM PST 23
Finished Dec 24 12:33:52 PM PST 23
Peak memory 248180 kb
Host smart-b11942c2-c9b4-4279-961e-0d7b1761e3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2913890810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2913890810
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1302041670
Short name T802
Test name
Test status
Simulation time 588353716 ps
CPU time 18.97 seconds
Started Dec 24 12:33:05 PM PST 23
Finished Dec 24 12:34:05 PM PST 23
Peak memory 239188 kb
Host smart-6294d19d-dbd9-4363-be44-74fbab19d554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1302041670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1302041670
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4092870510
Short name T189
Test name
Test status
Simulation time 256099875 ps
CPU time 6.33 seconds
Started Dec 24 12:33:03 PM PST 23
Finished Dec 24 12:33:51 PM PST 23
Peak memory 243520 kb
Host smart-2e9a28e5-b696-41ec-ab79-4be5bfc5853a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092870510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.4092870510
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1426403420
Short name T190
Test name
Test status
Simulation time 460386016 ps
CPU time 8.11 seconds
Started Dec 24 12:33:08 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 236432 kb
Host smart-914463e7-9375-46a9-b3b6-d7cd4c2eed24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1426403420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1426403420
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1539169249
Short name T750
Test name
Test status
Simulation time 8784098 ps
CPU time 1.39 seconds
Started Dec 24 12:32:49 PM PST 23
Finished Dec 24 12:33:19 PM PST 23
Peak memory 236476 kb
Host smart-6bf17d3c-7588-455f-8430-48915e24ea8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1539169249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1539169249
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3446830713
Short name T160
Test name
Test status
Simulation time 706472516 ps
CPU time 19.33 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:29 PM PST 23
Peak memory 248612 kb
Host smart-6f26eff1-c7c2-4b8b-b595-f5019c986f51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3446830713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3446830713
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.477874126
Short name T142
Test name
Test status
Simulation time 3606041073 ps
CPU time 96.75 seconds
Started Dec 24 12:33:08 PM PST 23
Finished Dec 24 12:35:26 PM PST 23
Peak memory 265276 kb
Host smart-e7c098b8-7c65-477d-b1a3-39d7c1773eaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=477874126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.477874126
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2652408795
Short name T168
Test name
Test status
Simulation time 5788360526 ps
CPU time 688.79 seconds
Started Dec 24 12:32:40 PM PST 23
Finished Dec 24 12:44:35 PM PST 23
Peak memory 265228 kb
Host smart-241b23e5-ea9a-43f8-ad1e-65af05247ca8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652408795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2652408795
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4259599489
Short name T173
Test name
Test status
Simulation time 139678188 ps
CPU time 9.08 seconds
Started Dec 24 12:32:49 PM PST 23
Finished Dec 24 12:33:30 PM PST 23
Peak memory 252204 kb
Host smart-b29c2985-68ec-4476-a692-6cae872cdc3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4259599489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4259599489
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.83543436
Short name T81
Test name
Test status
Simulation time 21627825755 ps
CPU time 1188.7 seconds
Started Dec 24 01:27:44 PM PST 23
Finished Dec 24 01:47:34 PM PST 23
Peak memory 271532 kb
Host smart-6021fb7a-8d57-464f-a248-bdf24fb272d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83543436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.83543436
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2677883217
Short name T226
Test name
Test status
Simulation time 358845241 ps
CPU time 18.94 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:28:02 PM PST 23
Peak memory 248632 kb
Host smart-d5eab91f-f69a-45fd-8b6e-defc24f958d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2677883217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2677883217
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1746432734
Short name T579
Test name
Test status
Simulation time 3163276558 ps
CPU time 118.96 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:29:42 PM PST 23
Peak memory 256284 kb
Host smart-79412624-af77-4381-825f-f1c63e2afe2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17464
32734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1746432734
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2832474329
Short name T515
Test name
Test status
Simulation time 246664167 ps
CPU time 3.85 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:27:47 PM PST 23
Peak memory 250108 kb
Host smart-4ff218a2-275d-4cce-92f9-9654c63ef717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28324
74329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2832474329
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2751660690
Short name T400
Test name
Test status
Simulation time 188899384709 ps
CPU time 2731.86 seconds
Started Dec 24 01:27:44 PM PST 23
Finished Dec 24 02:13:17 PM PST 23
Peak memory 289036 kb
Host smart-96bfac9d-c97a-4c3c-aa70-e993482fc5b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751660690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2751660690
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1494331856
Short name T667
Test name
Test status
Simulation time 1909317688 ps
CPU time 84.26 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:29:06 PM PST 23
Peak memory 247156 kb
Host smart-da5e28d1-c90e-433c-8968-58f788b27c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494331856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1494331856
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1913690656
Short name T421
Test name
Test status
Simulation time 1043884649 ps
CPU time 30.98 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:28:13 PM PST 23
Peak memory 248512 kb
Host smart-3224e501-0af2-45c5-99d0-88ae4b1f6933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19136
90656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1913690656
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2198739090
Short name T659
Test name
Test status
Simulation time 10992404558 ps
CPU time 45.66 seconds
Started Dec 24 01:27:43 PM PST 23
Finished Dec 24 01:28:30 PM PST 23
Peak memory 253420 kb
Host smart-ab3455db-17aa-44b6-af77-38c5262e4600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21987
39090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2198739090
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3159503156
Short name T701
Test name
Test status
Simulation time 942191095 ps
CPU time 58.74 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:28:41 PM PST 23
Peak memory 255216 kb
Host smart-a32a7272-2d7c-4d18-b5d4-568ffb28cfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31595
03156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3159503156
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2415031884
Short name T595
Test name
Test status
Simulation time 1391783418 ps
CPU time 29.03 seconds
Started Dec 24 01:27:41 PM PST 23
Finished Dec 24 01:28:11 PM PST 23
Peak memory 248552 kb
Host smart-7932edf1-2168-4630-adf1-4534650cfc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24150
31884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2415031884
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4077652867
Short name T289
Test name
Test status
Simulation time 880089043 ps
CPU time 86.21 seconds
Started Dec 24 01:27:42 PM PST 23
Finished Dec 24 01:29:10 PM PST 23
Peak memory 249680 kb
Host smart-eb4b482f-762a-428b-8dc6-2e965bb09332
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077652867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4077652867
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1288586887
Short name T290
Test name
Test status
Simulation time 44098973124 ps
CPU time 2689.97 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 02:13:10 PM PST 23
Peak memory 273108 kb
Host smart-9d9e33cb-b5f1-4a2d-99e9-c9656c1767a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288586887 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1288586887
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3145059364
Short name T227
Test name
Test status
Simulation time 22783898501 ps
CPU time 1262.58 seconds
Started Dec 24 01:28:11 PM PST 23
Finished Dec 24 01:49:23 PM PST 23
Peak memory 288664 kb
Host smart-f7569bef-8cf5-4daa-aea0-b7dc9a9e8331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145059364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3145059364
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.941390146
Short name T569
Test name
Test status
Simulation time 1079951829 ps
CPU time 47.73 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:29:04 PM PST 23
Peak memory 240464 kb
Host smart-d052c255-d36a-4ff1-bf2c-5c76f4d04b13
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=941390146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.941390146
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3949673374
Short name T410
Test name
Test status
Simulation time 456790144 ps
CPU time 14.07 seconds
Started Dec 24 01:27:56 PM PST 23
Finished Dec 24 01:28:11 PM PST 23
Peak memory 255536 kb
Host smart-8d981449-db8b-4c77-a585-1a6cefaf614f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496
73374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3949673374
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.221414998
Short name T437
Test name
Test status
Simulation time 778346856 ps
CPU time 20.44 seconds
Started Dec 24 01:27:55 PM PST 23
Finished Dec 24 01:28:16 PM PST 23
Peak memory 255148 kb
Host smart-075e4f2d-297b-44d9-b427-00e30871040e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22141
4998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.221414998
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1121736767
Short name T704
Test name
Test status
Simulation time 32297680926 ps
CPU time 796.81 seconds
Started Dec 24 01:28:07 PM PST 23
Finished Dec 24 01:41:33 PM PST 23
Peak memory 273140 kb
Host smart-b5f4cd0e-77fb-452d-971b-524fd7a3dafa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121736767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1121736767
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2520022622
Short name T496
Test name
Test status
Simulation time 30560569928 ps
CPU time 838.61 seconds
Started Dec 24 01:27:56 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 269196 kb
Host smart-59e1dc3b-0b87-4819-a331-129f4738e320
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520022622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2520022622
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1571387483
Short name T281
Test name
Test status
Simulation time 8071238005 ps
CPU time 156.05 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 01:30:56 PM PST 23
Peak memory 246340 kb
Host smart-6b7278e8-2f05-43b8-a23d-368a3c7b245a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571387483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1571387483
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3714017185
Short name T391
Test name
Test status
Simulation time 290401036 ps
CPU time 14.31 seconds
Started Dec 24 01:28:07 PM PST 23
Finished Dec 24 01:28:30 PM PST 23
Peak memory 248640 kb
Host smart-44abb999-9f9f-4d5e-85ae-663be3991931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37140
17185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3714017185
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.982213057
Short name T567
Test name
Test status
Simulation time 55604051 ps
CPU time 4.48 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 01:28:02 PM PST 23
Peak memory 238868 kb
Host smart-e5fea561-a803-4968-8c9a-5b2119553772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98221
3057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.982213057
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3141941783
Short name T47
Test name
Test status
Simulation time 3021778902 ps
CPU time 124.77 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:30:20 PM PST 23
Peak memory 276268 kb
Host smart-cd25221d-04e2-4f42-98fc-704866981509
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3141941783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3141941783
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1137904265
Short name T336
Test name
Test status
Simulation time 1092238173 ps
CPU time 12.33 seconds
Started Dec 24 01:27:56 PM PST 23
Finished Dec 24 01:28:10 PM PST 23
Peak memory 248612 kb
Host smart-5307e18b-dc82-4095-acee-a734ffb3551b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379
04265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1137904265
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1409341138
Short name T624
Test name
Test status
Simulation time 107868985 ps
CPU time 4.33 seconds
Started Dec 24 01:28:12 PM PST 23
Finished Dec 24 01:28:25 PM PST 23
Peak memory 240396 kb
Host smart-45f899bd-f2d0-4bec-912d-d87053e28934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14093
41138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1409341138
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.534086827
Short name T557
Test name
Test status
Simulation time 144127364861 ps
CPU time 2187.99 seconds
Started Dec 24 01:28:07 PM PST 23
Finished Dec 24 02:04:44 PM PST 23
Peak memory 282040 kb
Host smart-6ede2033-0b20-47bc-a8f0-a50f0d4f78e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534086827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.534086827
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2977458162
Short name T450
Test name
Test status
Simulation time 162556095947 ps
CPU time 3351.88 seconds
Started Dec 24 01:27:53 PM PST 23
Finished Dec 24 02:23:46 PM PST 23
Peak memory 320776 kb
Host smart-21c40101-9f24-4347-83fc-686417d06791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977458162 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2977458162
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3080751579
Short name T368
Test name
Test status
Simulation time 10463013929 ps
CPU time 1136.46 seconds
Started Dec 24 01:28:39 PM PST 23
Finished Dec 24 01:47:37 PM PST 23
Peak memory 289360 kb
Host smart-439ca255-540f-4098-8508-d9c4d76a6b1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080751579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3080751579
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2896747495
Short name T371
Test name
Test status
Simulation time 763201323 ps
CPU time 19.74 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 01:28:59 PM PST 23
Peak memory 240408 kb
Host smart-4c8c2a42-ffcf-4eaa-acec-5092c7c87c1b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2896747495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2896747495
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1537343916
Short name T651
Test name
Test status
Simulation time 31057977274 ps
CPU time 153.77 seconds
Started Dec 24 01:28:37 PM PST 23
Finished Dec 24 01:31:12 PM PST 23
Peak memory 247948 kb
Host smart-cf1ff262-e5be-46ae-a7e3-2cb80c9263c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15373
43916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1537343916
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2248937171
Short name T31
Test name
Test status
Simulation time 51032159 ps
CPU time 2.72 seconds
Started Dec 24 01:28:40 PM PST 23
Finished Dec 24 01:28:44 PM PST 23
Peak memory 238772 kb
Host smart-6337f03c-5e50-4107-a611-472d12026056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
37171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2248937171
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2650727251
Short name T375
Test name
Test status
Simulation time 110641032916 ps
CPU time 1529.31 seconds
Started Dec 24 01:28:36 PM PST 23
Finished Dec 24 01:54:06 PM PST 23
Peak memory 272356 kb
Host smart-31df172f-bb2e-4edc-a40d-e85d577e1371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650727251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2650727251
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3383931296
Short name T284
Test name
Test status
Simulation time 16048818815 ps
CPU time 657.15 seconds
Started Dec 24 01:28:39 PM PST 23
Finished Dec 24 01:39:38 PM PST 23
Peak memory 247572 kb
Host smart-656c8580-9710-4bb3-8cfb-4a4609cba07e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383931296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3383931296
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1342610775
Short name T337
Test name
Test status
Simulation time 736890251 ps
CPU time 45.17 seconds
Started Dec 24 01:28:43 PM PST 23
Finished Dec 24 01:29:30 PM PST 23
Peak memory 248536 kb
Host smart-12097c24-952d-47e0-a315-ea2bda1938d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13426
10775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1342610775
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1755914729
Short name T462
Test name
Test status
Simulation time 595299986 ps
CPU time 34.38 seconds
Started Dec 24 01:28:41 PM PST 23
Finished Dec 24 01:29:17 PM PST 23
Peak memory 253716 kb
Host smart-d92c0841-9ddd-45ad-ba39-6bf646f6bbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17559
14729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1755914729
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.448486221
Short name T439
Test name
Test status
Simulation time 2190712662 ps
CPU time 64.73 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 01:29:45 PM PST 23
Peak memory 254608 kb
Host smart-a5c6c42a-0fb9-4e55-bddb-27aa3f3a89c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44848
6221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.448486221
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1503328333
Short name T634
Test name
Test status
Simulation time 4376807534 ps
CPU time 15.55 seconds
Started Dec 24 01:28:42 PM PST 23
Finished Dec 24 01:28:58 PM PST 23
Peak memory 248664 kb
Host smart-904be024-832d-465f-9acf-9cfd7b769265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15033
28333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1503328333
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4245481799
Short name T345
Test name
Test status
Simulation time 333337352 ps
CPU time 45.61 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 01:29:25 PM PST 23
Peak memory 256796 kb
Host smart-c9b5eb5c-964e-4b8c-8560-5f8ee841ddf4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245481799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4245481799
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.206097572
Short name T394
Test name
Test status
Simulation time 160376101000 ps
CPU time 2468.25 seconds
Started Dec 24 01:28:37 PM PST 23
Finished Dec 24 02:09:47 PM PST 23
Peak memory 281472 kb
Host smart-5a309548-f738-4867-b285-06d3aed8d643
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206097572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.206097572
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1821238032
Short name T687
Test name
Test status
Simulation time 4597152829 ps
CPU time 33.93 seconds
Started Dec 24 01:28:40 PM PST 23
Finished Dec 24 01:29:16 PM PST 23
Peak memory 240512 kb
Host smart-1ac31897-401f-4942-a594-8a5aef262e63
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1821238032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1821238032
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2336308800
Short name T573
Test name
Test status
Simulation time 555622813 ps
CPU time 32.22 seconds
Started Dec 24 01:28:39 PM PST 23
Finished Dec 24 01:29:12 PM PST 23
Peak memory 256044 kb
Host smart-b4b0f9dd-2c95-4f9c-8e50-bda24048ba24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23363
08800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2336308800
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3602743784
Short name T699
Test name
Test status
Simulation time 247757309 ps
CPU time 13.73 seconds
Started Dec 24 01:28:41 PM PST 23
Finished Dec 24 01:28:56 PM PST 23
Peak memory 248692 kb
Host smart-e260ab99-2938-4d5f-b644-194ffc58436d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36027
43784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3602743784
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1169629412
Short name T535
Test name
Test status
Simulation time 36279578012 ps
CPU time 1920.37 seconds
Started Dec 24 01:28:43 PM PST 23
Finished Dec 24 02:00:45 PM PST 23
Peak memory 272216 kb
Host smart-a36b64e3-cdd4-4993-8b91-520dd0b089e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169629412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1169629412
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2618748767
Short name T217
Test name
Test status
Simulation time 37756160562 ps
CPU time 416.24 seconds
Started Dec 24 01:28:39 PM PST 23
Finished Dec 24 01:35:37 PM PST 23
Peak memory 247452 kb
Host smart-1b08ba56-8d75-40cb-9325-7e9d16379789
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618748767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2618748767
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2314265863
Short name T620
Test name
Test status
Simulation time 12300659971 ps
CPU time 43.1 seconds
Started Dec 24 01:28:40 PM PST 23
Finished Dec 24 01:29:25 PM PST 23
Peak memory 248672 kb
Host smart-56c4b7e6-30aa-4dda-af1b-f826337334e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23142
65863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2314265863
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.914863881
Short name T603
Test name
Test status
Simulation time 1070319053 ps
CPU time 63.04 seconds
Started Dec 24 01:28:37 PM PST 23
Finished Dec 24 01:29:41 PM PST 23
Peak memory 255380 kb
Host smart-3a051f1c-bd45-4605-bdf7-2a2328da5c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91486
3881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.914863881
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3569913578
Short name T245
Test name
Test status
Simulation time 2234396451 ps
CPU time 41.76 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 01:29:21 PM PST 23
Peak memory 254544 kb
Host smart-feaeb60b-2689-44fc-b8c4-50f22ae7feed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
13578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3569913578
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1912776678
Short name T675
Test name
Test status
Simulation time 43019108 ps
CPU time 3.87 seconds
Started Dec 24 01:28:42 PM PST 23
Finished Dec 24 01:28:47 PM PST 23
Peak memory 240320 kb
Host smart-a4b8c99e-5bc0-4e81-8aa3-cfd4f257e352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19127
76678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1912776678
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.4183068460
Short name T76
Test name
Test status
Simulation time 94750259413 ps
CPU time 1454.35 seconds
Started Dec 24 01:28:36 PM PST 23
Finished Dec 24 01:52:52 PM PST 23
Peak memory 273312 kb
Host smart-5752fd7c-3fae-47b0-9963-91d93864a176
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183068460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.4183068460
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.930360418
Short name T305
Test name
Test status
Simulation time 21499364788 ps
CPU time 1586.71 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 288900 kb
Host smart-9cc4206b-8936-4743-8d16-be7bdd3d778a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930360418 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.930360418
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1956710307
Short name T212
Test name
Test status
Simulation time 129355990 ps
CPU time 3.2 seconds
Started Dec 24 01:29:12 PM PST 23
Finished Dec 24 01:29:17 PM PST 23
Peak memory 248880 kb
Host smart-dd300882-d910-4b7f-bf86-6018f835dac1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1956710307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1956710307
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1894614373
Short name T88
Test name
Test status
Simulation time 44005868599 ps
CPU time 1201.42 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:49:17 PM PST 23
Peak memory 281476 kb
Host smart-967dfd5f-ba76-41d2-9c4f-771d6dde811f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894614373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1894614373
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.684105430
Short name T341
Test name
Test status
Simulation time 135180395 ps
CPU time 8.77 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:29:24 PM PST 23
Peak memory 240412 kb
Host smart-a9c2d4b2-a36c-4b7b-865e-c04c31c6ecb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=684105430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.684105430
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1127069268
Short name T473
Test name
Test status
Simulation time 4389187474 ps
CPU time 71.73 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:30:28 PM PST 23
Peak memory 255860 kb
Host smart-8a790299-5c5f-4fb1-8567-6286a4a03aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
69268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1127069268
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4024919465
Short name T477
Test name
Test status
Simulation time 275474256 ps
CPU time 23.68 seconds
Started Dec 24 01:29:08 PM PST 23
Finished Dec 24 01:29:35 PM PST 23
Peak memory 254920 kb
Host smart-f6bb31bd-6248-4fd2-acff-6567b0be872b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40249
19465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4024919465
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2938118499
Short name T678
Test name
Test status
Simulation time 20153204456 ps
CPU time 1297.06 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:50:52 PM PST 23
Peak memory 265080 kb
Host smart-ad810667-7c61-4347-b9a7-fc3436eb80ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938118499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2938118499
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2284136633
Short name T549
Test name
Test status
Simulation time 25273206222 ps
CPU time 1106.58 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:47:41 PM PST 23
Peak memory 270512 kb
Host smart-712330cc-e3ee-4f7e-9f75-5bcb5694ed8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284136633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2284136633
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.332604983
Short name T635
Test name
Test status
Simulation time 22609260555 ps
CPU time 194.53 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:32:30 PM PST 23
Peak memory 247440 kb
Host smart-3a6f8f7e-16d7-4b64-94ca-ba5a4a616c2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332604983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.332604983
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3113389812
Short name T355
Test name
Test status
Simulation time 5691000059 ps
CPU time 63.71 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:30:19 PM PST 23
Peak memory 248872 kb
Host smart-09d78776-9560-4703-83d9-491223e480bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31133
89812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3113389812
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.765390982
Short name T115
Test name
Test status
Simulation time 2581072825 ps
CPU time 43.51 seconds
Started Dec 24 01:29:12 PM PST 23
Finished Dec 24 01:29:57 PM PST 23
Peak memory 254700 kb
Host smart-99b6da6b-3947-4998-8a19-bc10f8d1d5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76539
0982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.765390982
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3396380204
Short name T720
Test name
Test status
Simulation time 1843702867 ps
CPU time 27.78 seconds
Started Dec 24 01:29:08 PM PST 23
Finished Dec 24 01:29:39 PM PST 23
Peak memory 255096 kb
Host smart-844ed7ea-0834-4c11-a311-206a46532b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
80204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3396380204
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1895089597
Short name T54
Test name
Test status
Simulation time 3251823570 ps
CPU time 54.59 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:30:09 PM PST 23
Peak memory 248612 kb
Host smart-3206c837-0053-4e2c-a2f0-eb47cedc6043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18950
89597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1895089597
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2788983112
Short name T233
Test name
Test status
Simulation time 24984502435 ps
CPU time 2543.72 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 02:11:39 PM PST 23
Peak memory 305272 kb
Host smart-b21cb9ca-c511-4861-8db5-969935798eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788983112 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2788983112
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.903983993
Short name T197
Test name
Test status
Simulation time 130583454 ps
CPU time 2.37 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:29:18 PM PST 23
Peak memory 248920 kb
Host smart-7b9851da-fdfb-4d46-8679-c34da4788ba4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=903983993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.903983993
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.730620535
Short name T397
Test name
Test status
Simulation time 38917656024 ps
CPU time 2307.29 seconds
Started Dec 24 01:29:04 PM PST 23
Finished Dec 24 02:07:35 PM PST 23
Peak memory 273228 kb
Host smart-0a47cdc9-3de6-40b4-844c-d693977f39e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730620535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.730620535
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1945072945
Short name T416
Test name
Test status
Simulation time 4630625555 ps
CPU time 48.64 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:30:03 PM PST 23
Peak memory 248708 kb
Host smart-9e69db2e-fa39-414e-aefe-986e2e4ff978
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1945072945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1945072945
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2646128544
Short name T382
Test name
Test status
Simulation time 2724158875 ps
CPU time 48.52 seconds
Started Dec 24 01:29:12 PM PST 23
Finished Dec 24 01:30:02 PM PST 23
Peak memory 248108 kb
Host smart-2a391bc6-2130-4ff5-8bfd-54c42c2ff138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26461
28544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2646128544
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.307723789
Short name T542
Test name
Test status
Simulation time 1093922113 ps
CPU time 34.66 seconds
Started Dec 24 01:29:06 PM PST 23
Finished Dec 24 01:29:43 PM PST 23
Peak memory 254520 kb
Host smart-9725932e-98dd-48bb-86fe-b69a364f63e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30772
3789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.307723789
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1365739168
Short name T220
Test name
Test status
Simulation time 22701283701 ps
CPU time 1645.9 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:56:41 PM PST 23
Peak memory 272692 kb
Host smart-9e05c31b-1e82-4f82-b76a-28e2c038a207
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365739168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1365739168
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.299094891
Short name T641
Test name
Test status
Simulation time 8955537367 ps
CPU time 193.75 seconds
Started Dec 24 01:29:07 PM PST 23
Finished Dec 24 01:32:24 PM PST 23
Peak memory 247568 kb
Host smart-98b11889-9f67-4edd-a8f2-dc9315bc9d47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299094891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.299094891
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1623510557
Short name T372
Test name
Test status
Simulation time 2203926007 ps
CPU time 63.19 seconds
Started Dec 24 01:29:05 PM PST 23
Finished Dec 24 01:30:10 PM PST 23
Peak memory 248772 kb
Host smart-407dd4b7-b2da-4ffb-9077-f11ea3e0ac0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16235
10557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1623510557
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2767362668
Short name T68
Test name
Test status
Simulation time 1519108803 ps
CPU time 32.94 seconds
Started Dec 24 01:29:12 PM PST 23
Finished Dec 24 01:29:47 PM PST 23
Peak memory 254900 kb
Host smart-3099f8ae-8302-459d-afd2-d221efbd3af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
62668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2767362668
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1412504497
Short name T576
Test name
Test status
Simulation time 3021297209 ps
CPU time 13.87 seconds
Started Dec 24 01:29:17 PM PST 23
Finished Dec 24 01:29:32 PM PST 23
Peak memory 253772 kb
Host smart-01bfa197-d3da-403c-840d-15b6b3ff6d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14125
04497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1412504497
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3406702136
Short name T563
Test name
Test status
Simulation time 1792841950 ps
CPU time 28.06 seconds
Started Dec 24 01:29:12 PM PST 23
Finished Dec 24 01:29:41 PM PST 23
Peak memory 248604 kb
Host smart-e8bbe82b-100e-4281-be2f-49ccd37f5303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
02136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3406702136
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2422169537
Short name T53
Test name
Test status
Simulation time 71666768508 ps
CPU time 3827.04 seconds
Started Dec 24 01:29:06 PM PST 23
Finished Dec 24 02:32:57 PM PST 23
Peak memory 305384 kb
Host smart-a1a5cc0b-4290-4c2a-8f6d-cdc1606c4792
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422169537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2422169537
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3862373685
Short name T121
Test name
Test status
Simulation time 23792381909 ps
CPU time 2015.1 seconds
Started Dec 24 01:29:05 PM PST 23
Finished Dec 24 02:02:43 PM PST 23
Peak memory 284620 kb
Host smart-8ddf240b-27da-4128-9aaf-69bf1e60c41b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862373685 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3862373685
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3550980990
Short name T202
Test name
Test status
Simulation time 34431051 ps
CPU time 2.77 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:29:17 PM PST 23
Peak memory 248828 kb
Host smart-be6fb027-27c2-45ff-a46a-1461bed8a3e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3550980990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3550980990
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1473749871
Short name T120
Test name
Test status
Simulation time 39146333756 ps
CPU time 2261.51 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 02:06:58 PM PST 23
Peak memory 283252 kb
Host smart-f373e05b-590f-4f90-8d3d-27638c568700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473749871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1473749871
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.726788683
Short name T530
Test name
Test status
Simulation time 174704418 ps
CPU time 11.09 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:29:26 PM PST 23
Peak memory 240452 kb
Host smart-dcd92e38-eb85-4031-a5e9-b445677a0ffb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=726788683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.726788683
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2102847600
Short name T214
Test name
Test status
Simulation time 12165865505 ps
CPU time 190.46 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:32:27 PM PST 23
Peak memory 256784 kb
Host smart-10fc2fd4-4011-4a30-8d91-44c08c33dbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21028
47600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2102847600
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2829225808
Short name T340
Test name
Test status
Simulation time 3573478612 ps
CPU time 42.47 seconds
Started Dec 24 01:29:11 PM PST 23
Finished Dec 24 01:29:55 PM PST 23
Peak memory 255856 kb
Host smart-cbad6984-f9b1-490e-b515-892ff8990117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292
25808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2829225808
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.194036528
Short name T262
Test name
Test status
Simulation time 10681250802 ps
CPU time 1127.66 seconds
Started Dec 24 01:29:12 PM PST 23
Finished Dec 24 01:48:01 PM PST 23
Peak memory 289096 kb
Host smart-3f433efc-c2a8-4d72-b0e6-aa80582e60b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194036528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.194036528
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2565007929
Short name T599
Test name
Test status
Simulation time 152498212149 ps
CPU time 2773.06 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 02:15:28 PM PST 23
Peak memory 288916 kb
Host smart-1ba6b1e7-dcda-429f-9e21-44cba2692343
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565007929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2565007929
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3911402554
Short name T8
Test name
Test status
Simulation time 24929203663 ps
CPU time 252.17 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:33:27 PM PST 23
Peak memory 246536 kb
Host smart-19e45bb8-4795-4060-8966-9c108d9650c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911402554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3911402554
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.446007248
Short name T702
Test name
Test status
Simulation time 327295635 ps
CPU time 30.57 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:29:45 PM PST 23
Peak memory 255016 kb
Host smart-93b51ff9-d158-4d16-aed2-577c502a51a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44600
7248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.446007248
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1293358012
Short name T652
Test name
Test status
Simulation time 1002632681 ps
CPU time 27.6 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:29:42 PM PST 23
Peak memory 255128 kb
Host smart-c3566c43-854c-4ac4-ac26-fadfab77bd6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12933
58012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1293358012
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2966778970
Short name T383
Test name
Test status
Simulation time 799440367 ps
CPU time 57.34 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:30:14 PM PST 23
Peak memory 248728 kb
Host smart-9cd540a4-6386-45f6-806a-fd269ba17074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29667
78970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2966778970
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.4013999814
Short name T249
Test name
Test status
Simulation time 20864944488 ps
CPU time 2224.1 seconds
Started Dec 24 01:29:11 PM PST 23
Finished Dec 24 02:06:17 PM PST 23
Peak memory 305344 kb
Host smart-981fa28b-a28b-40f8-956e-c6062795913d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013999814 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.4013999814
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1936687461
Short name T213
Test name
Test status
Simulation time 147483249 ps
CPU time 3.48 seconds
Started Dec 24 01:29:17 PM PST 23
Finished Dec 24 01:29:22 PM PST 23
Peak memory 248808 kb
Host smart-de576b8e-4c65-4355-8930-0922f2f69fbd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1936687461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1936687461
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3150358769
Short name T444
Test name
Test status
Simulation time 95554169302 ps
CPU time 721.43 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:41:16 PM PST 23
Peak memory 272140 kb
Host smart-38e169f6-c2dd-4e94-a685-654e063a3a68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150358769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3150358769
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1460509422
Short name T449
Test name
Test status
Simulation time 1054517841 ps
CPU time 47.45 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:30:03 PM PST 23
Peak memory 248640 kb
Host smart-57b31c67-dd0e-47d5-b19a-4ed352122fa5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1460509422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1460509422
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3722777966
Short name T446
Test name
Test status
Simulation time 1311482281 ps
CPU time 101.68 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:30:56 PM PST 23
Peak memory 256392 kb
Host smart-96a78539-45af-4c07-ac3d-9404606b9d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37227
77966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3722777966
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3782745029
Short name T511
Test name
Test status
Simulation time 3379679891 ps
CPU time 52.29 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:30:07 PM PST 23
Peak memory 254476 kb
Host smart-3578f19c-5ed9-457e-a7e6-9f027f1a67e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37827
45029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3782745029
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.974053793
Short name T555
Test name
Test status
Simulation time 13633319491 ps
CPU time 766.71 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 265088 kb
Host smart-acdd8a67-c939-4de4-aae4-a210e55910b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974053793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.974053793
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.825730454
Short name T38
Test name
Test status
Simulation time 12840813894 ps
CPU time 1212.6 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:49:27 PM PST 23
Peak memory 285888 kb
Host smart-1d2bbfa7-6f5a-476f-98da-6f1a9884d436
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825730454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.825730454
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1262367230
Short name T455
Test name
Test status
Simulation time 78840889 ps
CPU time 3.52 seconds
Started Dec 24 01:29:13 PM PST 23
Finished Dec 24 01:29:18 PM PST 23
Peak memory 240468 kb
Host smart-3a7a673c-43a4-42f4-9148-6e8de9c42c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
67230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1262367230
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2984283676
Short name T655
Test name
Test status
Simulation time 567930182 ps
CPU time 29.8 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:29:46 PM PST 23
Peak memory 248708 kb
Host smart-0ad79b2f-22d7-47a3-a682-4f9a496915de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29842
83676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2984283676
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2581145409
Short name T379
Test name
Test status
Simulation time 1070174968 ps
CPU time 5.54 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:29:21 PM PST 23
Peak memory 240480 kb
Host smart-9acdce64-372f-4f44-ba17-8ab28a99ae58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25811
45409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2581145409
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1404758946
Short name T584
Test name
Test status
Simulation time 429863377 ps
CPU time 14.34 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:29:31 PM PST 23
Peak memory 254820 kb
Host smart-59e42c08-8c0d-4568-b374-c6c74c778a65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404758946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1404758946
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3460799752
Short name T210
Test name
Test status
Simulation time 83440083 ps
CPU time 3.73 seconds
Started Dec 24 01:29:18 PM PST 23
Finished Dec 24 01:29:23 PM PST 23
Peak memory 248864 kb
Host smart-722c0347-4faf-4814-880d-9c742a66a72b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3460799752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3460799752
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4142904146
Short name T113
Test name
Test status
Simulation time 25692923137 ps
CPU time 1443.72 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 289508 kb
Host smart-1c040217-4011-41a6-9f67-7abe13dce575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142904146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4142904146
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1119030366
Short name T15
Test name
Test status
Simulation time 3306208724 ps
CPU time 72.27 seconds
Started Dec 24 01:29:18 PM PST 23
Finished Dec 24 01:30:32 PM PST 23
Peak memory 240408 kb
Host smart-8ee6325d-6c78-47c1-ab17-681b5e8ae51b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1119030366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1119030366
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1320928219
Short name T91
Test name
Test status
Simulation time 4428163889 ps
CPU time 114.98 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:31:11 PM PST 23
Peak memory 256748 kb
Host smart-2f014ce4-b2f7-4ed5-b589-95e2126bedd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
28219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1320928219
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2053137252
Short name T445
Test name
Test status
Simulation time 671206195 ps
CPU time 32.99 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 01:29:50 PM PST 23
Peak memory 247536 kb
Host smart-dd44c9af-509f-464b-9182-5344198cbf5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20531
37252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2053137252
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2170545579
Short name T522
Test name
Test status
Simulation time 199766778335 ps
CPU time 1605.94 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 01:56:03 PM PST 23
Peak memory 272188 kb
Host smart-940d857f-0e92-4899-a014-ce2bfa7e2c68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170545579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2170545579
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4013492841
Short name T363
Test name
Test status
Simulation time 63485977038 ps
CPU time 1563.15 seconds
Started Dec 24 01:29:17 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 289104 kb
Host smart-e7bde225-5817-4568-b9ed-e92cb8167350
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013492841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4013492841
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3643421005
Short name T596
Test name
Test status
Simulation time 10114180906 ps
CPU time 410.07 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:36:07 PM PST 23
Peak memory 248712 kb
Host smart-03e1939d-7886-4662-ab20-6f8aac0779d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643421005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3643421005
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1515171802
Short name T676
Test name
Test status
Simulation time 278727693 ps
CPU time 9 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:29:25 PM PST 23
Peak memory 254080 kb
Host smart-b5d29a5a-a936-4e1e-800b-6ed805a26387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151
71802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1515171802
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2957497873
Short name T43
Test name
Test status
Simulation time 1821955351 ps
CPU time 54.44 seconds
Started Dec 24 01:29:14 PM PST 23
Finished Dec 24 01:30:10 PM PST 23
Peak memory 247252 kb
Host smart-fa92d2bd-9b97-4127-bd34-917409c275a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574
97873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2957497873
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3106094846
Short name T665
Test name
Test status
Simulation time 630581042 ps
CPU time 36.24 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 01:29:54 PM PST 23
Peak memory 255852 kb
Host smart-85850796-4329-4c9f-9386-265076459ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31060
94846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3106094846
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2153423926
Short name T640
Test name
Test status
Simulation time 279878505 ps
CPU time 28.66 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:29:45 PM PST 23
Peak memory 248564 kb
Host smart-a002c5e8-fff1-4a05-9312-4e2680270c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21534
23926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2153423926
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2414237208
Short name T448
Test name
Test status
Simulation time 10443022779 ps
CPU time 988.96 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:45:46 PM PST 23
Peak memory 284156 kb
Host smart-07f8c6a5-b8d3-4bd8-a918-41ddf8ad682d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414237208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2414237208
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.483934337
Short name T206
Test name
Test status
Simulation time 44486356 ps
CPU time 3.62 seconds
Started Dec 24 01:29:20 PM PST 23
Finished Dec 24 01:29:25 PM PST 23
Peak memory 248868 kb
Host smart-71ca4921-1ed1-415b-89b0-d0777f88a9c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=483934337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.483934337
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3882120751
Short name T691
Test name
Test status
Simulation time 45984319044 ps
CPU time 1282.57 seconds
Started Dec 24 01:29:23 PM PST 23
Finished Dec 24 01:50:47 PM PST 23
Peak memory 289332 kb
Host smart-6dcd148e-5dc2-4f79-a430-4c4f7c877e0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882120751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3882120751
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.292889087
Short name T395
Test name
Test status
Simulation time 223484208 ps
CPU time 12.45 seconds
Started Dec 24 01:29:20 PM PST 23
Finished Dec 24 01:29:34 PM PST 23
Peak memory 240456 kb
Host smart-d510b069-f94b-47ac-b027-3b2181ff5f90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=292889087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.292889087
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2235890022
Short name T45
Test name
Test status
Simulation time 1657233574 ps
CPU time 80.36 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 01:30:38 PM PST 23
Peak memory 248008 kb
Host smart-35f7e081-65ea-42e4-801a-ea09ff9c3a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22358
90022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2235890022
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3699275520
Short name T703
Test name
Test status
Simulation time 852939185 ps
CPU time 48.96 seconds
Started Dec 24 01:29:19 PM PST 23
Finished Dec 24 01:30:09 PM PST 23
Peak memory 248360 kb
Host smart-922dd318-4628-407d-b6e4-d4e8a15fc367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36992
75520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3699275520
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.275937787
Short name T261
Test name
Test status
Simulation time 58524381093 ps
CPU time 1233.11 seconds
Started Dec 24 01:29:20 PM PST 23
Finished Dec 24 01:49:54 PM PST 23
Peak memory 272980 kb
Host smart-c1bb3dc8-b518-419e-8df1-997526071302
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275937787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.275937787
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3860809426
Short name T374
Test name
Test status
Simulation time 41791084218 ps
CPU time 2541.88 seconds
Started Dec 24 01:31:17 PM PST 23
Finished Dec 24 02:13:40 PM PST 23
Peak memory 289272 kb
Host smart-f587e30b-e699-4f87-a673-a2f4c9d060a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860809426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3860809426
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1800034867
Short name T433
Test name
Test status
Simulation time 5004315645 ps
CPU time 190.86 seconds
Started Dec 24 01:29:22 PM PST 23
Finished Dec 24 01:32:34 PM PST 23
Peak memory 247144 kb
Host smart-fa421e5b-a077-4019-8693-a058f379f5bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800034867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1800034867
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.129200714
Short name T714
Test name
Test status
Simulation time 309200370 ps
CPU time 25.49 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 01:29:43 PM PST 23
Peak memory 248644 kb
Host smart-68b697ed-3a95-4b6d-82ff-cfc03b8c7f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12920
0714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.129200714
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3944465249
Short name T606
Test name
Test status
Simulation time 255791484 ps
CPU time 15.96 seconds
Started Dec 24 01:29:22 PM PST 23
Finished Dec 24 01:29:39 PM PST 23
Peak memory 248016 kb
Host smart-eca18e70-d4ba-47bc-8bae-3c60392439cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
65249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3944465249
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2459656215
Short name T301
Test name
Test status
Simulation time 1872394362 ps
CPU time 29.88 seconds
Started Dec 24 01:29:18 PM PST 23
Finished Dec 24 01:29:50 PM PST 23
Peak memory 246888 kb
Host smart-1aa1e9db-2190-42b9-a6e2-94d96b67142f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24596
56215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2459656215
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2779939389
Short name T377
Test name
Test status
Simulation time 512119338 ps
CPU time 30.13 seconds
Started Dec 24 01:29:15 PM PST 23
Finished Dec 24 01:29:47 PM PST 23
Peak memory 248712 kb
Host smart-344bd41b-54ae-4788-9a5e-d668016c9978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27799
39389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2779939389
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.9630609
Short name T628
Test name
Test status
Simulation time 25688350554 ps
CPU time 1223.03 seconds
Started Dec 24 01:29:22 PM PST 23
Finished Dec 24 01:49:47 PM PST 23
Peak memory 288448 kb
Host smart-95f64164-8de8-4ac0-8e22-78dc0b7dd581
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9630609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handl
er_stress_all.9630609
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1449025405
Short name T560
Test name
Test status
Simulation time 124545123886 ps
CPU time 1780.81 seconds
Started Dec 24 01:29:19 PM PST 23
Finished Dec 24 01:59:01 PM PST 23
Peak memory 286840 kb
Host smart-eba2ea35-cfb6-4fd5-9440-ce6e25d33a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449025405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1449025405
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2528125118
Short name T207
Test name
Test status
Simulation time 103380902 ps
CPU time 2.85 seconds
Started Dec 24 01:29:20 PM PST 23
Finished Dec 24 01:29:24 PM PST 23
Peak memory 248800 kb
Host smart-54311118-759d-42c2-92d5-6229b8612dc9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2528125118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2528125118
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1693630098
Short name T71
Test name
Test status
Simulation time 45056408549 ps
CPU time 2389.89 seconds
Started Dec 24 01:29:17 PM PST 23
Finished Dec 24 02:09:08 PM PST 23
Peak memory 289448 kb
Host smart-d96c2019-4b66-4884-9c7c-16d38ef99b97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693630098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1693630098
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1304453204
Short name T471
Test name
Test status
Simulation time 515144395 ps
CPU time 12.95 seconds
Started Dec 24 01:31:17 PM PST 23
Finished Dec 24 01:31:31 PM PST 23
Peak memory 248308 kb
Host smart-d3d7783e-7454-45ea-b994-29eca2458d47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1304453204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1304453204
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3465999765
Short name T440
Test name
Test status
Simulation time 4547347372 ps
CPU time 126.09 seconds
Started Dec 24 01:31:00 PM PST 23
Finished Dec 24 01:33:15 PM PST 23
Peak memory 253924 kb
Host smart-d137f677-efc5-42bb-af31-5c62162944ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34659
99765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3465999765
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1815354253
Short name T338
Test name
Test status
Simulation time 330669090 ps
CPU time 29.69 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 01:29:52 PM PST 23
Peak memory 256092 kb
Host smart-a5886bea-c9c4-4d74-9b6f-778c6df83843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18153
54253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1815354253
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3131914666
Short name T722
Test name
Test status
Simulation time 25725600989 ps
CPU time 1315.69 seconds
Started Dec 24 01:31:17 PM PST 23
Finished Dec 24 01:53:14 PM PST 23
Peak memory 265868 kb
Host smart-16eb8b5e-3fef-4ac1-9d7c-051c19a89cc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131914666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3131914666
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1023395896
Short name T508
Test name
Test status
Simulation time 71433114516 ps
CPU time 314.49 seconds
Started Dec 24 01:29:23 PM PST 23
Finished Dec 24 01:34:38 PM PST 23
Peak memory 247444 kb
Host smart-2acea10a-ae0a-40ad-914a-5a00b332d3c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023395896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1023395896
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1756742638
Short name T442
Test name
Test status
Simulation time 1133669016 ps
CPU time 36.84 seconds
Started Dec 24 01:29:22 PM PST 23
Finished Dec 24 01:30:00 PM PST 23
Peak memory 248632 kb
Host smart-fbafe642-611a-46f7-a190-7b96a5c92a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17567
42638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1756742638
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4024988991
Short name T42
Test name
Test status
Simulation time 194108160 ps
CPU time 9.43 seconds
Started Dec 24 01:29:20 PM PST 23
Finished Dec 24 01:29:30 PM PST 23
Peak memory 251488 kb
Host smart-17095397-8a7f-4b51-a37f-72b4df29800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40249
88991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4024988991
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2350077794
Short name T57
Test name
Test status
Simulation time 295674569 ps
CPU time 31.81 seconds
Started Dec 24 01:29:20 PM PST 23
Finished Dec 24 01:29:52 PM PST 23
Peak memory 247924 kb
Host smart-3e3e7f46-7919-4943-939c-3b12cd88307b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23500
77794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2350077794
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.4076705299
Short name T602
Test name
Test status
Simulation time 395299260 ps
CPU time 22.87 seconds
Started Dec 24 01:29:16 PM PST 23
Finished Dec 24 01:29:41 PM PST 23
Peak memory 248472 kb
Host smart-5bf418dc-8d4c-48ae-b579-b72edc8fc6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
05299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.4076705299
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2222944836
Short name T591
Test name
Test status
Simulation time 79071355444 ps
CPU time 2230.81 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 02:06:34 PM PST 23
Peak memory 288940 kb
Host smart-fd5eb240-6de8-4159-8331-f19ab25c0a5d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222944836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2222944836
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.141445766
Short name T600
Test name
Test status
Simulation time 323396946028 ps
CPU time 1745.37 seconds
Started Dec 24 01:31:00 PM PST 23
Finished Dec 24 02:00:14 PM PST 23
Peak memory 280780 kb
Host smart-0e214d6c-4547-4932-850f-36e5e2750be3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141445766 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.141445766
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2594716349
Short name T198
Test name
Test status
Simulation time 38770035 ps
CPU time 3.46 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 01:29:26 PM PST 23
Peak memory 248460 kb
Host smart-8a4c9517-adaf-4bd3-b6f8-f49e09757223
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2594716349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2594716349
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2788275798
Short name T658
Test name
Test status
Simulation time 89637663443 ps
CPU time 2130.43 seconds
Started Dec 24 01:31:17 PM PST 23
Finished Dec 24 02:06:49 PM PST 23
Peak memory 270812 kb
Host smart-3df37b16-610f-4fcd-b004-69eecef58897
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788275798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2788275798
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.387561193
Short name T649
Test name
Test status
Simulation time 135667289 ps
CPU time 8.35 seconds
Started Dec 24 01:31:19 PM PST 23
Finished Dec 24 01:31:28 PM PST 23
Peak memory 240176 kb
Host smart-3d89caca-b02f-4676-b6bb-3722472e8a1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=387561193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.387561193
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.369090290
Short name T684
Test name
Test status
Simulation time 8035959021 ps
CPU time 143.53 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 01:31:46 PM PST 23
Peak memory 256180 kb
Host smart-9f42a385-a26a-4253-9096-0d2d4d61f258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36909
0290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.369090290
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3745604682
Short name T636
Test name
Test status
Simulation time 958808629 ps
CPU time 32.12 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 01:29:55 PM PST 23
Peak memory 248248 kb
Host smart-34e6e898-d8ff-48d4-8b29-e26f9179255a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37456
04682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3745604682
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.705042247
Short name T318
Test name
Test status
Simulation time 50595514186 ps
CPU time 2846.92 seconds
Started Dec 24 01:29:20 PM PST 23
Finished Dec 24 02:16:48 PM PST 23
Peak memory 281184 kb
Host smart-b4f62933-522a-49d5-b2d6-151ad251cbc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705042247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.705042247
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.285201948
Short name T362
Test name
Test status
Simulation time 62892414419 ps
CPU time 1898.85 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 02:01:01 PM PST 23
Peak memory 282416 kb
Host smart-54e6c74d-3160-415f-8896-e90314f5a1a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285201948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.285201948
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1431526025
Short name T288
Test name
Test status
Simulation time 4066583772 ps
CPU time 162.07 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 01:34:02 PM PST 23
Peak memory 247288 kb
Host smart-1f882e93-94ad-462f-bf0b-d949c52b9dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431526025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1431526025
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4194584270
Short name T551
Test name
Test status
Simulation time 564339026 ps
CPU time 35.7 seconds
Started Dec 24 01:29:19 PM PST 23
Finished Dec 24 01:29:56 PM PST 23
Peak memory 248676 kb
Host smart-6d22b90e-28d4-4ac3-87eb-41309be92b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41945
84270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4194584270
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3421975993
Short name T486
Test name
Test status
Simulation time 2998958152 ps
CPU time 21.52 seconds
Started Dec 24 01:29:19 PM PST 23
Finished Dec 24 01:29:42 PM PST 23
Peak memory 254184 kb
Host smart-823721c1-afcd-4bff-adf6-ea056f4345a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34219
75993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3421975993
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3108979230
Short name T83
Test name
Test status
Simulation time 454994411 ps
CPU time 29.85 seconds
Started Dec 24 01:29:19 PM PST 23
Finished Dec 24 01:29:50 PM PST 23
Peak memory 255456 kb
Host smart-9abf9a0c-e38a-48e1-80bd-03661abdba37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
79230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3108979230
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2159753094
Short name T438
Test name
Test status
Simulation time 518340618 ps
CPU time 7.92 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 01:29:30 PM PST 23
Peak memory 248288 kb
Host smart-7fb752bf-ff17-4a57-8a0d-2d896c8f35d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
53094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2159753094
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2007662361
Short name T65
Test name
Test status
Simulation time 155396210622 ps
CPU time 2429.14 seconds
Started Dec 24 01:29:23 PM PST 23
Finished Dec 24 02:09:54 PM PST 23
Peak memory 289076 kb
Host smart-9c1ed5aa-9c5b-45dc-be12-f6ffe66b0161
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007662361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2007662361
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1954005362
Short name T299
Test name
Test status
Simulation time 221274572158 ps
CPU time 6168.86 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 03:14:10 PM PST 23
Peak memory 305228 kb
Host smart-6dd68d7d-a258-4b0a-802f-dc1165afaa75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954005362 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1954005362
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.50967769
Short name T211
Test name
Test status
Simulation time 114019001 ps
CPU time 3.3 seconds
Started Dec 24 01:28:07 PM PST 23
Finished Dec 24 01:28:19 PM PST 23
Peak memory 248660 kb
Host smart-7373ce00-2e32-44ef-9339-497fef944edd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=50967769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.50967769
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3972083454
Short name T358
Test name
Test status
Simulation time 2087486236 ps
CPU time 39.94 seconds
Started Dec 24 01:28:12 PM PST 23
Finished Dec 24 01:29:00 PM PST 23
Peak memory 248616 kb
Host smart-784ad02f-cdc0-4d22-be58-4dc684c003df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3972083454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3972083454
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2790150048
Short name T2
Test name
Test status
Simulation time 6319557838 ps
CPU time 174.47 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:31:10 PM PST 23
Peak memory 256176 kb
Host smart-476e1343-52b7-4099-9a75-a269ba55baa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
50048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2790150048
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1064174371
Short name T456
Test name
Test status
Simulation time 999535334 ps
CPU time 17.59 seconds
Started Dec 24 01:27:55 PM PST 23
Finished Dec 24 01:28:13 PM PST 23
Peak memory 248132 kb
Host smart-9f00f14f-8fd1-4f3d-b70e-3e0305a208e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10641
74371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1064174371
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4049331130
Short name T643
Test name
Test status
Simulation time 23799424282 ps
CPU time 1132.06 seconds
Started Dec 24 01:28:07 PM PST 23
Finished Dec 24 01:47:08 PM PST 23
Peak memory 273256 kb
Host smart-037a1d0b-a9cb-4818-b452-d476b7b5edb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049331130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4049331130
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2061064913
Short name T561
Test name
Test status
Simulation time 332954234120 ps
CPU time 2221.81 seconds
Started Dec 24 01:28:07 PM PST 23
Finished Dec 24 02:05:18 PM PST 23
Peak memory 272192 kb
Host smart-ffbfc7c7-0de5-4cf4-8948-5c78d8f8c726
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061064913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2061064913
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2851311467
Short name T265
Test name
Test status
Simulation time 8197954691 ps
CPU time 186.71 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:31:22 PM PST 23
Peak memory 247620 kb
Host smart-570a24b6-cb1a-47ae-87da-10360efdaa79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851311467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2851311467
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2828455427
Short name T688
Test name
Test status
Simulation time 436818603 ps
CPU time 7.78 seconds
Started Dec 24 01:27:58 PM PST 23
Finished Dec 24 01:28:06 PM PST 23
Peak memory 251460 kb
Host smart-076427b4-3484-4c44-bfd5-730212d25399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28284
55427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2828455427
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3186940534
Short name T708
Test name
Test status
Simulation time 294744788 ps
CPU time 17.73 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 01:28:16 PM PST 23
Peak memory 253996 kb
Host smart-e490466b-af65-4e7e-bb14-53445b56fc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869
40534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3186940534
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2533693955
Short name T12
Test name
Test status
Simulation time 826827294 ps
CPU time 24.45 seconds
Started Dec 24 01:27:54 PM PST 23
Finished Dec 24 01:28:19 PM PST 23
Peak memory 268908 kb
Host smart-0a9dcf40-5eae-407f-ab27-a9da1f05cc43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2533693955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2533693955
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2517108868
Short name T724
Test name
Test status
Simulation time 456403244 ps
CPU time 30.67 seconds
Started Dec 24 01:27:56 PM PST 23
Finished Dec 24 01:28:28 PM PST 23
Peak memory 256572 kb
Host smart-2fdc632a-6aa1-4075-af4d-7e8a38d14a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25171
08868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2517108868
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2911288643
Short name T666
Test name
Test status
Simulation time 2695082783 ps
CPU time 45.29 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 01:28:43 PM PST 23
Peak memory 256768 kb
Host smart-7e52a1c7-68d7-4453-84f3-7a4ec3cedf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29112
88643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2911288643
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3871131616
Short name T583
Test name
Test status
Simulation time 50454713361 ps
CPU time 3002.86 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 02:18:01 PM PST 23
Peak memory 289236 kb
Host smart-e2f76292-2c3f-4d1d-9757-0f66ba215806
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871131616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3871131616
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2422795818
Short name T533
Test name
Test status
Simulation time 16744253081 ps
CPU time 1832.3 seconds
Started Dec 24 01:28:07 PM PST 23
Finished Dec 24 01:58:48 PM PST 23
Peak memory 289492 kb
Host smart-1c70e9ea-7420-41bf-988a-3a718ed9389c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422795818 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2422795818
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3227650687
Short name T607
Test name
Test status
Simulation time 286065184375 ps
CPU time 2043.76 seconds
Started Dec 24 01:29:29 PM PST 23
Finished Dec 24 02:03:35 PM PST 23
Peak memory 273160 kb
Host smart-7f06a262-a723-41a8-8e3a-2b1cd0df4910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227650687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3227650687
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2056895226
Short name T692
Test name
Test status
Simulation time 3879975087 ps
CPU time 162.13 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 01:32:05 PM PST 23
Peak memory 256716 kb
Host smart-858674e2-74fa-4c82-9641-3b5e2a18af50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20568
95226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2056895226
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1127057532
Short name T78
Test name
Test status
Simulation time 1049919483 ps
CPU time 35.89 seconds
Started Dec 24 01:29:21 PM PST 23
Finished Dec 24 01:29:59 PM PST 23
Peak memory 254976 kb
Host smart-933710d0-3828-4a91-b2da-53d696a9e2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
57532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1127057532
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2529072570
Short name T616
Test name
Test status
Simulation time 38741970267 ps
CPU time 2094.71 seconds
Started Dec 24 01:29:19 PM PST 23
Finished Dec 24 02:04:15 PM PST 23
Peak memory 281440 kb
Host smart-f03ef149-4d73-4945-b3d1-330d94723d70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529072570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2529072570
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.231166851
Short name T361
Test name
Test status
Simulation time 26836842306 ps
CPU time 1604.72 seconds
Started Dec 24 01:29:29 PM PST 23
Finished Dec 24 01:56:16 PM PST 23
Peak memory 273000 kb
Host smart-e665b74f-bd01-4030-86c7-b62f253c0b23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231166851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.231166851
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.885646660
Short name T124
Test name
Test status
Simulation time 7220293984 ps
CPU time 283.1 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 01:36:03 PM PST 23
Peak memory 254468 kb
Host smart-936d616b-f7b1-48ca-b01f-3f21be5a6b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885646660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.885646660
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3044605473
Short name T366
Test name
Test status
Simulation time 1045327827 ps
CPU time 56.68 seconds
Started Dec 24 01:29:29 PM PST 23
Finished Dec 24 01:30:28 PM PST 23
Peak memory 254216 kb
Host smart-03e98bc4-53cc-4f84-93be-cfcb1e91f029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30446
05473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3044605473
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.798168292
Short name T58
Test name
Test status
Simulation time 352060030 ps
CPU time 7.17 seconds
Started Dec 24 01:31:00 PM PST 23
Finished Dec 24 01:31:16 PM PST 23
Peak memory 249940 kb
Host smart-150bb306-98ed-40d2-b19f-62125358e0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79816
8292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.798168292
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.463008304
Short name T52
Test name
Test status
Simulation time 556263095 ps
CPU time 29.31 seconds
Started Dec 24 01:29:29 PM PST 23
Finished Dec 24 01:30:01 PM PST 23
Peak memory 248448 kb
Host smart-8245528d-7e74-4bb1-a6ef-47a459fe4ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46300
8304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.463008304
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1905309092
Short name T497
Test name
Test status
Simulation time 43245616 ps
CPU time 4.97 seconds
Started Dec 24 01:29:29 PM PST 23
Finished Dec 24 01:29:36 PM PST 23
Peak memory 240168 kb
Host smart-2299c552-671b-4db1-9de5-e86a33bc454e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19053
09092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1905309092
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.876415423
Short name T482
Test name
Test status
Simulation time 119185355652 ps
CPU time 3809.91 seconds
Started Dec 24 01:29:32 PM PST 23
Finished Dec 24 02:33:04 PM PST 23
Peak memory 306212 kb
Host smart-4990ca0f-39a7-4e5f-98d6-fd3d3fdc0851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876415423 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.876415423
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3582655374
Short name T614
Test name
Test status
Simulation time 168365071173 ps
CPU time 1145.3 seconds
Started Dec 24 01:29:36 PM PST 23
Finished Dec 24 01:48:43 PM PST 23
Peak memory 271532 kb
Host smart-eb822d79-f348-46da-92b9-4b1be99dcc5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582655374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3582655374
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1141363138
Short name T680
Test name
Test status
Simulation time 10833530078 ps
CPU time 254.01 seconds
Started Dec 24 01:29:31 PM PST 23
Finished Dec 24 01:33:46 PM PST 23
Peak memory 250760 kb
Host smart-ba305665-d79e-48bc-b902-10834db5f11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413
63138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1141363138
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3173018553
Short name T350
Test name
Test status
Simulation time 878303754 ps
CPU time 59 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 01:30:34 PM PST 23
Peak memory 256200 kb
Host smart-3c5b5add-30e2-412e-8ac0-f48334afc8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31730
18553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3173018553
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3481057567
Short name T654
Test name
Test status
Simulation time 444167980367 ps
CPU time 2441.54 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 02:10:16 PM PST 23
Peak memory 284320 kb
Host smart-c76695d1-a1da-4e3b-b645-bf198f793854
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481057567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3481057567
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.824402728
Short name T353
Test name
Test status
Simulation time 123070716582 ps
CPU time 2046.42 seconds
Started Dec 24 01:29:32 PM PST 23
Finished Dec 24 02:03:39 PM PST 23
Peak memory 284904 kb
Host smart-eaf97dee-abfa-4b0f-9597-78989fe7b957
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824402728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.824402728
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.4038645725
Short name T44
Test name
Test status
Simulation time 41510292664 ps
CPU time 268.06 seconds
Started Dec 24 01:29:36 PM PST 23
Finished Dec 24 01:34:06 PM PST 23
Peak memory 246580 kb
Host smart-ae21ba31-f199-4987-8c54-dfda85c8268f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038645725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.4038645725
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3528033457
Short name T195
Test name
Test status
Simulation time 1040282627 ps
CPU time 23.77 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 01:29:59 PM PST 23
Peak memory 255284 kb
Host smart-58fc436a-6a0f-46a3-9122-406f08c59901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
33457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3528033457
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2196074549
Short name T430
Test name
Test status
Simulation time 294972781 ps
CPU time 28.9 seconds
Started Dec 24 01:29:32 PM PST 23
Finished Dec 24 01:30:02 PM PST 23
Peak memory 247384 kb
Host smart-9da3b0c7-ba5f-4128-8826-5c4d5be48779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
74549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2196074549
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3301993261
Short name T413
Test name
Test status
Simulation time 375467194 ps
CPU time 13.71 seconds
Started Dec 24 01:29:35 PM PST 23
Finished Dec 24 01:29:50 PM PST 23
Peak memory 251692 kb
Host smart-22806ee3-0a88-4999-8902-aa8ec3a8f233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33019
93261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3301993261
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.177192496
Short name T568
Test name
Test status
Simulation time 121323856 ps
CPU time 12.14 seconds
Started Dec 24 01:29:32 PM PST 23
Finished Dec 24 01:29:45 PM PST 23
Peak memory 248688 kb
Host smart-2fe6dee8-ff25-4a45-805a-1b40dc18d004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17719
2496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.177192496
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4262988590
Short name T302
Test name
Test status
Simulation time 77435713783 ps
CPU time 2735.99 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 02:15:12 PM PST 23
Peak memory 301212 kb
Host smart-7bf4415b-4915-4a7f-a0e4-c72af8d7efa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262988590 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4262988590
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1758358622
Short name T420
Test name
Test status
Simulation time 70503405302 ps
CPU time 1397.8 seconds
Started Dec 24 01:29:36 PM PST 23
Finished Dec 24 01:52:55 PM PST 23
Peak memory 283396 kb
Host smart-e213a0e2-19e7-40aa-a984-568dc72d3b64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758358622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1758358622
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2213964280
Short name T90
Test name
Test status
Simulation time 2644573575 ps
CPU time 38.68 seconds
Started Dec 24 01:29:31 PM PST 23
Finished Dec 24 01:30:11 PM PST 23
Peak memory 255780 kb
Host smart-67a05ae0-7992-40c1-8279-fee992a4eb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22139
64280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2213964280
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3313286981
Short name T681
Test name
Test status
Simulation time 67345909163 ps
CPU time 1280.64 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 01:50:56 PM PST 23
Peak memory 281512 kb
Host smart-d4187f8d-b295-4ecb-a388-3a9ec56092df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313286981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3313286981
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.319011188
Short name T279
Test name
Test status
Simulation time 10608522349 ps
CPU time 264.43 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 01:33:58 PM PST 23
Peak memory 248648 kb
Host smart-a373c214-2b23-4cde-9a9e-14db3a5ee5f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319011188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.319011188
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2753651547
Short name T252
Test name
Test status
Simulation time 1793373586 ps
CPU time 32.56 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 01:30:07 PM PST 23
Peak memory 248576 kb
Host smart-357a78b1-7e44-44f9-b303-1b3ba60824df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27536
51547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2753651547
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1671917628
Short name T64
Test name
Test status
Simulation time 2795374728 ps
CPU time 42.17 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 01:30:17 PM PST 23
Peak memory 248372 kb
Host smart-a29a627a-3b19-44a5-8783-23d19995c027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16719
17628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1671917628
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1651564303
Short name T537
Test name
Test status
Simulation time 324821889 ps
CPU time 11.37 seconds
Started Dec 24 01:29:38 PM PST 23
Finished Dec 24 01:29:50 PM PST 23
Peak memory 246980 kb
Host smart-3289ba82-f181-4ab5-a11c-79deb4247382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16515
64303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1651564303
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2790143855
Short name T346
Test name
Test status
Simulation time 1026904505 ps
CPU time 60.17 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 01:30:35 PM PST 23
Peak memory 248604 kb
Host smart-b8987d68-7a0d-4a33-a090-d28974ebb64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
43855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2790143855
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2533040961
Short name T536
Test name
Test status
Simulation time 144881863027 ps
CPU time 2268.66 seconds
Started Dec 24 01:29:33 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 288976 kb
Host smart-5d0c9c5a-2dfb-47ed-903e-78e208435af9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533040961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2533040961
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2651505072
Short name T73
Test name
Test status
Simulation time 134511742266 ps
CPU time 4416.88 seconds
Started Dec 24 01:29:39 PM PST 23
Finished Dec 24 02:43:18 PM PST 23
Peak memory 305532 kb
Host smart-a824904b-9627-4c89-a232-4fb2e65039a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651505072 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2651505072
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3888230168
Short name T393
Test name
Test status
Simulation time 87895673866 ps
CPU time 1177.84 seconds
Started Dec 24 01:29:35 PM PST 23
Finished Dec 24 01:49:14 PM PST 23
Peak memory 265076 kb
Host smart-6e503e52-b0d7-4a56-b725-0ca47eb0f7b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888230168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3888230168
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3473350968
Short name T334
Test name
Test status
Simulation time 651432934 ps
CPU time 23.01 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 01:29:58 PM PST 23
Peak memory 254240 kb
Host smart-ddfbe152-d1de-4d2a-9770-caf3fedcb526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34733
50968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3473350968
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3662468806
Short name T405
Test name
Test status
Simulation time 3944479148 ps
CPU time 26.92 seconds
Started Dec 24 01:29:37 PM PST 23
Finished Dec 24 01:30:05 PM PST 23
Peak memory 247844 kb
Host smart-a77825b9-af4a-409d-ab3d-08bc8af9e4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36624
68806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3662468806
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.802337674
Short name T307
Test name
Test status
Simulation time 34198645537 ps
CPU time 2081.8 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 02:04:18 PM PST 23
Peak memory 283124 kb
Host smart-2b1e2429-6498-48c8-8d22-d6e8dae96aab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802337674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.802337674
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3746604563
Short name T244
Test name
Test status
Simulation time 9469219416 ps
CPU time 762.81 seconds
Started Dec 24 01:29:47 PM PST 23
Finished Dec 24 01:42:31 PM PST 23
Peak memory 268040 kb
Host smart-c583b39b-d8d1-4c3c-82f3-c02ef29b9438
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746604563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3746604563
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2102272997
Short name T369
Test name
Test status
Simulation time 1160594637 ps
CPU time 66.18 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 01:30:41 PM PST 23
Peak memory 248492 kb
Host smart-bd57de3e-d2cc-4a48-a5d2-279a75625cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21022
72997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2102272997
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1332112571
Short name T108
Test name
Test status
Simulation time 2347732466 ps
CPU time 36.29 seconds
Started Dec 24 01:29:39 PM PST 23
Finished Dec 24 01:30:17 PM PST 23
Peak memory 255140 kb
Host smart-90a73a71-49b2-4248-af20-828bc70c10d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13321
12571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1332112571
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4226749367
Short name T96
Test name
Test status
Simulation time 316602021 ps
CPU time 32.64 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 01:30:08 PM PST 23
Peak memory 248656 kb
Host smart-020f950a-b9d6-4e87-8ff8-46f9147a6b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42267
49367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4226749367
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3249820781
Short name T694
Test name
Test status
Simulation time 113861336 ps
CPU time 14.51 seconds
Started Dec 24 01:29:32 PM PST 23
Finished Dec 24 01:29:48 PM PST 23
Peak memory 248892 kb
Host smart-cc6277a7-554d-485e-a7ff-5063c1683bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32498
20781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3249820781
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.716011817
Short name T359
Test name
Test status
Simulation time 102968682334 ps
CPU time 1567.62 seconds
Started Dec 24 01:29:34 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 288644 kb
Host smart-4c286ed9-e99c-43eb-bbb0-30289eca6dce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716011817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.716011817
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1512917588
Short name T670
Test name
Test status
Simulation time 19754682717 ps
CPU time 1008.59 seconds
Started Dec 24 01:29:37 PM PST 23
Finished Dec 24 01:46:27 PM PST 23
Peak memory 268196 kb
Host smart-80cb0fde-e542-407d-b644-ef0fb5eec0c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512917588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1512917588
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.589688871
Short name T476
Test name
Test status
Simulation time 19897819149 ps
CPU time 189.34 seconds
Started Dec 24 01:29:46 PM PST 23
Finished Dec 24 01:32:57 PM PST 23
Peak memory 256880 kb
Host smart-8c38686e-ba07-469e-9442-e915b96fda39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58968
8871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.589688871
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2570584008
Short name T429
Test name
Test status
Simulation time 665199211 ps
CPU time 21.51 seconds
Started Dec 24 01:29:47 PM PST 23
Finished Dec 24 01:30:09 PM PST 23
Peak memory 253460 kb
Host smart-332b122b-f485-4ac0-a301-7be392727bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705
84008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2570584008
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1738859342
Short name T592
Test name
Test status
Simulation time 49256309706 ps
CPU time 2728.52 seconds
Started Dec 24 01:29:37 PM PST 23
Finished Dec 24 02:15:07 PM PST 23
Peak memory 289412 kb
Host smart-4f6d0860-36b4-43db-9545-bb1c41dec1a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738859342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1738859342
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.548495469
Short name T351
Test name
Test status
Simulation time 84328133956 ps
CPU time 1246.03 seconds
Started Dec 24 01:30:03 PM PST 23
Finished Dec 24 01:50:50 PM PST 23
Peak memory 265096 kb
Host smart-1ec313f0-7d48-4547-9ed2-b51e67e3ba96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548495469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.548495469
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4011373092
Short name T234
Test name
Test status
Simulation time 774968069 ps
CPU time 14.92 seconds
Started Dec 24 01:29:47 PM PST 23
Finished Dec 24 01:30:03 PM PST 23
Peak memory 248696 kb
Host smart-c9e6505c-4d0f-4e2d-ade5-de7a136e65e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40113
73092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4011373092
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2523575768
Short name T118
Test name
Test status
Simulation time 4814004633 ps
CPU time 66.46 seconds
Started Dec 24 01:29:47 PM PST 23
Finished Dec 24 01:30:55 PM PST 23
Peak memory 255132 kb
Host smart-a7e94569-9217-49e5-a44e-ee512cdb0e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25235
75768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2523575768
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1667644676
Short name T378
Test name
Test status
Simulation time 671532950 ps
CPU time 32.39 seconds
Started Dec 24 01:29:40 PM PST 23
Finished Dec 24 01:30:14 PM PST 23
Peak memory 246696 kb
Host smart-a393bd12-93e5-4524-903e-4a08a5e27a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16676
44676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1667644676
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2199380999
Short name T386
Test name
Test status
Simulation time 1106192078 ps
CPU time 26.09 seconds
Started Dec 24 01:29:36 PM PST 23
Finished Dec 24 01:30:03 PM PST 23
Peak memory 248520 kb
Host smart-5105196a-51a5-4382-8439-10c1b489eba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21993
80999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2199380999
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2672054070
Short name T103
Test name
Test status
Simulation time 17429758450 ps
CPU time 1494.77 seconds
Started Dec 24 01:29:55 PM PST 23
Finished Dec 24 01:54:51 PM PST 23
Peak memory 289156 kb
Host smart-8c6805c5-52ad-4606-8019-26673e2a00c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672054070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2672054070
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2366500029
Short name T59
Test name
Test status
Simulation time 39690142882 ps
CPU time 3552.3 seconds
Started Dec 24 01:30:01 PM PST 23
Finished Dec 24 02:29:15 PM PST 23
Peak memory 287604 kb
Host smart-6688dd04-96d0-42c1-8c0d-256a21e65045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366500029 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2366500029
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2123558421
Short name T387
Test name
Test status
Simulation time 10540450017 ps
CPU time 1029.05 seconds
Started Dec 24 01:30:08 PM PST 23
Finished Dec 24 01:47:18 PM PST 23
Peak memory 273284 kb
Host smart-fab6b1d6-1355-4900-a007-ace098066f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123558421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2123558421
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1243291761
Short name T99
Test name
Test status
Simulation time 720715236 ps
CPU time 27.79 seconds
Started Dec 24 01:30:02 PM PST 23
Finished Dec 24 01:30:31 PM PST 23
Peak memory 248284 kb
Host smart-8b451200-2622-4bcc-a322-6a91ec31740a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432
91761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1243291761
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3410200590
Short name T380
Test name
Test status
Simulation time 794073765 ps
CPU time 51.66 seconds
Started Dec 24 01:30:01 PM PST 23
Finished Dec 24 01:30:54 PM PST 23
Peak memory 248552 kb
Host smart-78413bb8-1cf1-4785-9d6b-17aaff869fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34102
00590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3410200590
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3349527106
Short name T320
Test name
Test status
Simulation time 166516474827 ps
CPU time 2332.85 seconds
Started Dec 24 01:30:02 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 272588 kb
Host smart-490a62d2-3d6d-4d7a-82d6-c352c97c37da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349527106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3349527106
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.982866361
Short name T238
Test name
Test status
Simulation time 74565985077 ps
CPU time 1420.87 seconds
Started Dec 24 01:30:09 PM PST 23
Finished Dec 24 01:53:51 PM PST 23
Peak memory 289624 kb
Host smart-43fc1bf1-6b68-46da-a19a-7e8b528e7351
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982866361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.982866361
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.936029544
Short name T280
Test name
Test status
Simulation time 10906851649 ps
CPU time 353.41 seconds
Started Dec 24 01:30:09 PM PST 23
Finished Dec 24 01:36:03 PM PST 23
Peak memory 247524 kb
Host smart-36fb9636-e9f2-42d5-a896-d9a770797701
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936029544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.936029544
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3759411095
Short name T364
Test name
Test status
Simulation time 812071082 ps
CPU time 10.55 seconds
Started Dec 24 01:30:01 PM PST 23
Finished Dec 24 01:30:12 PM PST 23
Peak memory 248760 kb
Host smart-12454f5b-cde5-49be-bcad-7f37911a407b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37594
11095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3759411095
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3930779449
Short name T485
Test name
Test status
Simulation time 4689485176 ps
CPU time 74.77 seconds
Started Dec 24 01:30:01 PM PST 23
Finished Dec 24 01:31:17 PM PST 23
Peak memory 253932 kb
Host smart-7ce771d5-b3cb-4d47-b24f-ae2dbe14b26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307
79449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3930779449
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2857085114
Short name T75
Test name
Test status
Simulation time 515817528 ps
CPU time 29.83 seconds
Started Dec 24 01:30:13 PM PST 23
Finished Dec 24 01:30:44 PM PST 23
Peak memory 255252 kb
Host smart-75e567d9-6cc8-480a-93a6-0194954fc14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28570
85114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2857085114
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2879717144
Short name T381
Test name
Test status
Simulation time 684971516 ps
CPU time 41.7 seconds
Started Dec 24 01:29:55 PM PST 23
Finished Dec 24 01:30:38 PM PST 23
Peak memory 248660 kb
Host smart-8db895e8-9ce7-47c4-89b0-1c98459f28d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28797
17144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2879717144
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.4144217368
Short name T466
Test name
Test status
Simulation time 17360175724 ps
CPU time 1589.09 seconds
Started Dec 24 01:30:07 PM PST 23
Finished Dec 24 01:56:38 PM PST 23
Peak memory 289264 kb
Host smart-fb7f8cd3-76cc-49d8-a6ea-1844c8bacf88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144217368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.4144217368
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2339874031
Short name T116
Test name
Test status
Simulation time 338507057856 ps
CPU time 5298.72 seconds
Started Dec 24 01:30:01 PM PST 23
Finished Dec 24 02:58:22 PM PST 23
Peak memory 322480 kb
Host smart-e0689dba-61df-4766-9e65-4982a3d3ac61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339874031 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2339874031
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1532371195
Short name T419
Test name
Test status
Simulation time 73865574256 ps
CPU time 1707.23 seconds
Started Dec 24 01:30:00 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 273052 kb
Host smart-8b3bcc3f-6fa0-4754-bbfc-10ddd6aecacd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532371195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1532371195
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2077357085
Short name T619
Test name
Test status
Simulation time 25330332849 ps
CPU time 207.7 seconds
Started Dec 24 01:30:10 PM PST 23
Finished Dec 24 01:33:40 PM PST 23
Peak memory 256704 kb
Host smart-917fc494-8897-4c51-9612-fbfc145b4df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20773
57085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2077357085
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1974317555
Short name T100
Test name
Test status
Simulation time 936255990 ps
CPU time 53.21 seconds
Started Dec 24 01:30:07 PM PST 23
Finished Dec 24 01:31:02 PM PST 23
Peak memory 254952 kb
Host smart-a8d3e8be-dd7d-4b19-9ecf-744887e1b2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743
17555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1974317555
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3496894707
Short name T480
Test name
Test status
Simulation time 7642731488 ps
CPU time 648.66 seconds
Started Dec 24 01:30:19 PM PST 23
Finished Dec 24 01:41:09 PM PST 23
Peak memory 273200 kb
Host smart-cf122da0-8760-4391-959b-4a99aa00de73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496894707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3496894707
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2605134800
Short name T428
Test name
Test status
Simulation time 34968803370 ps
CPU time 953.37 seconds
Started Dec 24 01:30:04 PM PST 23
Finished Dec 24 01:45:59 PM PST 23
Peak memory 284172 kb
Host smart-fe9467bf-a9fa-461a-8721-1dfdcd575260
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605134800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2605134800
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2342433498
Short name T570
Test name
Test status
Simulation time 10781371375 ps
CPU time 424.11 seconds
Started Dec 24 01:30:10 PM PST 23
Finished Dec 24 01:37:17 PM PST 23
Peak memory 247572 kb
Host smart-ab5ff085-4d7b-4cc2-aad6-bf80b6b31c5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342433498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2342433498
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3495766983
Short name T490
Test name
Test status
Simulation time 1104529434 ps
CPU time 28.31 seconds
Started Dec 24 01:30:07 PM PST 23
Finished Dec 24 01:30:36 PM PST 23
Peak memory 248704 kb
Host smart-05dfbc28-2f53-49a1-bd2d-16fe4e820b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957
66983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3495766983
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2164418980
Short name T656
Test name
Test status
Simulation time 1115796836 ps
CPU time 62.52 seconds
Started Dec 24 01:30:08 PM PST 23
Finished Dec 24 01:31:12 PM PST 23
Peak memory 255124 kb
Host smart-1d0b5492-95f7-4a15-b5bf-e3ebccf5e756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644
18980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2164418980
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1244800496
Short name T716
Test name
Test status
Simulation time 181610024 ps
CPU time 17.05 seconds
Started Dec 24 01:30:02 PM PST 23
Finished Dec 24 01:30:20 PM PST 23
Peak memory 248592 kb
Host smart-2240e0f6-c61b-4788-8782-cd6d13394334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448
00496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1244800496
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3425157843
Short name T673
Test name
Test status
Simulation time 171060164808 ps
CPU time 2654.49 seconds
Started Dec 24 01:30:08 PM PST 23
Finished Dec 24 02:14:24 PM PST 23
Peak memory 281496 kb
Host smart-def52508-7e1f-4c78-9015-218edc7402bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425157843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3425157843
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1060968395
Short name T693
Test name
Test status
Simulation time 178352175099 ps
CPU time 2775.52 seconds
Started Dec 24 01:30:18 PM PST 23
Finished Dec 24 02:16:35 PM PST 23
Peak memory 282688 kb
Host smart-bb8eb3e5-f324-4844-9fab-4f7c9d1396cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060968395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1060968395
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.815109889
Short name T653
Test name
Test status
Simulation time 2017423350 ps
CPU time 119.74 seconds
Started Dec 24 01:30:17 PM PST 23
Finished Dec 24 01:32:18 PM PST 23
Peak memory 255776 kb
Host smart-b956f2a0-bcca-4325-8c8b-09ab65fb61a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81510
9889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.815109889
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.555489038
Short name T543
Test name
Test status
Simulation time 196529185 ps
CPU time 18.47 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 01:30:43 PM PST 23
Peak memory 255092 kb
Host smart-140d6cd9-ad78-4936-88c1-394e60ba6c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55548
9038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.555489038
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.719297373
Short name T259
Test name
Test status
Simulation time 83363569081 ps
CPU time 858.55 seconds
Started Dec 24 01:30:17 PM PST 23
Finished Dec 24 01:44:36 PM PST 23
Peak memory 272364 kb
Host smart-911f4516-b35a-42ce-bac7-1c330da84644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719297373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.719297373
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.598425347
Short name T510
Test name
Test status
Simulation time 12160333245 ps
CPU time 1087.42 seconds
Started Dec 24 01:30:17 PM PST 23
Finished Dec 24 01:48:25 PM PST 23
Peak memory 269088 kb
Host smart-0c70944e-9e1e-45eb-b06c-1a8126d6206b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598425347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.598425347
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1085871383
Short name T282
Test name
Test status
Simulation time 14761334210 ps
CPU time 307.07 seconds
Started Dec 24 01:30:33 PM PST 23
Finished Dec 24 01:35:41 PM PST 23
Peak memory 248612 kb
Host smart-1e476c05-ed04-4f1b-a033-929c69e46707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085871383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1085871383
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2638919348
Short name T648
Test name
Test status
Simulation time 3016794853 ps
CPU time 54.73 seconds
Started Dec 24 01:30:31 PM PST 23
Finished Dec 24 01:31:27 PM PST 23
Peak memory 248700 kb
Host smart-0a84d9f2-c8ca-4a41-94db-17e97081e619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26389
19348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2638919348
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.287769480
Short name T597
Test name
Test status
Simulation time 64251784 ps
CPU time 7.71 seconds
Started Dec 24 01:29:57 PM PST 23
Finished Dec 24 01:30:05 PM PST 23
Peak memory 248252 kb
Host smart-6d86d7fb-6c13-4c8a-a385-48d0a8c735c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
9480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.287769480
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2158599414
Short name T546
Test name
Test status
Simulation time 2015373507 ps
CPU time 34.28 seconds
Started Dec 24 01:30:08 PM PST 23
Finished Dec 24 01:30:43 PM PST 23
Peak memory 255488 kb
Host smart-688a3942-6b56-48be-b904-2d9c26cb3bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21585
99414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2158599414
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1829909626
Short name T562
Test name
Test status
Simulation time 198332978 ps
CPU time 13.35 seconds
Started Dec 24 01:30:13 PM PST 23
Finished Dec 24 01:30:27 PM PST 23
Peak memory 253620 kb
Host smart-e38f54b1-a727-4184-a65d-819201d228fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18299
09626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1829909626
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.4266498322
Short name T39
Test name
Test status
Simulation time 13510816434 ps
CPU time 1143.31 seconds
Started Dec 24 01:30:11 PM PST 23
Finished Dec 24 01:49:17 PM PST 23
Peak memory 288860 kb
Host smart-6b8d6a8c-a81d-411b-8e79-f37c6b994032
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266498322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.4266498322
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.522377802
Short name T102
Test name
Test status
Simulation time 68397208355 ps
CPU time 4065.71 seconds
Started Dec 24 01:30:17 PM PST 23
Finished Dec 24 02:38:05 PM PST 23
Peak memory 305700 kb
Host smart-d544b8fd-170f-4ade-8272-afdeeac388ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522377802 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.522377802
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2315403570
Short name T512
Test name
Test status
Simulation time 7975464976 ps
CPU time 951.35 seconds
Started Dec 24 01:30:18 PM PST 23
Finished Dec 24 01:46:10 PM PST 23
Peak memory 273060 kb
Host smart-615ee273-fc86-4548-9776-f290af687acf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315403570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2315403570
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4148676373
Short name T472
Test name
Test status
Simulation time 2880251168 ps
CPU time 65.67 seconds
Started Dec 24 01:30:30 PM PST 23
Finished Dec 24 01:31:36 PM PST 23
Peak memory 256292 kb
Host smart-893da752-07bc-4483-a589-ca97e70e713c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
76373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4148676373
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.244193493
Short name T385
Test name
Test status
Simulation time 665701853 ps
CPU time 11.97 seconds
Started Dec 24 01:30:17 PM PST 23
Finished Dec 24 01:30:30 PM PST 23
Peak memory 251816 kb
Host smart-ff35f8d6-e0b8-452b-8651-169d2c774c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
3493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.244193493
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1489575442
Short name T717
Test name
Test status
Simulation time 27346830753 ps
CPU time 1174.35 seconds
Started Dec 24 01:30:23 PM PST 23
Finished Dec 24 01:49:58 PM PST 23
Peak memory 288320 kb
Host smart-3d8e7fe4-1127-4634-956a-5f92de5ef6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489575442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1489575442
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.305121008
Short name T6
Test name
Test status
Simulation time 27030747758 ps
CPU time 1118.77 seconds
Started Dec 24 01:30:23 PM PST 23
Finished Dec 24 01:49:03 PM PST 23
Peak memory 286196 kb
Host smart-5f977f18-08c4-48a2-a781-7598b43576b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305121008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.305121008
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.369118775
Short name T565
Test name
Test status
Simulation time 5880733238 ps
CPU time 132.91 seconds
Started Dec 24 01:30:25 PM PST 23
Finished Dec 24 01:32:39 PM PST 23
Peak memory 247568 kb
Host smart-81f52135-3f1b-400c-bfa7-5d448df629f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369118775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.369118775
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2138064633
Short name T425
Test name
Test status
Simulation time 915250888 ps
CPU time 50.75 seconds
Started Dec 24 01:30:19 PM PST 23
Finished Dec 24 01:31:10 PM PST 23
Peak memory 255276 kb
Host smart-845e9a42-de70-4615-be2e-4dcbe2fbec39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
64633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2138064633
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1499138324
Short name T682
Test name
Test status
Simulation time 1750294208 ps
CPU time 34.43 seconds
Started Dec 24 01:30:21 PM PST 23
Finished Dec 24 01:30:56 PM PST 23
Peak memory 254816 kb
Host smart-4a567e8e-9827-4b91-83ab-0085dc6004e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14991
38324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1499138324
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2302383300
Short name T365
Test name
Test status
Simulation time 1031016567 ps
CPU time 62.59 seconds
Started Dec 24 01:30:30 PM PST 23
Finished Dec 24 01:31:34 PM PST 23
Peak memory 247692 kb
Host smart-15c1cfa0-340a-4037-9147-9db0daae7fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23023
83300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2302383300
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1724425252
Short name T671
Test name
Test status
Simulation time 2938641092 ps
CPU time 51.93 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 01:31:17 PM PST 23
Peak memory 248748 kb
Host smart-e9dbafee-f601-411c-be91-f66c980fcd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17244
25252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1724425252
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1929796792
Short name T105
Test name
Test status
Simulation time 76826865074 ps
CPU time 3545.03 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 02:29:31 PM PST 23
Peak memory 303520 kb
Host smart-fbfd81c3-a70d-4a91-99d2-2cbb4f043cb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929796792 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1929796792
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.288908862
Short name T232
Test name
Test status
Simulation time 8581190201 ps
CPU time 744.35 seconds
Started Dec 24 01:30:18 PM PST 23
Finished Dec 24 01:42:44 PM PST 23
Peak memory 264960 kb
Host smart-d28a7e6a-5d73-432c-a7e8-c1771b42939a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288908862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.288908862
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.21331861
Short name T412
Test name
Test status
Simulation time 1619234331 ps
CPU time 137.67 seconds
Started Dec 24 01:30:17 PM PST 23
Finished Dec 24 01:32:36 PM PST 23
Peak memory 255904 kb
Host smart-06cb764c-441f-4f16-9696-717d46900074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21331
861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.21331861
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1129318372
Short name T347
Test name
Test status
Simulation time 568079372 ps
CPU time 35.85 seconds
Started Dec 24 01:30:23 PM PST 23
Finished Dec 24 01:31:00 PM PST 23
Peak memory 255100 kb
Host smart-12a5d604-ca5b-4cff-ac3c-3a5b00812ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11293
18372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1129318372
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2181334364
Short name T308
Test name
Test status
Simulation time 145303984790 ps
CPU time 2068.92 seconds
Started Dec 24 01:30:18 PM PST 23
Finished Dec 24 02:04:48 PM PST 23
Peak memory 289188 kb
Host smart-b2cb42ae-7626-4591-93e5-678b2651add3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181334364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2181334364
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.469085221
Short name T402
Test name
Test status
Simulation time 19733539845 ps
CPU time 1602.81 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 01:57:08 PM PST 23
Peak memory 289096 kb
Host smart-853316af-8a2f-489f-959b-f2508637d47b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469085221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.469085221
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1317224226
Short name T272
Test name
Test status
Simulation time 54508768681 ps
CPU time 587.19 seconds
Started Dec 24 01:30:08 PM PST 23
Finished Dec 24 01:39:56 PM PST 23
Peak memory 247364 kb
Host smart-33d217a2-6086-43b1-b904-ae3582804c66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317224226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1317224226
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3902782979
Short name T627
Test name
Test status
Simulation time 755267031 ps
CPU time 33.89 seconds
Started Dec 24 01:30:09 PM PST 23
Finished Dec 24 01:30:44 PM PST 23
Peak memory 254796 kb
Host smart-22954f71-273d-45fa-89a2-00a6c57be531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39027
82979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3902782979
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.4046098955
Short name T617
Test name
Test status
Simulation time 146182067 ps
CPU time 5.75 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 01:30:30 PM PST 23
Peak memory 238604 kb
Host smart-f126b0e6-bbb8-4056-8aa3-d37ea9531ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460
98955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4046098955
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1802775174
Short name T360
Test name
Test status
Simulation time 519146768 ps
CPU time 14.87 seconds
Started Dec 24 01:30:31 PM PST 23
Finished Dec 24 01:30:47 PM PST 23
Peak memory 254796 kb
Host smart-3e20ee43-cdcb-4863-84c3-36e48d1e9c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18027
75174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1802775174
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.813430875
Short name T332
Test name
Test status
Simulation time 1189777269 ps
CPU time 42.15 seconds
Started Dec 24 01:30:30 PM PST 23
Finished Dec 24 01:31:13 PM PST 23
Peak memory 248712 kb
Host smart-bbc91996-657b-492f-b4fb-e0f8ee053f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81343
0875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.813430875
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1594323434
Short name T427
Test name
Test status
Simulation time 225001069068 ps
CPU time 2380.71 seconds
Started Dec 24 01:30:35 PM PST 23
Finished Dec 24 02:10:17 PM PST 23
Peak memory 288560 kb
Host smart-04d413a9-f78a-444b-9e2f-8b5da9cb5870
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594323434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1594323434
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2291321802
Short name T292
Test name
Test status
Simulation time 358441702717 ps
CPU time 3365.96 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 02:26:45 PM PST 23
Peak memory 322496 kb
Host smart-53ee3ac0-2d98-4c5d-8a30-5ec23640e96d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291321802 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2291321802
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3446230309
Short name T196
Test name
Test status
Simulation time 126386680 ps
CPU time 3.54 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:28:19 PM PST 23
Peak memory 248832 kb
Host smart-17b7f5eb-3cbd-44d6-8ee5-f6d97debe8e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3446230309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3446230309
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3073050021
Short name T392
Test name
Test status
Simulation time 40622005988 ps
CPU time 2227.1 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 02:05:28 PM PST 23
Peak memory 272316 kb
Host smart-8e6a38c8-e478-4517-b394-532b46f11476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073050021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3073050021
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3549696344
Short name T516
Test name
Test status
Simulation time 175291197 ps
CPU time 10.75 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:28:27 PM PST 23
Peak memory 248680 kb
Host smart-4c14279a-646b-4cf3-a208-2151b24291e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3549696344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3549696344
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3604442619
Short name T335
Test name
Test status
Simulation time 2096190101 ps
CPU time 42.86 seconds
Started Dec 24 01:28:09 PM PST 23
Finished Dec 24 01:29:00 PM PST 23
Peak memory 256064 kb
Host smart-9c103ee7-d521-499b-ab17-3dd624568f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36044
42619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3604442619
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1277601636
Short name T357
Test name
Test status
Simulation time 1345431846 ps
CPU time 33.59 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 01:28:32 PM PST 23
Peak memory 255160 kb
Host smart-66e2d904-118f-40cb-a6c6-b15b11e962f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12776
01636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1277601636
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.846917209
Short name T310
Test name
Test status
Simulation time 160674026629 ps
CPU time 2522.35 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 02:10:01 PM PST 23
Peak memory 289088 kb
Host smart-5cb34771-01eb-4cb3-a653-498d6425b9ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846917209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.846917209
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1010161937
Short name T623
Test name
Test status
Simulation time 73056763417 ps
CPU time 1366.43 seconds
Started Dec 24 01:27:58 PM PST 23
Finished Dec 24 01:50:45 PM PST 23
Peak memory 289444 kb
Host smart-93dc52b4-e9e7-4395-9094-48f8551bb1a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010161937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1010161937
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.845870599
Short name T706
Test name
Test status
Simulation time 47536156528 ps
CPU time 497.83 seconds
Started Dec 24 01:28:06 PM PST 23
Finished Dec 24 01:36:34 PM PST 23
Peak memory 247196 kb
Host smart-83bdd177-f9be-47da-af7d-e9eb027a70d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845870599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.845870599
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1168858350
Short name T685
Test name
Test status
Simulation time 1761712765 ps
CPU time 17.56 seconds
Started Dec 24 01:28:04 PM PST 23
Finished Dec 24 01:28:26 PM PST 23
Peak memory 248672 kb
Host smart-fe4df233-bb21-4fea-aea7-5cfc96285b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11688
58350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1168858350
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1769982614
Short name T339
Test name
Test status
Simulation time 424278892 ps
CPU time 32.16 seconds
Started Dec 24 01:27:55 PM PST 23
Finished Dec 24 01:28:28 PM PST 23
Peak memory 248804 kb
Host smart-52180e9d-a94f-4355-b9e4-8aa2b24568a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17699
82614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1769982614
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1950218310
Short name T11
Test name
Test status
Simulation time 233351680 ps
CPU time 13.02 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 01:28:36 PM PST 23
Peak memory 277504 kb
Host smart-724da195-0f96-4ec4-8111-4910dcb81b4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1950218310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1950218310
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1451694572
Short name T468
Test name
Test status
Simulation time 512587543 ps
CPU time 9.53 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 01:28:07 PM PST 23
Peak memory 248608 kb
Host smart-15abd9ab-ee06-4695-8852-65bb39fffbfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
94572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1451694572
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.208699839
Short name T463
Test name
Test status
Simulation time 1209898030 ps
CPU time 32.99 seconds
Started Dec 24 01:27:55 PM PST 23
Finished Dec 24 01:28:29 PM PST 23
Peak memory 248608 kb
Host smart-621a75d9-34a0-4f68-8d6f-e598c260a25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20869
9839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.208699839
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4044908396
Short name T695
Test name
Test status
Simulation time 2662323206 ps
CPU time 39.51 seconds
Started Dec 24 01:27:57 PM PST 23
Finished Dec 24 01:28:37 PM PST 23
Peak memory 248656 kb
Host smart-d9163064-1fcd-464b-b7cc-14a879a763a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044908396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4044908396
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3686127046
Short name T122
Test name
Test status
Simulation time 61814647936 ps
CPU time 3656.55 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 02:29:21 PM PST 23
Peak memory 332120 kb
Host smart-de790276-9cd8-48f1-bcb2-00f641548114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686127046 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3686127046
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4280144580
Short name T594
Test name
Test status
Simulation time 439326045296 ps
CPU time 2263.44 seconds
Started Dec 24 01:30:30 PM PST 23
Finished Dec 24 02:08:14 PM PST 23
Peak memory 272844 kb
Host smart-52394e8f-c672-40b3-9f1b-4e2c54e39eb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280144580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4280144580
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2757931551
Short name T418
Test name
Test status
Simulation time 6707570293 ps
CPU time 151.5 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:33:05 PM PST 23
Peak memory 256188 kb
Host smart-00247e8c-a0dd-4dcd-b52c-d219a28c8b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27579
31551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2757931551
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2890774631
Short name T80
Test name
Test status
Simulation time 1061035051 ps
CPU time 24.49 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 01:30:50 PM PST 23
Peak memory 254808 kb
Host smart-6450693d-6fc8-4b28-b9a4-392279a2293f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28907
74631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2890774631
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.218142268
Short name T586
Test name
Test status
Simulation time 5301441833 ps
CPU time 578.93 seconds
Started Dec 24 01:30:27 PM PST 23
Finished Dec 24 01:40:07 PM PST 23
Peak memory 264476 kb
Host smart-e265b886-f92e-457d-be71-b00ab1ef5214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218142268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.218142268
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3910192460
Short name T128
Test name
Test status
Simulation time 1035418078 ps
CPU time 59.71 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 01:31:41 PM PST 23
Peak memory 248584 kb
Host smart-85f40d00-bff0-416e-86fa-8754728d404b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39101
92460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3910192460
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2305983299
Short name T642
Test name
Test status
Simulation time 517229122 ps
CPU time 10.31 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 01:30:35 PM PST 23
Peak memory 246688 kb
Host smart-ed83870b-cd43-41a7-adee-e4420f1250c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23059
83299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2305983299
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.678877326
Short name T719
Test name
Test status
Simulation time 1458107670 ps
CPU time 39.05 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:31:12 PM PST 23
Peak memory 248680 kb
Host smart-1ea1e5c1-231b-433a-b9cd-549eb4816dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67887
7326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.678877326
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3242926778
Short name T505
Test name
Test status
Simulation time 110507323208 ps
CPU time 1871.05 seconds
Started Dec 24 01:30:31 PM PST 23
Finished Dec 24 02:01:43 PM PST 23
Peak memory 289708 kb
Host smart-a6a51436-18b8-4ccc-a197-18bbf67a5434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242926778 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3242926778
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3657942906
Short name T513
Test name
Test status
Simulation time 24988142173 ps
CPU time 1632.56 seconds
Started Dec 24 01:30:31 PM PST 23
Finished Dec 24 01:57:45 PM PST 23
Peak memory 272676 kb
Host smart-c1e901a0-f509-441f-8261-3bf2dfdcd99c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657942906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3657942906
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2513258272
Short name T621
Test name
Test status
Simulation time 4790288011 ps
CPU time 273.57 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 01:35:14 PM PST 23
Peak memory 256168 kb
Host smart-b428822a-b034-4231-88ef-3d47bf588b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25132
58272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2513258272
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1551254965
Short name T396
Test name
Test status
Simulation time 279303897 ps
CPU time 10.8 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 01:30:52 PM PST 23
Peak memory 252492 kb
Host smart-5681276c-e7a3-4b14-b376-f0fd17dd81b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15512
54965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1551254965
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2915764184
Short name T531
Test name
Test status
Simulation time 103187502320 ps
CPU time 1015.22 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:47:38 PM PST 23
Peak memory 283104 kb
Host smart-c09fb189-c16a-49f4-ab27-e3fb2aec8d3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915764184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2915764184
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3847877832
Short name T271
Test name
Test status
Simulation time 54353767059 ps
CPU time 278.53 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:35:17 PM PST 23
Peak memory 247432 kb
Host smart-0afe328a-594e-4a2b-a5d4-c74232cd4dd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847877832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3847877832
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.441685491
Short name T67
Test name
Test status
Simulation time 952043524 ps
CPU time 19.83 seconds
Started Dec 24 01:30:33 PM PST 23
Finished Dec 24 01:30:54 PM PST 23
Peak memory 248612 kb
Host smart-16f11075-56bc-4e47-b514-aa1f2e412a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44168
5491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.441685491
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4097976166
Short name T342
Test name
Test status
Simulation time 384903185 ps
CPU time 9.45 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:30:43 PM PST 23
Peak memory 248156 kb
Host smart-0559c2ae-9b39-4905-9bb9-826aa0f6b25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40979
76166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4097976166
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3404850247
Short name T300
Test name
Test status
Simulation time 5775308405 ps
CPU time 42.5 seconds
Started Dec 24 01:30:31 PM PST 23
Finished Dec 24 01:31:15 PM PST 23
Peak memory 247876 kb
Host smart-a975a139-19c5-493b-8df1-6c033bcde793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
50247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3404850247
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1340961701
Short name T89
Test name
Test status
Simulation time 1627088126 ps
CPU time 20.93 seconds
Started Dec 24 01:30:38 PM PST 23
Finished Dec 24 01:31:01 PM PST 23
Peak memory 248432 kb
Host smart-713d5a7a-4070-47d6-b300-a267f5ff3811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13409
61701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1340961701
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3851280471
Short name T63
Test name
Test status
Simulation time 62049339390 ps
CPU time 1521.15 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:55:54 PM PST 23
Peak memory 288824 kb
Host smart-f64ea180-117e-4e40-a496-c6468e2a3bf2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851280471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3851280471
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.94391533
Short name T451
Test name
Test status
Simulation time 10045775675 ps
CPU time 1226.1 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:51:11 PM PST 23
Peak memory 289144 kb
Host smart-82ccb0f3-7127-4a5e-a414-294afa80df58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94391533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.94391533
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.707801162
Short name T478
Test name
Test status
Simulation time 237113523 ps
CPU time 5.22 seconds
Started Dec 24 01:30:35 PM PST 23
Finished Dec 24 01:30:41 PM PST 23
Peak memory 240348 kb
Host smart-e8ec8e4f-a9b7-44fe-92ab-b4226ad8e147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70780
1162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.707801162
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.389066878
Short name T644
Test name
Test status
Simulation time 3971543678 ps
CPU time 57.56 seconds
Started Dec 24 01:30:25 PM PST 23
Finished Dec 24 01:31:23 PM PST 23
Peak memory 256248 kb
Host smart-d15120d1-22a4-480f-a636-142a876423a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906
6878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.389066878
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3803379417
Short name T564
Test name
Test status
Simulation time 36504154185 ps
CPU time 1921.3 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 02:02:41 PM PST 23
Peak memory 273272 kb
Host smart-4750ac11-e07c-4dd7-b0f7-e4c5434d20a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803379417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3803379417
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3920497324
Short name T270
Test name
Test status
Simulation time 10942029000 ps
CPU time 444.44 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:38:10 PM PST 23
Peak memory 247516 kb
Host smart-ef9fa954-73bc-48a0-b606-88385ffb6cd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920497324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3920497324
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1265272538
Short name T697
Test name
Test status
Simulation time 576258039 ps
CPU time 33.59 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:31:07 PM PST 23
Peak memory 255352 kb
Host smart-112bdb77-8714-4bb5-a128-c24e6eae7ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12652
72538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1265272538
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2632525490
Short name T55
Test name
Test status
Simulation time 571372982 ps
CPU time 19.5 seconds
Started Dec 24 01:30:24 PM PST 23
Finished Dec 24 01:30:45 PM PST 23
Peak memory 254672 kb
Host smart-7b0d8994-0270-4158-ac95-0383c01b0df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325
25490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2632525490
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4040677874
Short name T467
Test name
Test status
Simulation time 2647866307 ps
CPU time 42.19 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:31:15 PM PST 23
Peak memory 248748 kb
Host smart-62806b70-1705-497e-a868-b4151dc56727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40406
77874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4040677874
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1107142915
Short name T469
Test name
Test status
Simulation time 1425437574 ps
CPU time 21.77 seconds
Started Dec 24 01:30:32 PM PST 23
Finished Dec 24 01:30:55 PM PST 23
Peak memory 248612 kb
Host smart-4d545fa4-5a0d-4179-8e97-7e31ac488124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11071
42915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1107142915
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.175301806
Short name T112
Test name
Test status
Simulation time 12978304663 ps
CPU time 1354.58 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:53:17 PM PST 23
Peak memory 289720 kb
Host smart-07248698-3b6d-4629-904e-7840d498b43b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175301806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.175301806
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.586837276
Short name T60
Test name
Test status
Simulation time 184069469335 ps
CPU time 2788.67 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 02:17:10 PM PST 23
Peak memory 289812 kb
Host smart-85aeb3b7-ad03-4732-9430-4a93b49e85c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586837276 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.586837276
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3812271851
Short name T700
Test name
Test status
Simulation time 7135712309 ps
CPU time 233.51 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:34:36 PM PST 23
Peak memory 256916 kb
Host smart-4f197166-34fa-467c-9f2c-472f9be256d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38122
71851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3812271851
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4185115237
Short name T548
Test name
Test status
Simulation time 1086759315 ps
CPU time 38.93 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:31:17 PM PST 23
Peak memory 255184 kb
Host smart-114511c9-8ab8-48eb-b714-65f3a10b75c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41851
15237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4185115237
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2187478398
Short name T517
Test name
Test status
Simulation time 250840010614 ps
CPU time 1279.58 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:52:04 PM PST 23
Peak memory 288984 kb
Host smart-e73a6419-e5c7-4dec-9e5c-4f13b3a19cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187478398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2187478398
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.353039109
Short name T263
Test name
Test status
Simulation time 21971869166 ps
CPU time 227.09 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 01:34:28 PM PST 23
Peak memory 246660 kb
Host smart-0eca124a-7f89-4675-ac70-d047382cd457
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353039109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.353039109
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.896714740
Short name T215
Test name
Test status
Simulation time 3989352219 ps
CPU time 56.36 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:31:34 PM PST 23
Peak memory 248676 kb
Host smart-efb65181-beed-4d0c-baad-78283c5a9dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89671
4740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.896714740
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.370345881
Short name T588
Test name
Test status
Simulation time 1570999436 ps
CPU time 27.52 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:31:07 PM PST 23
Peak memory 256688 kb
Host smart-d3da5d42-e702-4dcd-a7c3-33e9739fed2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37034
5881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.370345881
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2195925343
Short name T571
Test name
Test status
Simulation time 1702265172 ps
CPU time 18.42 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:31:02 PM PST 23
Peak memory 248584 kb
Host smart-821674a1-a07f-4c8f-bb0c-dbe8a40a7843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959
25343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2195925343
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3128515419
Short name T498
Test name
Test status
Simulation time 312602648 ps
CPU time 6.08 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:30:48 PM PST 23
Peak memory 248572 kb
Host smart-59481d5f-1887-4bd0-93a6-18fa38126b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31285
15419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3128515419
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1634090930
Short name T296
Test name
Test status
Simulation time 30554744508 ps
CPU time 1294.76 seconds
Started Dec 24 01:30:40 PM PST 23
Finished Dec 24 01:52:16 PM PST 23
Peak memory 289220 kb
Host smart-1433554a-85d2-435c-994d-eeaacb059894
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634090930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1634090930
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2496433521
Short name T123
Test name
Test status
Simulation time 45729258438 ps
CPU time 4012.58 seconds
Started Dec 24 01:30:38 PM PST 23
Finished Dec 24 02:37:33 PM PST 23
Peak memory 322276 kb
Host smart-0426f654-5391-4949-bdcb-b0107661eadc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496433521 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2496433521
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1385375622
Short name T544
Test name
Test status
Simulation time 8430709385 ps
CPU time 854.27 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:44:57 PM PST 23
Peak memory 273200 kb
Host smart-4b4958d4-3173-4594-b9e9-86c2a0a53805
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385375622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1385375622
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2789413192
Short name T669
Test name
Test status
Simulation time 5443523195 ps
CPU time 126.49 seconds
Started Dec 24 01:30:45 PM PST 23
Finished Dec 24 01:32:53 PM PST 23
Peak memory 256856 kb
Host smart-45437aa8-241d-4e72-aadc-08408208bc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
13192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2789413192
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.296305418
Short name T526
Test name
Test status
Simulation time 341253520 ps
CPU time 9.52 seconds
Started Dec 24 01:30:38 PM PST 23
Finished Dec 24 01:30:49 PM PST 23
Peak memory 248128 kb
Host smart-3f7b3ed8-ae5e-4e34-8134-e7e61abd0fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
5418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.296305418
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1696659718
Short name T315
Test name
Test status
Simulation time 27788249452 ps
CPU time 1608.19 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 01:57:34 PM PST 23
Peak memory 273112 kb
Host smart-f5206384-8aae-41c5-89b4-285c0ffe358a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696659718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1696659718
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3716797634
Short name T97
Test name
Test status
Simulation time 99302723025 ps
CPU time 2174.21 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 02:07:01 PM PST 23
Peak memory 272468 kb
Host smart-582f0f1c-1e48-4415-ab33-d1eb9e9e03a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716797634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3716797634
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.83068985
Short name T94
Test name
Test status
Simulation time 550888928 ps
CPU time 32.29 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:31:15 PM PST 23
Peak memory 255572 kb
Host smart-e77b3b39-c790-45b5-a1c0-f3beeb4eecfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83068
985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.83068985
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.155304557
Short name T632
Test name
Test status
Simulation time 3164956489 ps
CPU time 20.12 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:31:04 PM PST 23
Peak memory 247040 kb
Host smart-60d7bdbe-d84f-4ea8-a23a-6944a735ef39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530
4557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.155304557
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.461542391
Short name T725
Test name
Test status
Simulation time 932825933 ps
CPU time 22.77 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 01:31:03 PM PST 23
Peak memory 255420 kb
Host smart-ed252b56-1613-4e7c-8f3b-be4531fea1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46154
2391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.461542391
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2407237444
Short name T465
Test name
Test status
Simulation time 3750949280 ps
CPU time 45.9 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:31:30 PM PST 23
Peak memory 248784 kb
Host smart-beb113b7-20a0-4110-b711-5db7d8cbf615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24072
37444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2407237444
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2618863411
Short name T110
Test name
Test status
Simulation time 2533638402 ps
CPU time 148.39 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:33:14 PM PST 23
Peak memory 256840 kb
Host smart-b1f82c65-1b7e-4d3b-b65f-3dce6badd8d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618863411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2618863411
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2760236657
Short name T541
Test name
Test status
Simulation time 34467698040 ps
CPU time 2194.57 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 286364 kb
Host smart-55e5b44c-3a26-42dd-a07f-ef18dc01a9cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760236657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2760236657
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.445340314
Short name T500
Test name
Test status
Simulation time 1386575446 ps
CPU time 109.5 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:32:32 PM PST 23
Peak memory 256408 kb
Host smart-22b179b4-91ba-4ab7-bf7a-dbb31b40c186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44534
0314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.445340314
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.162482992
Short name T424
Test name
Test status
Simulation time 192585349 ps
CPU time 21.02 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 01:31:07 PM PST 23
Peak memory 253416 kb
Host smart-2fb62d9d-0aff-4a3d-ae98-707463d2a735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16248
2992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.162482992
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2341739045
Short name T277
Test name
Test status
Simulation time 113305494911 ps
CPU time 1558.69 seconds
Started Dec 24 01:30:36 PM PST 23
Finished Dec 24 01:56:36 PM PST 23
Peak memory 288412 kb
Host smart-b43d0414-6b9e-4ac0-8f09-e59ee65f575a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341739045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2341739045
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2045037184
Short name T661
Test name
Test status
Simulation time 144085729750 ps
CPU time 1565.47 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 287412 kb
Host smart-c9a50f04-ab77-414f-a4a1-941f419cb099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045037184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2045037184
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3807963880
Short name T645
Test name
Test status
Simulation time 12236631759 ps
CPU time 475.19 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:38:37 PM PST 23
Peak memory 246592 kb
Host smart-a6d73b8c-6c9d-48c0-a4b3-64de4cc76227
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807963880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3807963880
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1433339853
Short name T436
Test name
Test status
Simulation time 2419622493 ps
CPU time 40.58 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 01:31:27 PM PST 23
Peak memory 255328 kb
Host smart-89cba1e7-0261-40b4-b4f9-7eeac3d026be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14333
39853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1433339853
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2022345481
Short name T461
Test name
Test status
Simulation time 940081436 ps
CPU time 19.1 seconds
Started Dec 24 01:30:46 PM PST 23
Finished Dec 24 01:31:06 PM PST 23
Peak memory 254504 kb
Host smart-89da4fbe-6377-45c4-8e5e-60aefab89a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20223
45481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2022345481
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4094598218
Short name T18
Test name
Test status
Simulation time 314370793 ps
CPU time 10.81 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:30:55 PM PST 23
Peak memory 253260 kb
Host smart-0b3f24bd-0df1-42a8-9392-7f3c969e3f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40945
98218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4094598218
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1753628732
Short name T344
Test name
Test status
Simulation time 311778046 ps
CPU time 30.21 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:31:16 PM PST 23
Peak memory 248624 kb
Host smart-43314a1f-3747-4f75-a633-5c629af990b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17536
28732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1753628732
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2162442644
Short name T422
Test name
Test status
Simulation time 8671889469 ps
CPU time 450.17 seconds
Started Dec 24 01:30:38 PM PST 23
Finished Dec 24 01:38:10 PM PST 23
Peak memory 254776 kb
Host smart-7ee36ab9-a8ea-485b-9c3d-7f636b9e40ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162442644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2162442644
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.333852075
Short name T93
Test name
Test status
Simulation time 336508621562 ps
CPU time 2135.1 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 02:06:21 PM PST 23
Peak memory 289720 kb
Host smart-11a5478b-e30a-471a-8c11-e616b5340fc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333852075 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.333852075
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3451271571
Short name T453
Test name
Test status
Simulation time 33306938160 ps
CPU time 2046.36 seconds
Started Dec 24 01:30:36 PM PST 23
Finished Dec 24 02:04:44 PM PST 23
Peak memory 284520 kb
Host smart-59667a1b-ff2b-429a-9439-7cc4ca399a53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451271571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3451271571
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4265374988
Short name T587
Test name
Test status
Simulation time 13861794129 ps
CPU time 96.07 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:32:19 PM PST 23
Peak memory 248372 kb
Host smart-fc3e2ba2-ff1f-4b17-848e-b706c6144069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42653
74988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4265374988
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2825810119
Short name T33
Test name
Test status
Simulation time 1251541088 ps
CPU time 65.14 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:31:47 PM PST 23
Peak memory 256164 kb
Host smart-4e590546-d886-40ee-a69f-2b6545baebf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28258
10119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2825810119
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3349917580
Short name T509
Test name
Test status
Simulation time 68219440480 ps
CPU time 1870.58 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 02:01:57 PM PST 23
Peak memory 284228 kb
Host smart-fcbc00d9-cca9-460e-92f0-1f4145ef7b43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349917580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3349917580
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.310308029
Short name T650
Test name
Test status
Simulation time 42044191618 ps
CPU time 2299.56 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 273268 kb
Host smart-a1a2e27e-b4d8-4b5a-9eed-3f17621f4ea5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310308029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.310308029
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1051486739
Short name T278
Test name
Test status
Simulation time 31077569379 ps
CPU time 150.51 seconds
Started Dec 24 01:30:38 PM PST 23
Finished Dec 24 01:33:10 PM PST 23
Peak memory 247136 kb
Host smart-217c6337-1a06-4f76-8029-f9fe2db8a482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051486739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1051486739
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.922339313
Short name T679
Test name
Test status
Simulation time 488645231 ps
CPU time 10.32 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:30:53 PM PST 23
Peak memory 248532 kb
Host smart-8fe8e395-cda7-4212-bd20-b5f1aa330b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92233
9313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.922339313
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1868927034
Short name T547
Test name
Test status
Simulation time 133043109 ps
CPU time 7.79 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:30:50 PM PST 23
Peak memory 246988 kb
Host smart-b6d5c584-5641-4e27-8aa4-768da7b2a90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
27034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1868927034
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.279492359
Short name T554
Test name
Test status
Simulation time 2895325425 ps
CPU time 26.07 seconds
Started Dec 24 01:30:36 PM PST 23
Finished Dec 24 01:31:03 PM PST 23
Peak memory 254836 kb
Host smart-f460e35c-c94a-4e8a-b15f-976f24ffbbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27949
2359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.279492359
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3412603883
Short name T566
Test name
Test status
Simulation time 272017029 ps
CPU time 4.98 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 01:30:51 PM PST 23
Peak memory 238820 kb
Host smart-d6b06f34-05a2-4bfd-a48e-325ea34d920c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126
03883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3412603883
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1253761994
Short name T251
Test name
Test status
Simulation time 765083596 ps
CPU time 76.13 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:31:58 PM PST 23
Peak memory 249756 kb
Host smart-a9352c32-91c3-40de-97d0-a431693b9e5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253761994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1253761994
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.861686499
Short name T253
Test name
Test status
Simulation time 33951731034 ps
CPU time 2139.1 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 02:06:23 PM PST 23
Peak memory 289160 kb
Host smart-bec5570e-5055-4bc8-91fb-1d3855fe5a9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861686499 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.861686499
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4234678832
Short name T384
Test name
Test status
Simulation time 17535677951 ps
CPU time 914.11 seconds
Started Dec 24 01:30:39 PM PST 23
Finished Dec 24 01:45:55 PM PST 23
Peak memory 269496 kb
Host smart-af15eb27-1b18-400d-9d8d-f25e6b6a1cf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234678832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4234678832
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1642740059
Short name T538
Test name
Test status
Simulation time 1901560219 ps
CPU time 104.64 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:32:23 PM PST 23
Peak memory 248044 kb
Host smart-c5f471ff-2512-4757-b584-0ab542e89779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16427
40059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1642740059
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2944439070
Short name T434
Test name
Test status
Simulation time 2053543903 ps
CPU time 31.03 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:31:13 PM PST 23
Peak memory 254352 kb
Host smart-401c5ca0-0ac0-4fec-abee-f1264627a458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29444
39070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2944439070
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3982996705
Short name T256
Test name
Test status
Simulation time 109752106101 ps
CPU time 1499.11 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 01:55:46 PM PST 23
Peak memory 271896 kb
Host smart-fd2c0e6d-a1eb-45c0-8da1-0caa1d3e75da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982996705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3982996705
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3923771250
Short name T343
Test name
Test status
Simulation time 37559258645 ps
CPU time 986.93 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:47:12 PM PST 23
Peak memory 272548 kb
Host smart-6102519d-67d0-4b1f-9d96-559cff4024a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923771250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3923771250
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2225088733
Short name T266
Test name
Test status
Simulation time 68883705838 ps
CPU time 489.55 seconds
Started Dec 24 01:30:36 PM PST 23
Finished Dec 24 01:38:47 PM PST 23
Peak memory 247512 kb
Host smart-9d7d2d2c-042c-4058-ab14-cc03a7adeb42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225088733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2225088733
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.249140563
Short name T590
Test name
Test status
Simulation time 2157973273 ps
CPU time 38.57 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:31:24 PM PST 23
Peak memory 248704 kb
Host smart-5d39e809-fe5e-422d-84f5-6aba43230a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24914
0563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.249140563
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1620900269
Short name T483
Test name
Test status
Simulation time 335015346 ps
CPU time 25.82 seconds
Started Dec 24 01:30:43 PM PST 23
Finished Dec 24 01:31:11 PM PST 23
Peak memory 254280 kb
Host smart-53cae145-c95e-40f5-8c93-7bce85e0e9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16209
00269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1620900269
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4009549444
Short name T404
Test name
Test status
Simulation time 326476222 ps
CPU time 6.85 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:30:49 PM PST 23
Peak memory 251076 kb
Host smart-c406ad0b-52ed-4537-96e7-a6786c7aed69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40095
49444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4009549444
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2486914551
Short name T32
Test name
Test status
Simulation time 195340928 ps
CPU time 12.44 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:30:55 PM PST 23
Peak memory 248572 kb
Host smart-7973bfd7-b302-4762-bd82-f34aba7e76ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24869
14551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2486914551
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.868241703
Short name T713
Test name
Test status
Simulation time 10451459807 ps
CPU time 579.66 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:40:24 PM PST 23
Peak memory 254892 kb
Host smart-da79a97f-77d3-448c-bee3-8843f2f19d9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868241703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.868241703
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3265306683
Short name T106
Test name
Test status
Simulation time 33713565701 ps
CPU time 1737.81 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:59:42 PM PST 23
Peak memory 287436 kb
Host smart-ca37e929-4e91-45c8-a7c8-ce55d7b57224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265306683 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3265306683
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3467315348
Short name T40
Test name
Test status
Simulation time 12682575465 ps
CPU time 1254.51 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:51:34 PM PST 23
Peak memory 286612 kb
Host smart-11ee32bf-e260-4ce3-a5ae-506d2a6603a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467315348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3467315348
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2089115192
Short name T19
Test name
Test status
Simulation time 10010382020 ps
CPU time 260.11 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:34:58 PM PST 23
Peak memory 250748 kb
Host smart-ff30539a-66a7-4b29-b2f0-3c28b8ce4b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20891
15192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2089115192
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3732018499
Short name T507
Test name
Test status
Simulation time 802698211 ps
CPU time 51.23 seconds
Started Dec 24 01:30:42 PM PST 23
Finished Dec 24 01:31:35 PM PST 23
Peak memory 255116 kb
Host smart-9b99ac23-dd55-485e-8a68-cbb29ada9e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37320
18499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3732018499
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1631013649
Short name T314
Test name
Test status
Simulation time 106082846921 ps
CPU time 3147.33 seconds
Started Dec 24 01:30:47 PM PST 23
Finished Dec 24 02:23:15 PM PST 23
Peak memory 289072 kb
Host smart-6418ae47-0b9f-49af-a2bf-c4c6a449573b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631013649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1631013649
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2933209646
Short name T356
Test name
Test status
Simulation time 13403236533 ps
CPU time 1192.64 seconds
Started Dec 24 01:31:06 PM PST 23
Finished Dec 24 01:51:03 PM PST 23
Peak memory 288756 kb
Host smart-0266fa30-8444-423a-ab8f-892b58459262
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933209646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2933209646
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.679136195
Short name T417
Test name
Test status
Simulation time 2010148917 ps
CPU time 12.12 seconds
Started Dec 24 01:30:41 PM PST 23
Finished Dec 24 01:30:55 PM PST 23
Peak memory 248712 kb
Host smart-8fee1d6c-09a9-4ede-86d2-10e198135fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67913
6195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.679136195
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3558546643
Short name T611
Test name
Test status
Simulation time 510565820 ps
CPU time 18.21 seconds
Started Dec 24 01:30:37 PM PST 23
Finished Dec 24 01:30:56 PM PST 23
Peak memory 251516 kb
Host smart-d041f5f5-e3f2-48de-b927-8fd06e40e21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35585
46643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3558546643
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.4199109274
Short name T491
Test name
Test status
Simulation time 241297417 ps
CPU time 27.35 seconds
Started Dec 24 01:30:40 PM PST 23
Finished Dec 24 01:31:09 PM PST 23
Peak memory 247880 kb
Host smart-3cc8456a-59bd-4b92-bff6-5ade59b9b1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41991
09274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.4199109274
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1462641272
Short name T348
Test name
Test status
Simulation time 1127240051 ps
CPU time 36.03 seconds
Started Dec 24 01:30:44 PM PST 23
Finished Dec 24 01:31:22 PM PST 23
Peak memory 248636 kb
Host smart-8470e2c8-2c6c-42e5-97e0-440c3ccdd278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14626
41272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1462641272
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2209702957
Short name T222
Test name
Test status
Simulation time 125551510201 ps
CPU time 1063.36 seconds
Started Dec 24 01:30:48 PM PST 23
Finished Dec 24 01:48:32 PM PST 23
Peak memory 287316 kb
Host smart-e5f60515-c267-4253-9c62-c692273e682b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209702957 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2209702957
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.821773451
Short name T662
Test name
Test status
Simulation time 51573092752 ps
CPU time 1240.05 seconds
Started Dec 24 01:30:56 PM PST 23
Finished Dec 24 01:51:42 PM PST 23
Peak memory 288788 kb
Host smart-25add850-448d-48bd-b6fc-e59606e6b77d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821773451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.821773451
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1821553016
Short name T710
Test name
Test status
Simulation time 5720987326 ps
CPU time 287.21 seconds
Started Dec 24 01:30:47 PM PST 23
Finished Dec 24 01:35:35 PM PST 23
Peak memory 256228 kb
Host smart-d56789f7-09f0-4362-90a0-80d06db592f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18215
53016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1821553016
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2342618855
Short name T574
Test name
Test status
Simulation time 1056797912 ps
CPU time 27.3 seconds
Started Dec 24 01:30:46 PM PST 23
Finished Dec 24 01:31:14 PM PST 23
Peak memory 255120 kb
Host smart-f9624f46-ba98-4ca1-834f-2b5a183a145d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23426
18855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2342618855
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.849726175
Short name T689
Test name
Test status
Simulation time 24291041563 ps
CPU time 499.12 seconds
Started Dec 24 01:30:47 PM PST 23
Finished Dec 24 01:39:07 PM PST 23
Peak memory 264892 kb
Host smart-6b610c28-0313-4960-a76c-de0406c01476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849726175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.849726175
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3889450525
Short name T668
Test name
Test status
Simulation time 12926477443 ps
CPU time 492.39 seconds
Started Dec 24 01:30:53 PM PST 23
Finished Dec 24 01:39:06 PM PST 23
Peak memory 248664 kb
Host smart-19ec9c92-6927-4b51-84d3-9df7af341949
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889450525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3889450525
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2833367448
Short name T506
Test name
Test status
Simulation time 2044116280 ps
CPU time 36.93 seconds
Started Dec 24 01:30:48 PM PST 23
Finished Dec 24 01:31:25 PM PST 23
Peak memory 248688 kb
Host smart-7cc1d133-65c4-41e1-a61a-bc85d01cad38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28333
67448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2833367448
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1352656233
Short name T247
Test name
Test status
Simulation time 1603788672 ps
CPU time 31.98 seconds
Started Dec 24 01:30:53 PM PST 23
Finished Dec 24 01:31:26 PM PST 23
Peak memory 255944 kb
Host smart-bc563f29-69a9-4028-bc86-583f32a2a6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526
56233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1352656233
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.693671258
Short name T303
Test name
Test status
Simulation time 140194493 ps
CPU time 17.33 seconds
Started Dec 24 01:30:47 PM PST 23
Finished Dec 24 01:31:06 PM PST 23
Peak memory 247052 kb
Host smart-97d3cfc9-f4a1-4832-b8ab-314f400c103c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69367
1258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.693671258
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2410369084
Short name T575
Test name
Test status
Simulation time 230868433 ps
CPU time 2.79 seconds
Started Dec 24 01:30:56 PM PST 23
Finished Dec 24 01:31:05 PM PST 23
Peak memory 240512 kb
Host smart-793e4db3-b76a-4b78-b82c-d7c05d237eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24103
69084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2410369084
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1676873941
Short name T403
Test name
Test status
Simulation time 36279618845 ps
CPU time 987.3 seconds
Started Dec 24 01:30:57 PM PST 23
Finished Dec 24 01:47:33 PM PST 23
Peak memory 281440 kb
Host smart-f5b7ce78-69c7-4384-b471-c369dacc2046
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676873941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1676873941
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3855425358
Short name T48
Test name
Test status
Simulation time 35024459506 ps
CPU time 1104.93 seconds
Started Dec 24 01:30:47 PM PST 23
Finished Dec 24 01:49:13 PM PST 23
Peak memory 269508 kb
Host smart-26a96d24-9376-43a2-9918-abcbe62dc2ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855425358 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3855425358
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2325687639
Short name T200
Test name
Test status
Simulation time 22107855 ps
CPU time 2.5 seconds
Started Dec 24 01:28:08 PM PST 23
Finished Dec 24 01:28:19 PM PST 23
Peak memory 248816 kb
Host smart-bdfd86ef-aa3d-4fd8-959c-1318ec9e90bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2325687639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2325687639
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1071836070
Short name T470
Test name
Test status
Simulation time 105388330773 ps
CPU time 1682.46 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 01:56:23 PM PST 23
Peak memory 273184 kb
Host smart-b23042ae-1cb5-418d-bc9d-db0e0608fc27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071836070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1071836070
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.716766415
Short name T399
Test name
Test status
Simulation time 278188082 ps
CPU time 13.55 seconds
Started Dec 24 01:28:17 PM PST 23
Finished Dec 24 01:28:36 PM PST 23
Peak memory 240464 kb
Host smart-12ce87a6-24d1-4d17-bd34-f6aeb10b86c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=716766415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.716766415
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2836865886
Short name T481
Test name
Test status
Simulation time 346010513 ps
CPU time 34.42 seconds
Started Dec 24 01:28:09 PM PST 23
Finished Dec 24 01:28:53 PM PST 23
Peak memory 247920 kb
Host smart-adb5a45a-2e63-4d9a-b70f-ad9cef9f0ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28368
65886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2836865886
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2693214773
Short name T577
Test name
Test status
Simulation time 1151476809 ps
CPU time 35.08 seconds
Started Dec 24 01:28:12 PM PST 23
Finished Dec 24 01:28:55 PM PST 23
Peak memory 254696 kb
Host smart-907dd17f-ae11-4d07-b6c4-16a889b05cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932
14773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2693214773
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3115747916
Short name T319
Test name
Test status
Simulation time 177318054652 ps
CPU time 2715.35 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 02:13:39 PM PST 23
Peak memory 288828 kb
Host smart-b67697cc-a17a-422e-bb48-938c2a9768f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115747916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3115747916
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.884303662
Short name T354
Test name
Test status
Simulation time 46522613744 ps
CPU time 809.94 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 272204 kb
Host smart-2c494005-6aec-45a9-8291-8e4be6f613eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884303662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.884303662
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2659336531
Short name T267
Test name
Test status
Simulation time 9282310707 ps
CPU time 381.09 seconds
Started Dec 24 01:28:11 PM PST 23
Finished Dec 24 01:34:41 PM PST 23
Peak memory 247296 kb
Host smart-414ac4ae-b388-4b18-a6a5-2aa7fcc1c830
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659336531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2659336531
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3685044413
Short name T388
Test name
Test status
Simulation time 148533205 ps
CPU time 5.67 seconds
Started Dec 24 01:28:18 PM PST 23
Finished Dec 24 01:28:29 PM PST 23
Peak memory 240352 kb
Host smart-6d021c85-6e98-4425-b2fb-63c3ef35294f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36850
44413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3685044413
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3587024690
Short name T712
Test name
Test status
Simulation time 4919721133 ps
CPU time 36.08 seconds
Started Dec 24 01:28:12 PM PST 23
Finished Dec 24 01:28:57 PM PST 23
Peak memory 248784 kb
Host smart-d1f7e773-e8e6-43c0-a3cd-f18e16a32c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35870
24690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3587024690
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.155983385
Short name T10
Test name
Test status
Simulation time 687831843 ps
CPU time 21.94 seconds
Started Dec 24 01:28:09 PM PST 23
Finished Dec 24 01:28:41 PM PST 23
Peak memory 264240 kb
Host smart-9153e9ba-8eb7-4275-970c-b56b4b4e1b40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=155983385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.155983385
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1633152680
Short name T608
Test name
Test status
Simulation time 356585589 ps
CPU time 7.32 seconds
Started Dec 24 01:28:08 PM PST 23
Finished Dec 24 01:28:23 PM PST 23
Peak memory 250156 kb
Host smart-3b0d5b7f-9314-4aec-8608-b4c0a45f7511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16331
52680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1633152680
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.66504085
Short name T129
Test name
Test status
Simulation time 715213723 ps
CPU time 41.65 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 01:29:02 PM PST 23
Peak memory 248608 kb
Host smart-ed2b9cdc-8da3-43c8-93cd-93c44504cc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66504
085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.66504085
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4020804060
Short name T131
Test name
Test status
Simulation time 150661352229 ps
CPU time 2496.79 seconds
Started Dec 24 01:28:09 PM PST 23
Finished Dec 24 02:09:57 PM PST 23
Peak memory 289600 kb
Host smart-1c8c5122-0dd7-4889-865d-d7c31cda36a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020804060 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4020804060
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.439656796
Short name T69
Test name
Test status
Simulation time 100581765182 ps
CPU time 1717.21 seconds
Started Dec 24 01:30:45 PM PST 23
Finished Dec 24 01:59:24 PM PST 23
Peak memory 273428 kb
Host smart-1b15e283-9cbd-47de-971f-9ce6f0068cf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439656796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.439656796
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.4064400089
Short name T408
Test name
Test status
Simulation time 3824751564 ps
CPU time 126.66 seconds
Started Dec 24 01:30:56 PM PST 23
Finished Dec 24 01:33:09 PM PST 23
Peak memory 248288 kb
Host smart-bd236e53-17b0-4eb2-9780-42bca97f9b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40644
00089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.4064400089
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.585654763
Short name T520
Test name
Test status
Simulation time 109788527 ps
CPU time 10.17 seconds
Started Dec 24 01:30:47 PM PST 23
Finished Dec 24 01:30:58 PM PST 23
Peak memory 253860 kb
Host smart-9d6e1c3b-d320-41ba-a1b8-ced991c27829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58565
4763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.585654763
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.188446446
Short name T257
Test name
Test status
Simulation time 77930566579 ps
CPU time 2088.24 seconds
Started Dec 24 01:31:08 PM PST 23
Finished Dec 24 02:06:04 PM PST 23
Peak memory 281468 kb
Host smart-bf9ede7a-2680-4bcb-a9c7-932a360279ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188446446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.188446446
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1597115098
Short name T521
Test name
Test status
Simulation time 56422805627 ps
CPU time 1885.87 seconds
Started Dec 24 01:30:56 PM PST 23
Finished Dec 24 02:02:28 PM PST 23
Peak memory 289064 kb
Host smart-3e5454f6-d56e-493c-9659-d46612685932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597115098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1597115098
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1557417523
Short name T269
Test name
Test status
Simulation time 68404149198 ps
CPU time 413.42 seconds
Started Dec 24 01:30:52 PM PST 23
Finished Dec 24 01:37:46 PM PST 23
Peak memory 247284 kb
Host smart-419a68e2-d718-4c50-af9c-bc47d1e9a382
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557417523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1557417523
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2003951851
Short name T589
Test name
Test status
Simulation time 1781645507 ps
CPU time 27.53 seconds
Started Dec 24 01:31:05 PM PST 23
Finished Dec 24 01:31:37 PM PST 23
Peak memory 256776 kb
Host smart-8f6e320e-5c54-4df2-8757-6013ffdba2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20039
51851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2003951851
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.4190455468
Short name T458
Test name
Test status
Simulation time 977485179 ps
CPU time 51.52 seconds
Started Dec 24 01:30:52 PM PST 23
Finished Dec 24 01:31:44 PM PST 23
Peak memory 254788 kb
Host smart-ca198944-2288-4a21-a491-f136bd93a9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41904
55468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4190455468
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.449809933
Short name T726
Test name
Test status
Simulation time 441532350 ps
CPU time 32.35 seconds
Started Dec 24 01:30:48 PM PST 23
Finished Dec 24 01:31:21 PM PST 23
Peak memory 255092 kb
Host smart-8c992488-a6ed-4bce-9122-d2f7e058c226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44980
9933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.449809933
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2184736561
Short name T398
Test name
Test status
Simulation time 649603788 ps
CPU time 19.3 seconds
Started Dec 24 01:30:46 PM PST 23
Finished Dec 24 01:31:07 PM PST 23
Peak memory 248732 kb
Host smart-30ec6366-c9a0-41ff-a244-cac880686830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
36561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2184736561
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2655020334
Short name T74
Test name
Test status
Simulation time 55991251603 ps
CPU time 1519.3 seconds
Started Dec 24 01:30:57 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 289692 kb
Host smart-3e8c4575-9a85-4d63-87eb-6cd041b17fd9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655020334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2655020334
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2680552041
Short name T241
Test name
Test status
Simulation time 81961610935 ps
CPU time 3596.19 seconds
Started Dec 24 01:31:05 PM PST 23
Finished Dec 24 02:31:07 PM PST 23
Peak memory 321964 kb
Host smart-4c26f301-2bcb-478b-97af-9c48855c9714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680552041 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2680552041
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1348451396
Short name T373
Test name
Test status
Simulation time 125235385014 ps
CPU time 1989.2 seconds
Started Dec 24 01:31:14 PM PST 23
Finished Dec 24 02:04:26 PM PST 23
Peak memory 273376 kb
Host smart-65b245d0-4fb6-4476-a909-b74db8a6e528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348451396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1348451396
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3138751473
Short name T545
Test name
Test status
Simulation time 9024498255 ps
CPU time 248.53 seconds
Started Dec 24 01:31:21 PM PST 23
Finished Dec 24 01:35:30 PM PST 23
Peak memory 255728 kb
Host smart-60b74ad9-b17a-4a7c-ad03-74315af4cdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31387
51473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3138751473
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.391823887
Short name T534
Test name
Test status
Simulation time 1852559841 ps
CPU time 52.9 seconds
Started Dec 24 01:31:16 PM PST 23
Finished Dec 24 01:32:11 PM PST 23
Peak memory 255164 kb
Host smart-d1352fda-80a2-42fc-97e3-cc1e72f5a6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
3887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.391823887
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3169216494
Short name T524
Test name
Test status
Simulation time 7851030473 ps
CPU time 785.6 seconds
Started Dec 24 01:31:21 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 272820 kb
Host smart-a9266a40-15e3-4fbe-9896-c80fe6613bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169216494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3169216494
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2755466968
Short name T474
Test name
Test status
Simulation time 18245270240 ps
CPU time 1031.76 seconds
Started Dec 24 01:31:21 PM PST 23
Finished Dec 24 01:48:34 PM PST 23
Peak memory 273252 kb
Host smart-b14d67fe-60b2-4fb8-8ef1-a0d503650a78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755466968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2755466968
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3353232256
Short name T432
Test name
Test status
Simulation time 2565311597 ps
CPU time 73.19 seconds
Started Dec 24 01:30:53 PM PST 23
Finished Dec 24 01:32:07 PM PST 23
Peak memory 248736 kb
Host smart-5f810342-2698-4949-990e-19bebb96e617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33532
32256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3353232256
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2776695259
Short name T431
Test name
Test status
Simulation time 487819625 ps
CPU time 32.86 seconds
Started Dec 24 01:30:47 PM PST 23
Finished Dec 24 01:31:21 PM PST 23
Peak memory 254208 kb
Host smart-bbb95bcf-0f33-457d-ada5-2619565b6c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27766
95259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2776695259
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3330799697
Short name T492
Test name
Test status
Simulation time 2850762067 ps
CPU time 45.46 seconds
Started Dec 24 01:31:29 PM PST 23
Finished Dec 24 01:32:16 PM PST 23
Peak memory 255728 kb
Host smart-8326b152-6ced-41a1-9026-72634b8fc004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
99697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3330799697
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.604433338
Short name T677
Test name
Test status
Simulation time 1057718192 ps
CPU time 40.9 seconds
Started Dec 24 01:30:56 PM PST 23
Finished Dec 24 01:31:43 PM PST 23
Peak memory 248588 kb
Host smart-e6863392-3ce3-47c7-96b5-4e381ded9f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60443
3338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.604433338
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.958203824
Short name T49
Test name
Test status
Simulation time 684401272197 ps
CPU time 3356.83 seconds
Started Dec 24 01:31:16 PM PST 23
Finished Dec 24 02:27:14 PM PST 23
Peak memory 300224 kb
Host smart-8f0594c7-b733-4af3-96a2-778a57f0a76f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958203824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.958203824
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2102522852
Short name T231
Test name
Test status
Simulation time 71866716406 ps
CPU time 7512.59 seconds
Started Dec 24 01:31:14 PM PST 23
Finished Dec 24 03:36:30 PM PST 23
Peak memory 393144 kb
Host smart-bf6ccb93-2e01-46e6-a36b-6bc5ccd8b2fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102522852 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2102522852
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.655960469
Short name T132
Test name
Test status
Simulation time 169896820862 ps
CPU time 1974.14 seconds
Started Dec 24 01:31:15 PM PST 23
Finished Dec 24 02:04:11 PM PST 23
Peak memory 284320 kb
Host smart-ed373c74-760e-48d2-bc5e-599a15fee00b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655960469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.655960469
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3515796749
Short name T20
Test name
Test status
Simulation time 14558890598 ps
CPU time 193.84 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 01:34:34 PM PST 23
Peak memory 256936 kb
Host smart-03d07915-3586-40e5-befc-29d3055a0aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35157
96749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3515796749
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2426609471
Short name T489
Test name
Test status
Simulation time 1424051468 ps
CPU time 25.1 seconds
Started Dec 24 01:31:17 PM PST 23
Finished Dec 24 01:31:43 PM PST 23
Peak memory 254356 kb
Host smart-8c2f7605-0318-42d6-b705-c940a39d8667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24266
09471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2426609471
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3459256812
Short name T316
Test name
Test status
Simulation time 74853771768 ps
CPU time 2038.29 seconds
Started Dec 24 01:31:14 PM PST 23
Finished Dec 24 02:05:15 PM PST 23
Peak memory 272272 kb
Host smart-ed020287-b4d6-41f0-b8fe-2ab8155ba1f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459256812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3459256812
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2238024788
Short name T460
Test name
Test status
Simulation time 30036154868 ps
CPU time 1383.56 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 285660 kb
Host smart-f2fe6e87-ba32-4284-9918-389b818db631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238024788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2238024788
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1847462624
Short name T532
Test name
Test status
Simulation time 2452226250 ps
CPU time 84.77 seconds
Started Dec 24 01:31:21 PM PST 23
Finished Dec 24 01:32:47 PM PST 23
Peak memory 248692 kb
Host smart-6a10bbbf-80ab-44df-8688-8a7afe576376
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847462624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1847462624
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3302263786
Short name T637
Test name
Test status
Simulation time 880585381 ps
CPU time 4.98 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 01:31:26 PM PST 23
Peak memory 248696 kb
Host smart-66d4dbbf-864d-45b6-8ea8-fef6431fbc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33022
63786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3302263786
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.101741779
Short name T705
Test name
Test status
Simulation time 2027229779 ps
CPU time 32.68 seconds
Started Dec 24 01:31:30 PM PST 23
Finished Dec 24 01:32:04 PM PST 23
Peak memory 252732 kb
Host smart-d30af78d-73a1-42ae-96c0-85344c6f5aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
1779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.101741779
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2656574048
Short name T464
Test name
Test status
Simulation time 5123660114 ps
CPU time 23.83 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 01:31:45 PM PST 23
Peak memory 255636 kb
Host smart-06a56917-7faf-470e-aba4-1cd88f464db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26565
74048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2656574048
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1833164052
Short name T411
Test name
Test status
Simulation time 1971248788 ps
CPU time 21.94 seconds
Started Dec 24 01:31:17 PM PST 23
Finished Dec 24 01:31:40 PM PST 23
Peak memory 248680 kb
Host smart-44d53cab-c7fd-4b99-9391-238a78d4acc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18331
64052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1833164052
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2415842593
Short name T291
Test name
Test status
Simulation time 211395096777 ps
CPU time 2567.78 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 02:14:31 PM PST 23
Peak memory 289468 kb
Host smart-97efad39-fe04-4b12-a013-fda402f2cd2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415842593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2415842593
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2374334304
Short name T104
Test name
Test status
Simulation time 28038042485 ps
CPU time 1904.26 seconds
Started Dec 24 01:31:21 PM PST 23
Finished Dec 24 02:03:06 PM PST 23
Peak memory 289252 kb
Host smart-e44d4e26-0aa5-4ba2-976f-37612a27852e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374334304 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2374334304
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1461652992
Short name T376
Test name
Test status
Simulation time 28390006118 ps
CPU time 1796.4 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 02:01:43 PM PST 23
Peak memory 268276 kb
Host smart-27264fb5-60f5-4528-9298-1bb8e04ab417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461652992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1461652992
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3635385010
Short name T237
Test name
Test status
Simulation time 2908536034 ps
CPU time 49.77 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 01:32:36 PM PST 23
Peak memory 255736 kb
Host smart-388d95c7-7637-4ab3-9d45-beb32087dd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36353
85010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3635385010
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.394519346
Short name T98
Test name
Test status
Simulation time 216641955 ps
CPU time 15 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:32:00 PM PST 23
Peak memory 255044 kb
Host smart-0ae0d22d-6019-4da2-9243-f8a03453598f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39451
9346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.394519346
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.5219809
Short name T312
Test name
Test status
Simulation time 97654650375 ps
CPU time 2917.33 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 02:20:20 PM PST 23
Peak memory 288040 kb
Host smart-d9f7dc3a-5ca3-4cb2-b68b-8eb538296545
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5219809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.5219809
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1202041850
Short name T618
Test name
Test status
Simulation time 60684007121 ps
CPU time 1058.86 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 01:49:21 PM PST 23
Peak memory 264808 kb
Host smart-be5790d1-effc-41f8-b58e-d61bea5cb536
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202041850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1202041850
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3503850846
Short name T674
Test name
Test status
Simulation time 8800126844 ps
CPU time 377.26 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:38:00 PM PST 23
Peak memory 247576 kb
Host smart-ac7103b0-b288-4e65-a48b-a8df02c15a7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503850846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3503850846
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3737278432
Short name T484
Test name
Test status
Simulation time 178499596 ps
CPU time 21.58 seconds
Started Dec 24 01:31:20 PM PST 23
Finished Dec 24 01:31:43 PM PST 23
Peak memory 248556 kb
Host smart-a2b31ddb-291e-42d2-a8da-aa970edc7d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37372
78432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3737278432
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3141411335
Short name T528
Test name
Test status
Simulation time 878603616 ps
CPU time 27.18 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:32:12 PM PST 23
Peak memory 255116 kb
Host smart-565a63af-8465-42c9-bfe1-04f4e51e67d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31414
11335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3141411335
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3938378894
Short name T494
Test name
Test status
Simulation time 446154880 ps
CPU time 23.73 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:32:08 PM PST 23
Peak memory 254512 kb
Host smart-fc600ebd-5f58-4718-813d-dcd19b917489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39383
78894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3938378894
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4006306697
Short name T598
Test name
Test status
Simulation time 1616139343 ps
CPU time 44.91 seconds
Started Dec 24 01:31:33 PM PST 23
Finished Dec 24 01:32:19 PM PST 23
Peak memory 248636 kb
Host smart-8c6cc071-64a7-4f45-a967-c565fad117b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40063
06697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4006306697
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3844145192
Short name T295
Test name
Test status
Simulation time 6829361473 ps
CPU time 256.68 seconds
Started Dec 24 01:31:31 PM PST 23
Finished Dec 24 01:35:49 PM PST 23
Peak memory 255660 kb
Host smart-f545a41e-97e5-47d9-9472-69acf2c9587f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844145192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3844145192
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2715698870
Short name T558
Test name
Test status
Simulation time 37794694321 ps
CPU time 874.37 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:46:19 PM PST 23
Peak memory 266096 kb
Host smart-21dd28b3-6083-4932-bc54-ccf18658f607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715698870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2715698870
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3913212479
Short name T514
Test name
Test status
Simulation time 6904343323 ps
CPU time 199.88 seconds
Started Dec 24 01:31:29 PM PST 23
Finished Dec 24 01:34:49 PM PST 23
Peak memory 256808 kb
Host smart-a7d25fb1-e4cc-4c63-b435-f56555913318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39132
12479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3913212479
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.109473329
Short name T457
Test name
Test status
Simulation time 484153220 ps
CPU time 8.98 seconds
Started Dec 24 01:31:29 PM PST 23
Finished Dec 24 01:31:39 PM PST 23
Peak memory 248960 kb
Host smart-ded2fa31-472b-4a81-ba18-74cf8d60392a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10947
3329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.109473329
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2208491477
Short name T330
Test name
Test status
Simulation time 12844534249 ps
CPU time 851.71 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:45:55 PM PST 23
Peak memory 271588 kb
Host smart-020025c8-0068-4707-aa8f-5779a965a1e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208491477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2208491477
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3747333712
Short name T646
Test name
Test status
Simulation time 43388538241 ps
CPU time 2430.46 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 02:12:14 PM PST 23
Peak memory 288668 kb
Host smart-bf82102f-733c-4355-8e18-a1fd0ed2098c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747333712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3747333712
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2549260892
Short name T610
Test name
Test status
Simulation time 10828358684 ps
CPU time 448.31 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 01:39:10 PM PST 23
Peak memory 247652 kb
Host smart-813718a2-2f53-47de-84c7-3b32b3c4cf6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549260892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2549260892
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2838139849
Short name T657
Test name
Test status
Simulation time 184760210 ps
CPU time 23.01 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:32:06 PM PST 23
Peak memory 248584 kb
Host smart-6ec52af7-533c-4674-a613-a9c96a811235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28381
39849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2838139849
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2804968701
Short name T585
Test name
Test status
Simulation time 483395848 ps
CPU time 16.99 seconds
Started Dec 24 01:31:31 PM PST 23
Finished Dec 24 01:31:49 PM PST 23
Peak memory 246708 kb
Host smart-0881ded7-fa49-4b5b-9684-79356065c8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28049
68701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2804968701
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.301905703
Short name T294
Test name
Test status
Simulation time 1838100484 ps
CPU time 31.6 seconds
Started Dec 24 01:31:29 PM PST 23
Finished Dec 24 01:32:02 PM PST 23
Peak memory 248568 kb
Host smart-a7f790ec-5c8c-475e-a09c-1864efd4b6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30190
5703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.301905703
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2317722468
Short name T401
Test name
Test status
Simulation time 16469732 ps
CPU time 2.93 seconds
Started Dec 24 01:31:30 PM PST 23
Finished Dec 24 01:31:34 PM PST 23
Peak memory 240396 kb
Host smart-4a05033e-df0c-4253-b7d3-673467e929e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23177
22468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2317722468
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.746064903
Short name T527
Test name
Test status
Simulation time 36926128465 ps
CPU time 1909.4 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 02:03:33 PM PST 23
Peak memory 288668 kb
Host smart-c42a36ed-5ce3-4f11-98a5-52eaf0ec598f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746064903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.746064903
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1128691706
Short name T127
Test name
Test status
Simulation time 371835483337 ps
CPU time 5764.27 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 03:07:48 PM PST 23
Peak memory 320172 kb
Host smart-8235329b-cc74-4fd6-84e0-de83ff581dfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128691706 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1128691706
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.86718631
Short name T107
Test name
Test status
Simulation time 76298606071 ps
CPU time 2358.89 seconds
Started Dec 24 01:31:40 PM PST 23
Finished Dec 24 02:11:00 PM PST 23
Peak memory 288916 kb
Host smart-898f071e-c600-471c-9b73-2412813b116e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86718631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.86718631
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1639403947
Short name T660
Test name
Test status
Simulation time 4268674926 ps
CPU time 226.19 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:35:30 PM PST 23
Peak memory 249632 kb
Host smart-a44abe0b-acda-4daf-afc1-c1c509b417d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16394
03947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1639403947
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2899570616
Short name T224
Test name
Test status
Simulation time 785249752 ps
CPU time 46 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:32:29 PM PST 23
Peak memory 255464 kb
Host smart-ed7de7cf-dd62-4655-b0cf-0785921c3d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995
70616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2899570616
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2199885792
Short name T311
Test name
Test status
Simulation time 42079354768 ps
CPU time 2357.97 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 02:11:03 PM PST 23
Peak memory 288848 kb
Host smart-0eeca662-2865-447b-8068-ef49958922dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199885792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2199885792
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2793539935
Short name T423
Test name
Test status
Simulation time 51143365848 ps
CPU time 1247.39 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:52:32 PM PST 23
Peak memory 289052 kb
Host smart-4e30a1ca-ee90-4186-82e3-28661df8a796
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793539935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2793539935
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.92760587
Short name T503
Test name
Test status
Simulation time 10801023399 ps
CPU time 118.61 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:33:42 PM PST 23
Peak memory 246500 kb
Host smart-3a6678ed-eba2-4203-a2a5-65d64d275033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92760587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.92760587
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1591475369
Short name T447
Test name
Test status
Simulation time 109487674 ps
CPU time 11.36 seconds
Started Dec 24 01:32:04 PM PST 23
Finished Dec 24 01:32:16 PM PST 23
Peak memory 248584 kb
Host smart-3cebe12e-11ed-4a41-a68f-56212ad6567f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
75369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1591475369
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3316717779
Short name T604
Test name
Test status
Simulation time 569105771 ps
CPU time 29.26 seconds
Started Dec 24 01:31:51 PM PST 23
Finished Dec 24 01:32:21 PM PST 23
Peak memory 247096 kb
Host smart-29b6a338-52de-408b-bb9c-e5f5eb1618e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33167
17779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3316717779
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.250959369
Short name T333
Test name
Test status
Simulation time 258756597 ps
CPU time 18 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:32:02 PM PST 23
Peak memory 254624 kb
Host smart-162b3a3d-d0ea-4c2e-bc8b-7078f3a376e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25095
9369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.250959369
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1364767531
Short name T612
Test name
Test status
Simulation time 765967980 ps
CPU time 47.2 seconds
Started Dec 24 01:31:46 PM PST 23
Finished Dec 24 01:32:34 PM PST 23
Peak memory 248548 kb
Host smart-0ddd1656-8ebd-4781-aa93-75e9ae0a9a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13647
67531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1364767531
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1096634797
Short name T61
Test name
Test status
Simulation time 27930992666 ps
CPU time 1748.68 seconds
Started Dec 24 01:31:46 PM PST 23
Finished Dec 24 02:00:56 PM PST 23
Peak memory 282268 kb
Host smart-fdee79b4-4a2b-4d03-aa9a-6c601808ce32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096634797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1096634797
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.484783479
Short name T582
Test name
Test status
Simulation time 72541675056 ps
CPU time 4904.27 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 02:53:27 PM PST 23
Peak memory 322180 kb
Host smart-c927b9dc-0c39-41cd-9749-e6786a2e9058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484783479 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.484783479
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3190477667
Short name T629
Test name
Test status
Simulation time 204928968792 ps
CPU time 3183.85 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 02:24:47 PM PST 23
Peak memory 289328 kb
Host smart-9124901d-1ec7-4c8e-84f9-6724b18190d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190477667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3190477667
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1760830723
Short name T236
Test name
Test status
Simulation time 1454905980 ps
CPU time 115.77 seconds
Started Dec 24 01:31:48 PM PST 23
Finished Dec 24 01:33:44 PM PST 23
Peak memory 256420 kb
Host smart-5e817d5d-345d-4e94-847e-323cb0e68e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17608
30723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1760830723
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1086178207
Short name T605
Test name
Test status
Simulation time 675790021 ps
CPU time 13.26 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:31:57 PM PST 23
Peak memory 252424 kb
Host smart-4b62a1ed-dd6a-4070-a488-478516f71727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
78207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1086178207
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3415086799
Short name T248
Test name
Test status
Simulation time 294989652173 ps
CPU time 1758.76 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 02:01:04 PM PST 23
Peak memory 289604 kb
Host smart-0b466d99-347c-4772-829f-510fcccf91d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415086799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3415086799
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.811664135
Short name T441
Test name
Test status
Simulation time 83590683400 ps
CPU time 1247.79 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:52:33 PM PST 23
Peak memory 266336 kb
Host smart-c1d18c4d-6b90-49f2-9b7f-d989b200a10c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811664135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.811664135
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2901305094
Short name T275
Test name
Test status
Simulation time 102468517148 ps
CPU time 283.65 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:36:28 PM PST 23
Peak memory 247532 kb
Host smart-3375a398-657e-415c-aa16-bd0d636cb5ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901305094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2901305094
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1867747800
Short name T407
Test name
Test status
Simulation time 411101292 ps
CPU time 29.19 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 01:32:12 PM PST 23
Peak memory 255396 kb
Host smart-302a3431-b28c-41e0-9074-9e105e640fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18677
47800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1867747800
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4265759667
Short name T454
Test name
Test status
Simulation time 11471142075 ps
CPU time 50.1 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:32:35 PM PST 23
Peak memory 255568 kb
Host smart-24e1dd36-da59-4364-8835-1d83e4277cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42657
59667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4265759667
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2064072507
Short name T626
Test name
Test status
Simulation time 1005422187 ps
CPU time 40.2 seconds
Started Dec 24 01:31:40 PM PST 23
Finished Dec 24 01:32:21 PM PST 23
Peak memory 254436 kb
Host smart-73062c59-eb0d-4987-9dd3-b50dd176eddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20640
72507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2064072507
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3990309673
Short name T686
Test name
Test status
Simulation time 4961172373 ps
CPU time 60.41 seconds
Started Dec 24 01:32:00 PM PST 23
Finished Dec 24 01:33:01 PM PST 23
Peak memory 248712 kb
Host smart-59f3d845-f140-4d67-9f7a-31d2b95a9fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903
09673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3990309673
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4257937084
Short name T633
Test name
Test status
Simulation time 793782197315 ps
CPU time 2528.78 seconds
Started Dec 24 01:32:00 PM PST 23
Finished Dec 24 02:14:10 PM PST 23
Peak memory 288908 kb
Host smart-f833259f-49db-4f08-96aa-c368fec4a53e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257937084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4257937084
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1129998054
Short name T639
Test name
Test status
Simulation time 65150229565 ps
CPU time 1078.7 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:49:43 PM PST 23
Peak memory 283008 kb
Host smart-3a5964a9-4316-4036-bec1-69a27bf645da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129998054 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1129998054
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.4174543415
Short name T613
Test name
Test status
Simulation time 35440117618 ps
CPU time 933.05 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 01:47:19 PM PST 23
Peak memory 284568 kb
Host smart-5ec4f351-2a68-48b9-9fe6-60fec189874e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174543415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.4174543415
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1335023705
Short name T254
Test name
Test status
Simulation time 17374720896 ps
CPU time 118.94 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:33:43 PM PST 23
Peak memory 256364 kb
Host smart-52dfb60c-6c65-4fd4-94d1-812da14fc843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13350
23705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1335023705
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3414636349
Short name T550
Test name
Test status
Simulation time 1031186815 ps
CPU time 18.15 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 01:32:04 PM PST 23
Peak memory 253052 kb
Host smart-10c21925-38e2-416b-a5cf-184c945b3a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34146
36349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3414636349
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1353659373
Short name T260
Test name
Test status
Simulation time 12203387646 ps
CPU time 814.38 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 01:45:17 PM PST 23
Peak memory 268100 kb
Host smart-c19702dd-5a08-4798-b479-6800153af097
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353659373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1353659373
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2230674553
Short name T690
Test name
Test status
Simulation time 134887801952 ps
CPU time 1984.77 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 02:04:58 PM PST 23
Peak memory 282164 kb
Host smart-0555224e-314f-4ce8-a007-24bb08845c48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230674553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2230674553
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2942119963
Short name T287
Test name
Test status
Simulation time 68399514683 ps
CPU time 354.14 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 01:37:36 PM PST 23
Peak memory 247200 kb
Host smart-8bd5b9b7-9fc2-48e4-8288-c2d5b775ac31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942119963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2942119963
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.995382610
Short name T493
Test name
Test status
Simulation time 3027290749 ps
CPU time 30.37 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 01:32:16 PM PST 23
Peak memory 255848 kb
Host smart-5f1fdc10-6fa1-478e-8a8c-ce20d5c9715c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99538
2610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.995382610
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1955197276
Short name T593
Test name
Test status
Simulation time 785750981 ps
CPU time 48.82 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 01:32:35 PM PST 23
Peak memory 254440 kb
Host smart-89cc0b00-118c-4596-b419-bc9c27b04d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551
97276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1955197276
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2729068469
Short name T79
Test name
Test status
Simulation time 94083492 ps
CPU time 8.22 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 01:31:55 PM PST 23
Peak memory 252656 kb
Host smart-8a4931f0-f8c5-42b3-b9d3-39ba73740c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27290
68469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2729068469
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2318833533
Short name T683
Test name
Test status
Simulation time 9428570546 ps
CPU time 44.6 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 01:32:37 PM PST 23
Peak memory 248744 kb
Host smart-7531333c-b627-459b-8711-8704f1b7a620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23188
33533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2318833533
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3269663162
Short name T414
Test name
Test status
Simulation time 351470637 ps
CPU time 36 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:32:22 PM PST 23
Peak memory 248568 kb
Host smart-0b811e28-9903-40d9-96bb-e44192d413ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269663162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3269663162
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2083732093
Short name T578
Test name
Test status
Simulation time 150410627248 ps
CPU time 2177.36 seconds
Started Dec 24 01:31:51 PM PST 23
Finished Dec 24 02:08:09 PM PST 23
Peak memory 288968 kb
Host smart-a85c9e20-39cb-4c61-a28a-0281efa8b002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083732093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2083732093
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1176862735
Short name T84
Test name
Test status
Simulation time 5144522223 ps
CPU time 289.13 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:36:34 PM PST 23
Peak memory 256300 kb
Host smart-5fd2aa8a-657a-43d2-ba95-aa9fc239f863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11768
62735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1176862735
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3516601236
Short name T426
Test name
Test status
Simulation time 693103314 ps
CPU time 32.2 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:32:16 PM PST 23
Peak memory 254368 kb
Host smart-b94e1358-9a8f-4d63-8453-54acce75e422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35166
01236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3516601236
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.401143759
Short name T322
Test name
Test status
Simulation time 10120187909 ps
CPU time 757.53 seconds
Started Dec 24 01:31:42 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 265060 kb
Host smart-3ad7a054-023c-4330-9bf7-b2123b1ec68a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401143759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.401143759
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2675854427
Short name T518
Test name
Test status
Simulation time 137182307367 ps
CPU time 2172.97 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 02:07:55 PM PST 23
Peak memory 273236 kb
Host smart-8e19b95c-4b81-402b-b19e-19d47b1b131e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675854427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2675854427
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1961319528
Short name T488
Test name
Test status
Simulation time 26754110016 ps
CPU time 168.66 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:34:33 PM PST 23
Peak memory 247288 kb
Host smart-a69faf87-9d19-4aab-8b6c-cf9a7848cbc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961319528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1961319528
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3833326262
Short name T479
Test name
Test status
Simulation time 992307866 ps
CPU time 30.62 seconds
Started Dec 24 01:31:53 PM PST 23
Finished Dec 24 01:32:24 PM PST 23
Peak memory 255236 kb
Host smart-f328a511-be78-4e6f-8a00-53750b49e8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38333
26262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3833326262
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1729924624
Short name T502
Test name
Test status
Simulation time 3520659037 ps
CPU time 48.85 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 01:32:32 PM PST 23
Peak memory 248376 kb
Host smart-81b4f0f9-6e24-43a2-ae68-42f077d70c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17299
24624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1729924624
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.773260312
Short name T370
Test name
Test status
Simulation time 667816581 ps
CPU time 31.63 seconds
Started Dec 24 01:31:51 PM PST 23
Finished Dec 24 01:32:24 PM PST 23
Peak memory 248568 kb
Host smart-05b12ad6-8f69-4f8d-a031-339c6f3335d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77326
0312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.773260312
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3413376854
Short name T77
Test name
Test status
Simulation time 1208199397 ps
CPU time 71.93 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:32:56 PM PST 23
Peak memory 248512 kb
Host smart-454e7788-5dec-462a-ae90-6752e70784c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413376854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3413376854
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2039688846
Short name T452
Test name
Test status
Simulation time 27682377206 ps
CPU time 1677.67 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 01:59:50 PM PST 23
Peak memory 273516 kb
Host smart-daf9cae0-3caa-4520-a1a9-230a347cf1af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039688846 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2039688846
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3259185068
Short name T415
Test name
Test status
Simulation time 25540629152 ps
CPU time 1079.82 seconds
Started Dec 24 01:31:43 PM PST 23
Finished Dec 24 01:49:44 PM PST 23
Peak memory 270176 kb
Host smart-f09eaf4a-5a76-4818-b12c-ef0535e4dc95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259185068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3259185068
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2417882290
Short name T389
Test name
Test status
Simulation time 5059151599 ps
CPU time 208.68 seconds
Started Dec 24 01:31:40 PM PST 23
Finished Dec 24 01:35:11 PM PST 23
Peak memory 256124 kb
Host smart-b282c450-2bcf-4008-bd54-9ffa6d31a26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24178
82290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2417882290
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2531964745
Short name T487
Test name
Test status
Simulation time 1127045013 ps
CPU time 39.04 seconds
Started Dec 24 01:31:41 PM PST 23
Finished Dec 24 01:32:22 PM PST 23
Peak memory 254340 kb
Host smart-9de7fd93-0cf7-4a15-b07e-6dd83f825416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25319
64745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2531964745
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3522427656
Short name T313
Test name
Test status
Simulation time 151416467003 ps
CPU time 2379.37 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 02:11:32 PM PST 23
Peak memory 288964 kb
Host smart-aac73a67-b5cd-4629-a46f-a3f123b72786
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522427656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3522427656
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.162676011
Short name T721
Test name
Test status
Simulation time 25192238837 ps
CPU time 1570.31 seconds
Started Dec 24 01:31:53 PM PST 23
Finished Dec 24 01:58:04 PM PST 23
Peak memory 273268 kb
Host smart-bc1df09c-1b2b-4ecd-9865-c6d5042caab1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162676011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.162676011
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2190844311
Short name T553
Test name
Test status
Simulation time 8791330741 ps
CPU time 358.34 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 01:37:51 PM PST 23
Peak memory 246716 kb
Host smart-a9dffd44-6cfe-4e95-8594-87433bb15e15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190844311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2190844311
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.745351126
Short name T501
Test name
Test status
Simulation time 751652305 ps
CPU time 51.39 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:32:36 PM PST 23
Peak memory 248576 kb
Host smart-bd01219d-7dfa-4e44-b1ad-5f42165e06da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74535
1126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.745351126
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.442080590
Short name T349
Test name
Test status
Simulation time 361110666 ps
CPU time 38.69 seconds
Started Dec 24 01:31:44 PM PST 23
Finished Dec 24 01:32:24 PM PST 23
Peak memory 255068 kb
Host smart-8b80c565-9134-4f4b-b6d6-bc6c18fd725c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44208
0590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.442080590
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3910899043
Short name T35
Test name
Test status
Simulation time 987529690 ps
CPU time 44.67 seconds
Started Dec 24 01:31:46 PM PST 23
Finished Dec 24 01:32:32 PM PST 23
Peak memory 255264 kb
Host smart-df42979e-a53a-4003-ad2c-ecd082bb6019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39108
99043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3910899043
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3516824253
Short name T525
Test name
Test status
Simulation time 135191895 ps
CPU time 12.15 seconds
Started Dec 24 01:31:45 PM PST 23
Finished Dec 24 01:31:58 PM PST 23
Peak memory 255440 kb
Host smart-a5aa325f-1598-404f-9327-4bb8f03d7065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35168
24253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3516824253
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2010451700
Short name T615
Test name
Test status
Simulation time 296850872491 ps
CPU time 4294.82 seconds
Started Dec 24 01:31:57 PM PST 23
Finished Dec 24 02:43:33 PM PST 23
Peak memory 301492 kb
Host smart-db365553-7732-405a-9705-52984739397e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010451700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2010451700
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4142876379
Short name T209
Test name
Test status
Simulation time 17870380 ps
CPU time 2.77 seconds
Started Dec 24 01:28:12 PM PST 23
Finished Dec 24 01:28:23 PM PST 23
Peak memory 248880 kb
Host smart-b8a930d8-ca65-48c5-9b31-3736aa1941bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4142876379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4142876379
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.231033648
Short name T41
Test name
Test status
Simulation time 52500174500 ps
CPU time 1466.85 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 01:52:47 PM PST 23
Peak memory 272836 kb
Host smart-53517772-0bb1-4c97-a0aa-983c6f70d682
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231033648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.231033648
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2399542309
Short name T435
Test name
Test status
Simulation time 422505910 ps
CPU time 20.82 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:28:45 PM PST 23
Peak memory 248532 kb
Host smart-95dd31ec-c24d-466a-805a-0c3e42f30578
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2399542309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2399542309
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2575150670
Short name T580
Test name
Test status
Simulation time 1738878601 ps
CPU time 32.64 seconds
Started Dec 24 01:28:08 PM PST 23
Finished Dec 24 01:28:49 PM PST 23
Peak memory 254836 kb
Host smart-b659a4f8-2d5b-4492-b2a9-88a500957f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
50670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2575150670
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.593461170
Short name T523
Test name
Test status
Simulation time 507470047 ps
CPU time 17.84 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 01:28:38 PM PST 23
Peak memory 255300 kb
Host smart-b4d3244a-2135-45bd-a148-63dc2afa523a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59346
1170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.593461170
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.854137013
Short name T581
Test name
Test status
Simulation time 14387661832 ps
CPU time 1435.15 seconds
Started Dec 24 01:28:20 PM PST 23
Finished Dec 24 01:52:19 PM PST 23
Peak memory 289088 kb
Host smart-63c94ec9-ffb0-4ba0-b0b7-d5b59816cd23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854137013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.854137013
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1684348455
Short name T559
Test name
Test status
Simulation time 20793559328 ps
CPU time 1420.12 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 01:52:03 PM PST 23
Peak memory 273236 kb
Host smart-712c9eae-096d-4653-a4b0-35f00ead959b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684348455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1684348455
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2258528281
Short name T286
Test name
Test status
Simulation time 20701540733 ps
CPU time 249.87 seconds
Started Dec 24 01:28:10 PM PST 23
Finished Dec 24 01:32:30 PM PST 23
Peak memory 247504 kb
Host smart-3fb9f1e2-0f91-44ce-b310-509871c67e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258528281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2258528281
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1901948588
Short name T504
Test name
Test status
Simulation time 704201104 ps
CPU time 13.29 seconds
Started Dec 24 01:28:09 PM PST 23
Finished Dec 24 01:28:30 PM PST 23
Peak memory 253436 kb
Host smart-671237c6-5b49-4f43-81e7-3eb6048cb79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19019
48588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1901948588
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.847321590
Short name T672
Test name
Test status
Simulation time 373498389 ps
CPU time 41.59 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:29:07 PM PST 23
Peak memory 247024 kb
Host smart-392ab532-a0c1-4f5f-831c-f0fa04d8513d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84732
1590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.847321590
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1074624126
Short name T230
Test name
Test status
Simulation time 1071788404 ps
CPU time 32.56 seconds
Started Dec 24 01:28:12 PM PST 23
Finished Dec 24 01:28:53 PM PST 23
Peak memory 248476 kb
Host smart-3348ff53-d408-4087-ae2f-e38262bf2a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10746
24126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1074624126
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.568424788
Short name T219
Test name
Test status
Simulation time 5154891830 ps
CPU time 24.64 seconds
Started Dec 24 01:28:18 PM PST 23
Finished Dec 24 01:28:48 PM PST 23
Peak memory 248704 kb
Host smart-62bc5c1b-09bd-4073-820a-acff0ee72a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56842
4788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.568424788
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.732552670
Short name T631
Test name
Test status
Simulation time 40975658163 ps
CPU time 1767.18 seconds
Started Dec 24 01:28:18 PM PST 23
Finished Dec 24 01:57:50 PM PST 23
Peak memory 288816 kb
Host smart-387bb216-c281-4238-8993-2398b9dbc25d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732552670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.732552670
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3936268110
Short name T50
Test name
Test status
Simulation time 311639651 ps
CPU time 2.58 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:28:27 PM PST 23
Peak memory 248812 kb
Host smart-d6eb05fd-75a3-4da7-8fe6-f38c78efa923
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3936268110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3936268110
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2377105207
Short name T499
Test name
Test status
Simulation time 7722612410 ps
CPU time 600.62 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 01:38:24 PM PST 23
Peak memory 264976 kb
Host smart-ada63bf0-7480-4024-9e1d-a4bb0afa0451
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377105207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2377105207
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3975168193
Short name T698
Test name
Test status
Simulation time 1844148049 ps
CPU time 20.94 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:28:47 PM PST 23
Peak memory 248648 kb
Host smart-ad1dd42a-48e3-4e04-be4a-95fdb425a09e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3975168193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3975168193
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2327295859
Short name T390
Test name
Test status
Simulation time 9976457770 ps
CPU time 97.86 seconds
Started Dec 24 01:28:20 PM PST 23
Finished Dec 24 01:30:02 PM PST 23
Peak memory 248680 kb
Host smart-155661ef-ce39-4d4d-b64a-01ad3e574895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272
95859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2327295859
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.898028543
Short name T352
Test name
Test status
Simulation time 9384166689 ps
CPU time 42.75 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:29:08 PM PST 23
Peak memory 248180 kb
Host smart-cae61f4b-d72d-4a34-a085-0ea5c7c539dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89802
8543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.898028543
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.46006451
Short name T539
Test name
Test status
Simulation time 268193094977 ps
CPU time 1348.6 seconds
Started Dec 24 01:28:22 PM PST 23
Finished Dec 24 01:50:54 PM PST 23
Peak memory 281144 kb
Host smart-3f63355c-0117-4430-ac4f-387f25684520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46006451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.46006451
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3048723894
Short name T216
Test name
Test status
Simulation time 55625918580 ps
CPU time 1149.27 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:47:34 PM PST 23
Peak memory 288488 kb
Host smart-0f22103e-b551-4c9d-8764-72066ac085e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048723894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3048723894
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3306786584
Short name T495
Test name
Test status
Simulation time 1267010203 ps
CPU time 72.59 seconds
Started Dec 24 01:28:26 PM PST 23
Finished Dec 24 01:29:40 PM PST 23
Peak memory 248508 kb
Host smart-0afa3fd1-0510-4b6f-b086-cf0ce8b905d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
86584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3306786584
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1159018420
Short name T367
Test name
Test status
Simulation time 2886003365 ps
CPU time 57.65 seconds
Started Dec 24 01:28:25 PM PST 23
Finished Dec 24 01:29:24 PM PST 23
Peak memory 247532 kb
Host smart-a0c116dc-c100-4a21-b060-303af87befde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11590
18420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1159018420
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3471067012
Short name T540
Test name
Test status
Simulation time 868789633 ps
CPU time 20.84 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 01:28:45 PM PST 23
Peak memory 248696 kb
Host smart-d7579e51-9e13-439f-8604-428a6ce626aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34710
67012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3471067012
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3431110122
Short name T459
Test name
Test status
Simulation time 96074929831 ps
CPU time 3367.72 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 02:24:32 PM PST 23
Peak memory 297468 kb
Host smart-501b8387-2321-449c-91b0-97b83d42b064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431110122 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3431110122
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2676385070
Short name T208
Test name
Test status
Simulation time 91498518 ps
CPU time 2.49 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:28:28 PM PST 23
Peak memory 248872 kb
Host smart-76be5ed4-4325-4dbe-a788-69a0e1ba531e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2676385070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2676385070
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.550863633
Short name T609
Test name
Test status
Simulation time 54675135368 ps
CPU time 1222.3 seconds
Started Dec 24 01:28:19 PM PST 23
Finished Dec 24 01:48:46 PM PST 23
Peak memory 289428 kb
Host smart-bc9160cb-4457-4d0b-911b-b850c2024cbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550863633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.550863633
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.942336868
Short name T556
Test name
Test status
Simulation time 918315000 ps
CPU time 13.11 seconds
Started Dec 24 01:28:26 PM PST 23
Finished Dec 24 01:28:41 PM PST 23
Peak memory 248488 kb
Host smart-0a5a5db3-e80c-432d-aa2f-ca7ec5f6fa91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=942336868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.942336868
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2021994301
Short name T709
Test name
Test status
Simulation time 3397469040 ps
CPU time 70.93 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:29:37 PM PST 23
Peak memory 256180 kb
Host smart-fcf4e023-e014-4708-a0c8-52b8e32d5bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20219
94301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2021994301
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3578756891
Short name T406
Test name
Test status
Simulation time 451405600 ps
CPU time 24.44 seconds
Started Dec 24 01:28:22 PM PST 23
Finished Dec 24 01:28:49 PM PST 23
Peak memory 248092 kb
Host smart-0352fc30-efd8-4264-a939-0b5a9be9e7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35787
56891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3578756891
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1768876091
Short name T317
Test name
Test status
Simulation time 33352095437 ps
CPU time 1242.71 seconds
Started Dec 24 01:28:20 PM PST 23
Finished Dec 24 01:49:07 PM PST 23
Peak memory 289580 kb
Host smart-5f0221e9-d697-44bf-9a2e-4d2044dc7021
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768876091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1768876091
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3613406641
Short name T715
Test name
Test status
Simulation time 14106404071 ps
CPU time 294.02 seconds
Started Dec 24 01:28:25 PM PST 23
Finished Dec 24 01:33:20 PM PST 23
Peak memory 247680 kb
Host smart-d6735f40-48fa-4d67-9638-c3c6c440a2fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613406641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3613406641
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1791676036
Short name T663
Test name
Test status
Simulation time 1335531581 ps
CPU time 12.31 seconds
Started Dec 24 01:28:22 PM PST 23
Finished Dec 24 01:28:37 PM PST 23
Peak memory 248576 kb
Host smart-d4e87fa8-74c8-4300-85df-8b7e1e15c25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
76036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1791676036
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3760479645
Short name T630
Test name
Test status
Simulation time 485967080 ps
CPU time 13.17 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:28:39 PM PST 23
Peak memory 246932 kb
Host smart-df9027c0-f0fc-4df6-a7be-3145125a7cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37604
79645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3760479645
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1349126515
Short name T297
Test name
Test status
Simulation time 1344156563 ps
CPU time 39.81 seconds
Started Dec 24 01:28:25 PM PST 23
Finished Dec 24 01:29:06 PM PST 23
Peak memory 254560 kb
Host smart-bec095a1-471e-4dbe-a6ae-3e97cd59cba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13491
26515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1349126515
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1759619797
Short name T87
Test name
Test status
Simulation time 2016992046 ps
CPU time 64.72 seconds
Started Dec 24 01:28:20 PM PST 23
Finished Dec 24 01:29:29 PM PST 23
Peak memory 248656 kb
Host smart-8422fcc5-8a65-4b48-8d96-85d1bb72c4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17596
19797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1759619797
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1677064693
Short name T707
Test name
Test status
Simulation time 117350459039 ps
CPU time 3086.7 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 02:19:53 PM PST 23
Peak memory 289184 kb
Host smart-8401548d-2ac6-4ecc-abba-df6f526467b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677064693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1677064693
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1351169195
Short name T82
Test name
Test status
Simulation time 128164296 ps
CPU time 3.24 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:28:28 PM PST 23
Peak memory 248624 kb
Host smart-dc4715fb-d4d1-49bb-a7d3-2102223c1e22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1351169195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1351169195
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2632868959
Short name T443
Test name
Test status
Simulation time 91294052453 ps
CPU time 1382.84 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:51:28 PM PST 23
Peak memory 272656 kb
Host smart-7888b889-b7d8-4af3-b904-10bde07d5ab0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632868959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2632868959
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.4028042731
Short name T625
Test name
Test status
Simulation time 2661511365 ps
CPU time 15.48 seconds
Started Dec 24 01:28:21 PM PST 23
Finished Dec 24 01:28:40 PM PST 23
Peak memory 240444 kb
Host smart-35a26bc2-ac95-48a4-8f8d-0e9470603cdc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4028042731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4028042731
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2795057775
Short name T109
Test name
Test status
Simulation time 8709051032 ps
CPU time 269.02 seconds
Started Dec 24 01:28:20 PM PST 23
Finished Dec 24 01:32:53 PM PST 23
Peak memory 256308 kb
Host smart-99728c16-b803-4d75-9cbb-d7d2b562f901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27950
57775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2795057775
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2034494643
Short name T622
Test name
Test status
Simulation time 575787969 ps
CPU time 26.78 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:28:52 PM PST 23
Peak memory 254168 kb
Host smart-d6605286-9161-4f79-a4c0-d50c45181cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20344
94643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2034494643
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.862548979
Short name T409
Test name
Test status
Simulation time 18303939323 ps
CPU time 686.61 seconds
Started Dec 24 01:28:25 PM PST 23
Finished Dec 24 01:39:54 PM PST 23
Peak memory 265168 kb
Host smart-6ce1f970-214f-4dd6-83b2-2c7ea3ca58a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862548979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.862548979
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1363070602
Short name T243
Test name
Test status
Simulation time 186556692634 ps
CPU time 2452 seconds
Started Dec 24 01:28:24 PM PST 23
Finished Dec 24 02:09:18 PM PST 23
Peak memory 287648 kb
Host smart-0b66994c-2f9f-4c95-82b3-ffcf7ff63125
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363070602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1363070602
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.194941510
Short name T664
Test name
Test status
Simulation time 11206868799 ps
CPU time 474.39 seconds
Started Dec 24 01:28:22 PM PST 23
Finished Dec 24 01:36:19 PM PST 23
Peak memory 247624 kb
Host smart-769bbbe4-e90e-4e7d-b856-26471b8bfd99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194941510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.194941510
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1964915691
Short name T696
Test name
Test status
Simulation time 1187129719 ps
CPU time 58.87 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:29:25 PM PST 23
Peak memory 255508 kb
Host smart-2e18cf61-8907-492e-be94-602c2679795e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
15691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1964915691
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1563469805
Short name T552
Test name
Test status
Simulation time 2848077861 ps
CPU time 46.82 seconds
Started Dec 24 01:28:23 PM PST 23
Finished Dec 24 01:29:13 PM PST 23
Peak memory 255380 kb
Host smart-f2f2d0a3-ca1b-4eb1-8c54-0077cd7c4604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15634
69805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1563469805
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3762928508
Short name T718
Test name
Test status
Simulation time 289761360 ps
CPU time 23.82 seconds
Started Dec 24 01:28:18 PM PST 23
Finished Dec 24 01:28:47 PM PST 23
Peak memory 248652 kb
Host smart-bba6c12f-a312-4f82-81e8-ab7e200730b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37629
28508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3762928508
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3786748846
Short name T1
Test name
Test status
Simulation time 2339281622 ps
CPU time 37.41 seconds
Started Dec 24 01:28:26 PM PST 23
Finished Dec 24 01:29:05 PM PST 23
Peak memory 248804 kb
Host smart-a61834de-6ae0-404c-8f3f-6bfaee2358fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37867
48846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3786748846
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1381098555
Short name T572
Test name
Test status
Simulation time 3660604500 ps
CPU time 54.53 seconds
Started Dec 24 01:28:26 PM PST 23
Finished Dec 24 01:29:22 PM PST 23
Peak memory 256220 kb
Host smart-05211b1c-6ed8-44cb-b18d-e4e434f27323
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381098555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1381098555
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2391732767
Short name T204
Test name
Test status
Simulation time 150078452 ps
CPU time 3.82 seconds
Started Dec 24 01:28:42 PM PST 23
Finished Dec 24 01:28:47 PM PST 23
Peak memory 248904 kb
Host smart-44c5bda7-8504-4ec4-8a35-7eee93cb14a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2391732767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2391732767
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3535626232
Short name T529
Test name
Test status
Simulation time 95103560556 ps
CPU time 2695.98 seconds
Started Dec 24 01:28:39 PM PST 23
Finished Dec 24 02:13:36 PM PST 23
Peak memory 287092 kb
Host smart-f03b319c-d44e-4beb-be7b-78a465c8bb5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535626232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3535626232
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.586710218
Short name T647
Test name
Test status
Simulation time 415041186 ps
CPU time 19.83 seconds
Started Dec 24 01:28:36 PM PST 23
Finished Dec 24 01:28:57 PM PST 23
Peak memory 240464 kb
Host smart-d09d94dc-c773-4dbd-81bd-187762db7d1d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=586710218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.586710218
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2063207315
Short name T130
Test name
Test status
Simulation time 12245766559 ps
CPU time 92.91 seconds
Started Dec 24 01:28:42 PM PST 23
Finished Dec 24 01:30:17 PM PST 23
Peak memory 248680 kb
Host smart-8d6337a2-2c1e-4be9-8305-227a3a1284bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
07315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2063207315
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.844481110
Short name T601
Test name
Test status
Simulation time 165696511 ps
CPU time 13.93 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 01:28:53 PM PST 23
Peak memory 254800 kb
Host smart-3f264657-3f78-4b0d-add6-f5b7dd7d9f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84448
1110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.844481110
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3540233600
Short name T258
Test name
Test status
Simulation time 54971769121 ps
CPU time 1146.21 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 01:47:46 PM PST 23
Peak memory 281444 kb
Host smart-06d57fda-16ce-4c11-91c1-7f562f02323e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540233600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3540233600
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2228981344
Short name T475
Test name
Test status
Simulation time 63667689964 ps
CPU time 807.22 seconds
Started Dec 24 01:28:35 PM PST 23
Finished Dec 24 01:42:03 PM PST 23
Peak memory 271992 kb
Host smart-f0190c4b-b5c1-4f04-bb18-ce5ea4a78905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228981344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2228981344
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4221464442
Short name T86
Test name
Test status
Simulation time 41371719336 ps
CPU time 270.18 seconds
Started Dec 24 01:28:39 PM PST 23
Finished Dec 24 01:33:10 PM PST 23
Peak memory 247884 kb
Host smart-c3b4d261-ef0f-4678-8211-b1ebe466ef0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221464442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4221464442
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1786978451
Short name T218
Test name
Test status
Simulation time 229003151 ps
CPU time 19.68 seconds
Started Dec 24 01:28:37 PM PST 23
Finished Dec 24 01:28:58 PM PST 23
Peak memory 255252 kb
Host smart-3aba0945-143d-4ec6-b8d8-11a5aef71c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17869
78451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1786978451
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.160742168
Short name T85
Test name
Test status
Simulation time 76410937 ps
CPU time 6.25 seconds
Started Dec 24 01:28:43 PM PST 23
Finished Dec 24 01:28:51 PM PST 23
Peak memory 238600 kb
Host smart-17a4e876-f8aa-418e-9b95-b2fbebeae208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16074
2168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.160742168
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.903192150
Short name T638
Test name
Test status
Simulation time 45491886 ps
CPU time 4.04 seconds
Started Dec 24 01:28:40 PM PST 23
Finished Dec 24 01:28:46 PM PST 23
Peak memory 238700 kb
Host smart-43dbd78d-48ea-4966-bd27-4c0b97426548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90319
2150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.903192150
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.620562382
Short name T519
Test name
Test status
Simulation time 47556251 ps
CPU time 4.39 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 01:28:43 PM PST 23
Peak memory 240488 kb
Host smart-adaf8c89-eaa1-4684-aee4-36e85be33c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62056
2382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.620562382
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3552435394
Short name T723
Test name
Test status
Simulation time 204087939770 ps
CPU time 3002.5 seconds
Started Dec 24 01:28:38 PM PST 23
Finished Dec 24 02:18:42 PM PST 23
Peak memory 305356 kb
Host smart-7472e144-cb3f-4c97-afaf-4d1d209a86d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552435394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3552435394
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.329890678
Short name T711
Test name
Test status
Simulation time 26088050472 ps
CPU time 2837.77 seconds
Started Dec 24 01:28:36 PM PST 23
Finished Dec 24 02:15:55 PM PST 23
Peak memory 297892 kb
Host smart-567d5c2d-9244-48e4-80b5-fcc6141d5742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329890678 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.329890678
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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