Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	93416	1			T4	1		T15	13		T79	298
class_i[0x1]	56581	1			T1	4		T15	8		T34	51
class_i[0x2]	52882	1			T1	8		T3	86		T4	4
class_i[0x3]	52550	1			T4	6		T9	1		T37	3285

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	66534	1			T1	3		T3	15		T4	1
alert[0x1]	62927	1			T1	2		T3	18		T4	2
alert[0x2]	60371	1			T1	3		T3	30		T4	7
alert[0x3]	65597	1			T1	4		T3	23		T4	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

255180

1

T1

8

T3

86

T4

11

esc_ping_fail

249

1

T1

4

T9

7

T10

11

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	66462	1			T1	2		T3	15		T4	1
esc_integrity_fail	alert[0x1]	62857	1			T1	1		T3	18		T4	2
esc_integrity_fail	alert[0x2]	60312	1			T1	2		T3	30		T4	7
esc_integrity_fail	alert[0x3]	65549	1			T1	3		T3	23		T4	1
esc_ping_fail	alert[0x0]	72	1			T1	1		T9	3		T10	2
esc_ping_fail	alert[0x1]	70	1			T1	1		T9	1		T10	3
esc_ping_fail	alert[0x2]	59	1			T1	1		T9	2		T10	3
esc_ping_fail	alert[0x3]	48	1			T1	1		T9	1		T10	3

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	93364	1			T4	1		T15	13		T79	298
esc_integrity_fail	class_i[0x1]	56508	1			T15	8		T34	51		T35	90
esc_integrity_fail	class_i[0x2]	52829	1			T1	8		T3	86		T4	4
esc_integrity_fail	class_i[0x3]	52479	1			T4	6		T37	3285		T79	3
esc_ping_fail	class_i[0x0]	52	1			T10	11		T209	1		T210	7
esc_ping_fail	class_i[0x1]	73	1			T1	4		T300	6		T316	4
esc_ping_fail	class_i[0x2]	53	1			T9	6		T209	6		T233	2
esc_ping_fail	class_i[0x3]	71	1			T9	1		T209	2		T210	1