Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	85	1			T33	1		T81	1		T96	1
class_index[0x1]	62	1			T34	2		T81	1		T99	1
class_index[0x2]	73	1			T35	2		T97	1		T62	1
class_index[0x3]	76	1			T33	1		T34	2		T77	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	107	1			T33	2		T77	1		T81	1
intr_timeout_cnt[1]	63	1			T81	1		T99	1		T97	1
intr_timeout_cnt[2]	33	1			T35	2		T97	2		T68	1
intr_timeout_cnt[3]	17	1			T34	2		T96	1		T70	1
intr_timeout_cnt[4]	16	1			T34	1		T41	2		T66	1
intr_timeout_cnt[5]	19	1			T91	1		T40	1		T41	1
intr_timeout_cnt[6]	8	1			T34	1		T272	1		T273	1
intr_timeout_cnt[7]	14	1			T274	1		T243	1		T120	1
intr_timeout_cnt[8]	9	1			T91	1		T104	1		T106	1
intr_timeout_cnt[9]	10	1			T68	1		T69	1		T272	2

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	25	1			T33	1		T62	3		T41	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T81	1		T40	1		T107	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T130	1		T275	1		T276	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T96	1		T241	1		T277	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T41	1		T248	1		T278	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T268	1		T279	1		T280	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T273	1		T262	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	11	1			T274	1		T243	1		T120	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T91	1		T121	1		T281	1
class_index[0x0]	intr_timeout_cnt[9]	3	1			T69	1		T272	2		-	-
class_index[0x1]	intr_timeout_cnt[0]	21	1			T81	1		T91	1		T101	3
class_index[0x1]	intr_timeout_cnt[1]	11	1			T99	1		T91	1		T92	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T120	4		T282	1		T283	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T34	2		T70	1		T284	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T66	1		T272	1		T285	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T40	1		T107	1		T279	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T76	1		T286	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T248	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T104	1		T255	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T75	1		T287	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	24	1			T62	1		T40	1		T41	1
class_index[0x2]	intr_timeout_cnt[1]	21	1			T91	1		T69	1		T243	1
class_index[0x2]	intr_timeout_cnt[2]	10	1			T35	2		T97	1		T69	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T288	1		T278	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	3	1			T41	1		T289	1		T290	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T69	1		T70	1		T271	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T291	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T275	1		T284	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T106	1		T120	1		T292	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T120	1		T283	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	37	1			T33	1		T77	1		T55	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T97	1		T70	1		T272	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T97	1		T68	1		T69	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T293	1		T294	1		T271	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T34	1		T131	1		T295	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T91	1		T41	1		T275	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T34	1		T272	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T38	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T68	1		T296	1		T297	1