Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357852	1			T23	1		T27	8		T29	8
all_values[1]	357852	1			T23	1		T27	8		T29	8
all_values[2]	357852	1			T23	1		T27	8		T29	8
all_values[3]	357852	1			T23	1		T27	8		T29	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

712070

1

T23

4

T27

17

T29

17

auto[1]

719338

1

T27

15

T29

15

T136

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851730

1

T23

4

T27

15

T29

25

auto[1]

579678

1

T27

17

T29

7

T136

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100145	1			T23	1		T27	2		T29	5
all_values[0]	auto[0]	auto[1]	77950	1			T27	4		T136	2		T202	1
all_values[0]	auto[1]	auto[0]	101642	1			T29	3		T202	2		T354	1
all_values[0]	auto[1]	auto[1]	78115	1			T27	2		T136	1		T202	4
all_values[1]	auto[0]	auto[0]	108666	1			T23	1		T27	1		T136	1
all_values[1]	auto[0]	auto[1]	69415	1			T27	3		T29	2		T202	4
all_values[1]	auto[1]	auto[0]	110404	1			T27	2		T29	5		T136	2
all_values[1]	auto[1]	auto[1]	69367	1			T27	2		T29	1		T136	2
all_values[2]	auto[0]	auto[0]	107271	1			T23	1		T27	2		T29	4
all_values[2]	auto[0]	auto[1]	70885	1			T27	2		T202	1		T355	2
all_values[2]	auto[1]	auto[0]	108714	1			T27	4		T29	4		T136	5
all_values[2]	auto[1]	auto[1]	70982	1			T202	3		T355	2		T356	1
all_values[3]	auto[0]	auto[0]	106557	1			T23	1		T27	3		T29	3
all_values[3]	auto[0]	auto[1]	71181	1			T29	3		T136	1		T202	4
all_values[3]	auto[1]	auto[0]	108331	1			T27	1		T29	1		T136	3
all_values[3]	auto[1]	auto[1]	71783	1			T27	4		T29	1		T136	1