Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357852	1			T23	1		T27	8		T29	8
all_pins[1]	357852	1			T23	1		T27	8		T29	8
all_pins[2]	357852	1			T23	1		T27	8		T29	8
all_pins[3]	357852	1			T23	1		T27	8		T29	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1141161	1			T23	4		T27	24		T29	30
values[0x1]	290247	1			T27	8		T29	2		T136	4
transitions[0x0=>0x1]	194099	1			T27	7		T29	2		T136	3
transitions[0x1=>0x0]	194366	1			T27	7		T29	2		T136	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	279737	1			T23	1		T27	6		T29	8
all_pins[0]	values[0x1]	78115	1			T27	2		T136	1		T202	4
all_pins[0]	transitions[0x0=>0x1]	77401	1			T27	1		T202	2		T356	1
all_pins[0]	transitions[0x1=>0x0]	71336	1			T27	3		T29	1		T136	1
all_pins[1]	values[0x0]	288485	1			T23	1		T27	6		T29	7
all_pins[1]	values[0x1]	69367	1			T27	2		T29	1		T136	2
all_pins[1]	transitions[0x0=>0x1]	37199	1			T27	2		T29	1		T136	2
all_pins[1]	transitions[0x1=>0x0]	45947	1			T27	2		T136	1		T202	4
all_pins[2]	values[0x0]	286870	1			T23	1		T27	8		T29	8
all_pins[2]	values[0x1]	70982	1			T202	3		T355	2		T356	1
all_pins[2]	transitions[0x0=>0x1]	39635	1			T202	2		T355	2		T356	1
all_pins[2]	transitions[0x1=>0x0]	38020	1			T27	2		T29	1		T136	2
all_pins[3]	values[0x0]	286069	1			T23	1		T27	4		T29	7
all_pins[3]	values[0x1]	71783	1			T27	4		T29	1		T136	1
all_pins[3]	transitions[0x0=>0x1]	39864	1			T27	4		T29	1		T136	1
all_pins[3]	transitions[0x1=>0x0]	39063	1			T202	3		T355	2		T356	1