Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T27	7		T29	7		T136	4
all_values[1]	263	1			T27	7		T29	7		T136	4
all_values[2]	263	1			T27	7		T29	7		T136	4
all_values[3]	263	1			T27	7		T29	7		T136	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

562

1

T27

16

T29

17

T136

4

auto[1]

490

1

T27

12

T29

11

T136

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

428

1

T27

11

T29

16

T136

6

auto[1]

624

1

T27

17

T29

12

T136

10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639

1

T27

15

T29

17

T136

8

auto[1]

413

1

T27

13

T29

11

T136

8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

64

1

T27

1

T29

2

T202

1

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T27

1

T136

1

T246

2

all_values[0]

auto[0]

auto[1]

auto[0]

39

1

T29

4

T202

1

T354

1

all_values[0]

auto[0]

auto[1]

auto[1]

33

1

T27

1

T202

2

T357

1

all_values[0]

auto[1]

auto[0]

auto[1]

49

1

T27

2

T29

1

T136

1

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T27

2

T136

2

T202

2

all_values[1]

auto[0]

auto[0]

auto[0]

48

1

T29

2

T203

3

T355

2

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T27

1

T202

1

T355

1

all_values[1]

auto[0]

auto[1]

auto[0]

54

1

T27

2

T29

1

T136

1

all_values[1]

auto[0]

auto[1]

auto[1]

27

1

T136

1

T202

2

T358

1

all_values[1]

auto[1]

auto[0]

auto[1]

58

1

T27

2

T29

1

T136

1

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T27

2

T29

3

T136

1

all_values[2]

auto[0]

auto[0]

auto[0]

59

1

T27

3

T29

4

T202

1

all_values[2]

auto[0]

auto[0]

auto[1]

18

1

T355

1

T356

1

T359

1

all_values[2]

auto[0]

auto[1]

auto[0]

60

1

T27

2

T29

2

T136

4

all_values[2]

auto[0]

auto[1]

auto[1]

26

1

T202

1

T355

1

T360

1

all_values[2]

auto[1]

auto[0]

auto[1]

56

1

T27

2

T29

1

T202

1

all_values[2]

auto[1]

auto[1]

auto[1]

44

1

T202

2

T203

1

T355

1

all_values[3]

auto[0]

auto[0]

auto[0]

63

1

T27

3

T203

1

T355

2

all_values[3]

auto[0]

auto[0]

auto[1]

32

1

T29

1

T202

1

T203

1

all_values[3]

auto[0]

auto[1]

auto[0]

41

1

T29

1

T136

1

T202

1

all_values[3]

auto[0]

auto[1]

auto[1]

23

1

T27

1

T354

1

T357

2

all_values[3]

auto[1]

auto[0]

auto[1]

63

1

T27

1

T29

5

T136

1

all_values[3]

auto[1]

auto[1]

auto[1]

41

1

T27

2

T136

2

T202

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal