Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83650	1			T4	1049		T39	1154		T60	462
accum_cnt_1000	235430	1			T3	356		T4	1061		T5	814
accum_cnt_100	28443	1			T2	13		T3	157		T4	57
accum_cnt_50	65073	1			T2	12		T3	216		T4	60
accum_cnt_10	192697	1			T1	31		T2	2		T3	427
accum_cnt_0	417836	1			T1	49		T2	81		T3	712

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	264369	1			T1	20		T2	27		T3	467
class_index[0x1]	264369	1			T1	20		T2	27		T3	467
class_index[0x2]	264369	1			T1	20		T2	27		T3	467
class_index[0x3]	264368	1			T1	20		T2	27		T3	467

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24217	1			T4	545		T39	583		T60	266
class_index[0x0]	accum_cnt_1000	63748	1			T3	134		T4	494		T17	733
class_index[0x0]	accum_cnt_100	7454	1			T2	13		T3	58		T4	28
class_index[0x0]	accum_cnt_50	18163	1			T2	12		T3	64		T4	30
class_index[0x0]	accum_cnt_10	45432	1			T2	2		T3	174		T4	4
class_index[0x0]	accum_cnt_0	91902	1			T1	20		T3	37		T4	1
class_index[0x1]	accum_cnt_2000	18414	1			T39	571		T60	196		T37	382
class_index[0x1]	accum_cnt_1000	51869	1			T3	86		T6	354		T16	363
class_index[0x1]	accum_cnt_100	7280	1			T3	27		T6	160		T58	6
class_index[0x1]	accum_cnt_50	17247	1			T3	53		T33	40		T6	153
class_index[0x1]	accum_cnt_10	48049	1			T3	49		T4	1143		T5	1088
class_index[0x1]	accum_cnt_0	115183	1			T1	20		T2	27		T3	252
class_index[0x2]	accum_cnt_2000	22331	1			T37	373		T124	32		T43	541
class_index[0x2]	accum_cnt_1000	61541	1			T3	5		T7	714		T59	62
class_index[0x2]	accum_cnt_100	7329	1			T3	24		T7	144		T59	14
class_index[0x2]	accum_cnt_50	15000	1			T3	32		T57	2		T7	139
class_index[0x2]	accum_cnt_10	48089	1			T1	13		T3	129		T19	44
class_index[0x2]	accum_cnt_0	102538	1			T1	7		T2	27		T3	277
class_index[0x3]	accum_cnt_2000	18688	1			T4	504		T37	220		T83	184
class_index[0x3]	accum_cnt_1000	58272	1			T3	131		T4	567		T5	814
class_index[0x3]	accum_cnt_100	6380	1			T3	48		T4	29		T5	151
class_index[0x3]	accum_cnt_50	14663	1			T3	67		T4	30		T5	106
class_index[0x3]	accum_cnt_10	51127	1			T1	18		T3	75		T4	13
class_index[0x3]	accum_cnt_0	108213	1			T1	2		T2	27		T3	146