Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4565	1			T15	385		T96	17		T62	1
alert[0x1]	7952	1			T9	1		T209	1		T97	1042
alert[0x2]	6783	1			T3	6		T83	9		T97	11
alert[0x3]	7245	1			T15	169		T83	2		T40	2
alert[0x4]	3485	1			T9	1		T209	2		T49	13
alert[0x5]	7650	1			T10	1		T209	1		T63	9
alert[0x6]	2657	1			T1	1		T83	61		T10	1
alert[0x7]	5435	1			T10	1		T210	1		T41	35
alert[0x8]	11340	1			T15	1357		T83	6		T62	13
alert[0x9]	8752	1			T62	57		T40	10		T103	3
alert[0xa]	4076	1			T8	1		T15	265		T10	1
alert[0xb]	4707	1			T9	1		T209	1		T96	4
alert[0xc]	3247	1			T15	5		T9	1		T83	14
alert[0xd]	5519	1			T210	1		T259	109		T300	1
alert[0xe]	5655	1			T15	29		T83	102		T95	8
alert[0xf]	6161	1			T83	103		T210	1		T62	24
alert[0x10]	7018	1			T15	584		T83	6		T96	1
alert[0x11]	7307	1			T1	1		T10	1		T210	1
alert[0x12]	3974	1			T96	47		T97	45		T63	226
alert[0x13]	10032	1			T8	1		T15	3		T62	20
alert[0x14]	3161	1			T9	1		T83	117		T209	1
alert[0x15]	4915	1			T1	1		T15	192		T41	62
alert[0x16]	7220	1			T15	33		T210	1		T49	3
alert[0x17]	8146	1			T1	2		T15	806		T83	11
alert[0x18]	3785	1			T15	58		T34	6		T209	1
alert[0x19]	3332	1			T9	1		T83	98		T209	1
alert[0x1a]	3111	1			T3	4		T97	343		T62	92
alert[0x1b]	5024	1			T3	57		T15	229		T9	1
alert[0x1c]	5718	1			T79	1		T10	1		T96	5
alert[0x1d]	2082	1			T209	1		T210	1		T97	25
alert[0x1e]	15556	1			T1	1		T15	65		T62	184
alert[0x1f]	7546	1			T15	1593		T10	1		T96	3
alert[0x20]	5186	1			T83	98		T96	4		T97	9
alert[0x21]	5967	1			T49	3		T40	20		T63	9
alert[0x22]	8475	1			T1	1		T83	769		T10	1
alert[0x23]	3754	1			T9	1		T96	2		T91	2
alert[0x24]	2004	1			T15	33		T83	70		T10	1
alert[0x25]	5778	1			T15	427		T96	2		T62	56
alert[0x26]	6435	1			T3	22		T83	477		T96	1
alert[0x27]	5361	1			T3	1		T83	99		T210	1
alert[0x28]	5491	1			T1	1		T3	9		T15	148
alert[0x29]	5943	1			T96	1		T97	3		T41	16
alert[0x2a]	5095	1			T15	232		T10	1		T62	26
alert[0x2b]	4723	1			T10	1		T96	1		T40	14
alert[0x2c]	12730	1			T3	1		T83	19		T52	1
alert[0x2d]	16567	1			T3	1		T83	53		T210	1
alert[0x2e]	2472	1			T9	1		T79	1		T83	16
alert[0x2f]	5840	1			T9	1		T49	2		T62	74
alert[0x30]	2907	1			T3	3		T15	63		T83	114
alert[0x31]	7822	1			T83	115		T10	1		T209	2
alert[0x32]	3566	1			T15	581		T10	1		T97	14
alert[0x33]	8991	1			T1	1		T15	28		T9	1
alert[0x34]	6455	1			T83	82		T209	1		T210	1
alert[0x35]	3448	1			T15	38		T83	12		T95	1
alert[0x36]	2548	1			T83	7		T10	1		T210	1
alert[0x37]	11527	1			T15	1915		T83	25		T62	10
alert[0x38]	4367	1			T15	4		T83	72		T49	3
alert[0x39]	3648	1			T15	229		T83	278		T62	23
alert[0x3a]	1687	1			T3	7		T49	3		T40	1
alert[0x3b]	3442	1			T15	36		T83	492		T49	14
alert[0x3c]	9090	1			T83	68		T209	1		T49	2
alert[0x3d]	2851	1			T1	1		T3	20		T15	368
alert[0x3e]	11295	1			T64	160		T104	766		T107	39
alert[0x3f]	6818	1			T15	46		T83	63		T210	1
alert[0x40]	9823	1			T62	106		T259	13		T300	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	181727	1			T1	1		T15	9921		T79	1
class_i[0x1]	70823	1			T1	1		T3	131		T9	11
class_i[0x2]	46617	1			T34	6		T79	1		T83	10
class_i[0x3]	96095	1			T1	8		T8	2		T209	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

394645

1

T3

131

T15

9921

T34

6

alert_ping_fail

617

1

T1

10

T8

2

T9

11

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4560	1			T15	385		T96	17		T62	1
alert_integrity_fail	alert[0x1]	7942	1			T97	1042		T62	21		T41	640
alert_integrity_fail	alert[0x2]	6776	1			T3	6		T83	9		T97	11
alert_integrity_fail	alert[0x3]	7242	1			T15	169		T83	2		T40	2
alert_integrity_fail	alert[0x4]	3479	1			T49	13		T96	2		T97	11
alert_integrity_fail	alert[0x5]	7636	1			T63	9		T64	3893		T107	61
alert_integrity_fail	alert[0x6]	2641	1			T83	61		T62	27		T259	13
alert_integrity_fail	alert[0x7]	5419	1			T41	35		T64	70		T104	7
alert_integrity_fail	alert[0x8]	11330	1			T15	1357		T83	6		T62	13
alert_integrity_fail	alert[0x9]	8744	1			T62	57		T40	10		T103	3
alert_integrity_fail	alert[0xa]	4065	1			T15	265		T49	3		T97	26
alert_integrity_fail	alert[0xb]	4694	1			T96	4		T62	265		T91	1
alert_integrity_fail	alert[0xc]	3240	1			T15	5		T83	14		T95	4
alert_integrity_fail	alert[0xd]	5509	1			T259	109		T63	46		T104	11
alert_integrity_fail	alert[0xe]	5644	1			T15	29		T83	102		T95	8
alert_integrity_fail	alert[0xf]	6151	1			T83	103		T62	24		T40	9
alert_integrity_fail	alert[0x10]	7008	1			T15	584		T83	6		T96	1
alert_integrity_fail	alert[0x11]	7297	1			T97	47		T40	4		T41	309
alert_integrity_fail	alert[0x12]	3967	1			T96	47		T97	45		T63	226
alert_integrity_fail	alert[0x13]	10018	1			T15	3		T62	20		T63	58
alert_integrity_fail	alert[0x14]	3153	1			T83	117		T97	48		T91	3
alert_integrity_fail	alert[0x15]	4906	1			T15	192		T41	62		T259	2973
alert_integrity_fail	alert[0x16]	7203	1			T15	33		T49	3		T56	20
alert_integrity_fail	alert[0x17]	8132	1			T15	806		T83	11		T259	11
alert_integrity_fail	alert[0x18]	3770	1			T15	58		T34	6		T63	6
alert_integrity_fail	alert[0x19]	3319	1			T83	98		T56	7		T96	11
alert_integrity_fail	alert[0x1a]	3103	1			T3	4		T97	343		T62	92
alert_integrity_fail	alert[0x1b]	5006	1			T3	57		T15	229		T83	28
alert_integrity_fail	alert[0x1c]	5711	1			T79	1		T96	5		T40	1
alert_integrity_fail	alert[0x1d]	2069	1			T97	25		T62	17		T41	36
alert_integrity_fail	alert[0x1e]	15548	1			T15	65		T62	184		T91	1
alert_integrity_fail	alert[0x1f]	7533	1			T15	1593		T96	3		T259	66
alert_integrity_fail	alert[0x20]	5177	1			T83	98		T96	4		T97	9
alert_integrity_fail	alert[0x21]	5965	1			T49	3		T40	20		T63	9
alert_integrity_fail	alert[0x22]	8464	1			T83	769		T259	26		T64	149
alert_integrity_fail	alert[0x23]	3744	1			T96	2		T91	2		T40	120
alert_integrity_fail	alert[0x24]	1994	1			T15	33		T83	70		T96	4
alert_integrity_fail	alert[0x25]	5767	1			T15	427		T96	2		T62	56
alert_integrity_fail	alert[0x26]	6428	1			T3	22		T83	477		T96	1
alert_integrity_fail	alert[0x27]	5352	1			T3	1		T83	99		T62	53
alert_integrity_fail	alert[0x28]	5476	1			T3	9		T15	148		T62	3
alert_integrity_fail	alert[0x29]	5940	1			T96	1		T97	3		T41	16
alert_integrity_fail	alert[0x2a]	5084	1			T15	232		T62	26		T40	6
alert_integrity_fail	alert[0x2b]	4715	1			T96	1		T40	14		T259	58
alert_integrity_fail	alert[0x2c]	12720	1			T3	1		T83	19		T41	186
alert_integrity_fail	alert[0x2d]	16559	1			T3	1		T83	53		T97	19
alert_integrity_fail	alert[0x2e]	2461	1			T79	1		T83	16		T49	3
alert_integrity_fail	alert[0x2f]	5833	1			T49	2		T62	74		T40	11
alert_integrity_fail	alert[0x30]	2895	1			T3	3		T15	63		T83	114
alert_integrity_fail	alert[0x31]	7812	1			T83	115		T62	3		T301	9
alert_integrity_fail	alert[0x32]	3560	1			T15	581		T97	14		T41	313
alert_integrity_fail	alert[0x33]	8979	1			T15	28		T83	84		T62	14
alert_integrity_fail	alert[0x34]	6444	1			T83	82		T49	7		T259	693
alert_integrity_fail	alert[0x35]	3443	1			T15	38		T83	12		T95	1
alert_integrity_fail	alert[0x36]	2536	1			T83	7		T97	100		T62	127
alert_integrity_fail	alert[0x37]	11523	1			T15	1915		T83	25		T62	10
alert_integrity_fail	alert[0x38]	4362	1			T15	4		T83	72		T49	3
alert_integrity_fail	alert[0x39]	3640	1			T15	229		T83	278		T62	23
alert_integrity_fail	alert[0x3a]	1678	1			T3	7		T49	3		T40	1
alert_integrity_fail	alert[0x3b]	3439	1			T15	36		T83	492		T49	14
alert_integrity_fail	alert[0x3c]	9081	1			T83	68		T49	2		T96	63
alert_integrity_fail	alert[0x3d]	2841	1			T3	20		T15	368		T83	22
alert_integrity_fail	alert[0x3e]	11288	1			T64	160		T104	766		T107	39
alert_integrity_fail	alert[0x3f]	6810	1			T15	46		T83	63		T62	104
alert_integrity_fail	alert[0x40]	9820	1			T62	106		T259	13		T63	457
alert_ping_fail	alert[0x0]	5	1			T302	1		T264	1		T303	1
alert_ping_fail	alert[0x1]	10	1			T9	1		T209	1		T304	1
alert_ping_fail	alert[0x2]	7	1			T305	1		T304	2		T306	1
alert_ping_fail	alert[0x3]	3	1			T300	1		T302	1		T307	1
alert_ping_fail	alert[0x4]	6	1			T9	1		T209	2		T303	1
alert_ping_fail	alert[0x5]	14	1			T10	1		T209	1		T308	2
alert_ping_fail	alert[0x6]	16	1			T1	1		T10	1		T209	1
alert_ping_fail	alert[0x7]	16	1			T10	1		T210	1		T309	3
alert_ping_fail	alert[0x8]	10	1			T233	1		T304	1		T310	2
alert_ping_fail	alert[0x9]	8	1			T300	1		T311	1		T312	1
alert_ping_fail	alert[0xa]	11	1			T8	1		T10	1		T302	2
alert_ping_fail	alert[0xb]	13	1			T9	1		T209	1		T302	2
alert_ping_fail	alert[0xc]	7	1			T9	1		T313	1		T305	1
alert_ping_fail	alert[0xd]	10	1			T210	1		T300	1		T305	2
alert_ping_fail	alert[0xe]	11	1			T210	1		T233	1		T302	2
alert_ping_fail	alert[0xf]	10	1			T210	1		T313	1		T237	2
alert_ping_fail	alert[0x10]	10	1			T233	1		T300	1		T310	1
alert_ping_fail	alert[0x11]	10	1			T1	1		T10	1		T210	1
alert_ping_fail	alert[0x12]	7	1			T313	1		T305	1		T314	1
alert_ping_fail	alert[0x13]	14	1			T8	1		T302	1		T311	1
alert_ping_fail	alert[0x14]	8	1			T9	1		T209	1		T313	1
alert_ping_fail	alert[0x15]	9	1			T1	1		T237	1		T315	1
alert_ping_fail	alert[0x16]	17	1			T210	1		T300	1		T314	3
alert_ping_fail	alert[0x17]	14	1			T1	2		T10	1		T308	1
alert_ping_fail	alert[0x18]	15	1			T209	1		T210	1		T304	1
alert_ping_fail	alert[0x19]	13	1			T9	1		T209	1		T316	1
alert_ping_fail	alert[0x1a]	8	1			T313	1		T302	1		T317	1
alert_ping_fail	alert[0x1b]	18	1			T9	1		T209	2		T318	1
alert_ping_fail	alert[0x1c]	7	1			T10	1		T300	1		T319	1
alert_ping_fail	alert[0x1d]	13	1			T209	1		T210	1		T314	1
alert_ping_fail	alert[0x1e]	8	1			T1	1		T300	1		T304	1
alert_ping_fail	alert[0x1f]	13	1			T10	1		T306	1		T237	1
alert_ping_fail	alert[0x20]	9	1			T318	1		T306	1		T320	1
alert_ping_fail	alert[0x21]	2	1			T264	1		T321	1		-	-
alert_ping_fail	alert[0x22]	11	1			T1	1		T10	1		T300	1
alert_ping_fail	alert[0x23]	10	1			T9	1		T304	1		T320	1
alert_ping_fail	alert[0x24]	10	1			T10	1		T209	1		T305	1
alert_ping_fail	alert[0x25]	11	1			T300	2		T320	1		T322	2
alert_ping_fail	alert[0x26]	7	1			T306	1		T237	1		T323	1
alert_ping_fail	alert[0x27]	9	1			T210	1		T233	1		T316	1
alert_ping_fail	alert[0x28]	15	1			T1	1		T10	2		T300	1
alert_ping_fail	alert[0x29]	3	1			T324	1		T325	1		T252	1
alert_ping_fail	alert[0x2a]	11	1			T10	1		T233	1		T316	1
alert_ping_fail	alert[0x2b]	8	1			T10	1		T300	1		T305	2
alert_ping_fail	alert[0x2c]	10	1			T52	1		T308	1		T316	1
alert_ping_fail	alert[0x2d]	8	1			T210	1		T304	1		T306	1
alert_ping_fail	alert[0x2e]	11	1			T9	1		T10	2		T209	1
alert_ping_fail	alert[0x2f]	7	1			T9	1		T237	1		T326	1
alert_ping_fail	alert[0x30]	12	1			T10	1		T209	1		T327	1
alert_ping_fail	alert[0x31]	10	1			T10	1		T209	2		T210	1
alert_ping_fail	alert[0x32]	6	1			T10	1		T317	1		T312	1
alert_ping_fail	alert[0x33]	12	1			T1	1		T9	1		T300	1
alert_ping_fail	alert[0x34]	11	1			T209	1		T210	1		T237	1
alert_ping_fail	alert[0x35]	5	1			T317	2		T328	1		T329	1
alert_ping_fail	alert[0x36]	12	1			T10	1		T210	1		T304	1
alert_ping_fail	alert[0x37]	4	1			T233	1		T305	1		T317	1
alert_ping_fail	alert[0x38]	5	1			T300	1		T317	1		T330	1
alert_ping_fail	alert[0x39]	8	1			T320	1		T331	1		T332	1
alert_ping_fail	alert[0x3a]	9	1			T300	1		T302	2		T237	1
alert_ping_fail	alert[0x3b]	3	1			T333	1		T334	1		T335	1
alert_ping_fail	alert[0x3c]	9	1			T209	1		T314	1		T336	3
alert_ping_fail	alert[0x3d]	10	1			T1	1		T316	1		T311	1
alert_ping_fail	alert[0x3e]	7	1			T313	1		T312	1		T303	1
alert_ping_fail	alert[0x3f]	8	1			T210	1		T305	1		T333	1
alert_ping_fail	alert[0x40]	3	1			T300	1		T302	2		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	181488	1			T15	9921		T79	1		T83	4
alert_integrity_fail	class_i[0x1]	70673	1			T3	131		T83	3578		T56	30
alert_integrity_fail	class_i[0x2]	46462	1			T34	6		T79	1		T83	10
alert_integrity_fail	class_i[0x3]	96022	1			T49	16		T96	186		T62	1081
alert_ping_fail	class_i[0x0]	239	1			T1	1		T10	19		T209	1
alert_ping_fail	class_i[0x1]	150	1			T1	1		T9	11		T209	2
alert_ping_fail	class_i[0x2]	155	1			T10	1		T209	15		T233	2
alert_ping_fail	class_i[0x3]	73	1			T1	8		T8	2		T209	1