Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.68 99.97 100.00 100.00 99.30 99.72


Total test records in report: 848
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T779 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3341775751 Dec 27 12:31:33 PM PST 23 Dec 27 12:32:40 PM PST 23 926883920 ps
T780 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3611922765 Dec 27 12:31:21 PM PST 23 Dec 27 12:32:32 PM PST 23 524957807 ps
T781 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.510037259 Dec 27 12:33:25 PM PST 23 Dec 27 12:33:56 PM PST 23 471274319 ps
T782 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2176897612 Dec 27 12:33:53 PM PST 23 Dec 27 12:34:20 PM PST 23 172980844 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.619699867 Dec 27 12:30:39 PM PST 23 Dec 27 12:31:43 PM PST 23 540145524 ps
T148 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2921489967 Dec 27 12:31:28 PM PST 23 Dec 27 12:41:25 PM PST 23 8912451454 ps
T784 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3639650207 Dec 27 12:33:09 PM PST 23 Dec 27 12:33:55 PM PST 23 333569377 ps
T785 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1199023393 Dec 27 12:31:29 PM PST 23 Dec 27 12:32:42 PM PST 23 1338197301 ps
T786 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.24497483 Dec 27 12:30:37 PM PST 23 Dec 27 12:31:37 PM PST 23 503583055 ps
T787 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1304351932 Dec 27 12:31:07 PM PST 23 Dec 27 12:31:57 PM PST 23 6898049 ps
T788 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1758528871 Dec 27 12:32:57 PM PST 23 Dec 27 12:33:32 PM PST 23 27655452 ps
T156 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1981077099 Dec 27 12:31:06 PM PST 23 Dec 27 12:50:53 PM PST 23 28305226408 ps
T789 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3577141535 Dec 27 12:30:56 PM PST 23 Dec 27 12:31:56 PM PST 23 141680215 ps
T790 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1504610484 Dec 27 12:30:42 PM PST 23 Dec 27 12:31:40 PM PST 23 10370268 ps
T791 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3103917770 Dec 27 12:31:25 PM PST 23 Dec 27 12:32:16 PM PST 23 11086059 ps
T185 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2581148359 Dec 27 12:31:02 PM PST 23 Dec 27 12:31:55 PM PST 23 94720166 ps
T792 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.888606756 Dec 27 12:31:18 PM PST 23 Dec 27 12:32:09 PM PST 23 24379895 ps
T793 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1372925528 Dec 27 12:31:09 PM PST 23 Dec 27 12:31:59 PM PST 23 9343641 ps
T151 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.917896606 Dec 27 12:31:25 PM PST 23 Dec 27 12:35:23 PM PST 23 1888647288 ps
T794 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1901246054 Dec 27 12:31:01 PM PST 23 Dec 27 12:32:02 PM PST 23 346857855 ps
T159 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4117750599 Dec 27 12:31:30 PM PST 23 Dec 27 12:35:34 PM PST 23 6824903442 ps
T191 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1605050962 Dec 27 12:32:01 PM PST 23 Dec 27 12:32:50 PM PST 23 37813688 ps
T164 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3839428859 Dec 27 12:34:02 PM PST 23 Dec 27 12:38:59 PM PST 23 8345262511 ps
T795 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3681207603 Dec 27 12:31:20 PM PST 23 Dec 27 12:32:11 PM PST 23 29789455 ps
T796 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.67510613 Dec 27 12:31:14 PM PST 23 Dec 27 12:32:04 PM PST 23 8632931 ps
T797 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2368674314 Dec 27 12:34:19 PM PST 23 Dec 27 12:34:40 PM PST 23 60869642 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2407843649 Dec 27 12:31:07 PM PST 23 Dec 27 12:32:02 PM PST 23 117111469 ps
T799 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1510812456 Dec 27 12:30:11 PM PST 23 Dec 27 12:31:08 PM PST 23 181208119 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1981330807 Dec 27 12:30:30 PM PST 23 Dec 27 12:31:36 PM PST 23 273894778 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4098662199 Dec 27 12:32:53 PM PST 23 Dec 27 12:33:39 PM PST 23 871696364 ps
T169 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.391644412 Dec 27 12:31:08 PM PST 23 Dec 27 12:45:49 PM PST 23 12646126305 ps
T802 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.354136799 Dec 27 12:31:12 PM PST 23 Dec 27 12:32:11 PM PST 23 360398445 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.105367520 Dec 27 12:30:30 PM PST 23 Dec 27 12:32:39 PM PST 23 2446136763 ps
T163 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1055976683 Dec 27 12:30:37 PM PST 23 Dec 27 12:35:58 PM PST 23 9262831887 ps
T804 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1349627347 Dec 27 12:31:19 PM PST 23 Dec 27 12:32:10 PM PST 23 18845979 ps
T805 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.553917157 Dec 27 12:31:48 PM PST 23 Dec 27 12:32:56 PM PST 23 5660096632 ps
T176 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1513140933 Dec 27 12:31:10 PM PST 23 Dec 27 12:39:18 PM PST 23 6477857974 ps
T806 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1948108563 Dec 27 12:30:53 PM PST 23 Dec 27 12:31:50 PM PST 23 35934736 ps
T807 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3847477551 Dec 27 12:31:15 PM PST 23 Dec 27 12:32:09 PM PST 23 240733339 ps
T808 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.789424711 Dec 27 12:31:20 PM PST 23 Dec 27 12:32:27 PM PST 23 268530047 ps
T809 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4234561616 Dec 27 12:31:08 PM PST 23 Dec 27 12:31:58 PM PST 23 8798947 ps
T810 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4145701678 Dec 27 12:31:18 PM PST 23 Dec 27 12:32:14 PM PST 23 56433795 ps
T811 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3550649677 Dec 27 12:31:19 PM PST 23 Dec 27 12:32:11 PM PST 23 8081369 ps
T160 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3149652779 Dec 27 12:31:10 PM PST 23 Dec 27 12:36:53 PM PST 23 4053629204 ps
T812 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1213924751 Dec 27 12:30:48 PM PST 23 Dec 27 12:32:24 PM PST 23 661122084 ps
T813 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.327420139 Dec 27 12:30:37 PM PST 23 Dec 27 12:31:38 PM PST 23 754922535 ps
T168 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.907115456 Dec 27 12:30:33 PM PST 23 Dec 27 12:36:13 PM PST 23 15499826916 ps
T814 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3993786009 Dec 27 12:30:56 PM PST 23 Dec 27 12:31:52 PM PST 23 64934039 ps
T188 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.765399339 Dec 27 12:30:31 PM PST 23 Dec 27 12:31:36 PM PST 23 179876479 ps
T177 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3034800448 Dec 27 12:30:57 PM PST 23 Dec 27 12:45:20 PM PST 23 12803764361 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.822196133 Dec 27 12:31:08 PM PST 23 Dec 27 12:32:31 PM PST 23 521165776 ps
T189 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3845825987 Dec 27 12:30:54 PM PST 23 Dec 27 12:32:45 PM PST 23 3697874235 ps
T816 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4093791236 Dec 27 12:32:45 PM PST 23 Dec 27 12:33:52 PM PST 23 470306015 ps
T162 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1406945607 Dec 27 12:33:45 PM PST 23 Dec 27 12:38:54 PM PST 23 4365751881 ps
T817 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1231138407 Dec 27 12:32:47 PM PST 23 Dec 27 12:33:29 PM PST 23 72260678 ps
T818 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3539431646 Dec 27 12:31:21 PM PST 23 Dec 27 12:32:13 PM PST 23 6342087 ps
T819 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2956034543 Dec 27 12:31:50 PM PST 23 Dec 27 12:32:38 PM PST 23 10868272 ps
T820 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.124140638 Dec 27 12:31:47 PM PST 23 Dec 27 12:32:38 PM PST 23 20619062 ps
T821 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3601595073 Dec 27 12:31:50 PM PST 23 Dec 27 12:32:38 PM PST 23 16121171 ps
T361 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2876174011 Dec 27 12:31:19 PM PST 23 Dec 27 12:41:55 PM PST 23 22174103545 ps
T822 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2332444099 Dec 27 12:31:15 PM PST 23 Dec 27 12:32:15 PM PST 23 170603803 ps
T823 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3708318037 Dec 27 12:31:11 PM PST 23 Dec 27 12:32:06 PM PST 23 140457701 ps
T824 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1744303915 Dec 27 12:31:21 PM PST 23 Dec 27 12:32:33 PM PST 23 1042107607 ps
T825 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.444834957 Dec 27 12:31:11 PM PST 23 Dec 27 12:32:01 PM PST 23 18047233 ps
T194 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.101528897 Dec 27 12:31:20 PM PST 23 Dec 27 12:32:12 PM PST 23 286581643 ps
T826 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1959164648 Dec 27 12:30:41 PM PST 23 Dec 27 12:31:44 PM PST 23 93229935 ps
T827 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3429506734 Dec 27 12:31:16 PM PST 23 Dec 27 12:32:06 PM PST 23 13948113 ps
T171 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2799728229 Dec 27 12:31:25 PM PST 23 Dec 27 12:35:10 PM PST 23 11059817845 ps
T828 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3163901146 Dec 27 12:31:14 PM PST 23 Dec 27 12:32:09 PM PST 23 179681576 ps
T829 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2105801400 Dec 27 12:30:32 PM PST 23 Dec 27 12:31:38 PM PST 23 263070978 ps
T170 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.59363146 Dec 27 12:30:33 PM PST 23 Dec 27 12:37:42 PM PST 23 24302749686 ps
T363 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3978571489 Dec 27 12:31:17 PM PST 23 Dec 27 12:41:01 PM PST 23 67629392847 ps
T830 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.752101799 Dec 27 12:30:33 PM PST 23 Dec 27 12:32:49 PM PST 23 861657699 ps
T831 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.772077456 Dec 27 12:31:53 PM PST 23 Dec 27 12:33:16 PM PST 23 11398810034 ps
T832 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2550555213 Dec 27 12:30:33 PM PST 23 Dec 27 12:36:17 PM PST 23 20002378100 ps
T833 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3675356921 Dec 27 12:31:10 PM PST 23 Dec 27 12:32:39 PM PST 23 6188495140 ps
T834 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2952577593 Dec 27 12:30:31 PM PST 23 Dec 27 12:31:33 PM PST 23 307299283 ps
T835 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2949270160 Dec 27 12:30:32 PM PST 23 Dec 27 12:31:32 PM PST 23 235245950 ps
T174 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2791357590 Dec 27 12:31:43 PM PST 23 Dec 27 12:50:30 PM PST 23 15512811230 ps
T836 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1763517811 Dec 27 12:31:15 PM PST 23 Dec 27 12:32:13 PM PST 23 131185529 ps
T172 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2353766068 Dec 27 12:30:38 PM PST 23 Dec 27 12:40:35 PM PST 23 17799577105 ps
T837 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.817448510 Dec 27 12:31:08 PM PST 23 Dec 27 12:31:58 PM PST 23 11007986 ps
T838 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3915661157 Dec 27 12:30:28 PM PST 23 Dec 27 12:31:35 PM PST 23 443269934 ps
T187 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1534209229 Dec 27 12:31:04 PM PST 23 Dec 27 12:32:58 PM PST 23 928280001 ps
T839 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.723755024 Dec 27 12:31:05 PM PST 23 Dec 27 12:31:59 PM PST 23 41062072 ps
T167 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1667140596 Dec 27 12:31:01 PM PST 23 Dec 27 12:34:52 PM PST 23 4031583154 ps
T840 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2560099325 Dec 27 12:31:17 PM PST 23 Dec 27 12:39:34 PM PST 23 40731728382 ps
T841 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3079294528 Dec 27 12:30:37 PM PST 23 Dec 27 12:34:11 PM PST 23 3743385126 ps
T842 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.102920559 Dec 27 12:31:16 PM PST 23 Dec 27 12:32:06 PM PST 23 24055932 ps
T843 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1628710660 Dec 27 12:30:29 PM PST 23 Dec 27 12:31:35 PM PST 23 484884860 ps
T844 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4189663395 Dec 27 12:31:17 PM PST 23 Dec 27 12:32:07 PM PST 23 16345940 ps
T362 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.503721403 Dec 27 12:30:33 PM PST 23 Dec 27 12:40:15 PM PST 23 20347096327 ps
T175 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1176967767 Dec 27 12:31:08 PM PST 23 Dec 27 12:40:47 PM PST 23 8763878474 ps
T845 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.778518391 Dec 27 12:31:02 PM PST 23 Dec 27 12:32:00 PM PST 23 483071614 ps
T846 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3478514156 Dec 27 12:31:20 PM PST 23 Dec 27 12:32:14 PM PST 23 142673739 ps
T192 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3648645089 Dec 27 12:31:07 PM PST 23 Dec 27 12:31:59 PM PST 23 211522822 ps
T847 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1136937483 Dec 27 12:31:22 PM PST 23 Dec 27 12:32:13 PM PST 23 11312469 ps
T848 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4050736440 Dec 27 12:31:00 PM PST 23 Dec 27 12:31:54 PM PST 23 83390320 ps

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.90234005
Short name T14
Test name
Test status
Simulation time 23082431 ps
CPU time 3.35 seconds
Started Dec 27 12:31:51 PM PST 23
Finished Dec 27 12:32:41 PM PST 23
Peak memory 236292 kb
Host smart-73c993f4-a109-4c58-8ce0-ea825d34060e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=90234005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.90234005
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.516514284
Short name T3
Test name
Test status
Simulation time 15208343853 ps
CPU time 630.18 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:53:00 PM PST 23
Peak memory 264964 kb
Host smart-c60f3f46-ce06-451a-b19a-228727632bbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516514284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.516514284
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.306936025
Short name T153
Test name
Test status
Simulation time 35071988685 ps
CPU time 544.9 seconds
Started Dec 27 12:32:31 PM PST 23
Finished Dec 27 12:42:16 PM PST 23
Peak memory 269308 kb
Host smart-1a32fd92-2b0a-41eb-891e-3f32e6cf431c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306936025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.306936025
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2713571478
Short name T15
Test name
Test status
Simulation time 56462553205 ps
CPU time 3066.19 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 01:34:07 PM PST 23
Peak memory 289276 kb
Host smart-1dbe0fef-5b0d-427a-a6f7-4e746d8a2ab8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713571478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2713571478
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4182458631
Short name T12
Test name
Test status
Simulation time 493394574 ps
CPU time 19.59 seconds
Started Dec 27 12:41:11 PM PST 23
Finished Dec 27 12:42:34 PM PST 23
Peak memory 264836 kb
Host smart-054cb974-29f2-4aa8-9c6a-a094e9e8e7de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4182458631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4182458631
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2617060035
Short name T139
Test name
Test status
Simulation time 318607371 ps
CPU time 38.28 seconds
Started Dec 27 12:31:07 PM PST 23
Finished Dec 27 12:32:34 PM PST 23
Peak memory 239256 kb
Host smart-381395e5-92c3-4696-9490-85694d75a2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2617060035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2617060035
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3299557474
Short name T142
Test name
Test status
Simulation time 10271462838 ps
CPU time 162.09 seconds
Started Dec 27 12:33:30 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 270396 kb
Host smart-c5c611fe-370c-4d45-b41b-4fcfd6ce6771
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3299557474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3299557474
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.300002688
Short name T39
Test name
Test status
Simulation time 176320010664 ps
CPU time 2508.15 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 01:24:45 PM PST 23
Peak memory 287896 kb
Host smart-635f5e03-e9dc-4464-8429-1bb546047246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300002688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.300002688
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.354839357
Short name T62
Test name
Test status
Simulation time 48292141764 ps
CPU time 4790.1 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 02:02:12 PM PST 23
Peak memory 338284 kb
Host smart-4d31f5c1-157c-430f-a7d2-ab884d771660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354839357 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.354839357
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.195150944
Short name T52
Test name
Test status
Simulation time 27832717568 ps
CPU time 1593.78 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 01:08:46 PM PST 23
Peak memory 272840 kb
Host smart-5fd9e02e-78fb-4b24-ace7-4ed6759dc00d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195150944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.195150944
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1943417847
Short name T202
Test name
Test status
Simulation time 27712430 ps
CPU time 1.39 seconds
Started Dec 27 12:31:04 PM PST 23
Finished Dec 27 12:31:55 PM PST 23
Peak memory 235704 kb
Host smart-fc7c9be1-8b7d-48d2-88b4-53b448b8a7ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1943417847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1943417847
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2615675043
Short name T146
Test name
Test status
Simulation time 5637243849 ps
CPU time 561.83 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:42:07 PM PST 23
Peak memory 265268 kb
Host smart-2a124880-0af3-42fa-95ec-6c1711ea1ddf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615675043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2615675043
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3855220821
Short name T107
Test name
Test status
Simulation time 50656755345 ps
CPU time 2918.82 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 01:31:22 PM PST 23
Peak memory 289372 kb
Host smart-432cdc96-8bc1-4f34-a279-9287df541308
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855220821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3855220821
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1320473423
Short name T143
Test name
Test status
Simulation time 4859486126 ps
CPU time 186.24 seconds
Started Dec 27 12:31:04 PM PST 23
Finished Dec 27 12:35:00 PM PST 23
Peak memory 269636 kb
Host smart-c3e86d8e-11b0-47cd-a993-51c57705cc49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1320473423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1320473423
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2548813773
Short name T209
Test name
Test status
Simulation time 44921778757 ps
CPU time 430.97 seconds
Started Dec 27 12:41:37 PM PST 23
Finished Dec 27 12:49:47 PM PST 23
Peak memory 247568 kb
Host smart-f4cf51bd-2624-488d-94b0-a1cb566174a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548813773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2548813773
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.284524690
Short name T147
Test name
Test status
Simulation time 18671078556 ps
CPU time 321.32 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:37:25 PM PST 23
Peak memory 265280 kb
Host smart-36bfc66f-7100-4d45-9319-3ea0b850090e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=284524690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.284524690
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1980875150
Short name T308
Test name
Test status
Simulation time 62733419781 ps
CPU time 2087.77 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 01:17:48 PM PST 23
Peak memory 281452 kb
Host smart-c39958bf-b2d4-46da-92cb-d7471b6641d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980875150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1980875150
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3260415005
Short name T97
Test name
Test status
Simulation time 261044551102 ps
CPU time 3320.38 seconds
Started Dec 27 12:41:24 PM PST 23
Finished Dec 27 01:37:47 PM PST 23
Peak memory 297960 kb
Host smart-713b4f6f-a472-4ece-9717-bb5471a376e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260415005 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3260415005
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1176967767
Short name T175
Test name
Test status
Simulation time 8763878474 ps
CPU time 530.51 seconds
Started Dec 27 12:31:08 PM PST 23
Finished Dec 27 12:40:47 PM PST 23
Peak memory 265412 kb
Host smart-8e58b192-3a8e-4a31-aa07-73ecd62ee595
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176967767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1176967767
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1707279362
Short name T207
Test name
Test status
Simulation time 723008054 ps
CPU time 10.77 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 12:42:33 PM PST 23
Peak memory 240444 kb
Host smart-83aa8f8b-3a1f-4e82-99a3-4ec5aa980edf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1707279362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1707279362
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3126528301
Short name T339
Test name
Test status
Simulation time 31001166499 ps
CPU time 1262.18 seconds
Started Dec 27 12:42:22 PM PST 23
Finished Dec 27 01:04:07 PM PST 23
Peak memory 282872 kb
Host smart-2ce0f5ff-3bd7-4e8e-9ec6-6e35332c251e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126528301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3126528301
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1667268266
Short name T300
Test name
Test status
Simulation time 39499222335 ps
CPU time 394.13 seconds
Started Dec 27 12:41:57 PM PST 23
Finished Dec 27 12:49:24 PM PST 23
Peak memory 247212 kb
Host smart-21f2d46e-8c48-44b7-b299-8df98e048358
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667268266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1667268266
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3776850452
Short name T149
Test name
Test status
Simulation time 51659720362 ps
CPU time 845.9 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:46:14 PM PST 23
Peak memory 265160 kb
Host smart-e0d2b391-103c-4697-8a01-7e4594d2f14d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776850452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3776850452
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.941035078
Short name T104
Test name
Test status
Simulation time 67847897272 ps
CPU time 4380.02 seconds
Started Dec 27 12:41:48 PM PST 23
Finished Dec 27 01:55:45 PM PST 23
Peak memory 305716 kb
Host smart-d2548168-5e9e-4e94-9561-288567daa995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941035078 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.941035078
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2299721886
Short name T157
Test name
Test status
Simulation time 17276328723 ps
CPU time 564 seconds
Started Dec 27 12:30:22 PM PST 23
Finished Dec 27 12:40:42 PM PST 23
Peak memory 265292 kb
Host smart-b02321f9-1565-42d1-8a6d-ae2213b624a7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299721886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2299721886
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.887731974
Short name T34
Test name
Test status
Simulation time 674064490 ps
CPU time 12.91 seconds
Started Dec 27 12:41:56 PM PST 23
Finished Dec 27 12:43:02 PM PST 23
Peak memory 251540 kb
Host smart-e5737ab4-e3be-4a15-8f74-dbc3e590e64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88773
1974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.887731974
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1406945607
Short name T162
Test name
Test status
Simulation time 4365751881 ps
CPU time 292.97 seconds
Started Dec 27 12:33:45 PM PST 23
Finished Dec 27 12:38:54 PM PST 23
Peak memory 265252 kb
Host smart-d821cd7e-0a0b-47f0-9f4c-8873356c99c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1406945607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1406945607
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2427522912
Short name T33
Test name
Test status
Simulation time 3428198785 ps
CPU time 190.62 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 12:46:07 PM PST 23
Peak memory 256788 kb
Host smart-10d3c32c-78ec-4899-a071-c0d5c224a398
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427522912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2427522912
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.31201879
Short name T338
Test name
Test status
Simulation time 61138108064 ps
CPU time 2318.67 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 01:21:27 PM PST 23
Peak memory 288104 kb
Host smart-aaefa8ee-7c06-436c-851d-684acf5515e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31201879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.31201879
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.599242248
Short name T312
Test name
Test status
Simulation time 51000118658 ps
CPU time 598.15 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 12:52:57 PM PST 23
Peak memory 246560 kb
Host smart-8cdd172f-ce22-469b-9761-937de18e8bb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599242248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.599242248
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.319619253
Short name T69
Test name
Test status
Simulation time 42365625337 ps
CPU time 693.72 seconds
Started Dec 27 12:41:56 PM PST 23
Finished Dec 27 12:54:23 PM PST 23
Peak memory 264924 kb
Host smart-e19b4938-94d6-4346-937c-aea1caf0d69c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319619253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.319619253
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1104448558
Short name T27
Test name
Test status
Simulation time 31010926 ps
CPU time 1.35 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:07 PM PST 23
Peak memory 236508 kb
Host smart-0de47cd1-5697-4e9a-8b6e-8c5d850c5996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1104448558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1104448558
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2000225918
Short name T85
Test name
Test status
Simulation time 22457041917 ps
CPU time 1360.53 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 01:05:42 PM PST 23
Peak memory 272472 kb
Host smart-e4481a18-3947-4018-88c2-3c134b235b90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000225918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2000225918
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.503721403
Short name T362
Test name
Test status
Simulation time 20347096327 ps
CPU time 524.67 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:40:15 PM PST 23
Peak memory 265216 kb
Host smart-98f36d9a-4f1d-4df1-a6a3-4db429e36199
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503721403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.503721403
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.632522126
Short name T66
Test name
Test status
Simulation time 87825976605 ps
CPU time 8331.8 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 03:01:48 PM PST 23
Peak memory 371364 kb
Host smart-15f319bf-460e-48ab-a2ae-244c02ffabe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632522126 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.632522126
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.952809902
Short name T325
Test name
Test status
Simulation time 18033465159 ps
CPU time 648.63 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:53:10 PM PST 23
Peak memory 247244 kb
Host smart-495695de-f895-47d2-b9c0-63756acc8672
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952809902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.952809902
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.683046550
Short name T305
Test name
Test status
Simulation time 13033729129 ps
CPU time 530.64 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:51:13 PM PST 23
Peak memory 247172 kb
Host smart-a033f50b-3280-4c8c-8a3b-f75d90a94af0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683046550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.683046550
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.81780331
Short name T255
Test name
Test status
Simulation time 25380297532 ps
CPU time 1584.32 seconds
Started Dec 27 12:42:30 PM PST 23
Finished Dec 27 01:09:33 PM PST 23
Peak memory 271356 kb
Host smart-7ce2dca2-1dcb-4839-aa5c-80981bd86910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81780331 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.81780331
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1251107978
Short name T41
Test name
Test status
Simulation time 11415396471 ps
CPU time 1301.36 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 01:04:40 PM PST 23
Peak memory 289500 kb
Host smart-c41bf517-2924-4c78-b5ed-23e3285777aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251107978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1251107978
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1280195675
Short name T145
Test name
Test status
Simulation time 47814104678 ps
CPU time 286.53 seconds
Started Dec 27 12:31:40 PM PST 23
Finished Dec 27 12:37:16 PM PST 23
Peak memory 265236 kb
Host smart-e884bcda-fecf-47ab-bebf-ca4a48f610b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1280195675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1280195675
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.156301324
Short name T271
Test name
Test status
Simulation time 61034919828 ps
CPU time 3531.09 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 01:41:22 PM PST 23
Peak memory 306064 kb
Host smart-55b3ed77-4fcf-4ece-a31e-6d1d3942d9e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156301324 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.156301324
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2547527101
Short name T237
Test name
Test status
Simulation time 35620440688 ps
CPU time 368.62 seconds
Started Dec 27 12:41:53 PM PST 23
Finished Dec 27 12:48:56 PM PST 23
Peak memory 247348 kb
Host smart-afa6a48f-a95a-43b1-9a68-605b55b922f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547527101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2547527101
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.432686637
Short name T183
Test name
Test status
Simulation time 1197664035 ps
CPU time 35.94 seconds
Started Dec 27 12:32:48 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 239100 kb
Host smart-c6a9e322-ed42-495b-a27f-7a730a6d83ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=432686637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.432686637
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.207660539
Short name T80
Test name
Test status
Simulation time 49006479371 ps
CPU time 2062.1 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 01:16:45 PM PST 23
Peak memory 283956 kb
Host smart-86d0ed5f-6c05-4e99-8d98-c42bda73025a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207660539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.207660539
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.506260434
Short name T16
Test name
Test status
Simulation time 8611085251 ps
CPU time 698.92 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:54:23 PM PST 23
Peak memory 271832 kb
Host smart-64f760cc-345c-4649-a95f-57ad318079ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506260434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.506260434
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1344083824
Short name T262
Test name
Test status
Simulation time 732830164 ps
CPU time 21.5 seconds
Started Dec 27 12:41:26 PM PST 23
Finished Dec 27 12:42:49 PM PST 23
Peak memory 246896 kb
Host smart-b6336010-fbdd-4b2e-87a4-4c8741c24efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13440
83824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1344083824
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2100819699
Short name T70
Test name
Test status
Simulation time 71475365605 ps
CPU time 4212.57 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 01:53:14 PM PST 23
Peak memory 305404 kb
Host smart-7014d497-fa1c-4c39-9d69-207508c21d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100819699 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2100819699
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2837910099
Short name T292
Test name
Test status
Simulation time 1204768159 ps
CPU time 16.84 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:43:03 PM PST 23
Peak memory 248404 kb
Host smart-2e721551-5961-4ed0-8656-212bb93385dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28379
10099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2837910099
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.586722748
Short name T275
Test name
Test status
Simulation time 175884742352 ps
CPU time 1809.85 seconds
Started Dec 27 12:42:27 PM PST 23
Finished Dec 27 01:13:17 PM PST 23
Peak memory 273252 kb
Host smart-da7e0133-0a31-4c54-b6c1-66bad8abaec5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586722748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.586722748
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3839428859
Short name T164
Test name
Test status
Simulation time 8345262511 ps
CPU time 282.81 seconds
Started Dec 27 12:34:02 PM PST 23
Finished Dec 27 12:38:59 PM PST 23
Peak memory 265164 kb
Host smart-774fe0e5-c1be-4935-8813-48b8d86581af
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839428859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3839428859
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.727002192
Short name T180
Test name
Test status
Simulation time 128565971 ps
CPU time 7.5 seconds
Started Dec 27 12:32:47 PM PST 23
Finished Dec 27 12:33:30 PM PST 23
Peak memory 248260 kb
Host smart-41d3c26d-de25-424b-b8e6-1a0e044f8648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=727002192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.727002192
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1055976683
Short name T163
Test name
Test status
Simulation time 9262831887 ps
CPU time 264.93 seconds
Started Dec 27 12:30:37 PM PST 23
Finished Dec 27 12:35:58 PM PST 23
Peak memory 269000 kb
Host smart-791d394d-31c5-4329-948d-e6ebc139ea15
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055976683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1055976683
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.42055448
Short name T212
Test name
Test status
Simulation time 21301155 ps
CPU time 2.64 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 248716 kb
Host smart-5cac38e7-5b8f-4ad7-8c6a-c104087160a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=42055448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.42055448
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1534771600
Short name T223
Test name
Test status
Simulation time 41348910 ps
CPU time 3.4 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:23 PM PST 23
Peak memory 248764 kb
Host smart-9af50356-4779-48ac-bfa5-bdf3f1c4c19d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1534771600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1534771600
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.813919471
Short name T217
Test name
Test status
Simulation time 47750574 ps
CPU time 2.27 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:24 PM PST 23
Peak memory 248832 kb
Host smart-6a2653b4-b94f-4a67-972b-51a3d1524ce8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=813919471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.813919471
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2201925330
Short name T355
Test name
Test status
Simulation time 15142222 ps
CPU time 1.28 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 236452 kb
Host smart-aff7374f-1075-499c-8afd-3739622930af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2201925330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2201925330
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1702254306
Short name T76
Test name
Test status
Simulation time 122768160602 ps
CPU time 1679.06 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 01:10:21 PM PST 23
Peak memory 272996 kb
Host smart-e79d75f9-d37e-4ce5-bb03-3bfc9c194796
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702254306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1702254306
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.4229811643
Short name T353
Test name
Test status
Simulation time 10099195343 ps
CPU time 985.74 seconds
Started Dec 27 12:41:39 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 272480 kb
Host smart-e9d2b028-25b9-4805-acda-96d8076e947e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229811643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.4229811643
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.545338134
Short name T91
Test name
Test status
Simulation time 82416610437 ps
CPU time 2433.34 seconds
Started Dec 27 12:41:29 PM PST 23
Finished Dec 27 01:23:04 PM PST 23
Peak memory 286020 kb
Host smart-7df4db05-aeeb-4c54-a007-1d64e1174144
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545338134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.545338134
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1277490350
Short name T345
Test name
Test status
Simulation time 10201532003 ps
CPU time 878.07 seconds
Started Dec 27 12:42:02 PM PST 23
Finished Dec 27 12:57:30 PM PST 23
Peak memory 272604 kb
Host smart-d1f46a67-4edd-4d12-8007-16719bfe6392
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277490350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1277490350
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2286914550
Short name T252
Test name
Test status
Simulation time 53621856345 ps
CPU time 431.29 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:50:07 PM PST 23
Peak memory 248620 kb
Host smart-a865215e-dfed-4b29-b47d-21c9bb613c06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286914550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2286914550
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.828352924
Short name T321
Test name
Test status
Simulation time 12114709799 ps
CPU time 227.59 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 12:46:46 PM PST 23
Peak memory 246396 kb
Host smart-5eea3b2f-98e3-4993-81d9-02534ee1c284
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828352924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.828352924
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2489399
Short name T38
Test name
Test status
Simulation time 18705508584 ps
CPU time 1311.14 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 01:04:41 PM PST 23
Peak memory 282716 kb
Host smart-2341fb5d-1776-46c5-9b82-3e361d1d6915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489399 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2489399
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2732666840
Short name T248
Test name
Test status
Simulation time 126050849680 ps
CPU time 2061.88 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 01:17:16 PM PST 23
Peak memory 289052 kb
Host smart-a4fc4f4c-9085-4b83-a322-5c27ee73688f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732666840 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2732666840
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3977152721
Short name T138
Test name
Test status
Simulation time 145182191 ps
CPU time 6.87 seconds
Started Dec 27 12:30:51 PM PST 23
Finished Dec 27 12:31:57 PM PST 23
Peak memory 235452 kb
Host smart-a65e4b7d-169a-4a65-8b0c-1793dc8bdabc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3977152721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3977152721
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2799728229
Short name T171
Test name
Test status
Simulation time 11059817845 ps
CPU time 174.28 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:35:10 PM PST 23
Peak memory 265240 kb
Host smart-6c18c8c5-ccf1-449b-908f-40f37db62f9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2799728229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2799728229
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.133386900
Short name T266
Test name
Test status
Simulation time 3815678641 ps
CPU time 51.19 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 255324 kb
Host smart-a7245106-b71e-43ad-b620-96b00ff5cab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338
6900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.133386900
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3981064157
Short name T253
Test name
Test status
Simulation time 23379935440 ps
CPU time 1572.75 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 01:08:56 PM PST 23
Peak memory 288844 kb
Host smart-793465cc-b9c3-4bb5-93cc-8050c290fad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981064157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3981064157
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.701344110
Short name T296
Test name
Test status
Simulation time 4972456033 ps
CPU time 111.96 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:44:25 PM PST 23
Peak memory 256120 kb
Host smart-d7bf54c2-eacf-4da9-ac4a-f3de9f7195d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701344110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.701344110
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2411875890
Short name T287
Test name
Test status
Simulation time 150469811501 ps
CPU time 4662.53 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 02:00:20 PM PST 23
Peak memory 305776 kb
Host smart-35ff2aa2-dab4-45fe-a3c4-dd07099c4e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411875890 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2411875890
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.4044271502
Short name T335
Test name
Test status
Simulation time 5639767819 ps
CPU time 116.98 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 12:44:39 PM PST 23
Peak memory 247520 kb
Host smart-da027293-672c-456d-b7e3-c1e25922fd82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044271502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.4044271502
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.658256476
Short name T283
Test name
Test status
Simulation time 100759902015 ps
CPU time 4140.4 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 01:51:48 PM PST 23
Peak memory 304852 kb
Host smart-a8aaf7ee-4136-474e-a990-4803ecca4811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658256476 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.658256476
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.114969625
Short name T278
Test name
Test status
Simulation time 105889826 ps
CPU time 7.03 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 250432 kb
Host smart-a5713fbe-c5dc-4f8f-b980-e6e42f09822c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496
9625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.114969625
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3688490562
Short name T663
Test name
Test status
Simulation time 6528524563 ps
CPU time 261.27 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:47:07 PM PST 23
Peak memory 246960 kb
Host smart-0f75620d-1771-4034-8d83-c6b201649837
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688490562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3688490562
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.849418184
Short name T291
Test name
Test status
Simulation time 933954471 ps
CPU time 35.52 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:34 PM PST 23
Peak memory 255148 kb
Host smart-7f79be4c-24b0-4d62-bfd1-8c7f30d32b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84941
8184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.849418184
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2005006637
Short name T247
Test name
Test status
Simulation time 5198129144 ps
CPU time 265.35 seconds
Started Dec 27 12:42:18 PM PST 23
Finished Dec 27 12:47:28 PM PST 23
Peak memory 252120 kb
Host smart-fd7bb398-9ae7-470a-b22a-82a9713e9a2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005006637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2005006637
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1434437068
Short name T37
Test name
Test status
Simulation time 9197027801 ps
CPU time 922.22 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 272192 kb
Host smart-150a8ced-99c6-4506-b80f-6a74a4b404a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434437068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1434437068
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2369204129
Short name T671
Test name
Test status
Simulation time 20821098510 ps
CPU time 1816.43 seconds
Started Dec 27 12:41:03 PM PST 23
Finished Dec 27 01:12:24 PM PST 23
Peak memory 305956 kb
Host smart-e7737d69-fd03-4da4-b195-3d4b3b5b4e0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369204129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2369204129
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.917896606
Short name T151
Test name
Test status
Simulation time 1888647288 ps
CPU time 187.87 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:35:23 PM PST 23
Peak memory 265144 kb
Host smart-a7253e6f-dcd4-42bc-97b8-da9e845535f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=917896606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.917896606
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1534209229
Short name T187
Test name
Test status
Simulation time 928280001 ps
CPU time 64.18 seconds
Started Dec 27 12:31:04 PM PST 23
Finished Dec 27 12:32:58 PM PST 23
Peak memory 239156 kb
Host smart-8c9ec87f-d344-4b5d-903f-8b728ba1b902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1534209229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1534209229
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2842776067
Short name T182
Test name
Test status
Simulation time 318528978 ps
CPU time 37.5 seconds
Started Dec 27 12:33:34 PM PST 23
Finished Dec 27 12:34:28 PM PST 23
Peak memory 240084 kb
Host smart-247e13cc-684a-43af-ad86-1d8cc28141f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2842776067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2842776067
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3276856377
Short name T152
Test name
Test status
Simulation time 2062373088 ps
CPU time 174.67 seconds
Started Dec 27 12:30:31 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 272744 kb
Host smart-a02ef0b1-ead7-4de9-8dfb-c804f1850e60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3276856377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3276856377
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3648645089
Short name T192
Test name
Test status
Simulation time 211522822 ps
CPU time 3.64 seconds
Started Dec 27 12:31:07 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 236356 kb
Host smart-9cb61832-e177-4d05-97df-2382db4b549f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3648645089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3648645089
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2581148359
Short name T185
Test name
Test status
Simulation time 94720166 ps
CPU time 2.27 seconds
Started Dec 27 12:31:02 PM PST 23
Finished Dec 27 12:31:55 PM PST 23
Peak memory 236820 kb
Host smart-a2eef39f-6cf7-4f88-b043-997cbbaf6485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2581148359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2581148359
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.391644412
Short name T169
Test name
Test status
Simulation time 12646126305 ps
CPU time 832.08 seconds
Started Dec 27 12:31:08 PM PST 23
Finished Dec 27 12:45:49 PM PST 23
Peak memory 265292 kb
Host smart-936b19fd-34ca-4022-841c-1789c21d4636
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391644412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.391644412
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.552764822
Short name T184
Test name
Test status
Simulation time 55357402 ps
CPU time 2.09 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 236760 kb
Host smart-c2826fb3-0060-434d-b3f5-8976218c6bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=552764822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.552764822
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3247285721
Short name T190
Test name
Test status
Simulation time 111846201 ps
CPU time 2.94 seconds
Started Dec 27 12:30:54 PM PST 23
Finished Dec 27 12:31:49 PM PST 23
Peak memory 235464 kb
Host smart-59ff796b-9dba-48d2-9884-94b0d80cbcda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3247285721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3247285721
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1011023273
Short name T186
Test name
Test status
Simulation time 157711298 ps
CPU time 19.84 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:31 PM PST 23
Peak memory 240320 kb
Host smart-8abcfe90-54e3-4117-9e19-b80867769b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1011023273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1011023273
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3845825987
Short name T189
Test name
Test status
Simulation time 3697874235 ps
CPU time 58.91 seconds
Started Dec 27 12:30:54 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 239368 kb
Host smart-3829104a-9431-4f7b-8c09-447346b3b6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3845825987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3845825987
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1605050962
Short name T191
Test name
Test status
Simulation time 37813688 ps
CPU time 3 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 234528 kb
Host smart-1f4effc0-4967-4113-9793-c3d62214cf3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1605050962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1605050962
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.894936370
Short name T195
Test name
Test status
Simulation time 8057488616 ps
CPU time 59.89 seconds
Started Dec 27 12:31:12 PM PST 23
Finished Dec 27 12:33:00 PM PST 23
Peak memory 240500 kb
Host smart-eb3d44c6-02e7-4f57-8df5-f6966729cf51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=894936370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.894936370
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.101528897
Short name T194
Test name
Test status
Simulation time 286581643 ps
CPU time 2.53 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 235460 kb
Host smart-2e7e99e1-9403-4d84-99f3-4e20a2d1f2d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=101528897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.101528897
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2474606521
Short name T193
Test name
Test status
Simulation time 32243345 ps
CPU time 2.57 seconds
Started Dec 27 12:33:31 PM PST 23
Finished Dec 27 12:33:52 PM PST 23
Peak memory 236124 kb
Host smart-c9ddafce-9417-4e5f-8d65-dd5f8c2a50dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2474606521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2474606521
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.765399339
Short name T188
Test name
Test status
Simulation time 179876479 ps
CPU time 8.12 seconds
Started Dec 27 12:30:31 PM PST 23
Finished Dec 27 12:31:36 PM PST 23
Peak memory 236792 kb
Host smart-4937db92-ae87-4fbe-88d2-28193cc16bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=765399339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.765399339
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1923520678
Short name T32
Test name
Test status
Simulation time 8706205107 ps
CPU time 813.92 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:56:32 PM PST 23
Peak memory 268072 kb
Host smart-9f21f6d6-d4ee-43f5-bb04-7dc9800fc848
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923520678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1923520678
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3528198840
Short name T778
Test name
Test status
Simulation time 2153466522 ps
CPU time 121.43 seconds
Started Dec 27 12:30:43 PM PST 23
Finished Dec 27 12:33:42 PM PST 23
Peak memory 236360 kb
Host smart-f73e6d7f-ca26-4a7e-8a73-ed3248bfa07f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3528198840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3528198840
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.300882812
Short name T750
Test name
Test status
Simulation time 8707538524 ps
CPU time 484.74 seconds
Started Dec 27 12:30:48 PM PST 23
Finished Dec 27 12:39:47 PM PST 23
Peak memory 240284 kb
Host smart-f4cb6103-3afe-4025-abf9-e6c64de810a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=300882812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.300882812
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1981330807
Short name T800
Test name
Test status
Simulation time 273894778 ps
CPU time 9.55 seconds
Started Dec 27 12:30:30 PM PST 23
Finished Dec 27 12:31:36 PM PST 23
Peak memory 240228 kb
Host smart-0836002e-e614-4f0f-a8f4-65435910ce7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1981330807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1981330807
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2952577593
Short name T834
Test name
Test status
Simulation time 307299283 ps
CPU time 6.14 seconds
Started Dec 27 12:30:31 PM PST 23
Finished Dec 27 12:31:33 PM PST 23
Peak memory 242688 kb
Host smart-3da59fea-9afd-4013-ae24-0b59169c450e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952577593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2952577593
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1510812456
Short name T799
Test name
Test status
Simulation time 181208119 ps
CPU time 4.54 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:08 PM PST 23
Peak memory 236296 kb
Host smart-fc5afc38-f001-43ae-a4b0-132d7c1445a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1510812456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1510812456
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4252730240
Short name T772
Test name
Test status
Simulation time 21193280 ps
CPU time 1.32 seconds
Started Dec 27 12:30:49 PM PST 23
Finished Dec 27 12:31:45 PM PST 23
Peak memory 236172 kb
Host smart-04eb4598-12f6-499a-a59b-20f61d7943e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4252730240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4252730240
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2720964934
Short name T201
Test name
Test status
Simulation time 320766551 ps
CPU time 9.03 seconds
Started Dec 27 12:30:22 PM PST 23
Finished Dec 27 12:31:27 PM PST 23
Peak memory 243652 kb
Host smart-c591bbfb-6e50-4df0-9e6c-81e08ad73397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2720964934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2720964934
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3908266013
Short name T154
Test name
Test status
Simulation time 3254795862 ps
CPU time 100.66 seconds
Started Dec 27 12:30:13 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 265340 kb
Host smart-1cdada7f-1f7c-47c3-911c-80a9e07bb050
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3908266013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3908266013
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.105367520
Short name T803
Test name
Test status
Simulation time 2446136763 ps
CPU time 72.56 seconds
Started Dec 27 12:30:30 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 236472 kb
Host smart-50a0751b-84db-4239-8b61-6648e630b242
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=105367520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.105367520
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3766501569
Short name T758
Test name
Test status
Simulation time 17828469660 ps
CPU time 474.26 seconds
Started Dec 27 12:30:36 PM PST 23
Finished Dec 27 12:39:31 PM PST 23
Peak memory 236392 kb
Host smart-c3e415e3-88e7-4c89-8c6d-8327cf171441
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3766501569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3766501569
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2789679269
Short name T764
Test name
Test status
Simulation time 75544997 ps
CPU time 6.28 seconds
Started Dec 27 12:30:41 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 240260 kb
Host smart-25be5266-c5a4-4770-b154-147a86403a7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2789679269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2789679269
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1950418418
Short name T137
Test name
Test status
Simulation time 118539935 ps
CPU time 6.01 seconds
Started Dec 27 12:30:18 PM PST 23
Finished Dec 27 12:31:19 PM PST 23
Peak memory 252084 kb
Host smart-5be8a252-988e-4bc6-9562-a6621d646eab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950418418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1950418418
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.264655522
Short name T26
Test name
Test status
Simulation time 63507842 ps
CPU time 4.78 seconds
Started Dec 27 12:30:35 PM PST 23
Finished Dec 27 12:31:41 PM PST 23
Peak memory 236412 kb
Host smart-d5c41347-9737-4292-9cea-d7551b9b29d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=264655522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.264655522
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2116490016
Short name T29
Test name
Test status
Simulation time 86258020 ps
CPU time 1.35 seconds
Started Dec 27 12:32:49 PM PST 23
Finished Dec 27 12:33:26 PM PST 23
Peak memory 236036 kb
Host smart-cdf75e61-b669-43f8-bf72-3456c2e40c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2116490016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2116490016
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3915661157
Short name T838
Test name
Test status
Simulation time 443269934 ps
CPU time 10.76 seconds
Started Dec 27 12:30:28 PM PST 23
Finished Dec 27 12:31:35 PM PST 23
Peak memory 244560 kb
Host smart-63b3e93b-e1e0-4139-a2a1-98db92a3788d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3915661157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3915661157
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3639650207
Short name T784
Test name
Test status
Simulation time 333569377 ps
CPU time 15.42 seconds
Started Dec 27 12:33:09 PM PST 23
Finished Dec 27 12:33:55 PM PST 23
Peak memory 249596 kb
Host smart-0f523935-d75f-4b59-b1f8-0db146c8656f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3639650207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3639650207
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3163901146
Short name T828
Test name
Test status
Simulation time 179681576 ps
CPU time 5.59 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:09 PM PST 23
Peak memory 255912 kb
Host smart-20e59b26-955d-4b14-8ccf-80e03da837f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163901146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3163901146
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.4245240547
Short name T200
Test name
Test status
Simulation time 44010009 ps
CPU time 3.11 seconds
Started Dec 27 12:31:07 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 238248 kb
Host smart-d9ef73d7-d9d0-4223-8e98-7a845ba8b113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4245240547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.4245240547
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3803531145
Short name T354
Test name
Test status
Simulation time 10613156 ps
CPU time 1.17 seconds
Started Dec 27 12:31:02 PM PST 23
Finished Dec 27 12:31:53 PM PST 23
Peak memory 236388 kb
Host smart-f096c1b7-9bac-4672-9fe5-4f851f696e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3803531145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3803531145
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3276795209
Short name T740
Test name
Test status
Simulation time 413928994 ps
CPU time 10.85 seconds
Started Dec 27 12:30:59 PM PST 23
Finished Dec 27 12:32:01 PM PST 23
Peak memory 240332 kb
Host smart-6a42f701-466c-4651-b81d-695b83c545eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3276795209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3276795209
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3270765517
Short name T150
Test name
Test status
Simulation time 12924547182 ps
CPU time 807.65 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:45:33 PM PST 23
Peak memory 265420 kb
Host smart-72eec8cc-f65b-40b8-b152-6f59c31144ad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270765517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3270765517
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.541417679
Short name T179
Test name
Test status
Simulation time 1306003252 ps
CPU time 9.01 seconds
Started Dec 27 12:33:41 PM PST 23
Finished Dec 27 12:34:06 PM PST 23
Peak memory 248296 kb
Host smart-ad1b23e1-2125-4869-a017-bbc32216cb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=541417679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.541417679
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3973600161
Short name T745
Test name
Test status
Simulation time 57644187 ps
CPU time 6.01 seconds
Started Dec 27 12:31:38 PM PST 23
Finished Dec 27 12:32:35 PM PST 23
Peak memory 243124 kb
Host smart-7beda461-c51c-465e-8523-8e9276904afb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973600161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3973600161
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3627405673
Short name T161
Test name
Test status
Simulation time 257865065 ps
CPU time 9.25 seconds
Started Dec 27 12:31:02 PM PST 23
Finished Dec 27 12:32:01 PM PST 23
Peak memory 236336 kb
Host smart-964fe648-7260-48f8-bbf7-4a0a484aabeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3627405673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3627405673
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2956034543
Short name T819
Test name
Test status
Simulation time 10868272 ps
CPU time 1.23 seconds
Started Dec 27 12:31:50 PM PST 23
Finished Dec 27 12:32:38 PM PST 23
Peak memory 235480 kb
Host smart-9153c994-93e3-4e09-952d-4f9ab9bc870c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2956034543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2956034543
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.772077456
Short name T831
Test name
Test status
Simulation time 11398810034 ps
CPU time 36.82 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:33:16 PM PST 23
Peak memory 248648 kb
Host smart-a1fbc427-1578-435e-96af-fc4470b8913b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=772077456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.772077456
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1887554240
Short name T155
Test name
Test status
Simulation time 8551889417 ps
CPU time 159.63 seconds
Started Dec 27 12:30:48 PM PST 23
Finished Dec 27 12:34:25 PM PST 23
Peak memory 265268 kb
Host smart-f8e55861-1bd9-49c0-9940-0b530140a610
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1887554240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1887554240
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.778518391
Short name T845
Test name
Test status
Simulation time 483071614 ps
CPU time 7.47 seconds
Started Dec 27 12:31:02 PM PST 23
Finished Dec 27 12:32:00 PM PST 23
Peak memory 253164 kb
Host smart-8a3bed45-eb0a-4d84-82f2-62f98594ad39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=778518391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.778518391
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.723755024
Short name T839
Test name
Test status
Simulation time 41062072 ps
CPU time 4.79 seconds
Started Dec 27 12:31:05 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 251164 kb
Host smart-eb21acf7-7a27-4b06-97aa-4ec905018ccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723755024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.723755024
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.721894561
Short name T165
Test name
Test status
Simulation time 254026843 ps
CPU time 8.66 seconds
Started Dec 27 12:31:24 PM PST 23
Finished Dec 27 12:32:22 PM PST 23
Peak memory 236264 kb
Host smart-ac829b76-13a6-4d35-9763-080c63a9ed63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=721894561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.721894561
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4159439609
Short name T751
Test name
Test status
Simulation time 9658758 ps
CPU time 1.41 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:32:02 PM PST 23
Peak memory 236452 kb
Host smart-654d7961-c279-44a3-835c-e01007cdfbd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4159439609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.4159439609
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1514834913
Short name T763
Test name
Test status
Simulation time 330281490 ps
CPU time 11.38 seconds
Started Dec 27 12:31:03 PM PST 23
Finished Dec 27 12:32:04 PM PST 23
Peak memory 240280 kb
Host smart-2988a390-2806-495b-93dd-866e537e8924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1514834913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1514834913
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1154752101
Short name T158
Test name
Test status
Simulation time 2119721224 ps
CPU time 170.78 seconds
Started Dec 27 12:30:50 PM PST 23
Finished Dec 27 12:34:35 PM PST 23
Peak memory 268488 kb
Host smart-a9bec28a-5402-478a-adca-f123953d1aaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1154752101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1154752101
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2791357590
Short name T174
Test name
Test status
Simulation time 15512811230 ps
CPU time 1078.21 seconds
Started Dec 27 12:31:43 PM PST 23
Finished Dec 27 12:50:30 PM PST 23
Peak memory 265180 kb
Host smart-24a79564-9ef9-40a9-b253-971112f93e76
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791357590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2791357590
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2331689642
Short name T178
Test name
Test status
Simulation time 103617663 ps
CPU time 7.14 seconds
Started Dec 27 12:31:23 PM PST 23
Finished Dec 27 12:32:20 PM PST 23
Peak memory 248928 kb
Host smart-ab3f53c1-f283-47ee-a55c-378f0e6646e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2331689642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2331689642
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3267768416
Short name T244
Test name
Test status
Simulation time 239165717 ps
CPU time 4.06 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 238460 kb
Host smart-4d4b1fb1-f42f-4855-97fb-c5c419aa61f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267768416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3267768416
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.869705826
Short name T776
Test name
Test status
Simulation time 35426913 ps
CPU time 5.18 seconds
Started Dec 27 12:30:52 PM PST 23
Finished Dec 27 12:31:50 PM PST 23
Peak memory 240192 kb
Host smart-07ccec9d-689d-4312-88cc-9dbf1b8b852b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=869705826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.869705826
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3550649677
Short name T811
Test name
Test status
Simulation time 8081369 ps
CPU time 1.42 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 236160 kb
Host smart-5c21c8e8-dd27-483d-acbd-ef43c6786611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3550649677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3550649677
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.546437333
Short name T746
Test name
Test status
Simulation time 83805703 ps
CPU time 9.34 seconds
Started Dec 27 12:30:45 PM PST 23
Finished Dec 27 12:31:50 PM PST 23
Peak memory 243672 kb
Host smart-252b7ce4-c782-4b01-b3ab-39bf2106fcc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=546437333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.546437333
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3978571489
Short name T363
Test name
Test status
Simulation time 67629392847 ps
CPU time 533.79 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:41:01 PM PST 23
Peak memory 269092 kb
Host smart-80abf5d3-5f8d-4384-b9cf-fd775d85bfa1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978571489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3978571489
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2905434694
Short name T23
Test name
Test status
Simulation time 657355237 ps
CPU time 21.04 seconds
Started Dec 27 12:31:10 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 248572 kb
Host smart-2a95ca86-88fc-49ce-b03d-a204f6aafd9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2905434694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2905434694
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1170379576
Short name T753
Test name
Test status
Simulation time 169521584 ps
CPU time 5.52 seconds
Started Dec 27 12:31:23 PM PST 23
Finished Dec 27 12:32:18 PM PST 23
Peak memory 248720 kb
Host smart-94f5ab4e-35db-42e3-96fb-a8ef22f7ca09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170379576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1170379576
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3847477551
Short name T807
Test name
Test status
Simulation time 240733339 ps
CPU time 4.83 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:09 PM PST 23
Peak memory 236288 kb
Host smart-b4016674-4046-41b0-ac31-5ca591d67b4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3847477551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3847477551
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.888606756
Short name T792
Test name
Test status
Simulation time 24379895 ps
CPU time 1.31 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:09 PM PST 23
Peak memory 235636 kb
Host smart-b50ae503-ae3d-42c3-9396-68b1abe6ae30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=888606756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.888606756
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.789424711
Short name T808
Test name
Test status
Simulation time 268530047 ps
CPU time 18.26 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:27 PM PST 23
Peak memory 244540 kb
Host smart-96e95855-f25c-4239-b916-22c9ef696926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=789424711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.789424711
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1564295777
Short name T25
Test name
Test status
Simulation time 7381796517 ps
CPU time 204.64 seconds
Started Dec 27 12:31:03 PM PST 23
Finished Dec 27 12:35:18 PM PST 23
Peak memory 265388 kb
Host smart-30e9ef6d-8313-4a02-9dbd-b9d0358c988d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1564295777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1564295777
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2876174011
Short name T361
Test name
Test status
Simulation time 22174103545 ps
CPU time 585.96 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:41:55 PM PST 23
Peak memory 265040 kb
Host smart-fea3a04c-655b-4037-8159-fb0d292ebd3b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876174011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2876174011
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3611922765
Short name T780
Test name
Test status
Simulation time 524957807 ps
CPU time 15.89 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 247908 kb
Host smart-11d60990-4afa-48b8-bb93-557b5ce5494c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3611922765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3611922765
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.124140638
Short name T820
Test name
Test status
Simulation time 20619062 ps
CPU time 3.83 seconds
Started Dec 27 12:31:47 PM PST 23
Finished Dec 27 12:32:38 PM PST 23
Peak memory 255912 kb
Host smart-d3de5046-661c-4698-a69d-175e8621e6a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124140638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.124140638
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2430870294
Short name T739
Test name
Test status
Simulation time 373610593 ps
CPU time 4.83 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 240296 kb
Host smart-b45c27db-0001-4f7f-a8a8-f8243ba5a213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2430870294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2430870294
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1926937107
Short name T774
Test name
Test status
Simulation time 18769772 ps
CPU time 1.31 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:07 PM PST 23
Peak memory 236312 kb
Host smart-1bdce52a-e297-4538-aaca-a2a851666489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1926937107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1926937107
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.553917157
Short name T805
Test name
Test status
Simulation time 5660096632 ps
CPU time 20.93 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:32:56 PM PST 23
Peak memory 244472 kb
Host smart-ce4b6161-0e84-4533-b2f1-eec6db43dd79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=553917157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.553917157
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2873583022
Short name T760
Test name
Test status
Simulation time 134853026 ps
CPU time 8.07 seconds
Started Dec 27 12:31:55 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 254948 kb
Host smart-5db67bf1-5e0b-4d3d-b3ec-782b1be1dde3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2873583022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2873583022
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.986080068
Short name T367
Test name
Test status
Simulation time 34024750 ps
CPU time 3.82 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:15 PM PST 23
Peak memory 238828 kb
Host smart-50794a74-d6ce-4fd7-b2df-136fce667797
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986080068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.986080068
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.299111984
Short name T762
Test name
Test status
Simulation time 122203473 ps
CPU time 8.41 seconds
Started Dec 27 12:31:08 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 236316 kb
Host smart-2a7c66ba-a134-476d-a4b6-fbc7f4a2c21a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=299111984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.299111984
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.840362851
Short name T773
Test name
Test status
Simulation time 17276802 ps
CPU time 1.24 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 236280 kb
Host smart-13744fa1-4caa-4180-b239-8ad1ab8b06e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=840362851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.840362851
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.822196133
Short name T815
Test name
Test status
Simulation time 521165776 ps
CPU time 34.94 seconds
Started Dec 27 12:31:08 PM PST 23
Finished Dec 27 12:32:31 PM PST 23
Peak memory 244496 kb
Host smart-f9a4905c-fd37-4566-8962-cd267d49e58e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=822196133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.822196133
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2921489967
Short name T148
Test name
Test status
Simulation time 8912451454 ps
CPU time 546 seconds
Started Dec 27 12:31:28 PM PST 23
Finished Dec 27 12:41:25 PM PST 23
Peak memory 265244 kb
Host smart-c42cd181-fa78-4153-b7d3-4a6e2188e340
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921489967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2921489967
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2176897612
Short name T782
Test name
Test status
Simulation time 172980844 ps
CPU time 11.16 seconds
Started Dec 27 12:33:53 PM PST 23
Finished Dec 27 12:34:20 PM PST 23
Peak memory 248468 kb
Host smart-28c7155f-234a-4fb3-983c-306c827b4999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2176897612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2176897612
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1448580443
Short name T757
Test name
Test status
Simulation time 267813333 ps
CPU time 6.38 seconds
Started Dec 27 12:31:06 PM PST 23
Finished Dec 27 12:32:02 PM PST 23
Peak memory 251508 kb
Host smart-c358c98e-77c1-4cea-bbf2-343721bd5122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448580443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1448580443
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2334818960
Short name T199
Test name
Test status
Simulation time 117446335 ps
CPU time 4.66 seconds
Started Dec 27 12:31:02 PM PST 23
Finished Dec 27 12:31:57 PM PST 23
Peak memory 235448 kb
Host smart-c4f01554-6008-4115-9a37-e69285f443fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2334818960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2334818960
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.817448510
Short name T837
Test name
Test status
Simulation time 11007986 ps
CPU time 1.26 seconds
Started Dec 27 12:31:08 PM PST 23
Finished Dec 27 12:31:58 PM PST 23
Peak memory 234648 kb
Host smart-aceb598f-a7e4-4120-ab3f-a3a235e15064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=817448510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.817448510
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.354136799
Short name T802
Test name
Test status
Simulation time 360398445 ps
CPU time 10.05 seconds
Started Dec 27 12:31:12 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 240244 kb
Host smart-7cde075f-ce41-49d3-af4b-85fa397089c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=354136799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.354136799
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4117750599
Short name T159
Test name
Test status
Simulation time 6824903442 ps
CPU time 193.77 seconds
Started Dec 27 12:31:30 PM PST 23
Finished Dec 27 12:35:34 PM PST 23
Peak memory 273040 kb
Host smart-1c854956-bfc2-4a53-a864-97bfacf66806
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4117750599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4117750599
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3034800448
Short name T177
Test name
Test status
Simulation time 12803764361 ps
CPU time 811.49 seconds
Started Dec 27 12:30:57 PM PST 23
Finished Dec 27 12:45:20 PM PST 23
Peak memory 265324 kb
Host smart-19acb342-52af-4c83-94b2-aba18e3426d6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034800448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3034800448
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1901246054
Short name T794
Test name
Test status
Simulation time 346857855 ps
CPU time 10.09 seconds
Started Dec 27 12:31:01 PM PST 23
Finished Dec 27 12:32:02 PM PST 23
Peak memory 248364 kb
Host smart-d22d38a4-f8ac-48f2-9a05-96b3a8f1f04f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1901246054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1901246054
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.265869248
Short name T24
Test name
Test status
Simulation time 41583123 ps
CPU time 3.63 seconds
Started Dec 27 12:31:09 PM PST 23
Finished Dec 27 12:32:01 PM PST 23
Peak memory 248680 kb
Host smart-5fc58326-cb1e-47a7-9ae0-0bf2e3f9f8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265869248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.265869248
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2368674314
Short name T797
Test name
Test status
Simulation time 60869642 ps
CPU time 4.65 seconds
Started Dec 27 12:34:19 PM PST 23
Finished Dec 27 12:34:40 PM PST 23
Peak memory 235428 kb
Host smart-9bd02a4b-641f-40e6-8efb-6a54df835a32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2368674314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2368674314
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.458090815
Short name T766
Test name
Test status
Simulation time 1540943333 ps
CPU time 21.34 seconds
Started Dec 27 12:33:37 PM PST 23
Finished Dec 27 12:34:14 PM PST 23
Peak memory 244328 kb
Host smart-b5e5539f-8834-45a0-89b0-b1342b86f7c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=458090815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.458090815
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.752639459
Short name T755
Test name
Test status
Simulation time 989427873 ps
CPU time 10.39 seconds
Started Dec 27 12:33:37 PM PST 23
Finished Dec 27 12:34:03 PM PST 23
Peak memory 248256 kb
Host smart-7ad41eaa-15a3-4d7c-92a6-e47d209b3a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=752639459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.752639459
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3708318037
Short name T823
Test name
Test status
Simulation time 140457701 ps
CPU time 7.23 seconds
Started Dec 27 12:31:11 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 248564 kb
Host smart-4727aaff-0aa0-4b4f-9911-8fe307394ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708318037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3708318037
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.765987708
Short name T245
Test name
Test status
Simulation time 248680525 ps
CPU time 5.04 seconds
Started Dec 27 12:31:10 PM PST 23
Finished Dec 27 12:32:04 PM PST 23
Peak memory 238272 kb
Host smart-be3ad404-b1ae-47bf-a4c7-8b861e57f0a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=765987708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.765987708
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4220828166
Short name T359
Test name
Test status
Simulation time 51200354 ps
CPU time 1.43 seconds
Started Dec 27 12:30:57 PM PST 23
Finished Dec 27 12:31:50 PM PST 23
Peak memory 235656 kb
Host smart-f7a93b49-3eb4-4c91-ae72-1e6b28fac83a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4220828166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4220828166
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1744303915
Short name T824
Test name
Test status
Simulation time 1042107607 ps
CPU time 21.9 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:33 PM PST 23
Peak memory 244484 kb
Host smart-92c33bc3-2816-4194-a867-662c4b48f03a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1744303915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1744303915
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3149652779
Short name T160
Test name
Test status
Simulation time 4053629204 ps
CPU time 294.28 seconds
Started Dec 27 12:31:10 PM PST 23
Finished Dec 27 12:36:53 PM PST 23
Peak memory 265192 kb
Host smart-58ce7a8b-268b-4594-9208-7bde4cd4555d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3149652779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3149652779
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4098662199
Short name T801
Test name
Test status
Simulation time 871696364 ps
CPU time 10.84 seconds
Started Dec 27 12:32:53 PM PST 23
Finished Dec 27 12:33:39 PM PST 23
Peak memory 247584 kb
Host smart-15631051-7dc2-4675-b858-957adc93b572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098662199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4098662199
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2550555213
Short name T832
Test name
Test status
Simulation time 20002378100 ps
CPU time 286.55 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:36:17 PM PST 23
Peak memory 238792 kb
Host smart-85c329dd-7a02-4947-8e49-5108a2dda3eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2550555213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2550555213
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.752101799
Short name T830
Test name
Test status
Simulation time 861657699 ps
CPU time 78.24 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 235488 kb
Host smart-9877d61c-983b-4af9-b663-b643c87499b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=752101799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.752101799
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.986925109
Short name T31
Test name
Test status
Simulation time 46773832 ps
CPU time 5.8 seconds
Started Dec 27 12:30:41 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 240288 kb
Host smart-ff6fa018-df55-4693-b545-08cdf55dc3e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=986925109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.986925109
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3993786009
Short name T814
Test name
Test status
Simulation time 64934039 ps
CPU time 4.11 seconds
Started Dec 27 12:30:56 PM PST 23
Finished Dec 27 12:31:52 PM PST 23
Peak memory 236496 kb
Host smart-f58360b2-26f6-491a-8d05-fe07c4df260a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993786009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3993786009
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1213964691
Short name T196
Test name
Test status
Simulation time 244940792 ps
CPU time 5.07 seconds
Started Dec 27 12:30:32 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 240384 kb
Host smart-29a75db9-82dd-45ef-a406-bc4940cccf7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1213964691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1213964691
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4258622814
Short name T769
Test name
Test status
Simulation time 6172833 ps
CPU time 1.31 seconds
Started Dec 27 12:30:31 PM PST 23
Finished Dec 27 12:31:28 PM PST 23
Peak memory 234524 kb
Host smart-c5738145-8f0a-4fdb-95e7-97a639295076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4258622814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4258622814
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3882724895
Short name T741
Test name
Test status
Simulation time 1040248515 ps
CPU time 17.48 seconds
Started Dec 27 12:30:34 PM PST 23
Finished Dec 27 12:31:49 PM PST 23
Peak memory 244536 kb
Host smart-447ea1d7-929d-4b3c-a9fe-c8e87f9a7146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3882724895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3882724895
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3965095498
Short name T181
Test name
Test status
Simulation time 45311940 ps
CPU time 4.75 seconds
Started Dec 27 12:30:46 PM PST 23
Finished Dec 27 12:31:46 PM PST 23
Peak memory 248560 kb
Host smart-02c8d936-e0d9-4b3a-a42b-0729d83264c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3965095498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3965095498
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3429506734
Short name T827
Test name
Test status
Simulation time 13948113 ps
CPU time 1.33 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 235644 kb
Host smart-9667b4c7-94de-4471-bff9-3019b495716c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3429506734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3429506734
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3632082442
Short name T748
Test name
Test status
Simulation time 7804152 ps
CPU time 1.25 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 234412 kb
Host smart-f8316945-07ca-4250-93fd-d8b1c6132313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3632082442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3632082442
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4234561616
Short name T809
Test name
Test status
Simulation time 8798947 ps
CPU time 1.53 seconds
Started Dec 27 12:31:08 PM PST 23
Finished Dec 27 12:31:58 PM PST 23
Peak memory 235576 kb
Host smart-bf3197de-3235-4341-a578-6713a1353fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4234561616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4234561616
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1349627347
Short name T804
Test name
Test status
Simulation time 18845979 ps
CPU time 1.3 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 236356 kb
Host smart-4f122b6e-f5dc-40b9-8bc2-1e66dc839a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1349627347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1349627347
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.444834957
Short name T825
Test name
Test status
Simulation time 18047233 ps
CPU time 1.35 seconds
Started Dec 27 12:31:11 PM PST 23
Finished Dec 27 12:32:01 PM PST 23
Peak memory 234500 kb
Host smart-9abb712b-bae2-42d5-88ed-c81caea3a38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=444834957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.444834957
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2891352918
Short name T357
Test name
Test status
Simulation time 23579822 ps
CPU time 1.34 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 235544 kb
Host smart-7706caa4-b4be-46ab-9e22-e4bea5698bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2891352918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2891352918
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2132554791
Short name T752
Test name
Test status
Simulation time 8744496 ps
CPU time 1.42 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 236344 kb
Host smart-ff840fd8-7a53-4ffb-961c-40015a45cb2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2132554791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2132554791
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.514958871
Short name T136
Test name
Test status
Simulation time 9183043 ps
CPU time 1.21 seconds
Started Dec 27 12:31:09 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 234464 kb
Host smart-83559af2-6bcf-42e5-9c7a-60338d49768e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=514958871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.514958871
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1346056285
Short name T358
Test name
Test status
Simulation time 10683236 ps
CPU time 1.5 seconds
Started Dec 27 12:31:04 PM PST 23
Finished Dec 27 12:31:55 PM PST 23
Peak memory 235560 kb
Host smart-1f1ecb61-3eca-4672-b44b-415a5882db71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1346056285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1346056285
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1284348522
Short name T747
Test name
Test status
Simulation time 4393009305 ps
CPU time 276.61 seconds
Started Dec 27 12:30:24 PM PST 23
Finished Dec 27 12:35:57 PM PST 23
Peak memory 240396 kb
Host smart-bbb2756d-cd2f-4d08-b2fd-3a1a6af39f0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1284348522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1284348522
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1953327778
Short name T749
Test name
Test status
Simulation time 23766324849 ps
CPU time 372.44 seconds
Started Dec 27 12:30:38 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 236400 kb
Host smart-53da29ee-50bd-48b5-a5dd-f1f136d50289
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1953327778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1953327778
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1628710660
Short name T843
Test name
Test status
Simulation time 484884860 ps
CPU time 9.13 seconds
Started Dec 27 12:30:29 PM PST 23
Finished Dec 27 12:31:35 PM PST 23
Peak memory 240288 kb
Host smart-3686d790-5ffa-4eae-b5d8-3c0eda76d62f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1628710660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1628710660
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2099473884
Short name T771
Test name
Test status
Simulation time 56502973 ps
CPU time 3.55 seconds
Started Dec 27 12:30:40 PM PST 23
Finished Dec 27 12:31:40 PM PST 23
Peak memory 237444 kb
Host smart-8a8143d8-3b8e-4a17-ba38-10e195740515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099473884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2099473884
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1959164648
Short name T826
Test name
Test status
Simulation time 93229935 ps
CPU time 7.16 seconds
Started Dec 27 12:30:41 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 236288 kb
Host smart-48452494-6fd1-4409-871d-a0bc6dae83b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1959164648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1959164648
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1853683487
Short name T360
Test name
Test status
Simulation time 10380244 ps
CPU time 1.48 seconds
Started Dec 27 12:30:32 PM PST 23
Finished Dec 27 12:31:31 PM PST 23
Peak memory 236496 kb
Host smart-191c58f6-68a4-4bf3-b5d5-27a23a0ada93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1853683487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1853683487
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2332444099
Short name T822
Test name
Test status
Simulation time 170603803 ps
CPU time 10.87 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:15 PM PST 23
Peak memory 240292 kb
Host smart-0f195482-dd86-44a3-8d6a-cb9d55b40311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2332444099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2332444099
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2353766068
Short name T172
Test name
Test status
Simulation time 17799577105 ps
CPU time 540.3 seconds
Started Dec 27 12:30:38 PM PST 23
Finished Dec 27 12:40:35 PM PST 23
Peak memory 265228 kb
Host smart-cc45ab57-d722-47f3-b00d-0b63c0b3a847
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353766068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2353766068
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.224195278
Short name T756
Test name
Test status
Simulation time 185431394 ps
CPU time 11.21 seconds
Started Dec 27 12:30:37 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 248564 kb
Host smart-6aed2a59-4b52-46ae-b367-6ea59d5be189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=224195278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.224195278
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2949270160
Short name T835
Test name
Test status
Simulation time 235245950 ps
CPU time 3.16 seconds
Started Dec 27 12:30:32 PM PST 23
Finished Dec 27 12:31:32 PM PST 23
Peak memory 236276 kb
Host smart-6ab87b0a-60b2-4f6e-9f3d-efbd9cbce520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2949270160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2949270160
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1372925528
Short name T793
Test name
Test status
Simulation time 9343641 ps
CPU time 1.31 seconds
Started Dec 27 12:31:09 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 235476 kb
Host smart-4c47263e-9562-4183-a8ce-e9e0fe898bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1372925528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1372925528
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.67510613
Short name T796
Test name
Test status
Simulation time 8632931 ps
CPU time 1.47 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:04 PM PST 23
Peak memory 235524 kb
Host smart-2426ef39-3282-4dc9-ba70-a684989eb742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=67510613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.67510613
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3103917770
Short name T791
Test name
Test status
Simulation time 11086059 ps
CPU time 1.4 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:32:16 PM PST 23
Peak memory 236288 kb
Host smart-34c55495-b657-4a96-aeab-0b4ecac5bf7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3103917770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3103917770
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4076984018
Short name T770
Test name
Test status
Simulation time 24852439 ps
CPU time 1.27 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 236384 kb
Host smart-7363c830-3a52-49fe-9b7f-4883721feb65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4076984018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4076984018
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2656981672
Short name T754
Test name
Test status
Simulation time 20252687 ps
CPU time 1.36 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 236288 kb
Host smart-e8074b9d-b004-49ef-8ea2-6998ca874987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2656981672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2656981672
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3863727845
Short name T743
Test name
Test status
Simulation time 11380890 ps
CPU time 1.59 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:04 PM PST 23
Peak memory 235604 kb
Host smart-8df97cfc-d4a5-428d-bdf0-853b141ad531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3863727845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3863727845
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1225366054
Short name T356
Test name
Test status
Simulation time 8950609 ps
CPU time 1.46 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:09 PM PST 23
Peak memory 235500 kb
Host smart-01189c84-52a7-496c-ad16-988c80ece1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1225366054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1225366054
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.465467561
Short name T364
Test name
Test status
Simulation time 11961761 ps
CPU time 1.51 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:32:36 PM PST 23
Peak memory 236364 kb
Host smart-c2cb7761-e2b5-4e20-8598-a88e123fc578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=465467561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.465467561
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.868871188
Short name T761
Test name
Test status
Simulation time 10620193 ps
CPU time 1.23 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 235596 kb
Host smart-e07b66a8-58f4-4c3d-9758-5044ab32899f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=868871188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.868871188
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2183694424
Short name T777
Test name
Test status
Simulation time 15805561 ps
CPU time 1.32 seconds
Started Dec 27 12:31:06 PM PST 23
Finished Dec 27 12:31:57 PM PST 23
Peak memory 236388 kb
Host smart-d3aaf095-cad2-4eab-8bb2-be28dbdb8276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2183694424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2183694424
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2479187345
Short name T765
Test name
Test status
Simulation time 8504204292 ps
CPU time 118.43 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:34:07 PM PST 23
Peak memory 236412 kb
Host smart-06376d5b-54b6-41df-ac8e-7963e06eeb8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2479187345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2479187345
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1964559645
Short name T173
Test name
Test status
Simulation time 6802994603 ps
CPU time 196.38 seconds
Started Dec 27 12:31:05 PM PST 23
Finished Dec 27 12:35:11 PM PST 23
Peak memory 236432 kb
Host smart-1a55acbb-59b1-4c32-907b-fa03cc05f359
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1964559645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1964559645
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.619699867
Short name T783
Test name
Test status
Simulation time 540145524 ps
CPU time 8.16 seconds
Started Dec 27 12:30:39 PM PST 23
Finished Dec 27 12:31:43 PM PST 23
Peak memory 240316 kb
Host smart-f51b9a86-8162-49bc-83d6-e0aa0c6493d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=619699867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.619699867
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1231138407
Short name T817
Test name
Test status
Simulation time 72260678 ps
CPU time 6.44 seconds
Started Dec 27 12:32:47 PM PST 23
Finished Dec 27 12:33:29 PM PST 23
Peak memory 248116 kb
Host smart-a052ea6b-7cf1-4f8c-a3ac-581524cce0ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231138407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1231138407
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1948108563
Short name T806
Test name
Test status
Simulation time 35934736 ps
CPU time 4.97 seconds
Started Dec 27 12:30:53 PM PST 23
Finished Dec 27 12:31:50 PM PST 23
Peak memory 240260 kb
Host smart-b7f5967c-2322-4da3-8ecd-a8ef16d23a13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1948108563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1948108563
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4189663395
Short name T844
Test name
Test status
Simulation time 16345940 ps
CPU time 1.22 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:07 PM PST 23
Peak memory 235440 kb
Host smart-282d9617-7129-40c6-b39a-ae962757fdd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4189663395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4189663395
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3341775751
Short name T779
Test name
Test status
Simulation time 926883920 ps
CPU time 15.78 seconds
Started Dec 27 12:31:33 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 243628 kb
Host smart-b218c33d-251d-4701-9f61-7a75c956ce64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3341775751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3341775751
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1487436963
Short name T144
Test name
Test status
Simulation time 4269929712 ps
CPU time 272.25 seconds
Started Dec 27 12:31:06 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 271984 kb
Host smart-13a76895-e80e-440c-9e7c-35caad8b05fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1487436963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1487436963
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1513140933
Short name T176
Test name
Test status
Simulation time 6477857974 ps
CPU time 439.57 seconds
Started Dec 27 12:31:10 PM PST 23
Finished Dec 27 12:39:18 PM PST 23
Peak memory 265548 kb
Host smart-6a4b04e5-c9ad-4707-9e0b-ca0de6983396
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513140933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1513140933
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.812953865
Short name T141
Test name
Test status
Simulation time 97871098 ps
CPU time 6.05 seconds
Started Dec 27 12:30:41 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 248520 kb
Host smart-080aa723-d46c-4aa7-8ad4-d17f2e61fa3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=812953865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.812953865
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3539431646
Short name T818
Test name
Test status
Simulation time 6342087 ps
CPU time 1.37 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 236444 kb
Host smart-d7e9ba76-60cd-4f39-8b19-0859c3760c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3539431646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3539431646
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1320583503
Short name T366
Test name
Test status
Simulation time 8826297 ps
CPU time 1.37 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 234544 kb
Host smart-aa149c6b-da4d-4ecd-aebb-121372478762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1320583503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1320583503
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.690564763
Short name T767
Test name
Test status
Simulation time 25587374 ps
CPU time 1.38 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 236368 kb
Host smart-722e6c05-8dee-4c37-aa67-48b072762ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=690564763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.690564763
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1136937483
Short name T847
Test name
Test status
Simulation time 11312469 ps
CPU time 1.19 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 235500 kb
Host smart-9b4b52a2-885f-4b7a-b20e-d27de424745a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136937483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1136937483
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3601595073
Short name T821
Test name
Test status
Simulation time 16121171 ps
CPU time 1.21 seconds
Started Dec 27 12:31:50 PM PST 23
Finished Dec 27 12:32:38 PM PST 23
Peak memory 234512 kb
Host smart-c19800b5-8924-4514-ad79-75ad63539bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3601595073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3601595073
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3681207603
Short name T795
Test name
Test status
Simulation time 29789455 ps
CPU time 1.4 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 235552 kb
Host smart-7af6ae1d-41ff-4385-90fa-ce86fe0667e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3681207603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3681207603
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1652488534
Short name T203
Test name
Test status
Simulation time 7931695 ps
CPU time 1.33 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:32:17 PM PST 23
Peak memory 234484 kb
Host smart-aba69df1-9f19-457a-aa82-82c51a24be4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1652488534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1652488534
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1304351932
Short name T787
Test name
Test status
Simulation time 6898049 ps
CPU time 1.4 seconds
Started Dec 27 12:31:07 PM PST 23
Finished Dec 27 12:31:57 PM PST 23
Peak memory 235448 kb
Host smart-c2511cb9-c925-4b33-8b59-8ca10ff01017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1304351932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1304351932
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.102920559
Short name T842
Test name
Test status
Simulation time 24055932 ps
CPU time 1.25 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 235476 kb
Host smart-4f3340b9-07f8-4621-9284-773c36972f94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=102920559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.102920559
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3181231544
Short name T140
Test name
Test status
Simulation time 72222164 ps
CPU time 6.38 seconds
Started Dec 27 12:32:11 PM PST 23
Finished Dec 27 12:33:01 PM PST 23
Peak memory 250540 kb
Host smart-31d88bde-4180-4e86-b2f3-a8cd5de35177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181231544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3181231544
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4050736440
Short name T848
Test name
Test status
Simulation time 83390320 ps
CPU time 3.04 seconds
Started Dec 27 12:31:00 PM PST 23
Finished Dec 27 12:31:54 PM PST 23
Peak memory 238280 kb
Host smart-ae68b33e-e88b-4c85-81ee-bd902b30e74c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4050736440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4050736440
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1758528871
Short name T788
Test name
Test status
Simulation time 27655452 ps
CPU time 1.34 seconds
Started Dec 27 12:32:57 PM PST 23
Finished Dec 27 12:33:32 PM PST 23
Peak memory 235384 kb
Host smart-394406a2-8018-4662-85f9-fbbe65571b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758528871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1758528871
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.484677359
Short name T775
Test name
Test status
Simulation time 363068708 ps
CPU time 22.62 seconds
Started Dec 27 12:30:49 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 244612 kb
Host smart-daa48dfd-3e1f-438d-a6e3-1f2e07205883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=484677359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.484677359
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1667140596
Short name T167
Test name
Test status
Simulation time 4031583154 ps
CPU time 180.07 seconds
Started Dec 27 12:31:01 PM PST 23
Finished Dec 27 12:34:52 PM PST 23
Peak memory 265344 kb
Host smart-f64d9e4f-5214-4d27-a772-d60fc20548a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1667140596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1667140596
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3819632502
Short name T768
Test name
Test status
Simulation time 224160755 ps
CPU time 14.25 seconds
Started Dec 27 12:33:00 PM PST 23
Finished Dec 27 12:33:47 PM PST 23
Peak memory 247772 kb
Host smart-f14da6a2-c7f6-4241-9bea-416f8a197f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3819632502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3819632502
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4093791236
Short name T816
Test name
Test status
Simulation time 470306015 ps
CPU time 30.51 seconds
Started Dec 27 12:32:45 PM PST 23
Finished Dec 27 12:33:52 PM PST 23
Peak memory 240032 kb
Host smart-4c132ec4-52b1-4872-b3b9-b675422f82f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4093791236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4093791236
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.24497483
Short name T786
Test name
Test status
Simulation time 503583055 ps
CPU time 3.7 seconds
Started Dec 27 12:30:37 PM PST 23
Finished Dec 27 12:31:37 PM PST 23
Peak memory 238260 kb
Host smart-65e38aa4-895d-4df1-853a-d3b345286f6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.alert_handler_csr_mem_rw_with_rand_reset.24497483
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2105801400
Short name T829
Test name
Test status
Simulation time 263070978 ps
CPU time 8.52 seconds
Started Dec 27 12:30:32 PM PST 23
Finished Dec 27 12:31:38 PM PST 23
Peak memory 240280 kb
Host smart-22c3ef25-e67b-4938-bb89-f5f3c42640ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2105801400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2105801400
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2721390552
Short name T246
Test name
Test status
Simulation time 8534882 ps
CPU time 1.4 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 236328 kb
Host smart-f562e1f7-eaca-4ddf-ab4d-4a0de803cdcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2721390552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2721390552
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3594481880
Short name T197
Test name
Test status
Simulation time 2775418490 ps
CPU time 40.73 seconds
Started Dec 27 12:30:37 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 244604 kb
Host smart-d9f70ccd-9708-45a4-a875-5dd7b3595b57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3594481880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3594481880
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.59363146
Short name T170
Test name
Test status
Simulation time 24302749686 ps
CPU time 371.27 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:37:42 PM PST 23
Peak memory 273060 kb
Host smart-974d5d46-cd3a-40f7-9b07-c25e8eefafef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59363146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors
.59363146
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2091054949
Short name T744
Test name
Test status
Simulation time 61868224 ps
CPU time 6.02 seconds
Started Dec 27 12:32:41 PM PST 23
Finished Dec 27 12:33:24 PM PST 23
Peak memory 248044 kb
Host smart-031f2837-ce0f-42b5-884d-3ff7c52f3511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2091054949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2091054949
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2407843649
Short name T798
Test name
Test status
Simulation time 117111469 ps
CPU time 5.93 seconds
Started Dec 27 12:31:07 PM PST 23
Finished Dec 27 12:32:02 PM PST 23
Peak memory 243700 kb
Host smart-6af71c65-6864-4143-9501-f1d854eb1ca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407843649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2407843649
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.327420139
Short name T813
Test name
Test status
Simulation time 754922535 ps
CPU time 4.75 seconds
Started Dec 27 12:30:37 PM PST 23
Finished Dec 27 12:31:38 PM PST 23
Peak memory 238332 kb
Host smart-4f4b89e5-adb6-4f3c-bd56-ca95461ece9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=327420139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.327420139
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1597737199
Short name T759
Test name
Test status
Simulation time 8620896 ps
CPU time 1.26 seconds
Started Dec 27 12:30:50 PM PST 23
Finished Dec 27 12:31:45 PM PST 23
Peak memory 236484 kb
Host smart-0120ec70-6f3f-4e24-ba07-2db807a908de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1597737199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1597737199
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1213924751
Short name T812
Test name
Test status
Simulation time 661122084 ps
CPU time 41.93 seconds
Started Dec 27 12:30:48 PM PST 23
Finished Dec 27 12:32:24 PM PST 23
Peak memory 244496 kb
Host smart-62a4196e-3fe7-498c-afbc-ad6dab3b03e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1213924751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1213924751
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3079294528
Short name T841
Test name
Test status
Simulation time 3743385126 ps
CPU time 156.98 seconds
Started Dec 27 12:30:37 PM PST 23
Finished Dec 27 12:34:11 PM PST 23
Peak memory 265244 kb
Host smart-7957605a-d7ff-442e-8d10-1c6209dc6562
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3079294528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3079294528
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1155850547
Short name T30
Test name
Test status
Simulation time 9756095235 ps
CPU time 289.89 seconds
Started Dec 27 12:31:00 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 265332 kb
Host smart-9d41fb6c-fa28-430c-9551-c92ada30a067
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155850547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1155850547
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3577141535
Short name T789
Test name
Test status
Simulation time 141680215 ps
CPU time 9.09 seconds
Started Dec 27 12:30:56 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 248684 kb
Host smart-01bb4c14-2f83-4de5-b251-1dad8c41f780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3577141535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3577141535
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.764796534
Short name T166
Test name
Test status
Simulation time 294992476 ps
CPU time 19.93 seconds
Started Dec 27 12:30:35 PM PST 23
Finished Dec 27 12:31:52 PM PST 23
Peak memory 236544 kb
Host smart-c0d1e051-2f23-47e7-9b6e-9f0f7335ff45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=764796534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.764796534
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3478514156
Short name T846
Test name
Test status
Simulation time 142673739 ps
CPU time 4.76 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 251552 kb
Host smart-cf96641c-d825-414c-819a-144ef75f28fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478514156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3478514156
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3066814400
Short name T365
Test name
Test status
Simulation time 21906610 ps
CPU time 1.19 seconds
Started Dec 27 12:30:55 PM PST 23
Finished Dec 27 12:31:48 PM PST 23
Peak memory 235420 kb
Host smart-95e81f27-9b3b-4929-942c-464a147a83a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3066814400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3066814400
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2882495164
Short name T198
Test name
Test status
Simulation time 301319787 ps
CPU time 10.74 seconds
Started Dec 27 12:30:39 PM PST 23
Finished Dec 27 12:31:46 PM PST 23
Peak memory 240212 kb
Host smart-d6345936-96bb-4684-8ba4-0e238871b18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2882495164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2882495164
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1117932208
Short name T28
Test name
Test status
Simulation time 7304128014 ps
CPU time 257.75 seconds
Started Dec 27 12:30:55 PM PST 23
Finished Dec 27 12:36:04 PM PST 23
Peak memory 265244 kb
Host smart-0714a99e-0e4d-412d-b93c-ebb6c8d59104
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1117932208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1117932208
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2560099325
Short name T840
Test name
Test status
Simulation time 40731728382 ps
CPU time 447.67 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:39:34 PM PST 23
Peak memory 269056 kb
Host smart-d21af251-eda7-4f3e-8bc6-8a82f82baea9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560099325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2560099325
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1199023393
Short name T785
Test name
Test status
Simulation time 1338197301 ps
CPU time 22.65 seconds
Started Dec 27 12:31:29 PM PST 23
Finished Dec 27 12:32:42 PM PST 23
Peak memory 247968 kb
Host smart-a8e73b38-513a-419f-ba20-fb71a19c1e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1199023393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1199023393
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4145701678
Short name T810
Test name
Test status
Simulation time 56433795 ps
CPU time 6.1 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 252208 kb
Host smart-44f719b9-3be0-4076-a6c6-3ce518965300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145701678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.4145701678
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.510037259
Short name T781
Test name
Test status
Simulation time 471274319 ps
CPU time 8.33 seconds
Started Dec 27 12:33:25 PM PST 23
Finished Dec 27 12:33:56 PM PST 23
Peak memory 236208 kb
Host smart-7a60f52b-7435-4328-a107-af01cd906dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=510037259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.510037259
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1504610484
Short name T790
Test name
Test status
Simulation time 10370268 ps
CPU time 1.2 seconds
Started Dec 27 12:30:42 PM PST 23
Finished Dec 27 12:31:40 PM PST 23
Peak memory 235460 kb
Host smart-766334e7-95b6-4399-a955-9adcec4c8cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1504610484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1504610484
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2742673715
Short name T742
Test name
Test status
Simulation time 168144515 ps
CPU time 21.3 seconds
Started Dec 27 12:31:12 PM PST 23
Finished Dec 27 12:32:21 PM PST 23
Peak memory 248604 kb
Host smart-68ce3c55-037a-466c-916f-343196cb7b98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2742673715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2742673715
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.907115456
Short name T168
Test name
Test status
Simulation time 15499826916 ps
CPU time 282.97 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 272232 kb
Host smart-601884cf-c766-4477-a08d-9f328751fb60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=907115456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.907115456
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1981077099
Short name T156
Test name
Test status
Simulation time 28305226408 ps
CPU time 1137.75 seconds
Started Dec 27 12:31:06 PM PST 23
Finished Dec 27 12:50:53 PM PST 23
Peak memory 265356 kb
Host smart-54b828e0-be6d-44ba-908b-604362717e1e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981077099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1981077099
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1763517811
Short name T836
Test name
Test status
Simulation time 131185529 ps
CPU time 8.22 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 248500 kb
Host smart-f50e31a8-5cdc-405b-bddf-0c495ac3e3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763517811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1763517811
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3675356921
Short name T833
Test name
Test status
Simulation time 6188495140 ps
CPU time 40.43 seconds
Started Dec 27 12:31:10 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 239344 kb
Host smart-da1b32f3-142a-467e-bd8c-6165f3f07de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3675356921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3675356921
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1627423341
Short name T407
Test name
Test status
Simulation time 28891609596 ps
CPU time 1342.79 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 01:04:42 PM PST 23
Peak memory 284448 kb
Host smart-9ebfa396-874a-4c88-adb3-b4951a5af5f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627423341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1627423341
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1100156640
Short name T484
Test name
Test status
Simulation time 245562135 ps
CPU time 11.5 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:32 PM PST 23
Peak memory 240312 kb
Host smart-a418b86a-9d52-499f-a7a2-adbb708dd53d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1100156640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1100156640
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.687863589
Short name T612
Test name
Test status
Simulation time 4775715066 ps
CPU time 253.12 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 12:46:17 PM PST 23
Peak memory 256836 kb
Host smart-81d3b368-a387-44ad-8199-284757612d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68786
3589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.687863589
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1242348370
Short name T662
Test name
Test status
Simulation time 377387650 ps
CPU time 20.39 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:26 PM PST 23
Peak memory 248128 kb
Host smart-33d5076e-71c5-4166-95b4-37fe0c4725c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12423
48370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1242348370
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1869265383
Short name T422
Test name
Test status
Simulation time 25538268151 ps
CPU time 1550.55 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 01:08:33 PM PST 23
Peak memory 272488 kb
Host smart-913b102f-e2b5-4e02-ad91-4fd626e14517
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869265383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1869265383
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.945195682
Short name T679
Test name
Test status
Simulation time 315249667 ps
CPU time 9.92 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 12:42:33 PM PST 23
Peak memory 248524 kb
Host smart-cfd884cf-03a9-4d72-9c10-bd7bb4d3b07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94519
5682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.945195682
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3829560273
Short name T503
Test name
Test status
Simulation time 366299470 ps
CPU time 21.95 seconds
Started Dec 27 12:40:53 PM PST 23
Finished Dec 27 12:42:19 PM PST 23
Peak memory 247264 kb
Host smart-d0dbcfde-273c-4196-afb8-ad7c41daa6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38295
60273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3829560273
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.152568554
Short name T46
Test name
Test status
Simulation time 352478971 ps
CPU time 21.09 seconds
Started Dec 27 12:41:21 PM PST 23
Finished Dec 27 12:42:44 PM PST 23
Peak memory 269660 kb
Host smart-58281a99-7921-4f3a-9266-00ef3f97b774
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=152568554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.152568554
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2339693318
Short name T656
Test name
Test status
Simulation time 1213730592 ps
CPU time 38.06 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:50 PM PST 23
Peak memory 255200 kb
Host smart-a9b7b64d-fa4f-4832-ab0a-d928fa785f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396
93318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2339693318
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3812484053
Short name T525
Test name
Test status
Simulation time 281595412 ps
CPU time 26.67 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 12:42:30 PM PST 23
Peak memory 248456 kb
Host smart-c57c0e41-c547-47b4-b3b0-84410971cf0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38124
84053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3812484053
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.182980028
Short name T130
Test name
Test status
Simulation time 10830034516 ps
CPU time 239.6 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:46:18 PM PST 23
Peak memory 254280 kb
Host smart-c26e2bb7-428c-46ff-876c-ef00a674e7ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182980028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.182980028
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2999695163
Short name T228
Test name
Test status
Simulation time 29598824 ps
CPU time 2.91 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:42:11 PM PST 23
Peak memory 248820 kb
Host smart-80340bb7-6464-4c0d-a15e-146a65c6d290
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2999695163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2999695163
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.139112251
Short name T408
Test name
Test status
Simulation time 98207448 ps
CPU time 6.13 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:26 PM PST 23
Peak memory 240272 kb
Host smart-4e4d01c3-eb37-41bb-bc7a-b1dd269a7de8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=139112251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.139112251
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1914847986
Short name T482
Test name
Test status
Simulation time 2400950636 ps
CPU time 65.59 seconds
Started Dec 27 12:41:05 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 255396 kb
Host smart-071b3978-7924-404f-be7a-98803e7ad3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19148
47986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1914847986
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1469238725
Short name T88
Test name
Test status
Simulation time 541052171 ps
CPU time 22.84 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:42:37 PM PST 23
Peak memory 248480 kb
Host smart-82bf18fa-5c72-4265-974a-6a250c1e0bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14692
38725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1469238725
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.802151143
Short name T309
Test name
Test status
Simulation time 58221535225 ps
CPU time 3398.47 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 01:38:38 PM PST 23
Peak memory 289104 kb
Host smart-0fed9aeb-e40f-4111-ab82-d81aab68f792
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802151143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.802151143
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2621691822
Short name T111
Test name
Test status
Simulation time 39622373572 ps
CPU time 693.05 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:53:45 PM PST 23
Peak memory 267984 kb
Host smart-77582892-c966-4b83-af78-cf270f4e9b86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621691822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2621691822
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1759798476
Short name T706
Test name
Test status
Simulation time 13884817069 ps
CPU time 580.05 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 12:51:45 PM PST 23
Peak memory 246428 kb
Host smart-482ac2f2-66b9-4f2b-a2bd-22b3a0fe80eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759798476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1759798476
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.942293276
Short name T454
Test name
Test status
Simulation time 4064627161 ps
CPU time 50.15 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 248876 kb
Host smart-e565d7fe-12b1-4386-8629-6d33442401f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94229
3276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.942293276
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1315054158
Short name T725
Test name
Test status
Simulation time 170225703 ps
CPU time 10.44 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 12:42:10 PM PST 23
Peak memory 246816 kb
Host smart-a8f3bc93-c374-4779-8716-ec077429a93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13150
54158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1315054158
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2319046376
Short name T47
Test name
Test status
Simulation time 660609151 ps
CPU time 16.43 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 12:42:37 PM PST 23
Peak memory 277508 kb
Host smart-19387520-2d86-4556-bf5f-d64dfd130950
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2319046376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2319046376
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1095572346
Short name T650
Test name
Test status
Simulation time 156720975 ps
CPU time 4.23 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:27 PM PST 23
Peak memory 238580 kb
Host smart-b3dbd365-2f9f-4dd3-9256-812835715e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10955
72346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1095572346
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1673614435
Short name T587
Test name
Test status
Simulation time 2273618144 ps
CPU time 32.7 seconds
Started Dec 27 12:41:11 PM PST 23
Finished Dec 27 12:42:47 PM PST 23
Peak memory 248624 kb
Host smart-377c2ecd-bcd2-4c94-babb-ed8ce9b161d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
14435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1673614435
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3611147946
Short name T550
Test name
Test status
Simulation time 244009297192 ps
CPU time 1665.46 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 01:10:22 PM PST 23
Peak memory 273184 kb
Host smart-713d3826-81e1-4ace-9d2c-ac8bb591f1fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611147946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3611147946
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.415624246
Short name T428
Test name
Test status
Simulation time 216364455 ps
CPU time 7.06 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 12:42:29 PM PST 23
Peak memory 240308 kb
Host smart-98f9b4b4-284e-4ef4-a17e-24d8e86528d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=415624246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.415624246
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.119580028
Short name T651
Test name
Test status
Simulation time 11802285158 ps
CPU time 160.05 seconds
Started Dec 27 12:41:13 PM PST 23
Finished Dec 27 12:44:58 PM PST 23
Peak memory 256736 kb
Host smart-04ed6e68-399e-4454-9735-54fab7638212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
0028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.119580028
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2094070327
Short name T633
Test name
Test status
Simulation time 170639529 ps
CPU time 11.09 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:31 PM PST 23
Peak memory 253520 kb
Host smart-c4deeb44-755a-421c-9065-9395bc245dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20940
70327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2094070327
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.587315686
Short name T516
Test name
Test status
Simulation time 85926024603 ps
CPU time 1529.2 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 01:07:51 PM PST 23
Peak memory 271840 kb
Host smart-8e6b57c3-6a15-4f6f-b09b-0b1262d0d916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587315686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.587315686
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3194118373
Short name T67
Test name
Test status
Simulation time 1723170664 ps
CPU time 29.97 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:49 PM PST 23
Peak memory 256740 kb
Host smart-ac657339-81d1-4e40-b096-3071f4dee994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31941
18373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3194118373
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.691600922
Short name T625
Test name
Test status
Simulation time 2822955516 ps
CPU time 20.27 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 12:42:40 PM PST 23
Peak memory 248672 kb
Host smart-a6de64cd-3440-4dcd-b241-f205043c2541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69160
0922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.691600922
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3007663467
Short name T486
Test name
Test status
Simulation time 1350384070 ps
CPU time 19.97 seconds
Started Dec 27 12:41:25 PM PST 23
Finished Dec 27 12:42:47 PM PST 23
Peak memory 248580 kb
Host smart-c0208a6c-0c68-47e8-bf1b-50b264986484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30076
63467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3007663467
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2604222790
Short name T687
Test name
Test status
Simulation time 532115623 ps
CPU time 20.7 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:42:39 PM PST 23
Peak memory 248548 kb
Host smart-9de2cf5e-7c7c-48e2-bc70-4f4ab518a46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26042
22790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2604222790
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1092389152
Short name T204
Test name
Test status
Simulation time 30284970597 ps
CPU time 1447.91 seconds
Started Dec 27 12:41:11 PM PST 23
Finished Dec 27 01:06:23 PM PST 23
Peak memory 288940 kb
Host smart-d21b6f55-2522-41c9-a832-12c924213568
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092389152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1092389152
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1941754516
Short name T123
Test name
Test status
Simulation time 20631033575 ps
CPU time 1441.67 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 01:06:23 PM PST 23
Peak memory 272500 kb
Host smart-6f35bc35-3c8a-45ea-91ec-27614845dcfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941754516 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1941754516
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1458964657
Short name T717
Test name
Test status
Simulation time 166151532567 ps
CPU time 2593 seconds
Started Dec 27 12:41:26 PM PST 23
Finished Dec 27 01:25:41 PM PST 23
Peak memory 284536 kb
Host smart-c305cee3-a5de-4008-a554-507904f446ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458964657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1458964657
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2287557814
Short name T702
Test name
Test status
Simulation time 1108989530 ps
CPU time 34.59 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 12:42:51 PM PST 23
Peak memory 255908 kb
Host smart-2d654567-7656-403c-944b-78640c2cbbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22875
57814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2287557814
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2135210973
Short name T564
Test name
Test status
Simulation time 1242758362 ps
CPU time 20.98 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:42:45 PM PST 23
Peak memory 255160 kb
Host smart-ccf67453-e9f9-4e52-8442-11dd0d2476bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21352
10973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2135210973
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.4115234739
Short name T350
Test name
Test status
Simulation time 43435628164 ps
CPU time 1197.47 seconds
Started Dec 27 12:41:29 PM PST 23
Finished Dec 27 01:02:28 PM PST 23
Peak memory 284348 kb
Host smart-d4ae499b-17a2-469c-9717-d0cf4b6ff47c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115234739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.4115234739
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3235119384
Short name T521
Test name
Test status
Simulation time 27873612101 ps
CPU time 1664.73 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 01:10:07 PM PST 23
Peak memory 284416 kb
Host smart-2de2a1cd-24a4-46cd-a475-9484431e5458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235119384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3235119384
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2120235013
Short name T9
Test name
Test status
Simulation time 23010021145 ps
CPU time 233.96 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:46:15 PM PST 23
Peak memory 246288 kb
Host smart-435dcd4a-104b-4cd6-9f01-9df617549a0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120235013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2120235013
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1782834697
Short name T735
Test name
Test status
Simulation time 493089692 ps
CPU time 28.9 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:43:02 PM PST 23
Peak memory 255048 kb
Host smart-8cca2893-ceaa-43f2-a06a-89597cbebd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17828
34697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1782834697
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3200129680
Short name T549
Test name
Test status
Simulation time 392573546 ps
CPU time 21.42 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:43 PM PST 23
Peak memory 254276 kb
Host smart-334c7fb6-53f2-489a-8776-aa6131a93ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32001
29680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3200129680
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1315737279
Short name T537
Test name
Test status
Simulation time 4888505762 ps
CPU time 31.99 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 12:43:13 PM PST 23
Peak memory 248488 kb
Host smart-bac9b09d-d0f9-440a-8489-c2c9cd92c791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13157
37279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1315737279
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.77124946
Short name T643
Test name
Test status
Simulation time 276402422817 ps
CPU time 6053.76 seconds
Started Dec 27 12:41:21 PM PST 23
Finished Dec 27 02:23:17 PM PST 23
Peak memory 338752 kb
Host smart-be8bf452-5a00-473e-8f3c-ec7a6685690e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77124946 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.77124946
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3623844831
Short name T219
Test name
Test status
Simulation time 21820089 ps
CPU time 2.22 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 12:42:44 PM PST 23
Peak memory 248700 kb
Host smart-84eb1afa-b1fa-4f3d-90ee-f88f6846d0c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3623844831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3623844831
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2129589347
Short name T472
Test name
Test status
Simulation time 344944303185 ps
CPU time 2094.24 seconds
Started Dec 27 12:41:27 PM PST 23
Finished Dec 27 01:17:24 PM PST 23
Peak memory 288892 kb
Host smart-1e715ce1-c7c1-4319-95db-42decaaf9d24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129589347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2129589347
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1690067549
Short name T649
Test name
Test status
Simulation time 273220813 ps
CPU time 14.05 seconds
Started Dec 27 12:41:25 PM PST 23
Finished Dec 27 12:42:41 PM PST 23
Peak memory 240372 kb
Host smart-8b5e44bf-ee6a-4e56-93d3-365e90bf6273
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1690067549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1690067549
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1749683047
Short name T551
Test name
Test status
Simulation time 1660462766 ps
CPU time 125.84 seconds
Started Dec 27 12:41:29 PM PST 23
Finished Dec 27 12:44:37 PM PST 23
Peak memory 256072 kb
Host smart-58abdce0-8000-4d26-bcc9-750ffc25516b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
83047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1749683047
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1352113322
Short name T276
Test name
Test status
Simulation time 4179488674 ps
CPU time 38.17 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 256260 kb
Host smart-eea260d3-772d-4755-adc7-7b504a709be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521
13322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1352113322
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2742452843
Short name T467
Test name
Test status
Simulation time 41440440681 ps
CPU time 2137.13 seconds
Started Dec 27 12:41:26 PM PST 23
Finished Dec 27 01:18:05 PM PST 23
Peak memory 286768 kb
Host smart-5484146a-6677-4cc3-a42e-b02b9d80ec1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742452843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2742452843
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2673521869
Short name T461
Test name
Test status
Simulation time 21112955441 ps
CPU time 232.79 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 12:46:26 PM PST 23
Peak memory 247444 kb
Host smart-087c23bd-ce2d-4f91-a9ff-c720784246f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673521869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2673521869
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3801139668
Short name T531
Test name
Test status
Simulation time 1705988068 ps
CPU time 22.49 seconds
Started Dec 27 12:41:21 PM PST 23
Finished Dec 27 12:42:46 PM PST 23
Peak memory 248608 kb
Host smart-80969b2f-3d1c-494c-9e62-ca2478bdf9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38011
39668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3801139668
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2385399140
Short name T545
Test name
Test status
Simulation time 18396349 ps
CPU time 2.88 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 239436 kb
Host smart-27350a66-d45d-41c4-b630-6f116fed5798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23853
99140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2385399140
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4057013393
Short name T393
Test name
Test status
Simulation time 236666346 ps
CPU time 14.9 seconds
Started Dec 27 12:41:21 PM PST 23
Finished Dec 27 12:42:38 PM PST 23
Peak memory 248632 kb
Host smart-1ad8ec2f-b672-471a-a08a-02176fc001a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40570
13393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4057013393
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2447879521
Short name T371
Test name
Test status
Simulation time 415763242 ps
CPU time 23.9 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:36 PM PST 23
Peak memory 248580 kb
Host smart-cc10366f-352c-4726-8439-4e4074f42906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24478
79521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2447879521
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3496882609
Short name T689
Test name
Test status
Simulation time 66469704378 ps
CPU time 1371.87 seconds
Started Dec 27 12:41:37 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 289476 kb
Host smart-9d194a47-0609-4f20-b89d-9a8d29369f39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496882609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3496882609
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2009993812
Short name T714
Test name
Test status
Simulation time 114643263019 ps
CPU time 6059.35 seconds
Started Dec 27 12:41:29 PM PST 23
Finished Dec 27 02:23:31 PM PST 23
Peak memory 371056 kb
Host smart-e7d54f39-2083-48d9-be22-6911c62799c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009993812 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2009993812
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.565986781
Short name T227
Test name
Test status
Simulation time 15894920 ps
CPU time 2.49 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 248796 kb
Host smart-bf77fa16-4626-4434-8e80-79393ae4f946
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=565986781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.565986781
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1859314898
Short name T49
Test name
Test status
Simulation time 22491649414 ps
CPU time 600.91 seconds
Started Dec 27 12:41:31 PM PST 23
Finished Dec 27 12:52:33 PM PST 23
Peak memory 272848 kb
Host smart-bdbcf93d-984f-45f4-b549-b5ca16733fb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859314898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1859314898
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1087443385
Short name T420
Test name
Test status
Simulation time 377116184 ps
CPU time 10.48 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 12:42:46 PM PST 23
Peak memory 240356 kb
Host smart-cd06746a-a8da-411f-b485-7ab4a7903973
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1087443385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1087443385
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.936938607
Short name T78
Test name
Test status
Simulation time 1432750162 ps
CPU time 54.72 seconds
Started Dec 27 12:41:25 PM PST 23
Finished Dec 27 12:43:21 PM PST 23
Peak memory 248624 kb
Host smart-a8f82a00-808f-4d82-8458-a960658abe28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93693
8607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.936938607
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1168366573
Short name T710
Test name
Test status
Simulation time 1387668722 ps
CPU time 25.3 seconds
Started Dec 27 12:41:35 PM PST 23
Finished Dec 27 12:43:00 PM PST 23
Peak memory 254988 kb
Host smart-22c0eb38-1baa-4412-afa4-a7e2b3ea2ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11683
66573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1168366573
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3536707010
Short name T319
Test name
Test status
Simulation time 57043784921 ps
CPU time 1505.63 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 01:07:47 PM PST 23
Peak memory 272192 kb
Host smart-60c8bf68-3d65-4129-944e-375bdcbaa133
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536707010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3536707010
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2894267952
Short name T622
Test name
Test status
Simulation time 23861100083 ps
CPU time 1338.17 seconds
Started Dec 27 12:41:22 PM PST 23
Finished Dec 27 01:04:42 PM PST 23
Peak memory 272296 kb
Host smart-5caa055c-7441-4742-ab7e-bca7bd7c62ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894267952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2894267952
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.813281943
Short name T210
Test name
Test status
Simulation time 31866586271 ps
CPU time 330.31 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:48:00 PM PST 23
Peak memory 247452 kb
Host smart-834417d2-f8ee-469a-ab7d-10cc530ba4de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813281943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.813281943
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.883058967
Short name T397
Test name
Test status
Simulation time 340836318 ps
CPU time 27.47 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 248568 kb
Host smart-4fff9738-4d65-414a-8e95-763bc1cb5c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88305
8967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.883058967
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2732347057
Short name T728
Test name
Test status
Simulation time 321324687 ps
CPU time 25.55 seconds
Started Dec 27 12:41:25 PM PST 23
Finished Dec 27 12:42:52 PM PST 23
Peak memory 248564 kb
Host smart-669f2705-511e-4fba-816f-dda3b99799dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27323
47057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2732347057
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.976533803
Short name T42
Test name
Test status
Simulation time 120600420 ps
CPU time 9.76 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 12:42:52 PM PST 23
Peak memory 248620 kb
Host smart-15f2c220-2e9a-4df3-b0f1-792feaf6ca6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97653
3803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.976533803
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2581532700
Short name T284
Test name
Test status
Simulation time 61710805493 ps
CPU time 3566.22 seconds
Started Dec 27 12:41:24 PM PST 23
Finished Dec 27 01:41:52 PM PST 23
Peak memory 305716 kb
Host smart-d02818b9-b6a2-465b-9387-a76f0157ee80
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581532700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2581532700
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1127330921
Short name T280
Test name
Test status
Simulation time 711258540744 ps
CPU time 7951.57 seconds
Started Dec 27 12:41:24 PM PST 23
Finished Dec 27 02:54:58 PM PST 23
Peak memory 338060 kb
Host smart-2fa620bd-30d1-4ca6-a719-5284d9fc8810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127330921 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1127330921
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.50319929
Short name T225
Test name
Test status
Simulation time 50178609 ps
CPU time 3.88 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 12:42:36 PM PST 23
Peak memory 248692 kb
Host smart-39be0ab2-cfae-44e8-8a2c-d6239d7a9a3f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=50319929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.50319929
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4235244119
Short name T115
Test name
Test status
Simulation time 60949845545 ps
CPU time 1260.91 seconds
Started Dec 27 12:41:41 PM PST 23
Finished Dec 27 01:03:40 PM PST 23
Peak memory 273088 kb
Host smart-9f7a08d0-b55c-46b5-b4b3-4988e3b94ccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235244119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4235244119
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2159630602
Short name T688
Test name
Test status
Simulation time 2220165530 ps
CPU time 23.33 seconds
Started Dec 27 12:41:34 PM PST 23
Finished Dec 27 12:42:57 PM PST 23
Peak memory 240420 kb
Host smart-bb1258c8-ee87-4900-84a4-d2759bf0004f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2159630602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2159630602
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2835448127
Short name T596
Test name
Test status
Simulation time 315929094 ps
CPU time 21.46 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:42:46 PM PST 23
Peak memory 253952 kb
Host smart-18227df6-b291-44c7-a84f-3f87388bbadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28354
48127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2835448127
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3588058412
Short name T606
Test name
Test status
Simulation time 362521226 ps
CPU time 22.33 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:42:56 PM PST 23
Peak memory 254260 kb
Host smart-4d57b25b-2d4c-4d18-9433-46674d372b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35880
58412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3588058412
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2256558980
Short name T298
Test name
Test status
Simulation time 29357964113 ps
CPU time 1598.68 seconds
Started Dec 27 12:41:35 PM PST 23
Finished Dec 27 01:09:14 PM PST 23
Peak memory 272592 kb
Host smart-729397dd-5225-4483-8e56-23e9d2558348
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256558980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2256558980
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.663782668
Short name T630
Test name
Test status
Simulation time 16200159591 ps
CPU time 678.43 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:53:52 PM PST 23
Peak memory 265044 kb
Host smart-663cfe58-e0ba-4044-991a-097c4f1561f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663782668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.663782668
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1896007460
Short name T307
Test name
Test status
Simulation time 28639358038 ps
CPU time 288.68 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:47:13 PM PST 23
Peak memory 248184 kb
Host smart-a6f0f00d-22ef-489b-a338-f31799f80e6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896007460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1896007460
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3159951614
Short name T391
Test name
Test status
Simulation time 272619257 ps
CPU time 21.11 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:42:51 PM PST 23
Peak memory 248548 kb
Host smart-b7a0d9d9-e7f7-4c1a-b6e9-a802922e3085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31599
51614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3159951614
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2675498561
Short name T100
Test name
Test status
Simulation time 2567636172 ps
CPU time 42.11 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:43:15 PM PST 23
Peak memory 255664 kb
Host smart-92fa34d9-1b03-44eb-bbe9-1487bed75168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754
98561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2675498561
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1622949268
Short name T442
Test name
Test status
Simulation time 858018152 ps
CPU time 19.05 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:42:43 PM PST 23
Peak memory 248516 kb
Host smart-33789ba4-36d1-420f-803a-fed2ffb61cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16229
49268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1622949268
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4185333381
Short name T604
Test name
Test status
Simulation time 1485281772 ps
CPU time 123.79 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 12:44:36 PM PST 23
Peak memory 250848 kb
Host smart-4ee1b0a1-ef05-4335-9425-99ce245ea070
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185333381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4185333381
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.253531941
Short name T238
Test name
Test status
Simulation time 58997785429 ps
CPU time 3465.22 seconds
Started Dec 27 12:41:30 PM PST 23
Finished Dec 27 01:40:17 PM PST 23
Peak memory 301576 kb
Host smart-12747b86-c7cb-46c7-aff1-ea837d3b2b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253531941 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.253531941
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.781348832
Short name T221
Test name
Test status
Simulation time 13400401 ps
CPU time 2.17 seconds
Started Dec 27 12:41:30 PM PST 23
Finished Dec 27 12:42:34 PM PST 23
Peak memory 248756 kb
Host smart-e85c91c6-7e09-47aa-9a88-362bc7155bdf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=781348832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.781348832
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.52813052
Short name T718
Test name
Test status
Simulation time 74313893712 ps
CPU time 1237.51 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 273140 kb
Host smart-eba1e1df-bf27-45ad-b9cf-5892fdfa41a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52813052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.52813052
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1463744898
Short name T605
Test name
Test status
Simulation time 5113922186 ps
CPU time 53.06 seconds
Started Dec 27 12:41:29 PM PST 23
Finished Dec 27 12:43:24 PM PST 23
Peak memory 240396 kb
Host smart-2a5fa521-8ec3-4d30-805c-a31d52cfc9e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1463744898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1463744898
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3302344422
Short name T669
Test name
Test status
Simulation time 3503812196 ps
CPU time 142.82 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 12:45:00 PM PST 23
Peak memory 256296 kb
Host smart-da303269-3f78-482b-b707-5c9717ab08c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33023
44422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3302344422
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1910430919
Short name T476
Test name
Test status
Simulation time 7616680356 ps
CPU time 33.64 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:42:52 PM PST 23
Peak memory 253484 kb
Host smart-91acd1cc-e68d-40bb-a74a-f62838409846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104
30919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1910430919
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1150325955
Short name T5
Test name
Test status
Simulation time 10814833566 ps
CPU time 1059.35 seconds
Started Dec 27 12:41:24 PM PST 23
Finished Dec 27 01:00:05 PM PST 23
Peak memory 280924 kb
Host smart-29b46b8a-f8d8-4e26-bcf9-8261b32ad588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150325955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1150325955
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1837139099
Short name T692
Test name
Test status
Simulation time 24975983858 ps
CPU time 1668.66 seconds
Started Dec 27 12:41:39 PM PST 23
Finished Dec 27 01:10:27 PM PST 23
Peak memory 273140 kb
Host smart-2d7cbc47-cdae-4d7b-9d7b-29875188e59f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837139099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1837139099
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1423807511
Short name T436
Test name
Test status
Simulation time 7084597717 ps
CPU time 80.97 seconds
Started Dec 27 12:41:39 PM PST 23
Finished Dec 27 12:43:59 PM PST 23
Peak memory 247484 kb
Host smart-f1187c89-f9c4-4790-a29d-a6572712e07b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423807511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1423807511
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1772490252
Short name T691
Test name
Test status
Simulation time 397201317 ps
CPU time 23.63 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 12:42:45 PM PST 23
Peak memory 248892 kb
Host smart-39438b6f-650b-4390-9f93-eb638b72f8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724
90252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1772490252
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3200424784
Short name T384
Test name
Test status
Simulation time 481001586 ps
CPU time 28.25 seconds
Started Dec 27 12:41:27 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 254072 kb
Host smart-70aeed6f-d7b4-4595-9868-ca6c213dba6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32004
24784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3200424784
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2172554349
Short name T590
Test name
Test status
Simulation time 408280006 ps
CPU time 24.19 seconds
Started Dec 27 12:41:34 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 248488 kb
Host smart-2097c2fb-71af-40ef-9fc2-329ad3635d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21725
54349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2172554349
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3415433939
Short name T502
Test name
Test status
Simulation time 9233146990 ps
CPU time 40.87 seconds
Started Dec 27 12:41:26 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 255452 kb
Host smart-aaa16176-4435-4049-bc41-ef344006da5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34154
33939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3415433939
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3161733862
Short name T251
Test name
Test status
Simulation time 327031835602 ps
CPU time 1042.13 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 01:00:05 PM PST 23
Peak memory 282596 kb
Host smart-1922f8fe-833c-45be-a733-62fb150bb504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161733862 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3161733862
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.446571410
Short name T214
Test name
Test status
Simulation time 80935371 ps
CPU time 2.74 seconds
Started Dec 27 12:41:34 PM PST 23
Finished Dec 27 12:42:37 PM PST 23
Peak memory 248784 kb
Host smart-c1611916-391d-4d9a-b0de-3ba00f5d8e52
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=446571410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.446571410
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1096174284
Short name T666
Test name
Test status
Simulation time 103887435696 ps
CPU time 1659.24 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 01:10:04 PM PST 23
Peak memory 273024 kb
Host smart-37f36eb6-1e23-439b-a8dd-01e794d12bb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096174284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1096174284
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1158394073
Short name T490
Test name
Test status
Simulation time 1345453056 ps
CPU time 19.31 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 248516 kb
Host smart-780fd956-10cd-4d05-8959-33c3cb4b9de0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1158394073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1158394073
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4080208784
Short name T678
Test name
Test status
Simulation time 1660023049 ps
CPU time 49.99 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:43:20 PM PST 23
Peak memory 248016 kb
Host smart-d8f6a6cc-0ca9-40f4-aacc-c2dcde78c46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40802
08784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4080208784
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2470342091
Short name T421
Test name
Test status
Simulation time 194546519 ps
CPU time 8.51 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 12:42:44 PM PST 23
Peak memory 254056 kb
Host smart-65695839-b463-42be-8899-98e4778f2c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24703
42091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2470342091
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.387662300
Short name T318
Test name
Test status
Simulation time 49561559119 ps
CPU time 1055.59 seconds
Started Dec 27 12:41:30 PM PST 23
Finished Dec 27 01:00:08 PM PST 23
Peak memory 281928 kb
Host smart-ef024f69-85aa-453a-a9e5-5732f25e53f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387662300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.387662300
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1741790118
Short name T658
Test name
Test status
Simulation time 26856226303 ps
CPU time 1522.1 seconds
Started Dec 27 12:41:30 PM PST 23
Finished Dec 27 01:07:54 PM PST 23
Peak memory 264880 kb
Host smart-6ac34aaf-622d-4395-bddc-83e22f915488
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741790118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1741790118
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1084186730
Short name T675
Test name
Test status
Simulation time 63368087400 ps
CPU time 167.71 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 12:45:30 PM PST 23
Peak memory 247364 kb
Host smart-cd0484c1-f203-40e3-8818-74b51ab09885
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084186730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1084186730
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2429826036
Short name T736
Test name
Test status
Simulation time 765812724 ps
CPU time 16.7 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 12:42:53 PM PST 23
Peak memory 248688 kb
Host smart-7f4329e5-063a-46f9-8737-daa78966ca55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24298
26036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2429826036
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.66457228
Short name T565
Test name
Test status
Simulation time 1951050192 ps
CPU time 27.31 seconds
Started Dec 27 12:41:31 PM PST 23
Finished Dec 27 12:42:59 PM PST 23
Peak memory 255388 kb
Host smart-9cd638f9-9251-4a73-b790-bae0b08eb18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66457
228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.66457228
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2674391156
Short name T553
Test name
Test status
Simulation time 292435428 ps
CPU time 9.66 seconds
Started Dec 27 12:41:31 PM PST 23
Finished Dec 27 12:42:42 PM PST 23
Peak memory 248536 kb
Host smart-ef8e6395-2c82-4617-a1cb-59cb64057e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
91156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2674391156
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.58411892
Short name T738
Test name
Test status
Simulation time 990767898 ps
CPU time 28.74 seconds
Started Dec 27 12:41:27 PM PST 23
Finished Dec 27 12:42:57 PM PST 23
Peak memory 256800 kb
Host smart-fa5bceff-3cb2-4e79-8895-644fc4e8c848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58411
892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.58411892
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2188181117
Short name T377
Test name
Test status
Simulation time 20543053363 ps
CPU time 521.21 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:51:11 PM PST 23
Peak memory 256768 kb
Host smart-3c20e0d6-7d8b-4f23-bc56-40505ddb1881
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188181117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2188181117
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1829349171
Short name T607
Test name
Test status
Simulation time 63643344411 ps
CPU time 2193.2 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 01:19:03 PM PST 23
Peak memory 289512 kb
Host smart-50ba74fb-eba9-45b2-b7ba-4f1e4c03cca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829349171 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1829349171
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2736524332
Short name T224
Test name
Test status
Simulation time 17218712 ps
CPU time 2.26 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:42:27 PM PST 23
Peak memory 248856 kb
Host smart-2dc42dac-f9f5-4091-a5a0-1e23720bdc15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2736524332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2736524332
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.270489413
Short name T648
Test name
Test status
Simulation time 31040392488 ps
CPU time 1048.91 seconds
Started Dec 27 12:41:35 PM PST 23
Finished Dec 27 01:00:04 PM PST 23
Peak memory 264984 kb
Host smart-f86fa94b-c027-47d0-ac95-a11315034bc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270489413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.270489413
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.93536082
Short name T603
Test name
Test status
Simulation time 614622081 ps
CPU time 27.56 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 12:43:05 PM PST 23
Peak memory 248588 kb
Host smart-b9ab5481-666e-4055-8257-f5291016a14d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=93536082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.93536082
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1269843781
Short name T232
Test name
Test status
Simulation time 5817226236 ps
CPU time 185.37 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 12:45:27 PM PST 23
Peak memory 249540 kb
Host smart-5f8d2b66-6a2f-4611-a007-f393c69c9bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698
43781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1269843781
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1595902350
Short name T543
Test name
Test status
Simulation time 674313488 ps
CPU time 28.22 seconds
Started Dec 27 12:41:31 PM PST 23
Finished Dec 27 12:43:00 PM PST 23
Peak memory 254204 kb
Host smart-69a36d96-cbc9-45e5-bdd5-bdaf36e7aabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15959
02350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1595902350
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3219932056
Short name T670
Test name
Test status
Simulation time 592863005480 ps
CPU time 2512.96 seconds
Started Dec 27 12:41:40 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 287388 kb
Host smart-8893190c-0fa5-49c6-8594-19deb09a9d63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219932056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3219932056
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2315229115
Short name T303
Test name
Test status
Simulation time 10243380681 ps
CPU time 382.25 seconds
Started Dec 27 12:41:30 PM PST 23
Finished Dec 27 12:48:54 PM PST 23
Peak memory 247592 kb
Host smart-c3fc028e-1e60-4dce-a202-95ea1b20372d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315229115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2315229115
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1633495205
Short name T594
Test name
Test status
Simulation time 2964439205 ps
CPU time 44.24 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:43:29 PM PST 23
Peak memory 248660 kb
Host smart-ffcf03fc-7165-49b5-be25-083d096594a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16334
95205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1633495205
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1015850819
Short name T270
Test name
Test status
Simulation time 422264080 ps
CPU time 37.53 seconds
Started Dec 27 12:41:34 PM PST 23
Finished Dec 27 12:43:12 PM PST 23
Peak memory 249576 kb
Host smart-d0701446-86ba-4c7e-a4e5-8a49215dfcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10158
50819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1015850819
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.442523723
Short name T293
Test name
Test status
Simulation time 52928905 ps
CPU time 4.46 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 12:42:48 PM PST 23
Peak memory 238660 kb
Host smart-6006a40f-1c4a-4c92-bd3a-7e44a9789991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44252
3723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.442523723
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.517154350
Short name T514
Test name
Test status
Simulation time 782878055 ps
CPU time 46.15 seconds
Started Dec 27 12:41:29 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 255396 kb
Host smart-9d17399e-5213-4c99-81de-4ee9c8ac2627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51715
4350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.517154350
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2725121616
Short name T250
Test name
Test status
Simulation time 15325817302 ps
CPU time 1415.31 seconds
Started Dec 27 12:41:22 PM PST 23
Finished Dec 27 01:05:59 PM PST 23
Peak memory 289076 kb
Host smart-aa468ec1-1ba7-4eae-b848-17e3acfe66b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725121616 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2725121616
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2516070083
Short name T213
Test name
Test status
Simulation time 111091855 ps
CPU time 3.01 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:42:28 PM PST 23
Peak memory 248740 kb
Host smart-e825160a-946e-4791-a1e4-903f8016aaec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2516070083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2516070083
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2174584500
Short name T440
Test name
Test status
Simulation time 121811466188 ps
CPU time 2293.74 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 01:21:02 PM PST 23
Peak memory 288664 kb
Host smart-d5246ef5-715d-4b8d-b3dd-4b2eea710d96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174584500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2174584500
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.990736879
Short name T511
Test name
Test status
Simulation time 155060311 ps
CPU time 8.53 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 12:42:51 PM PST 23
Peak memory 240320 kb
Host smart-f9836312-fdb7-4a81-8505-dabf36b238e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=990736879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.990736879
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1447148538
Short name T599
Test name
Test status
Simulation time 8483139157 ps
CPU time 138.04 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 12:44:51 PM PST 23
Peak memory 256792 kb
Host smart-b73c6cb5-017f-4852-bf7a-762dab2e877e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14471
48538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1447148538
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2473498118
Short name T697
Test name
Test status
Simulation time 1734220190 ps
CPU time 46.01 seconds
Started Dec 27 12:41:48 PM PST 23
Finished Dec 27 12:43:30 PM PST 23
Peak memory 247904 kb
Host smart-08317ae6-ce63-4f54-acea-1a6b6008af38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24734
98118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2473498118
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1031047319
Short name T7
Test name
Test status
Simulation time 25476741181 ps
CPU time 1063.84 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 01:00:26 PM PST 23
Peak memory 288596 kb
Host smart-507f19f4-cfec-4c5a-80d3-e23290b7d6ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031047319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1031047319
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2079398219
Short name T585
Test name
Test status
Simulation time 3467229967 ps
CPU time 128.16 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 12:44:53 PM PST 23
Peak memory 247564 kb
Host smart-f414bd4f-109e-4f65-9cbb-371c795361c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079398219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2079398219
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1053260544
Short name T536
Test name
Test status
Simulation time 1081371621 ps
CPU time 4.17 seconds
Started Dec 27 12:41:42 PM PST 23
Finished Dec 27 12:42:44 PM PST 23
Peak memory 240348 kb
Host smart-0c764bad-6964-4853-a244-d8b0074d6a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10532
60544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1053260544
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.124257036
Short name T392
Test name
Test status
Simulation time 892690411 ps
CPU time 19.24 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 12:43:01 PM PST 23
Peak memory 247076 kb
Host smart-faae9be1-89a4-48e7-9b51-b9121cefbe49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12425
7036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.124257036
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1834186933
Short name T35
Test name
Test status
Simulation time 495990929 ps
CPU time 15.18 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 12:43:00 PM PST 23
Peak memory 252340 kb
Host smart-efe29e8e-3b32-4278-9540-9bee6ccb06d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18341
86933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1834186933
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.500030372
Short name T583
Test name
Test status
Simulation time 2950885985 ps
CPU time 47.65 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 12:43:21 PM PST 23
Peak memory 248656 kb
Host smart-d3199769-363a-4936-81d1-9dcfa924c8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50003
0372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.500030372
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3642129378
Short name T272
Test name
Test status
Simulation time 341419133439 ps
CPU time 4384.04 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 01:55:40 PM PST 23
Peak memory 304908 kb
Host smart-74159ebe-70e8-41e3-8e40-a5046cceea09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642129378 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3642129378
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4009729413
Short name T220
Test name
Test status
Simulation time 53168710 ps
CPU time 2.42 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 12:42:50 PM PST 23
Peak memory 248784 kb
Host smart-d3c84bcf-c120-4a2d-b77a-9cc3f12c3bfe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4009729413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4009729413
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2940918152
Short name T4
Test name
Test status
Simulation time 63424452605 ps
CPU time 1970.34 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 01:15:31 PM PST 23
Peak memory 284288 kb
Host smart-1bf110bf-a4e8-4acd-829a-e64f9f412e2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940918152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2940918152
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3827467262
Short name T552
Test name
Test status
Simulation time 669079869 ps
CPU time 8.9 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:42:43 PM PST 23
Peak memory 240344 kb
Host smart-eb702766-8cb6-404a-a625-e203ce276bef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3827467262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3827467262
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.478574229
Short name T447
Test name
Test status
Simulation time 1168528065 ps
CPU time 59.51 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:43:45 PM PST 23
Peak memory 248012 kb
Host smart-ed9642f7-6bfc-4994-b700-fd2c3ee0022e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47857
4229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.478574229
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.713793140
Short name T696
Test name
Test status
Simulation time 1240024375 ps
CPU time 64.88 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 12:43:46 PM PST 23
Peak memory 255028 kb
Host smart-f0fb6659-7796-4416-b855-8f360ea33f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71379
3140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.713793140
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2462726602
Short name T609
Test name
Test status
Simulation time 11837642059 ps
CPU time 998.51 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 284124 kb
Host smart-d59c8907-5978-4db2-8606-0f3ce7183f00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462726602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2462726602
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.35618170
Short name T387
Test name
Test status
Simulation time 26899883558 ps
CPU time 1378.52 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 01:05:44 PM PST 23
Peak memory 266132 kb
Host smart-c6c381d8-e1d6-461c-92cf-9b88b87aae88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35618170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.35618170
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1353482422
Short name T483
Test name
Test status
Simulation time 2847309028 ps
CPU time 32.98 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:43:07 PM PST 23
Peak memory 248652 kb
Host smart-b657433f-636d-4eaf-b9c2-8d9683065760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13534
82422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1353482422
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3596135538
Short name T498
Test name
Test status
Simulation time 400119355 ps
CPU time 5.79 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 12:42:47 PM PST 23
Peak memory 251440 kb
Host smart-61b352a1-3c4e-47dd-bc85-1a9585652edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
35538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3596135538
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3473661664
Short name T277
Test name
Test status
Simulation time 380337863 ps
CPU time 11.09 seconds
Started Dec 27 12:41:35 PM PST 23
Finished Dec 27 12:42:46 PM PST 23
Peak memory 248620 kb
Host smart-89b04739-87cc-4a38-a9d0-9f839b1aef1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34736
61664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3473661664
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1607097167
Short name T402
Test name
Test status
Simulation time 179258254 ps
CPU time 14.63 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 248568 kb
Host smart-f954034a-5c1a-4993-902a-bb41781d286f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16070
97167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1607097167
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3968326890
Short name T268
Test name
Test status
Simulation time 17858889410 ps
CPU time 1436.66 seconds
Started Dec 27 12:41:41 PM PST 23
Finished Dec 27 01:06:36 PM PST 23
Peak memory 288928 kb
Host smart-5c78441a-510a-4be6-91c1-c20f3f57658b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968326890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3968326890
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3289924198
Short name T211
Test name
Test status
Simulation time 45798873 ps
CPU time 3.47 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:17 PM PST 23
Peak memory 248772 kb
Host smart-6c9ccdf0-7395-4f6f-b194-0541790c41a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3289924198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3289924198
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.996666536
Short name T234
Test name
Test status
Simulation time 45711278904 ps
CPU time 2638.54 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 01:26:11 PM PST 23
Peak memory 281396 kb
Host smart-451afca4-5021-4613-85df-748e40d155da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996666536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.996666536
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3014439356
Short name T535
Test name
Test status
Simulation time 2385418178 ps
CPU time 48.99 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:54 PM PST 23
Peak memory 240432 kb
Host smart-3b882c7a-4450-497f-af4c-f9c48e905341
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3014439356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3014439356
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1829404093
Short name T705
Test name
Test status
Simulation time 830655732 ps
CPU time 61.73 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 248048 kb
Host smart-f7550767-73ec-4f97-80af-5a2d0837a66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
04093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1829404093
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2119959217
Short name T77
Test name
Test status
Simulation time 1831112956 ps
CPU time 8.98 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 254300 kb
Host smart-8cf66a4c-a6de-48ff-9f84-9a9f53b5ec34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21199
59217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2119959217
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.40538469
Short name T489
Test name
Test status
Simulation time 10818630229 ps
CPU time 1044.55 seconds
Started Dec 27 12:41:03 PM PST 23
Finished Dec 27 12:59:32 PM PST 23
Peak memory 272476 kb
Host smart-cc4c2c35-9a1a-48dd-9d8b-0998b124bb39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40538469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.40538469
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2655410144
Short name T382
Test name
Test status
Simulation time 48650680875 ps
CPU time 2821.27 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 01:29:18 PM PST 23
Peak memory 286916 kb
Host smart-708c7079-64fc-4558-847c-39f64d6ce7ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655410144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2655410144
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.164542721
Short name T304
Test name
Test status
Simulation time 7673457632 ps
CPU time 272.37 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 12:46:27 PM PST 23
Peak memory 247476 kb
Host smart-d4582e3d-9eee-4683-8669-8743ef79bc83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164542721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.164542721
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2441622055
Short name T570
Test name
Test status
Simulation time 360623370 ps
CPU time 27.03 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 12:42:48 PM PST 23
Peak memory 248516 kb
Host smart-d92df702-2e3a-401a-833b-4adaecdd76af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416
22055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2441622055
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1620775444
Short name T713
Test name
Test status
Simulation time 435209900 ps
CPU time 31.12 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:42:45 PM PST 23
Peak memory 255068 kb
Host smart-71e990d8-bdc3-4da5-b649-c5a86abd8478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16207
75444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1620775444
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3901865878
Short name T11
Test name
Test status
Simulation time 1589749951 ps
CPU time 23.67 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:37 PM PST 23
Peak memory 269400 kb
Host smart-3f0aac93-ce1f-4682-8424-f574ea1ea458
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3901865878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3901865878
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1511532346
Short name T106
Test name
Test status
Simulation time 628947388 ps
CPU time 36.75 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:59 PM PST 23
Peak memory 255048 kb
Host smart-0a2de60c-7a90-49ed-b6ce-8b5ce450df6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15115
32346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1511532346
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3479314476
Short name T576
Test name
Test status
Simulation time 1536000372 ps
CPU time 24.28 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:45 PM PST 23
Peak memory 255104 kb
Host smart-e07d00b7-5973-4083-bf50-4adbac0330a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
14476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3479314476
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1697893238
Short name T464
Test name
Test status
Simulation time 35124762127 ps
CPU time 1671.74 seconds
Started Dec 27 12:41:25 PM PST 23
Finished Dec 27 01:10:18 PM PST 23
Peak memory 303224 kb
Host smart-4cc4a458-c60e-4bbf-8b17-f34235b2b470
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697893238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1697893238
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2577055137
Short name T256
Test name
Test status
Simulation time 20295477469 ps
CPU time 1294.6 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 01:03:47 PM PST 23
Peak memory 272468 kb
Host smart-d3ea34e5-299a-48e6-8807-9f5c1ac0b687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577055137 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2577055137
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3447712334
Short name T380
Test name
Test status
Simulation time 70287109261 ps
CPU time 1171.67 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 01:02:15 PM PST 23
Peak memory 265032 kb
Host smart-b07c3e7a-c9ee-4933-9b15-fba44a8f764b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447712334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3447712334
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1079825781
Short name T59
Test name
Test status
Simulation time 11607984350 ps
CPU time 314.43 seconds
Started Dec 27 12:41:41 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 256440 kb
Host smart-21a3f2a0-58c4-479b-88ad-e5c1e39a118a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10798
25781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1079825781
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.547675926
Short name T722
Test name
Test status
Simulation time 1713342520 ps
CPU time 29.18 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 12:43:04 PM PST 23
Peak memory 255268 kb
Host smart-5ec3c585-d368-4cc9-ba3a-d8fa2c811d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54767
5926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.547675926
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.493164846
Short name T636
Test name
Test status
Simulation time 22988704391 ps
CPU time 829.86 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:56:37 PM PST 23
Peak memory 272628 kb
Host smart-9be267c5-e947-4307-b8fc-15b39d11cdb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493164846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.493164846
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2222497810
Short name T617
Test name
Test status
Simulation time 88292446982 ps
CPU time 2205.44 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 01:19:31 PM PST 23
Peak memory 289512 kb
Host smart-fa038442-9a51-43d7-9277-ecb3622b9434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222497810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2222497810
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1373020020
Short name T302
Test name
Test status
Simulation time 16912010649 ps
CPU time 339.91 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:48:25 PM PST 23
Peak memory 247556 kb
Host smart-bc7dfb59-f5c9-474b-b5ef-a791b67e0db4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373020020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1373020020
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3857462229
Short name T539
Test name
Test status
Simulation time 4363290902 ps
CPU time 60.57 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:43:44 PM PST 23
Peak memory 255340 kb
Host smart-92679ad6-ab9a-4ebe-a144-275c370d8c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38574
62229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3857462229
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1447974807
Short name T632
Test name
Test status
Simulation time 778840241 ps
CPU time 13.89 seconds
Started Dec 27 12:41:40 PM PST 23
Finished Dec 27 12:42:53 PM PST 23
Peak memory 246872 kb
Host smart-4300323b-f524-4d9c-873a-cd32a53331ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14479
74807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1447974807
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3372963409
Short name T685
Test name
Test status
Simulation time 513369167 ps
CPU time 22.9 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 248580 kb
Host smart-950cdd61-a878-4d7f-838b-a969c26194ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33729
63409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3372963409
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.857833169
Short name T94
Test name
Test status
Simulation time 50823346 ps
CPU time 6.42 seconds
Started Dec 27 12:41:30 PM PST 23
Finished Dec 27 12:42:38 PM PST 23
Peak memory 256760 kb
Host smart-73ddd2b4-d2a8-439f-b796-ca0ee6167f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85783
3169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.857833169
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.208201639
Short name T631
Test name
Test status
Simulation time 84686631576 ps
CPU time 2904.43 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 01:31:02 PM PST 23
Peak memory 288832 kb
Host smart-a580411c-1d1d-483a-b95f-fa9decf374c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208201639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.208201639
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.1012880445
Short name T121
Test name
Test status
Simulation time 43520942291 ps
CPU time 1372.85 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 01:05:29 PM PST 23
Peak memory 285316 kb
Host smart-e9ca8c20-3ebe-47ba-8af9-b277cf80a5bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012880445 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.1012880445
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.733894236
Short name T560
Test name
Test status
Simulation time 83039594751 ps
CPU time 1367.05 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 281388 kb
Host smart-d6a2abf6-1b8f-480e-b839-e2380c6a6264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733894236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.733894236
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.330091585
Short name T589
Test name
Test status
Simulation time 1790671670 ps
CPU time 40.39 seconds
Started Dec 27 12:41:37 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 248628 kb
Host smart-d3f6121d-a3f3-468c-9d58-dc4a25b1e576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33009
1585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.330091585
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.31629296
Short name T429
Test name
Test status
Simulation time 611782523 ps
CPU time 36.01 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:43:01 PM PST 23
Peak memory 254916 kb
Host smart-d20af82f-7309-4cda-a130-e21ab11d9a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31629
296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.31629296
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3937206320
Short name T611
Test name
Test status
Simulation time 166938284041 ps
CPU time 1061.22 seconds
Started Dec 27 12:41:41 PM PST 23
Finished Dec 27 01:00:20 PM PST 23
Peak memory 264960 kb
Host smart-caa48d02-77ef-4c33-b228-0b6176bff468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937206320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3937206320
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4253060580
Short name T677
Test name
Test status
Simulation time 34767584410 ps
CPU time 1847.39 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 01:13:20 PM PST 23
Peak memory 272056 kb
Host smart-a4ce20f9-9e5c-4844-b89d-ac01447df732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253060580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4253060580
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1452476804
Short name T639
Test name
Test status
Simulation time 142061027 ps
CPU time 13.48 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:42:57 PM PST 23
Peak memory 254448 kb
Host smart-64185f9d-0204-45df-b0b7-d6bf371bbb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
76804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1452476804
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.874816758
Short name T652
Test name
Test status
Simulation time 592667123 ps
CPU time 14.97 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 12:42:52 PM PST 23
Peak memory 253948 kb
Host smart-a7beea3b-952a-4245-95d9-aa130450c231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87481
6758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.874816758
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1991535046
Short name T279
Test name
Test status
Simulation time 313403741 ps
CPU time 11.18 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:42:55 PM PST 23
Peak memory 251192 kb
Host smart-3ba39f52-84d7-4ab5-bf14-eee050e44653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19915
35046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1991535046
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1562597125
Short name T619
Test name
Test status
Simulation time 343498153 ps
CPU time 30.02 seconds
Started Dec 27 12:41:53 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 248604 kb
Host smart-ad9f4ba1-9509-4d5b-8f44-4c6f3fe4241d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
97125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1562597125
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4128231046
Short name T701
Test name
Test status
Simulation time 27305722749 ps
CPU time 2349.73 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 01:21:55 PM PST 23
Peak memory 287528 kb
Host smart-0ab2cef8-7aa1-4378-ab88-b50661e2cfc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128231046 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4128231046
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2337494127
Short name T445
Test name
Test status
Simulation time 19112922618 ps
CPU time 1343.83 seconds
Started Dec 27 12:41:40 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 266040 kb
Host smart-4912f6d6-d3f1-4503-8085-75a14bd0186b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337494127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2337494127
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2143509812
Short name T642
Test name
Test status
Simulation time 5741289574 ps
CPU time 56.84 seconds
Started Dec 27 12:41:39 PM PST 23
Finished Dec 27 12:43:34 PM PST 23
Peak memory 248056 kb
Host smart-36c30367-3268-44fa-a6fc-903b6c44f9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21435
09812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2143509812
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3890885941
Short name T637
Test name
Test status
Simulation time 1585890074 ps
CPU time 15.41 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 253696 kb
Host smart-d2ce6179-2adc-44e3-ab73-bb69486f59bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38908
85941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3890885941
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3624223879
Short name T124
Test name
Test status
Simulation time 56597288399 ps
CPU time 1589.58 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 01:09:18 PM PST 23
Peak memory 272580 kb
Host smart-09926a64-b670-4248-aa2e-2be8f10eea8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624223879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3624223879
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1379725258
Short name T316
Test name
Test status
Simulation time 16256880002 ps
CPU time 168.55 seconds
Started Dec 27 12:41:34 PM PST 23
Finished Dec 27 12:45:23 PM PST 23
Peak memory 247156 kb
Host smart-ddeaa137-b82c-4a97-84b3-af78ed7b21d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379725258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1379725258
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1770476909
Short name T517
Test name
Test status
Simulation time 823814409 ps
CPU time 16.61 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:43:00 PM PST 23
Peak memory 248588 kb
Host smart-97896afe-352a-440a-9493-5cb67eb41a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17704
76909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1770476909
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2944320312
Short name T518
Test name
Test status
Simulation time 309582250 ps
CPU time 9.7 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 255340 kb
Host smart-b8e278f3-d67a-4093-9fd1-9f5bf272b8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
20312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2944320312
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3919519017
Short name T567
Test name
Test status
Simulation time 131427739 ps
CPU time 9.38 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:42:53 PM PST 23
Peak memory 253476 kb
Host smart-a6c4f041-5db4-4d92-859b-24e18f49a4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
19017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3919519017
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1236718321
Short name T18
Test name
Test status
Simulation time 376354785 ps
CPU time 19.64 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 248488 kb
Host smart-00ec078e-0905-47e7-8768-35dc98b9dac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12367
18321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1236718321
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.469791324
Short name T297
Test name
Test status
Simulation time 373582700784 ps
CPU time 2362.61 seconds
Started Dec 27 12:41:39 PM PST 23
Finished Dec 27 01:22:00 PM PST 23
Peak memory 289244 kb
Host smart-45686d26-2108-4701-8349-60ea0eda8b47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469791324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.469791324
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.727849883
Short name T659
Test name
Test status
Simulation time 116136547146 ps
CPU time 3599.23 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 01:42:43 PM PST 23
Peak memory 304584 kb
Host smart-61084469-0de2-4633-a470-c64847f3de0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727849883 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.727849883
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2300103007
Short name T113
Test name
Test status
Simulation time 154916007661 ps
CPU time 2365.81 seconds
Started Dec 27 12:41:56 PM PST 23
Finished Dec 27 01:22:15 PM PST 23
Peak memory 289424 kb
Host smart-36a01dc1-0f27-4cb1-940f-f99d9b2f725b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300103007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2300103007
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.569387219
Short name T258
Test name
Test status
Simulation time 3384141625 ps
CPU time 141.64 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:45:07 PM PST 23
Peak memory 256284 kb
Host smart-f6bbcf06-ec7d-41b9-be99-4edc3206471b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56938
7219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.569387219
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.378316451
Short name T372
Test name
Test status
Simulation time 861862145 ps
CPU time 51.59 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:43:43 PM PST 23
Peak memory 255240 kb
Host smart-f3322871-b7f3-4828-a7c1-73aef584c1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
6451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.378316451
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2271676229
Short name T349
Test name
Test status
Simulation time 43814910877 ps
CPU time 696.74 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 12:54:14 PM PST 23
Peak memory 264980 kb
Host smart-9bb5227e-d0cd-4119-b1a3-58b1c38d2ce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271676229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2271676229
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2265035103
Short name T723
Test name
Test status
Simulation time 192936754371 ps
CPU time 2819.46 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 01:29:43 PM PST 23
Peak memory 285156 kb
Host smart-c659401c-0326-4820-81b6-55c88749e578
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265035103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2265035103
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2395997136
Short name T434
Test name
Test status
Simulation time 210067574 ps
CPU time 16.65 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 12:42:52 PM PST 23
Peak memory 248596 kb
Host smart-33849d8c-cf2e-4139-a96e-acb45509ebad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
97136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2395997136
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.706370613
Short name T54
Test name
Test status
Simulation time 836880887 ps
CPU time 46.85 seconds
Started Dec 27 12:42:01 PM PST 23
Finished Dec 27 12:43:39 PM PST 23
Peak memory 254784 kb
Host smart-f192a82d-ec15-4278-84ba-dc6a563a52c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70637
0613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.706370613
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.563427893
Short name T95
Test name
Test status
Simulation time 1139089433 ps
CPU time 29.58 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 12:43:11 PM PST 23
Peak memory 256200 kb
Host smart-5589d9f9-48c4-43f9-a502-9a42e91a4e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56342
7893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.563427893
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1422469006
Short name T591
Test name
Test status
Simulation time 1816381459 ps
CPU time 29.84 seconds
Started Dec 27 12:41:41 PM PST 23
Finished Dec 27 12:43:09 PM PST 23
Peak memory 248528 kb
Host smart-8710a1f3-c9b1-4d93-acf1-81735e3d435c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
69006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1422469006
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3500634974
Short name T205
Test name
Test status
Simulation time 36729364520 ps
CPU time 1921.02 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 01:14:43 PM PST 23
Peak memory 302688 kb
Host smart-e95cbbac-4115-4cae-bd75-42b8951d5a37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500634974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3500634974
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1984149618
Short name T497
Test name
Test status
Simulation time 28963280068 ps
CPU time 1920.47 seconds
Started Dec 27 12:41:42 PM PST 23
Finished Dec 27 01:14:41 PM PST 23
Peak memory 272472 kb
Host smart-8a387da1-cc0d-421e-97a8-8d642690c622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984149618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1984149618
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1796075699
Short name T661
Test name
Test status
Simulation time 5087799001 ps
CPU time 83.74 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:44:07 PM PST 23
Peak memory 256264 kb
Host smart-ca027025-dad9-4f4b-976a-80aed320ba2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
75699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1796075699
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1281470912
Short name T602
Test name
Test status
Simulation time 162674766 ps
CPU time 7.09 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:42:53 PM PST 23
Peak memory 252576 kb
Host smart-cf91c791-8376-4d49-a7f1-c09d647a1d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12814
70912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1281470912
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2007175790
Short name T341
Test name
Test status
Simulation time 201766367375 ps
CPU time 1143.64 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 01:01:49 PM PST 23
Peak memory 272172 kb
Host smart-b1b3f2bf-8add-482d-b1df-669cdb235156
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007175790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2007175790
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2911325293
Short name T86
Test name
Test status
Simulation time 30940754969 ps
CPU time 1043.15 seconds
Started Dec 27 12:41:56 PM PST 23
Finished Dec 27 01:00:12 PM PST 23
Peak memory 270816 kb
Host smart-ce0c9786-38de-4346-b121-b75763cfb203
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911325293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2911325293
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.295061352
Short name T327
Test name
Test status
Simulation time 16276958171 ps
CPU time 137.97 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 12:44:59 PM PST 23
Peak memory 247412 kb
Host smart-11380cfa-6b37-4453-978a-c43e8a2c19a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295061352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.295061352
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1874697430
Short name T595
Test name
Test status
Simulation time 1516900240 ps
CPU time 24.26 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:23 PM PST 23
Peak memory 248608 kb
Host smart-8e7e8300-000f-4094-a72d-0c876b85477c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18746
97430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1874697430
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2622563602
Short name T522
Test name
Test status
Simulation time 2245282681 ps
CPU time 32.78 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:43:18 PM PST 23
Peak memory 247408 kb
Host smart-a09109f6-160b-4b1a-9884-57086ac546b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
63602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2622563602
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.45482705
Short name T665
Test name
Test status
Simulation time 1456564244 ps
CPU time 36.09 seconds
Started Dec 27 12:42:06 PM PST 23
Finished Dec 27 12:43:31 PM PST 23
Peak memory 248580 kb
Host smart-af6412c8-88d3-478a-89fe-419018c3f67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45482
705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.45482705
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.460266394
Short name T577
Test name
Test status
Simulation time 43408381 ps
CPU time 3.94 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 12:42:57 PM PST 23
Peak memory 240308 kb
Host smart-987aa882-e3d1-45d3-aefa-ff01d6c465dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46026
6394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.460266394
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3643769962
Short name T523
Test name
Test status
Simulation time 2915009571 ps
CPU time 151 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:45:19 PM PST 23
Peak memory 256804 kb
Host smart-ea30adb0-d112-4e94-840b-685dba2eb555
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643769962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3643769962
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.947333045
Short name T117
Test name
Test status
Simulation time 58958221785 ps
CPU time 3599.77 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 01:42:46 PM PST 23
Peak memory 289184 kb
Host smart-d2a16cf7-9311-4583-b684-16e8d7e747eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947333045 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.947333045
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1971355579
Short name T64
Test name
Test status
Simulation time 50039585126 ps
CPU time 2925.34 seconds
Started Dec 27 12:41:57 PM PST 23
Finished Dec 27 01:31:35 PM PST 23
Peak memory 289600 kb
Host smart-5dace2ac-4931-43fd-9e66-eda0d910ee7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971355579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1971355579
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3954323095
Short name T724
Test name
Test status
Simulation time 11990481672 ps
CPU time 164.67 seconds
Started Dec 27 12:41:41 PM PST 23
Finished Dec 27 12:45:24 PM PST 23
Peak memory 256308 kb
Host smart-8c57d0bc-f9d3-4efb-9f12-3345e4f58ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39543
23095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3954323095
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3025386196
Short name T282
Test name
Test status
Simulation time 339010886 ps
CPU time 28.22 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:43:16 PM PST 23
Peak memory 254244 kb
Host smart-04a786a1-e557-4c4b-a1d2-5e3e47e428bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30253
86196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3025386196
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1894698981
Short name T618
Test name
Test status
Simulation time 25482683228 ps
CPU time 561.6 seconds
Started Dec 27 12:42:01 PM PST 23
Finished Dec 27 12:52:13 PM PST 23
Peak memory 272772 kb
Host smart-1f6dba35-3690-4d32-b46e-0a558639451e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894698981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1894698981
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.98609321
Short name T383
Test name
Test status
Simulation time 38972903272 ps
CPU time 1187.1 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 01:02:32 PM PST 23
Peak memory 283596 kb
Host smart-e0f5f8f7-61b6-4db6-adad-24d7aa47ea72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98609321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.98609321
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3831329841
Short name T623
Test name
Test status
Simulation time 13663638337 ps
CPU time 119.2 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:44:49 PM PST 23
Peak memory 247172 kb
Host smart-9d0f2c35-22f8-4fa3-8006-a237d721371e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831329841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3831329841
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.119063996
Short name T413
Test name
Test status
Simulation time 16857292533 ps
CPU time 54.03 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:43:44 PM PST 23
Peak memory 248620 kb
Host smart-79963b19-5545-490b-93ff-427aaa56de4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11906
3996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.119063996
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3066962742
Short name T494
Test name
Test status
Simulation time 402758515 ps
CPU time 29.63 seconds
Started Dec 27 12:41:40 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 247104 kb
Host smart-c1d69e72-8311-4668-9324-e1630095ab91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30669
62742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3066962742
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2440221256
Short name T683
Test name
Test status
Simulation time 616479999 ps
CPU time 35.61 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 12:43:19 PM PST 23
Peak memory 254584 kb
Host smart-dac02f9b-38a5-4caf-bc51-e105544d6c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
21256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2440221256
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.966529835
Short name T501
Test name
Test status
Simulation time 3590989546 ps
CPU time 47.47 seconds
Started Dec 27 12:41:39 PM PST 23
Finished Dec 27 12:43:26 PM PST 23
Peak memory 248524 kb
Host smart-abd91b0a-b00c-4f22-9dab-d0755f169636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96652
9835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.966529835
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1879383380
Short name T82
Test name
Test status
Simulation time 4075654872 ps
CPU time 115.32 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 12:44:28 PM PST 23
Peak memory 256888 kb
Host smart-16e6fcd6-652c-489a-9366-687e2b7b8b9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879383380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1879383380
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3853302625
Short name T126
Test name
Test status
Simulation time 84878255406 ps
CPU time 2045.04 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 01:16:49 PM PST 23
Peak memory 297368 kb
Host smart-01cba2f4-725e-4795-b7e3-1cab50103c20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853302625 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3853302625
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.481335225
Short name T469
Test name
Test status
Simulation time 137045668431 ps
CPU time 1052.55 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 01:00:28 PM PST 23
Peak memory 283152 kb
Host smart-e62e606e-c976-4a2b-84e6-2d39bd10429f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481335225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.481335225
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2937119501
Short name T452
Test name
Test status
Simulation time 4506801049 ps
CPU time 255.89 seconds
Started Dec 27 12:41:48 PM PST 23
Finished Dec 27 12:47:00 PM PST 23
Peak memory 256740 kb
Host smart-0ba71733-630c-443e-843e-b60bb22451f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
19501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2937119501
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.695392116
Short name T412
Test name
Test status
Simulation time 323207640 ps
CPU time 6.22 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:42:50 PM PST 23
Peak memory 248760 kb
Host smart-1b40ff7b-5856-4541-ba88-711fe8ea9331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69539
2116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.695392116
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3677689085
Short name T326
Test name
Test status
Simulation time 24065063326 ps
CPU time 1280 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 01:04:09 PM PST 23
Peak memory 281480 kb
Host smart-73914c84-7076-41bf-8593-dcb6f5fe2d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677689085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3677689085
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.315065439
Short name T427
Test name
Test status
Simulation time 45139703266 ps
CPU time 2618.8 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 01:26:32 PM PST 23
Peak memory 284092 kb
Host smart-5ee069d9-91db-49ad-835e-63ee9901f392
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315065439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.315065439
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.599600766
Short name T480
Test name
Test status
Simulation time 862056688 ps
CPU time 23.69 seconds
Started Dec 27 12:41:59 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 256768 kb
Host smart-6a8d671c-2b97-47d5-8eaf-d26fefbcfcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59960
0766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.599600766
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1503657947
Short name T57
Test name
Test status
Simulation time 342224525 ps
CPU time 15.03 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 12:42:57 PM PST 23
Peak memory 254752 kb
Host smart-77bcaf90-bdd9-46d2-b24c-ffc1c2ae591a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15036
57947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1503657947
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4013569507
Short name T448
Test name
Test status
Simulation time 145387869 ps
CPU time 9.33 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 12:42:52 PM PST 23
Peak memory 248592 kb
Host smart-b8bb3a63-2a38-4a27-9734-9f04fe064505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40135
69507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4013569507
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3203294263
Short name T508
Test name
Test status
Simulation time 112899649213 ps
CPU time 1543.5 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 01:08:40 PM PST 23
Peak memory 289332 kb
Host smart-9b76b3dc-336b-47e5-883b-030d7be76493
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203294263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3203294263
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1473122733
Short name T638
Test name
Test status
Simulation time 3958706558 ps
CPU time 72 seconds
Started Dec 27 12:41:57 PM PST 23
Finished Dec 27 12:44:01 PM PST 23
Peak memory 249644 kb
Host smart-7282c0ca-0ace-4646-bf98-3dc3c100eb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14731
22733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1473122733
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1901453783
Short name T538
Test name
Test status
Simulation time 130073607 ps
CPU time 12.31 seconds
Started Dec 27 12:41:40 PM PST 23
Finished Dec 27 12:42:51 PM PST 23
Peak memory 254928 kb
Host smart-5a5d1bb0-6554-410b-a0d6-9ede46515328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19014
53783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1901453783
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.130522591
Short name T299
Test name
Test status
Simulation time 55663161308 ps
CPU time 1010.49 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:59:41 PM PST 23
Peak memory 272064 kb
Host smart-0db18944-bc7c-4a04-b2c2-acc186dc004a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130522591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.130522591
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3693574128
Short name T455
Test name
Test status
Simulation time 32925343305 ps
CPU time 838.16 seconds
Started Dec 27 12:41:59 PM PST 23
Finished Dec 27 12:56:49 PM PST 23
Peak memory 281460 kb
Host smart-543f52d7-3388-490d-a185-7660f44cf473
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693574128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3693574128
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2096735243
Short name T311
Test name
Test status
Simulation time 31339470746 ps
CPU time 313.93 seconds
Started Dec 27 12:41:45 PM PST 23
Finished Dec 27 12:47:56 PM PST 23
Peak memory 247572 kb
Host smart-e14b4fb9-474d-4954-858d-8c6697e0def2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096735243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2096735243
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3644255226
Short name T390
Test name
Test status
Simulation time 722100678 ps
CPU time 40.23 seconds
Started Dec 27 12:41:38 PM PST 23
Finished Dec 27 12:43:18 PM PST 23
Peak memory 256832 kb
Host smart-dcdfe52d-574f-4bb0-8967-5f0136ccb257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36442
55226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3644255226
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4007506725
Short name T646
Test name
Test status
Simulation time 959486489 ps
CPU time 54.35 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:43:38 PM PST 23
Peak memory 255044 kb
Host smart-f03379b0-9061-4afd-acdd-3ee58ca66274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40075
06725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4007506725
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.4247722504
Short name T230
Test name
Test status
Simulation time 639321487 ps
CPU time 37.98 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:43:12 PM PST 23
Peak memory 256772 kb
Host smart-bda936bb-dbbe-493b-a846-0ce6c7f25d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
22504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.4247722504
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3825748188
Short name T102
Test name
Test status
Simulation time 14133210236 ps
CPU time 715.9 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 12:54:55 PM PST 23
Peak memory 264932 kb
Host smart-a642bd45-a32e-4cd8-8492-34c6b3bc54d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825748188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3825748188
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2511183492
Short name T40
Test name
Test status
Simulation time 289236613754 ps
CPU time 1459.18 seconds
Started Dec 27 12:41:53 PM PST 23
Finished Dec 27 01:07:06 PM PST 23
Peak memory 288964 kb
Host smart-09e64cf7-1939-4f49-9fab-e94c18b39868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511183492 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2511183492
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.290395031
Short name T620
Test name
Test status
Simulation time 10591752397 ps
CPU time 1275.36 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 01:04:00 PM PST 23
Peak memory 287404 kb
Host smart-c95efad3-225c-4312-8a63-98766f1e7220
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290395031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.290395031
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1386978700
Short name T58
Test name
Test status
Simulation time 4283384410 ps
CPU time 112.4 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 12:44:34 PM PST 23
Peak memory 256152 kb
Host smart-155eae73-7212-4f3c-a9bf-96e29ecb5db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13869
78700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1386978700
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3320820538
Short name T547
Test name
Test status
Simulation time 384280069 ps
CPU time 16.8 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 254904 kb
Host smart-afdfa965-4a49-4bbd-a483-06a98d6c67f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33208
20538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3320820538
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1870040820
Short name T352
Test name
Test status
Simulation time 22963567145 ps
CPU time 1430.75 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 01:06:32 PM PST 23
Peak memory 272384 kb
Host smart-800d5192-5a97-48b5-bb2c-ca4a603d5942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870040820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1870040820
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3819178667
Short name T478
Test name
Test status
Simulation time 56622440095 ps
CPU time 1279.42 seconds
Started Dec 27 12:41:52 PM PST 23
Finished Dec 27 01:04:06 PM PST 23
Peak memory 288596 kb
Host smart-00d6f0d0-1322-41d5-8b7b-d4aaf0e4a30d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819178667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3819178667
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3548913501
Short name T332
Test name
Test status
Simulation time 27483496496 ps
CPU time 334.21 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 248648 kb
Host smart-4a33f6c8-4320-458a-8115-528378f6f532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548913501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3548913501
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2012214021
Short name T731
Test name
Test status
Simulation time 108463622 ps
CPU time 6.79 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:04 PM PST 23
Peak memory 248516 kb
Host smart-e61ea7f5-1b24-4091-b984-645cb782427a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20122
14021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2012214021
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3176123629
Short name T485
Test name
Test status
Simulation time 1434107967 ps
CPU time 29.92 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 12:43:18 PM PST 23
Peak memory 254304 kb
Host smart-5167cca6-d8a4-44a4-9c51-5434a74ac346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
23629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3176123629
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3438605113
Short name T644
Test name
Test status
Simulation time 747449376 ps
CPU time 47.5 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:43:36 PM PST 23
Peak memory 256320 kb
Host smart-167ed187-f5ee-4336-a7f6-0f807636801b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34386
05113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3438605113
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.994014548
Short name T505
Test name
Test status
Simulation time 2663479800 ps
CPU time 71.62 seconds
Started Dec 27 12:41:40 PM PST 23
Finished Dec 27 12:43:50 PM PST 23
Peak memory 248696 kb
Host smart-decd134c-6ef1-40e1-a2b9-0de1904ac279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99401
4548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.994014548
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1782450547
Short name T286
Test name
Test status
Simulation time 9097179768 ps
CPU time 512.41 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 12:51:17 PM PST 23
Peak memory 256804 kb
Host smart-e6f47cc3-a0ad-4075-9e6f-c4376ab362dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782450547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1782450547
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3806396195
Short name T726
Test name
Test status
Simulation time 206337270650 ps
CPU time 5248.24 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 02:10:22 PM PST 23
Peak memory 322448 kb
Host smart-019ae0ac-e15e-4724-bf2d-e15e4dbd703c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806396195 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3806396195
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2596170080
Short name T495
Test name
Test status
Simulation time 50236261839 ps
CPU time 1498.09 seconds
Started Dec 27 12:41:53 PM PST 23
Finished Dec 27 01:07:45 PM PST 23
Peak memory 289404 kb
Host smart-f0c95cd2-8311-4839-98c4-a83c939ef7b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596170080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2596170080
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1493566062
Short name T727
Test name
Test status
Simulation time 678792175 ps
CPU time 21.88 seconds
Started Dec 27 12:41:48 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 248872 kb
Host smart-278a5f0b-18bf-41a4-91fb-651fee10fcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14935
66062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1493566062
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3102123795
Short name T712
Test name
Test status
Simulation time 1358451027 ps
CPU time 28.98 seconds
Started Dec 27 12:41:43 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 254896 kb
Host smart-91632bfd-4fc3-4aba-a266-611b82afea68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31021
23795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3102123795
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2705394508
Short name T626
Test name
Test status
Simulation time 294715899491 ps
CPU time 1575.67 seconds
Started Dec 27 12:41:53 PM PST 23
Finished Dec 27 01:09:03 PM PST 23
Peak memory 272780 kb
Host smart-ab6862d7-dfa6-426f-9dda-12ccebfee80b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705394508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2705394508
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.736477010
Short name T112
Test name
Test status
Simulation time 69236137939 ps
CPU time 1532.43 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 01:08:15 PM PST 23
Peak memory 288340 kb
Host smart-cf30b63f-2160-4dc4-a8e4-d0f1dd6ff48b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736477010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.736477010
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.512849290
Short name T310
Test name
Test status
Simulation time 10335543184 ps
CPU time 391.35 seconds
Started Dec 27 12:41:52 PM PST 23
Finished Dec 27 12:49:18 PM PST 23
Peak memory 248536 kb
Host smart-f6ceb4e0-46c7-4c54-a493-e568124ed485
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512849290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.512849290
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2245422743
Short name T563
Test name
Test status
Simulation time 1949983521 ps
CPU time 53.87 seconds
Started Dec 27 12:41:47 PM PST 23
Finished Dec 27 12:43:37 PM PST 23
Peak memory 255072 kb
Host smart-0c8fc47c-7bd2-49ef-8176-b1df39324ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22454
22743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2245422743
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.447322986
Short name T640
Test name
Test status
Simulation time 2044422896 ps
CPU time 18.25 seconds
Started Dec 27 12:41:53 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 254988 kb
Host smart-9671a52c-58e4-4ed5-93d4-4bd4b09099ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44732
2986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.447322986
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3428646760
Short name T56
Test name
Test status
Simulation time 705273694 ps
CPU time 21.08 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:43:12 PM PST 23
Peak memory 248184 kb
Host smart-c0a3704d-2589-497c-8897-89c3ac57f957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34286
46760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3428646760
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1492834108
Short name T721
Test name
Test status
Simulation time 1349368796 ps
CPU time 17.42 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 248552 kb
Host smart-ce91763a-321c-48a6-bede-715d7a0d7e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14928
34108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1492834108
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.18716527
Short name T593
Test name
Test status
Simulation time 14688941008 ps
CPU time 173.22 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 12:45:41 PM PST 23
Peak memory 256888 kb
Host smart-5b3c7657-2c94-4483-81fe-aae317daaaef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_hand
ler_stress_all.18716527
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.124085072
Short name T290
Test name
Test status
Simulation time 332327021625 ps
CPU time 3851.88 seconds
Started Dec 27 12:42:01 PM PST 23
Finished Dec 27 01:47:04 PM PST 23
Peak memory 305156 kb
Host smart-81785cf0-7f12-46dc-b95f-851bed87922b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124085072 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.124085072
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3626023919
Short name T222
Test name
Test status
Simulation time 203650870 ps
CPU time 3.83 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:16 PM PST 23
Peak memory 248708 kb
Host smart-19948767-d228-4b64-a685-e65db16aa9f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3626023919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3626023919
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4188409020
Short name T544
Test name
Test status
Simulation time 136176282285 ps
CPU time 1994.04 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 01:15:17 PM PST 23
Peak memory 289432 kb
Host smart-905e37cf-5701-4b3a-af87-b7065c900fe3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188409020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4188409020
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1992676132
Short name T50
Test name
Test status
Simulation time 1957820791 ps
CPU time 9.25 seconds
Started Dec 27 12:41:22 PM PST 23
Finished Dec 27 12:42:33 PM PST 23
Peak memory 248612 kb
Host smart-59e9962a-9683-4505-b9a6-5e91470b1477
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1992676132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1992676132
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3075334028
Short name T573
Test name
Test status
Simulation time 4692092273 ps
CPU time 244.04 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:46:18 PM PST 23
Peak memory 256736 kb
Host smart-9ef7781f-2cda-4583-9ef0-6e1ef3679656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30753
34028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3075334028
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2079559261
Short name T101
Test name
Test status
Simulation time 948960224 ps
CPU time 51.49 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 12:43:07 PM PST 23
Peak memory 248076 kb
Host smart-632393a2-65c8-4ee8-ab2b-d3d582141ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20795
59261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2079559261
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3133519946
Short name T343
Test name
Test status
Simulation time 17696019557 ps
CPU time 1059.84 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:59:52 PM PST 23
Peak memory 269528 kb
Host smart-823dcfd9-aba9-463b-abf7-9101c6c8b5fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133519946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3133519946
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3879304608
Short name T616
Test name
Test status
Simulation time 57525305328 ps
CPU time 2280.1 seconds
Started Dec 27 12:41:05 PM PST 23
Finished Dec 27 01:20:10 PM PST 23
Peak memory 283292 kb
Host smart-fa8b3dc0-d1e5-4b9b-bccd-f460a4efa1c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879304608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3879304608
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.539192127
Short name T1
Test name
Test status
Simulation time 25967343981 ps
CPU time 271.46 seconds
Started Dec 27 12:41:13 PM PST 23
Finished Dec 27 12:46:49 PM PST 23
Peak memory 248504 kb
Host smart-ae4a1119-3988-4b4d-927b-9c047a1ae91a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539192127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.539192127
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.450780734
Short name T463
Test name
Test status
Simulation time 229977291 ps
CPU time 6 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 248436 kb
Host smart-1ee37c98-45a3-4ea9-b245-9c12f1a23593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45078
0734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.450780734
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.574099150
Short name T44
Test name
Test status
Simulation time 306909689 ps
CPU time 8.76 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 252364 kb
Host smart-673b69e0-05df-4c94-869a-c3ffb49b5149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57409
9150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.574099150
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.858133921
Short name T13
Test name
Test status
Simulation time 218214464 ps
CPU time 12.59 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 272640 kb
Host smart-58090a95-0827-467d-9726-be37d9336891
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=858133921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.858133921
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1760671986
Short name T641
Test name
Test status
Simulation time 1208542074 ps
CPU time 33.97 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 12:42:57 PM PST 23
Peak memory 247568 kb
Host smart-59690aa0-077c-481b-967f-9f08060f2120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
71986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1760671986
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.65224106
Short name T61
Test name
Test status
Simulation time 1338951433 ps
CPU time 8.77 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:31 PM PST 23
Peak memory 253236 kb
Host smart-2bb98d48-c7e9-407a-bdc1-7c3abb8fdfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65224
106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.65224106
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2419984794
Short name T400
Test name
Test status
Simulation time 1387232188 ps
CPU time 40.42 seconds
Started Dec 27 12:41:21 PM PST 23
Finished Dec 27 12:43:04 PM PST 23
Peak memory 256684 kb
Host smart-62598c0e-2660-4c25-b382-0ccc8d9e80a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419984794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2419984794
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.4121661382
Short name T269
Test name
Test status
Simulation time 53809002574 ps
CPU time 3446.07 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 01:39:52 PM PST 23
Peak memory 304976 kb
Host smart-d0ffb69b-e347-4a96-929c-046f6acbbe33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121661382 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.4121661382
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1897559976
Short name T415
Test name
Test status
Simulation time 326902762889 ps
CPU time 1421.72 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 01:06:39 PM PST 23
Peak memory 273160 kb
Host smart-a0dceaf2-963a-46f0-9058-d1b0e0eb3e25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897559976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1897559976
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1512521016
Short name T676
Test name
Test status
Simulation time 983098953 ps
CPU time 35.43 seconds
Started Dec 27 12:41:52 PM PST 23
Finished Dec 27 12:43:22 PM PST 23
Peak memory 248620 kb
Host smart-30a26040-ea3f-4248-829b-aacdf88a54ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
21016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1512521016
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3747932998
Short name T81
Test name
Test status
Simulation time 1227127109 ps
CPU time 60.17 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:43:49 PM PST 23
Peak memory 254336 kb
Host smart-aac4000f-4755-4c9b-b0e5-3ce193bcd61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37479
32998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3747932998
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1861822297
Short name T634
Test name
Test status
Simulation time 41500693236 ps
CPU time 1670.77 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 01:10:49 PM PST 23
Peak memory 289320 kb
Host smart-657186c1-301f-4c2a-8ac9-669b446dc980
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861822297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1861822297
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4077494664
Short name T686
Test name
Test status
Simulation time 43684154606 ps
CPU time 1417.46 seconds
Started Dec 27 12:41:57 PM PST 23
Finished Dec 27 01:06:27 PM PST 23
Peak memory 272176 kb
Host smart-3245f6b1-13dd-41bd-baa8-be8fc66b0776
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077494664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4077494664
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3850021951
Short name T264
Test name
Test status
Simulation time 38977538734 ps
CPU time 437.66 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:50:14 PM PST 23
Peak memory 247392 kb
Host smart-457491c2-3877-48a8-a778-8797d9cbcd4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850021951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3850021951
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3362365449
Short name T654
Test name
Test status
Simulation time 55383389 ps
CPU time 4.61 seconds
Started Dec 27 12:41:46 PM PST 23
Finished Dec 27 12:42:48 PM PST 23
Peak memory 240364 kb
Host smart-2cdd2a1e-35dd-459a-8e3a-f76c5ccc026e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33623
65449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3362365449
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4189462710
Short name T475
Test name
Test status
Simulation time 199784836 ps
CPU time 7.12 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:42:55 PM PST 23
Peak memory 249124 kb
Host smart-ba524d7a-4bbd-4500-a96e-b035e76cd59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
62710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4189462710
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2175814354
Short name T294
Test name
Test status
Simulation time 1494272846 ps
CPU time 18.81 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 248496 kb
Host smart-62a75615-d77a-40d4-b8e0-4a77b569d8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21758
14354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2175814354
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1701951337
Short name T414
Test name
Test status
Simulation time 685841688 ps
CPU time 12.95 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:43:02 PM PST 23
Peak memory 256728 kb
Host smart-dc840710-b808-41f8-ab18-09fae2dda207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
51337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1701951337
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2640679477
Short name T432
Test name
Test status
Simulation time 35434205785 ps
CPU time 1043.04 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 01:00:12 PM PST 23
Peak memory 271824 kb
Host smart-1d733b6f-94db-4d94-a9d7-0d3c5e082126
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640679477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2640679477
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.540692228
Short name T254
Test name
Test status
Simulation time 85043839898 ps
CPU time 1945.28 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 01:15:11 PM PST 23
Peak memory 306068 kb
Host smart-037e49d6-52cb-4bae-b010-002c40f54c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540692228 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.540692228
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3392350529
Short name T259
Test name
Test status
Simulation time 17245488618 ps
CPU time 713.23 seconds
Started Dec 27 12:41:52 PM PST 23
Finished Dec 27 12:54:40 PM PST 23
Peak memory 264988 kb
Host smart-3d47b144-d8de-4d16-a653-10474579219c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392350529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3392350529
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3057928184
Short name T491
Test name
Test status
Simulation time 2523421423 ps
CPU time 146.95 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 12:45:21 PM PST 23
Peak memory 256116 kb
Host smart-f7c087c0-fc68-4adc-9e0a-aa53fe8850b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
28184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3057928184
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.295755020
Short name T90
Test name
Test status
Simulation time 278792148 ps
CPU time 8.01 seconds
Started Dec 27 12:41:53 PM PST 23
Finished Dec 27 12:42:55 PM PST 23
Peak memory 253724 kb
Host smart-bb6b7582-2cc0-476a-ac22-261de44c161c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29575
5020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.295755020
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2159697695
Short name T348
Test name
Test status
Simulation time 68643126241 ps
CPU time 2023.72 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 01:16:25 PM PST 23
Peak memory 281192 kb
Host smart-b6d7c6fe-525a-48c5-af1c-fe1e63b549a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159697695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2159697695
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3545065323
Short name T60
Test name
Test status
Simulation time 346636969525 ps
CPU time 1537.51 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 01:08:33 PM PST 23
Peak memory 268012 kb
Host smart-a29f37bc-40bc-466e-a97b-e0d22fa3ba2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545065323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3545065323
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2483007410
Short name T331
Test name
Test status
Simulation time 18348108323 ps
CPU time 380.8 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:49:07 PM PST 23
Peak memory 246440 kb
Host smart-3304dcfc-7acf-42b3-99b4-8e36bd86f945
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483007410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2483007410
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1928129803
Short name T398
Test name
Test status
Simulation time 4997207987 ps
CPU time 65.3 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:43:51 PM PST 23
Peak memory 248552 kb
Host smart-2986f412-b1da-4fc9-850f-704c07346594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19281
29803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1928129803
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2603414009
Short name T674
Test name
Test status
Simulation time 867007026 ps
CPU time 20.9 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 254912 kb
Host smart-144c5915-b345-42e4-99e4-d98844a2af54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26034
14009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2603414009
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1054443044
Short name T96
Test name
Test status
Simulation time 301354188 ps
CPU time 30.45 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 12:43:23 PM PST 23
Peak memory 248544 kb
Host smart-8d669909-c4fe-4c75-b5e1-317d5237cc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544
43044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1054443044
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1153815217
Short name T504
Test name
Test status
Simulation time 4563312491 ps
CPU time 70.65 seconds
Started Dec 27 12:41:52 PM PST 23
Finished Dec 27 12:43:57 PM PST 23
Peak memory 248832 kb
Host smart-a03763c4-0a47-447d-a088-f65b987eb01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11538
15217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1153815217
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2107538222
Short name T261
Test name
Test status
Simulation time 12694759238 ps
CPU time 1082.54 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 01:00:51 PM PST 23
Peak memory 287872 kb
Host smart-7482f393-19e1-4f05-b73f-c2e3cc704116
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107538222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2107538222
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.447886363
Short name T243
Test name
Test status
Simulation time 264094531457 ps
CPU time 5862.36 seconds
Started Dec 27 12:41:48 PM PST 23
Finished Dec 27 02:20:27 PM PST 23
Peak memory 306120 kb
Host smart-003203db-1251-4c93-8f98-9c27bcbc65f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447886363 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.447886363
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.952241964
Short name T74
Test name
Test status
Simulation time 90842243025 ps
CPU time 1589.5 seconds
Started Dec 27 12:41:59 PM PST 23
Finished Dec 27 01:09:20 PM PST 23
Peak memory 270044 kb
Host smart-48a83908-aef8-4639-92d9-f2b213bead51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952241964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.952241964
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.857986874
Short name T559
Test name
Test status
Simulation time 7237703215 ps
CPU time 92.15 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:44:30 PM PST 23
Peak memory 248704 kb
Host smart-f8735abe-0a05-487f-a1db-64d42227063f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85798
6874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.857986874
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1323740102
Short name T53
Test name
Test status
Simulation time 498892402 ps
CPU time 9.75 seconds
Started Dec 27 12:41:49 PM PST 23
Finished Dec 27 12:42:55 PM PST 23
Peak memory 248524 kb
Host smart-70187ee6-bd73-4aac-b3a5-4d0f341a69ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13237
40102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1323740102
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.50103587
Short name T17
Test name
Test status
Simulation time 93213213633 ps
CPU time 1452.31 seconds
Started Dec 27 12:41:56 PM PST 23
Finished Dec 27 01:07:02 PM PST 23
Peak memory 269520 kb
Host smart-d55f9d20-3be9-4d97-a620-42b919bffcb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50103587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.50103587
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2047001701
Short name T395
Test name
Test status
Simulation time 17038349634 ps
CPU time 1096.4 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 01:01:16 PM PST 23
Peak memory 264968 kb
Host smart-a5db444d-13ee-45fd-a0ba-1c9771ca481d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047001701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2047001701
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1666279591
Short name T575
Test name
Test status
Simulation time 16971968127 ps
CPU time 126.45 seconds
Started Dec 27 12:41:56 PM PST 23
Finished Dec 27 12:44:56 PM PST 23
Peak memory 247680 kb
Host smart-2b774ed7-0c16-4e27-9ba1-a5afe4c66920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666279591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1666279591
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1820111462
Short name T36
Test name
Test status
Simulation time 492285847 ps
CPU time 28 seconds
Started Dec 27 12:42:05 PM PST 23
Finished Dec 27 12:43:22 PM PST 23
Peak memory 255376 kb
Host smart-a3ef6a33-2650-4c4e-87ad-7ef6420795f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18201
11462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1820111462
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1309904205
Short name T673
Test name
Test status
Simulation time 281632655 ps
CPU time 16.34 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 12:43:11 PM PST 23
Peak memory 247628 kb
Host smart-a970fff4-ffed-4d26-85fb-bff407fc9377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13099
04205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1309904205
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.571298345
Short name T92
Test name
Test status
Simulation time 1523898442 ps
CPU time 21.25 seconds
Started Dec 27 12:42:01 PM PST 23
Finished Dec 27 12:43:13 PM PST 23
Peak memory 248616 kb
Host smart-f04e945c-7d30-4b02-aff9-c636235cba42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57129
8345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.571298345
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2837258520
Short name T20
Test name
Test status
Simulation time 1151016634 ps
CPU time 10.94 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:42:56 PM PST 23
Peak memory 248592 kb
Host smart-a80cb8d8-8250-4a77-a77c-049530e5cc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
58520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2837258520
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2821897591
Short name T131
Test name
Test status
Simulation time 12239902051 ps
CPU time 957.64 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 273304 kb
Host smart-b04d5393-296d-4462-a113-c8b9c01bf5fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821897591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2821897591
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3292677935
Short name T75
Test name
Test status
Simulation time 319764321004 ps
CPU time 5169.46 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 02:09:04 PM PST 23
Peak memory 338448 kb
Host smart-c8b210c1-3a38-4d90-98a5-c2464e6fa3f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292677935 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3292677935
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.765736277
Short name T379
Test name
Test status
Simulation time 32699306608 ps
CPU time 929.32 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:58:20 PM PST 23
Peak memory 272940 kb
Host smart-eb5b0369-5823-42bb-8213-c079eef73fb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765736277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.765736277
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.129780968
Short name T668
Test name
Test status
Simulation time 1384308494 ps
CPU time 97.98 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:44:24 PM PST 23
Peak memory 248700 kb
Host smart-ab381f0a-353c-4503-9d0f-efa24ecc5327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12978
0968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.129780968
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3714787730
Short name T389
Test name
Test status
Simulation time 232818205 ps
CPU time 7.52 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 253252 kb
Host smart-61beede1-2c35-4cac-966f-0c0c6d65ae5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37147
87730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3714787730
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.774196568
Short name T704
Test name
Test status
Simulation time 48922548098 ps
CPU time 1348.27 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 270084 kb
Host smart-61bdafe4-52d8-4440-944c-cad750da7a54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774196568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.774196568
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1169255437
Short name T629
Test name
Test status
Simulation time 179696047427 ps
CPU time 2414.41 seconds
Started Dec 27 12:41:59 PM PST 23
Finished Dec 27 01:23:05 PM PST 23
Peak memory 288652 kb
Host smart-830881dc-9df4-453b-9c16-965d8b7f09b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169255437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1169255437
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1860795597
Short name T314
Test name
Test status
Simulation time 5063812694 ps
CPU time 106.05 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:44:36 PM PST 23
Peak memory 247488 kb
Host smart-36874ee7-6402-4f33-8461-496fa706bd1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860795597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1860795597
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2511134522
Short name T370
Test name
Test status
Simulation time 1106984174 ps
CPU time 60.26 seconds
Started Dec 27 12:41:56 PM PST 23
Finished Dec 27 12:43:49 PM PST 23
Peak memory 248560 kb
Host smart-c52e829c-423b-4107-9c5c-9b5078c590da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25111
34522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2511134522
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3559416745
Short name T109
Test name
Test status
Simulation time 116196757 ps
CPU time 4.56 seconds
Started Dec 27 12:41:57 PM PST 23
Finished Dec 27 12:42:54 PM PST 23
Peak memory 249188 kb
Host smart-b98d1e1b-6c79-4ea0-8bc6-b83b1f284c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
16745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3559416745
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1242979357
Short name T597
Test name
Test status
Simulation time 73544095 ps
CPU time 5.06 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:03 PM PST 23
Peak memory 248580 kb
Host smart-7336f838-d733-4fc7-8fe7-80577af85876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12429
79357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1242979357
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2435124175
Short name T79
Test name
Test status
Simulation time 311162424 ps
CPU time 17.77 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 248464 kb
Host smart-b03ea589-a01c-477f-b1cc-cda780266ebf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435124175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2435124175
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3911806377
Short name T110
Test name
Test status
Simulation time 23045518589 ps
CPU time 591.79 seconds
Started Dec 27 12:41:44 PM PST 23
Finished Dec 27 12:52:33 PM PST 23
Peak memory 265044 kb
Host smart-362e441a-824f-4d06-b5d1-be438a2e531b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911806377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3911806377
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1573378625
Short name T653
Test name
Test status
Simulation time 6234658316 ps
CPU time 56.74 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:56 PM PST 23
Peak memory 248220 kb
Host smart-c146a51c-1ca3-4280-8ada-78e45cac36e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15733
78625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1573378625
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1941279138
Short name T235
Test name
Test status
Simulation time 809405032 ps
CPU time 23.1 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:23 PM PST 23
Peak memory 253208 kb
Host smart-ea6eef32-2347-4539-937b-84595a4b3e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19412
79138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1941279138
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2534813273
Short name T574
Test name
Test status
Simulation time 180371455350 ps
CPU time 2558.94 seconds
Started Dec 27 12:42:14 PM PST 23
Finished Dec 27 01:25:39 PM PST 23
Peak memory 288628 kb
Host smart-9b4e02e0-c2f9-4993-9033-62d4987053dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534813273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2534813273
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4212684339
Short name T394
Test name
Test status
Simulation time 36205216583 ps
CPU time 2314.74 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 01:21:26 PM PST 23
Peak memory 288968 kb
Host smart-b0e0b89c-29d2-4259-bc11-96cbba4dfc63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212684339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4212684339
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3879430306
Short name T313
Test name
Test status
Simulation time 32314259326 ps
CPU time 320.19 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 247372 kb
Host smart-3b707708-c8cd-41d4-965a-44aa2eddfd86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879430306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3879430306
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3427234018
Short name T45
Test name
Test status
Simulation time 6038076283 ps
CPU time 60.52 seconds
Started Dec 27 12:41:57 PM PST 23
Finished Dec 27 12:43:50 PM PST 23
Peak memory 248568 kb
Host smart-4db7da18-0a1a-4481-b36c-0dd03818d6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34272
34018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3427234018
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.7450331
Short name T135
Test name
Test status
Simulation time 431297517 ps
CPU time 14.89 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 254996 kb
Host smart-65243b04-233b-4998-abc3-dd1e7044ea05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74503
31 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.7450331
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2740662928
Short name T289
Test name
Test status
Simulation time 2382814396 ps
CPU time 38.42 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 12:43:35 PM PST 23
Peak memory 254364 kb
Host smart-91ab8afd-47bd-4284-82c6-40f6f0c416a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27406
62928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2740662928
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3552513282
Short name T443
Test name
Test status
Simulation time 466862629 ps
CPU time 25.58 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 12:43:22 PM PST 23
Peak memory 248652 kb
Host smart-68cd44e5-7c31-462b-91c7-2ca456a9d48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35525
13282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3552513282
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1838184751
Short name T493
Test name
Test status
Simulation time 1071455771 ps
CPU time 58.29 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:43:49 PM PST 23
Peak memory 256584 kb
Host smart-7d5eab1a-aceb-45b5-9d96-a4e0936b316b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838184751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1838184751
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2599805709
Short name T114
Test name
Test status
Simulation time 64424827651 ps
CPU time 3510.83 seconds
Started Dec 27 12:41:55 PM PST 23
Finished Dec 27 01:41:20 PM PST 23
Peak memory 338148 kb
Host smart-6f491ee8-5f54-4f73-aedd-7d9c95f0976c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599805709 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2599805709
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3789916675
Short name T409
Test name
Test status
Simulation time 16578127684 ps
CPU time 780.46 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:55:58 PM PST 23
Peak memory 273216 kb
Host smart-6ae7898c-80af-4555-ac7f-e6819ef05bb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789916675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3789916675
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1132413108
Short name T558
Test name
Test status
Simulation time 6829053570 ps
CPU time 96.05 seconds
Started Dec 27 12:42:06 PM PST 23
Finished Dec 27 12:44:30 PM PST 23
Peak memory 249564 kb
Host smart-e642b217-0267-40ad-b6a3-e71c94a0d432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11324
13108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1132413108
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.172253254
Short name T690
Test name
Test status
Simulation time 249701487 ps
CPU time 25.44 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 12:43:24 PM PST 23
Peak memory 254972 kb
Host smart-6296c912-0e3d-445f-a3af-fed4018b77db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17225
3254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.172253254
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2753753514
Short name T571
Test name
Test status
Simulation time 55972786070 ps
CPU time 999.72 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:59:38 PM PST 23
Peak memory 264932 kb
Host smart-3ada63df-fe4d-4fd0-9b9c-368a5c63ca3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753753514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2753753514
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4229958429
Short name T323
Test name
Test status
Simulation time 4132027979 ps
CPU time 90.75 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 12:44:27 PM PST 23
Peak memory 247496 kb
Host smart-7eda0851-b198-43e2-a5dd-64858af41f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229958429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4229958429
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2119135620
Short name T386
Test name
Test status
Simulation time 252792842 ps
CPU time 18.59 seconds
Started Dec 27 12:42:01 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 248476 kb
Host smart-72d946ec-6e09-4974-b569-44aff8d0cdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
35620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2119135620
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2027586571
Short name T236
Test name
Test status
Simulation time 741242158 ps
CPU time 42.28 seconds
Started Dec 27 12:42:05 PM PST 23
Finished Dec 27 12:43:36 PM PST 23
Peak memory 255296 kb
Host smart-595ee886-ae12-46b3-9995-e27c5f0a8e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
86571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2027586571
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4109222772
Short name T72
Test name
Test status
Simulation time 168521420 ps
CPU time 5.95 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 12:42:59 PM PST 23
Peak memory 249068 kb
Host smart-952fe352-ac59-4400-b561-d9a4cf2174f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092
22772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4109222772
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1898343059
Short name T405
Test name
Test status
Simulation time 285420155 ps
CPU time 10.75 seconds
Started Dec 27 12:41:50 PM PST 23
Finished Dec 27 12:42:56 PM PST 23
Peak memory 248720 kb
Host smart-4728d57f-7994-46b8-914b-8f5e3ac95b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18983
43059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1898343059
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3183224005
Short name T693
Test name
Test status
Simulation time 28526878008 ps
CPU time 1552.33 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 01:08:45 PM PST 23
Peak memory 289048 kb
Host smart-2f40cbdb-6436-497e-ae4d-2ba2614dd39b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183224005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3183224005
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1980382278
Short name T285
Test name
Test status
Simulation time 155519822818 ps
CPU time 4249.12 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 01:53:43 PM PST 23
Peak memory 338344 kb
Host smart-008f0b05-32ad-4264-98b1-c898d059c1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980382278 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1980382278
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2043117367
Short name T515
Test name
Test status
Simulation time 14123605655 ps
CPU time 646.4 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 12:53:45 PM PST 23
Peak memory 265120 kb
Host smart-ed42eade-fbf1-477d-b879-04a66fba4bd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043117367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2043117367
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3917009942
Short name T263
Test name
Test status
Simulation time 704765924 ps
CPU time 40.95 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 12:43:35 PM PST 23
Peak memory 248588 kb
Host smart-8a815f0b-16ee-4054-aedd-c3b5aaef521f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39170
09942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3917009942
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2712694249
Short name T417
Test name
Test status
Simulation time 2445612093 ps
CPU time 49.3 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:43:45 PM PST 23
Peak memory 255192 kb
Host smart-b18a34ca-c2a7-499f-8f2a-94e26dbc1eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126
94249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2712694249
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1945770294
Short name T346
Test name
Test status
Simulation time 250106921788 ps
CPU time 3508.4 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 01:41:20 PM PST 23
Peak memory 288708 kb
Host smart-e311193e-4d60-4c35-8043-8177e6dc1532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945770294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1945770294
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2019764671
Short name T433
Test name
Test status
Simulation time 17471745998 ps
CPU time 1284.07 seconds
Started Dec 27 12:42:06 PM PST 23
Finished Dec 27 01:04:18 PM PST 23
Peak memory 288704 kb
Host smart-6f3b189a-109a-4928-85bb-44c20b5b9641
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019764671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2019764671
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.526626201
Short name T330
Test name
Test status
Simulation time 2144071306 ps
CPU time 86.36 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:44:18 PM PST 23
Peak memory 247216 kb
Host smart-c87b1d57-a177-4fcb-bd87-cc76446bf4bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526626201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.526626201
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1251276523
Short name T645
Test name
Test status
Simulation time 61266889 ps
CPU time 4.55 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 12:42:52 PM PST 23
Peak memory 240344 kb
Host smart-26c38a59-b331-49b4-8510-2785a71969c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
76523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1251276523
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3395252664
Short name T87
Test name
Test status
Simulation time 856589637 ps
CPU time 18.9 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 254804 kb
Host smart-3b709126-93ca-4aa6-b2de-fe12d17ec36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
52664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3395252664
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.719160799
Short name T698
Test name
Test status
Simulation time 211735813 ps
CPU time 20.38 seconds
Started Dec 27 12:41:54 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 255352 kb
Host smart-ab9492c1-5e3e-4707-830d-4626f7f81761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71916
0799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.719160799
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1477434389
Short name T586
Test name
Test status
Simulation time 3709379448 ps
CPU time 52.94 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 12:43:48 PM PST 23
Peak memory 248672 kb
Host smart-446b5b14-0b29-495a-90d3-580c757cc917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774
34389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1477434389
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.600647900
Short name T737
Test name
Test status
Simulation time 17937362391 ps
CPU time 1040.69 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 01:00:20 PM PST 23
Peak memory 266076 kb
Host smart-1642ee99-8d1b-4a35-90de-e642db606758
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600647900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.600647900
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2186236031
Short name T542
Test name
Test status
Simulation time 14617351671 ps
CPU time 963.23 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 271420 kb
Host smart-4b314ef1-a949-4ed7-bdcf-3b9c25a229a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186236031 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2186236031
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.146700794
Short name T425
Test name
Test status
Simulation time 1100434675 ps
CPU time 69.76 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 12:44:02 PM PST 23
Peak memory 247976 kb
Host smart-8f78fa77-1ba2-4b04-8e86-613fe412a87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14670
0794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.146700794
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1640963672
Short name T534
Test name
Test status
Simulation time 98071686 ps
CPU time 4.24 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:42:54 PM PST 23
Peak memory 238632 kb
Host smart-49c75340-21d0-4644-9c0d-8dc749accd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
63672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1640963672
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2229755950
Short name T600
Test name
Test status
Simulation time 117608783227 ps
CPU time 1651.73 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 01:10:25 PM PST 23
Peak memory 272748 kb
Host smart-79fb1fcf-44e9-4b41-90f9-a6de956889ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229755950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2229755950
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2049613582
Short name T337
Test name
Test status
Simulation time 26867241501 ps
CPU time 1438.54 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 01:06:57 PM PST 23
Peak memory 272156 kb
Host smart-2a5a313e-8316-4617-b31b-2686c4e11d90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049613582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2049613582
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.125904892
Short name T608
Test name
Test status
Simulation time 483648055 ps
CPU time 28.28 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:27 PM PST 23
Peak memory 248552 kb
Host smart-cb2b0bb4-f735-4689-b149-2f1d14e6d92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12590
4892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.125904892
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2612665282
Short name T99
Test name
Test status
Simulation time 1248233797 ps
CPU time 37.41 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 12:43:27 PM PST 23
Peak memory 254836 kb
Host smart-3d6198fb-d8ea-4d5c-95ae-98791b551afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26126
65282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2612665282
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1124735409
Short name T700
Test name
Test status
Simulation time 512989711 ps
CPU time 33.06 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 12:43:26 PM PST 23
Peak memory 254844 kb
Host smart-be139d9e-6d8b-4ae4-ba79-4f649f192f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11247
35409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1124735409
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3479775221
Short name T399
Test name
Test status
Simulation time 3284814670 ps
CPU time 26.33 seconds
Started Dec 27 12:41:57 PM PST 23
Finished Dec 27 12:43:16 PM PST 23
Peak memory 248560 kb
Host smart-da5ae95d-98a7-4fa1-b40e-b53c0c6673a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34797
75221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3479775221
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2284869434
Short name T63
Test name
Test status
Simulation time 39567622622 ps
CPU time 2686.74 seconds
Started Dec 27 12:41:58 PM PST 23
Finished Dec 27 01:27:37 PM PST 23
Peak memory 289720 kb
Host smart-a29ee5cf-1590-4c24-95f2-1e9aaba5f7bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284869434 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2284869434
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2834526011
Short name T720
Test name
Test status
Simulation time 40467349820 ps
CPU time 2612.86 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 01:26:32 PM PST 23
Peak memory 289392 kb
Host smart-b70d18ad-c928-424c-a897-cd29431ab519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834526011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2834526011
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3559704294
Short name T703
Test name
Test status
Simulation time 6020138029 ps
CPU time 107.18 seconds
Started Dec 27 12:42:26 PM PST 23
Finished Dec 27 12:44:54 PM PST 23
Peak memory 255808 kb
Host smart-ca1318b5-f74c-48ba-a4be-255e982d01f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35597
04294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3559704294
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1407096217
Short name T694
Test name
Test status
Simulation time 618404920 ps
CPU time 32.66 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:43:28 PM PST 23
Peak memory 254412 kb
Host smart-5e792aee-fb71-47b4-9351-b3b19116109b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070
96217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1407096217
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3168128000
Short name T315
Test name
Test status
Simulation time 32105200673 ps
CPU time 1829.22 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 01:13:31 PM PST 23
Peak memory 272696 kb
Host smart-1e1b4284-7f37-4867-b941-27e0a568d0dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168128000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3168128000
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3436043327
Short name T267
Test name
Test status
Simulation time 220378539804 ps
CPU time 3380.7 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 01:39:14 PM PST 23
Peak memory 289320 kb
Host smart-291b56a2-c38b-4b18-9f34-55cb465942e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436043327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3436043327
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.954190944
Short name T328
Test name
Test status
Simulation time 49200412478 ps
CPU time 158.99 seconds
Started Dec 27 12:42:05 PM PST 23
Finished Dec 27 12:45:33 PM PST 23
Peak memory 253644 kb
Host smart-068ed188-d718-423f-8a62-2c22d7dc092a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954190944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.954190944
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1205348894
Short name T492
Test name
Test status
Simulation time 340142036 ps
CPU time 32.31 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:30 PM PST 23
Peak memory 248632 kb
Host smart-71b9f85f-18c9-4473-9601-52febbe2b821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12053
48894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1205348894
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1673187791
Short name T242
Test name
Test status
Simulation time 585287002 ps
CPU time 26.66 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 12:43:29 PM PST 23
Peak memory 248684 kb
Host smart-39915660-f51c-4f52-84a8-840b7077a7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16731
87791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1673187791
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.894649628
Short name T396
Test name
Test status
Simulation time 249031269 ps
CPU time 28.8 seconds
Started Dec 27 12:42:22 PM PST 23
Finished Dec 27 12:43:34 PM PST 23
Peak memory 246680 kb
Host smart-4b215075-d986-4f56-8d1f-f3a2511cbc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89464
9628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.894649628
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3798084627
Short name T579
Test name
Test status
Simulation time 913535592 ps
CPU time 15.64 seconds
Started Dec 27 12:42:24 PM PST 23
Finished Dec 27 12:43:21 PM PST 23
Peak memory 248576 kb
Host smart-cebb84ee-1615-4251-84f9-9d7ed35169a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37980
84627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3798084627
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.280443284
Short name T116
Test name
Test status
Simulation time 129181154742 ps
CPU time 2084.67 seconds
Started Dec 27 12:42:06 PM PST 23
Finished Dec 27 01:17:39 PM PST 23
Peak memory 289692 kb
Host smart-e9900809-c738-41c3-a9cd-e09283c1ab73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280443284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.280443284
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3369263332
Short name T19
Test name
Test status
Simulation time 2049065843 ps
CPU time 105.9 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:44:44 PM PST 23
Peak memory 256328 kb
Host smart-3d6369d7-67d3-4cc8-a3c8-3f1509a5bdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33692
63332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3369263332
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.529651426
Short name T615
Test name
Test status
Simulation time 1085752554 ps
CPU time 10.87 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 12:43:04 PM PST 23
Peak memory 254232 kb
Host smart-fd38ad39-976f-410f-9b7d-d7cc5890748c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52965
1426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.529651426
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1309422292
Short name T374
Test name
Test status
Simulation time 193115694182 ps
CPU time 2351.79 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 01:22:08 PM PST 23
Peak memory 272760 kb
Host smart-7345e457-2b89-4d7a-9833-8bc57aee56a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309422292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1309422292
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3686928432
Short name T581
Test name
Test status
Simulation time 33031927 ps
CPU time 4.11 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 12:43:01 PM PST 23
Peak memory 251504 kb
Host smart-a8e68d08-2245-40e5-ab00-df6ea158ed57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36869
28432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3686928432
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2803522169
Short name T557
Test name
Test status
Simulation time 3004924797 ps
CPU time 44.95 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 12:43:36 PM PST 23
Peak memory 254848 kb
Host smart-914a07a0-64b6-45cc-81cb-79e6014df71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28035
22169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2803522169
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1033195206
Short name T540
Test name
Test status
Simulation time 3961789606 ps
CPU time 36.21 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:43:32 PM PST 23
Peak memory 255192 kb
Host smart-10d004f3-1123-4e29-a377-c81656e47f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
95206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1033195206
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3949777651
Short name T465
Test name
Test status
Simulation time 218307356 ps
CPU time 4.6 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 12:43:00 PM PST 23
Peak memory 240368 kb
Host smart-68059dd6-6678-4803-9cea-7e57717aabfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39497
77651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3949777651
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1250313307
Short name T129
Test name
Test status
Simulation time 21661606003 ps
CPU time 1118.9 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 01:01:40 PM PST 23
Peak memory 288224 kb
Host smart-82893a80-5fd3-4a59-baa9-136b38ba7eb5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250313307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1250313307
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3015629459
Short name T128
Test name
Test status
Simulation time 80035970484 ps
CPU time 2224.98 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 01:20:02 PM PST 23
Peak memory 314304 kb
Host smart-f3cdd2df-7f12-474c-8654-3ceabbb7d86a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015629459 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3015629459
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4205361038
Short name T218
Test name
Test status
Simulation time 16064721 ps
CPU time 2.24 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 248776 kb
Host smart-00f67e31-89b6-4588-aa26-345c42b9e53b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4205361038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4205361038
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2701173439
Short name T572
Test name
Test status
Simulation time 114520971895 ps
CPU time 3121.33 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 01:34:20 PM PST 23
Peak memory 288924 kb
Host smart-1cd1fec6-8def-4822-83d5-132fb462e708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701173439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2701173439
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2783577462
Short name T208
Test name
Test status
Simulation time 441028148 ps
CPU time 11.51 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 240332 kb
Host smart-700348ea-6fe6-4af7-bc7b-154deab6deca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2783577462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2783577462
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1569399306
Short name T449
Test name
Test status
Simulation time 527183567 ps
CPU time 29.36 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:50 PM PST 23
Peak memory 247716 kb
Host smart-541d48ff-2dbd-4b6f-9f8b-0755b45bad4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15693
99306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1569399306
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.449529265
Short name T55
Test name
Test status
Simulation time 98805053 ps
CPU time 10.36 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:16 PM PST 23
Peak memory 253852 kb
Host smart-924bfd1d-5ec5-442b-81b5-f1ad420db738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44952
9265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.449529265
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1414206828
Short name T6
Test name
Test status
Simulation time 55916321644 ps
CPU time 1105.59 seconds
Started Dec 27 12:41:27 PM PST 23
Finished Dec 27 01:00:55 PM PST 23
Peak memory 271240 kb
Host smart-320ef6ee-4fd4-42db-a6af-3baee66c57ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414206828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1414206828
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1919780394
Short name T613
Test name
Test status
Simulation time 33762464145 ps
CPU time 1563.74 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 01:08:19 PM PST 23
Peak memory 289280 kb
Host smart-30611539-a43d-417c-94ac-84ab67dabca6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919780394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1919780394
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1890702363
Short name T333
Test name
Test status
Simulation time 19363912467 ps
CPU time 214 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:45:42 PM PST 23
Peak memory 248656 kb
Host smart-25d90547-c170-409e-9315-6b02f933350c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890702363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1890702363
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.666902234
Short name T404
Test name
Test status
Simulation time 1387104015 ps
CPU time 20.5 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 12:42:24 PM PST 23
Peak memory 255268 kb
Host smart-f3ac324e-932d-4d3e-a746-6d60fcddf61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66690
2234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.666902234
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.61593225
Short name T458
Test name
Test status
Simulation time 1833966836 ps
CPU time 50.01 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:43:09 PM PST 23
Peak memory 248464 kb
Host smart-baee3e39-2341-4c3b-a6c4-068ca7e6ae19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61593
225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.61593225
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2340885362
Short name T568
Test name
Test status
Simulation time 736966252 ps
CPU time 40.73 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:54 PM PST 23
Peak memory 255068 kb
Host smart-e31260f3-bfda-449c-be22-2a3060d9f277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408
85362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2340885362
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.365458740
Short name T695
Test name
Test status
Simulation time 706414619 ps
CPU time 15.76 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 248536 kb
Host smart-e9108f3e-a4ba-49be-8168-cb3dabf9f00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36545
8740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.365458740
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3693537379
Short name T260
Test name
Test status
Simulation time 187433173137 ps
CPU time 2420.21 seconds
Started Dec 27 12:41:05 PM PST 23
Finished Dec 27 01:22:29 PM PST 23
Peak memory 283560 kb
Host smart-90940e95-7bc9-49c7-8cbc-0d509730e526
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693537379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3693537379
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1991453182
Short name T681
Test name
Test status
Simulation time 61559158917 ps
CPU time 3280.28 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 01:37:34 PM PST 23
Peak memory 289240 kb
Host smart-29c3b013-6759-4b0c-a898-6e857675dc2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991453182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1991453182
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2083697335
Short name T231
Test name
Test status
Simulation time 5184215421 ps
CPU time 141.09 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 12:45:16 PM PST 23
Peak memory 256044 kb
Host smart-ae63b069-9533-4556-acc6-299f4882a233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20836
97335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2083697335
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3774564653
Short name T556
Test name
Test status
Simulation time 983011636 ps
CPU time 52.08 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:49 PM PST 23
Peak memory 255248 kb
Host smart-74f7f6e4-ec8b-414a-a405-7b02ea3cb18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37745
64653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3774564653
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.716285038
Short name T733
Test name
Test status
Simulation time 36288420074 ps
CPU time 936.86 seconds
Started Dec 27 12:42:35 PM PST 23
Finished Dec 27 12:58:49 PM PST 23
Peak memory 270288 kb
Host smart-5ffc65f5-c979-44a4-813d-06546b7ac5c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716285038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.716285038
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2749957735
Short name T43
Test name
Test status
Simulation time 10141315530 ps
CPU time 1055.7 seconds
Started Dec 27 12:42:02 PM PST 23
Finished Dec 27 01:00:28 PM PST 23
Peak memory 285336 kb
Host smart-bed46fdc-74f0-42fb-92b2-6956d2cf9a20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749957735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2749957735
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2634842520
Short name T10
Test name
Test status
Simulation time 12340360404 ps
CPU time 500.32 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 12:51:21 PM PST 23
Peak memory 246468 kb
Host smart-b73374c3-c765-48cc-9a09-9d18d3bc3efc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634842520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2634842520
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1930628584
Short name T470
Test name
Test status
Simulation time 352324630 ps
CPU time 4.7 seconds
Started Dec 27 12:42:17 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 240440 kb
Host smart-94d739ee-aff5-4bbb-ac17-9fea65b0c11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19306
28584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1930628584
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1886106258
Short name T73
Test name
Test status
Simulation time 417950610 ps
CPU time 13.52 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:13 PM PST 23
Peak memory 246772 kb
Host smart-b26fe143-e911-4a65-96f5-ae89a9676fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18861
06258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1886106258
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1144939487
Short name T459
Test name
Test status
Simulation time 301397367 ps
CPU time 22.71 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:22 PM PST 23
Peak memory 248608 kb
Host smart-d727dfeb-32f9-4247-9e00-dc0a1ccaac2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11449
39487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1144939487
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2798146180
Short name T719
Test name
Test status
Simulation time 4621587566 ps
CPU time 24.5 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 12:43:25 PM PST 23
Peak memory 248504 kb
Host smart-517aec96-0db7-4e39-ab99-863c3973ab57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27981
46180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2798146180
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1124239477
Short name T439
Test name
Test status
Simulation time 1481794803 ps
CPU time 83.22 seconds
Started Dec 27 12:41:59 PM PST 23
Finished Dec 27 12:44:14 PM PST 23
Peak memory 256560 kb
Host smart-6d0ab543-5418-47db-b8fd-8271e142d3f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124239477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1124239477
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3910270923
Short name T68
Test name
Test status
Simulation time 36820804903 ps
CPU time 1304.96 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 01:04:41 PM PST 23
Peak memory 284872 kb
Host smart-67bf4a38-59c0-441d-9e08-0cef733c5d83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910270923 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3910270923
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.462566997
Short name T431
Test name
Test status
Simulation time 48280802126 ps
CPU time 2571.07 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 01:25:47 PM PST 23
Peak memory 283688 kb
Host smart-b47a8b0b-d567-4fa0-bcf9-6a66f3c028d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462566997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.462566997
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2192377278
Short name T709
Test name
Test status
Simulation time 16175154 ps
CPU time 2.68 seconds
Started Dec 27 12:42:39 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 238608 kb
Host smart-c8b80a74-436e-48b6-8765-86769b669c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
77278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2192377278
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3428231906
Short name T406
Test name
Test status
Simulation time 269537679 ps
CPU time 5.47 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:43:01 PM PST 23
Peak memory 249328 kb
Host smart-dafca9f4-85a1-420c-98ba-a8cd226fe5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34282
31906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3428231906
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1902062644
Short name T610
Test name
Test status
Simulation time 37004984484 ps
CPU time 1938.96 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 01:15:19 PM PST 23
Peak memory 273156 kb
Host smart-09d9f293-f055-48f2-8afa-020793db35e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902062644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1902062644
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2552950865
Short name T122
Test name
Test status
Simulation time 36103642839 ps
CPU time 1186.2 seconds
Started Dec 27 12:42:24 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 281316 kb
Host smart-8e4f24a8-578c-4e78-ae09-66ee76506ea4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552950865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2552950865
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2626152909
Short name T730
Test name
Test status
Simulation time 37902812401 ps
CPU time 395.55 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:49:37 PM PST 23
Peak memory 246648 kb
Host smart-4df653ff-5b86-4a5d-a60c-62ca0bc0e40f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626152909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2626152909
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1796212249
Short name T473
Test name
Test status
Simulation time 77085871 ps
CPU time 4.82 seconds
Started Dec 27 12:42:07 PM PST 23
Finished Dec 27 12:43:00 PM PST 23
Peak memory 240356 kb
Host smart-00eb4c32-7161-4441-b700-ac6b02154e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17962
12249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1796212249
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2075994450
Short name T699
Test name
Test status
Simulation time 262659497 ps
CPU time 20.41 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 254964 kb
Host smart-432c2cef-ee64-4a59-a32a-8c5f1809a6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20759
94450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2075994450
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.127392943
Short name T450
Test name
Test status
Simulation time 129290163 ps
CPU time 11.16 seconds
Started Dec 27 12:42:04 PM PST 23
Finished Dec 27 12:43:05 PM PST 23
Peak memory 247764 kb
Host smart-4b7ca94a-3571-4925-8577-d33ce962e4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12739
2943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.127392943
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1675536494
Short name T368
Test name
Test status
Simulation time 16742653759 ps
CPU time 45.83 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 12:43:46 PM PST 23
Peak memory 248732 kb
Host smart-d08bb7fa-f8e5-4cc3-b1b3-eaed9194bbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755
36494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1675536494
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2520649426
Short name T529
Test name
Test status
Simulation time 156440829974 ps
CPU time 2149.73 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 01:18:51 PM PST 23
Peak memory 281312 kb
Host smart-fcdbb242-688f-49e5-92ac-565e0a0697e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520649426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2520649426
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1100824690
Short name T132
Test name
Test status
Simulation time 99451979865 ps
CPU time 3273.01 seconds
Started Dec 27 12:42:14 PM PST 23
Finished Dec 27 01:37:33 PM PST 23
Peak memory 298528 kb
Host smart-17af9496-1808-4cf5-bc71-94e4544a7a95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100824690 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1100824690
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.136087419
Short name T471
Test name
Test status
Simulation time 29713052260 ps
CPU time 681.54 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 12:54:18 PM PST 23
Peak memory 265028 kb
Host smart-bbb4f2f5-3116-47e0-8668-9092267a20e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136087419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.136087419
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2196410614
Short name T524
Test name
Test status
Simulation time 1773697528 ps
CPU time 135.38 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:45:15 PM PST 23
Peak memory 256184 kb
Host smart-a010135b-b38a-4a41-a8bb-77739936fb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21964
10614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2196410614
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2223584922
Short name T474
Test name
Test status
Simulation time 517942712 ps
CPU time 25.32 seconds
Started Dec 27 12:42:06 PM PST 23
Finished Dec 27 12:43:20 PM PST 23
Peak memory 248376 kb
Host smart-817b692d-13cd-4828-b0f0-eddb11026d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22235
84922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2223584922
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2561508155
Short name T554
Test name
Test status
Simulation time 150859538610 ps
CPU time 2116.67 seconds
Started Dec 27 12:42:03 PM PST 23
Finished Dec 27 01:18:10 PM PST 23
Peak memory 282852 kb
Host smart-a10a29de-9687-4e05-b485-a57cdcc2d386
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561508155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2561508155
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3903233809
Short name T446
Test name
Test status
Simulation time 2331162121 ps
CPU time 36.1 seconds
Started Dec 27 12:42:19 PM PST 23
Finished Dec 27 12:43:39 PM PST 23
Peak memory 248540 kb
Host smart-8542439d-7a67-408c-b7fb-ff402d16f317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39032
33809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3903233809
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1283866952
Short name T468
Test name
Test status
Simulation time 2996294164 ps
CPU time 43.65 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:43:45 PM PST 23
Peak memory 254840 kb
Host smart-840f95bd-4d92-4f6b-8430-0759a2cb9590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
66952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1283866952
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1958399625
Short name T98
Test name
Test status
Simulation time 1014046338 ps
CPU time 26.6 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:26 PM PST 23
Peak memory 248648 kb
Host smart-6f4f0f54-0e15-42a3-a5b0-9f35c981f759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
99625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1958399625
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1794275863
Short name T614
Test name
Test status
Simulation time 16102356994 ps
CPU time 727.19 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:55:05 PM PST 23
Peak memory 267436 kb
Host smart-2a1d864c-58b3-4970-ba4a-ba2affb47de6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794275863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1794275863
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.522827179
Short name T569
Test name
Test status
Simulation time 114859546548 ps
CPU time 3870.48 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 01:47:32 PM PST 23
Peak memory 297672 kb
Host smart-4a024fec-7aea-40ef-81a7-848937ae1273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522827179 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.522827179
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.83103440
Short name T592
Test name
Test status
Simulation time 46102719233 ps
CPU time 1417.77 seconds
Started Dec 27 12:42:18 PM PST 23
Finished Dec 27 01:06:40 PM PST 23
Peak memory 270360 kb
Host smart-9ad74d26-0533-48d8-82e2-4ff486a243ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83103440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.83103440
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3898203464
Short name T635
Test name
Test status
Simulation time 694469390 ps
CPU time 28.19 seconds
Started Dec 27 12:42:17 PM PST 23
Finished Dec 27 12:43:30 PM PST 23
Peak memory 255884 kb
Host smart-cc17df64-c2e1-4397-b9fc-1e2ded6a8765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38982
03464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3898203464
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2944294718
Short name T684
Test name
Test status
Simulation time 2994428617 ps
CPU time 46.41 seconds
Started Dec 27 12:42:19 PM PST 23
Finished Dec 27 12:43:49 PM PST 23
Peak memory 248100 kb
Host smart-2de3ae5e-81f1-41ac-b570-98abf5409b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
94718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2944294718
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2045329103
Short name T342
Test name
Test status
Simulation time 30658192075 ps
CPU time 1812.98 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 01:13:12 PM PST 23
Peak memory 283404 kb
Host smart-adf9fd5e-cb2a-4826-a2ab-c63dfe2c4efc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045329103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2045329103
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2690193200
Short name T378
Test name
Test status
Simulation time 494322158375 ps
CPU time 1906.64 seconds
Started Dec 27 12:42:09 PM PST 23
Finished Dec 27 01:14:45 PM PST 23
Peak memory 287008 kb
Host smart-f602b1d0-1f98-4e12-b574-9dc2fddd7af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690193200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2690193200
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3742416982
Short name T322
Test name
Test status
Simulation time 31116821841 ps
CPU time 298.01 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 247300 kb
Host smart-8a2fca4e-a4c2-4731-9d6f-367c666c2489
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742416982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3742416982
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.4275408267
Short name T437
Test name
Test status
Simulation time 273789190 ps
CPU time 21.59 seconds
Started Dec 27 12:42:25 PM PST 23
Finished Dec 27 12:43:28 PM PST 23
Peak memory 255116 kb
Host smart-42120bd8-cc69-4b0f-82eb-184721bf2ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42754
08267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.4275408267
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1805435056
Short name T119
Test name
Test status
Simulation time 10232803579 ps
CPU time 38.05 seconds
Started Dec 27 12:42:25 PM PST 23
Finished Dec 27 12:43:44 PM PST 23
Peak memory 255636 kb
Host smart-9f1b3c3a-2440-45a2-a0da-474eb9dd21c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18054
35056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1805435056
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.606487356
Short name T707
Test name
Test status
Simulation time 1054998889 ps
CPU time 17.83 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:15 PM PST 23
Peak memory 248540 kb
Host smart-53278aee-bf69-432a-b090-a707e8c2169a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60648
7356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.606487356
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4009987082
Short name T481
Test name
Test status
Simulation time 727805397 ps
CPU time 43.83 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:43:40 PM PST 23
Peak memory 248608 kb
Host smart-58195cfa-bc3c-41fd-a0fb-b46114a94661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
87082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4009987082
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2582541401
Short name T628
Test name
Test status
Simulation time 18611201927 ps
CPU time 1639.37 seconds
Started Dec 27 12:42:00 PM PST 23
Finished Dec 27 01:10:11 PM PST 23
Peak memory 289080 kb
Host smart-6389d7a7-561f-4dad-a057-6aa9478689e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582541401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2582541401
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.287325743
Short name T527
Test name
Test status
Simulation time 243978744556 ps
CPU time 5710.31 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 02:18:11 PM PST 23
Peak memory 353820 kb
Host smart-dcbdc252-f913-4a14-ba8d-1f98ed5b495f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287325743 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.287325743
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2609832140
Short name T732
Test name
Test status
Simulation time 122208360022 ps
CPU time 1788.41 seconds
Started Dec 27 12:42:20 PM PST 23
Finished Dec 27 01:12:52 PM PST 23
Peak memory 282864 kb
Host smart-553e18b6-888d-4cb2-9800-923f6aa285cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609832140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2609832140
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2434180674
Short name T206
Test name
Test status
Simulation time 14217654691 ps
CPU time 195.88 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:46:17 PM PST 23
Peak memory 256700 kb
Host smart-51e33832-908d-47de-b555-7a8e0b64d949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24341
80674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2434180674
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2467586190
Short name T506
Test name
Test status
Simulation time 1337903409 ps
CPU time 30.76 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:43:32 PM PST 23
Peak memory 254148 kb
Host smart-6a7107a5-d995-44ba-b261-25f878b18b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24675
86190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2467586190
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.294553679
Short name T621
Test name
Test status
Simulation time 15746439784 ps
CPU time 1245.78 seconds
Started Dec 27 12:42:26 PM PST 23
Finished Dec 27 01:03:52 PM PST 23
Peak memory 281276 kb
Host smart-f04840b7-38cd-4841-bd0e-19963d714766
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294553679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.294553679
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3441114524
Short name T708
Test name
Test status
Simulation time 133484591810 ps
CPU time 1917.07 seconds
Started Dec 27 12:42:29 PM PST 23
Finished Dec 27 01:15:05 PM PST 23
Peak memory 283912 kb
Host smart-85d34021-645d-4aa4-8c8d-64515c4c27a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441114524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3441114524
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4097050700
Short name T734
Test name
Test status
Simulation time 2533965359 ps
CPU time 100.58 seconds
Started Dec 27 12:42:14 PM PST 23
Finished Dec 27 12:44:40 PM PST 23
Peak memory 247472 kb
Host smart-44850d0f-10fe-4943-9f2c-b19a47cf1bb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097050700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4097050700
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4142982011
Short name T457
Test name
Test status
Simulation time 6485683974 ps
CPU time 26.78 seconds
Started Dec 27 12:42:35 PM PST 23
Finished Dec 27 12:43:38 PM PST 23
Peak memory 248596 kb
Host smart-c426e40d-1d96-49c2-90a4-f2e17ef1985b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41429
82011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4142982011
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1890251670
Short name T512
Test name
Test status
Simulation time 3308755574 ps
CPU time 27.82 seconds
Started Dec 27 12:42:18 PM PST 23
Finished Dec 27 12:43:30 PM PST 23
Peak memory 255716 kb
Host smart-8c910a8e-3b3f-4158-9706-6f4ffc8205b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18902
51670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1890251670
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1751106844
Short name T460
Test name
Test status
Simulation time 4482425461 ps
CPU time 66.63 seconds
Started Dec 27 12:42:19 PM PST 23
Finished Dec 27 12:44:10 PM PST 23
Peak memory 248292 kb
Host smart-8208b0d2-9d57-4696-abb9-f597c6bd1211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17511
06844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1751106844
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.656211523
Short name T499
Test name
Test status
Simulation time 1133808433 ps
CPU time 20.37 seconds
Started Dec 27 12:42:37 PM PST 23
Finished Dec 27 12:43:33 PM PST 23
Peak memory 248476 kb
Host smart-3037a735-96f0-474e-91f8-352b6e4fa34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65621
1523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.656211523
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.921336785
Short name T555
Test name
Test status
Simulation time 62224826433 ps
CPU time 1056.4 seconds
Started Dec 27 12:42:14 PM PST 23
Finished Dec 27 01:00:37 PM PST 23
Peak memory 282540 kb
Host smart-3fc0a45b-765b-49bb-816c-47e212b7ee5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921336785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.921336785
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1341804374
Short name T83
Test name
Test status
Simulation time 14577870600 ps
CPU time 870.8 seconds
Started Dec 27 12:42:36 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 265032 kb
Host smart-0f92fb29-58df-4d68-ac14-bd8fa14af7ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341804374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1341804374
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1829197862
Short name T711
Test name
Test status
Simulation time 1657928277 ps
CPU time 96.75 seconds
Started Dec 27 12:42:23 PM PST 23
Finished Dec 27 12:44:42 PM PST 23
Peak memory 255976 kb
Host smart-89243353-ebd2-4a5d-8965-b5d828b0d58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18291
97862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1829197862
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3553247778
Short name T657
Test name
Test status
Simulation time 2067994243 ps
CPU time 24.72 seconds
Started Dec 27 12:42:14 PM PST 23
Finished Dec 27 12:43:25 PM PST 23
Peak memory 254356 kb
Host smart-39cb364c-e1de-4f4a-9ac7-806fd59fc7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35532
47778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3553247778
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1932573010
Short name T351
Test name
Test status
Simulation time 42629746607 ps
CPU time 1021.71 seconds
Started Dec 27 12:42:48 PM PST 23
Finished Dec 27 01:00:24 PM PST 23
Peak memory 288948 kb
Host smart-d2d4cd0b-9edf-47ef-873c-663e1a729c96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932573010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1932573010
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1700536272
Short name T84
Test name
Test status
Simulation time 131655216965 ps
CPU time 1443.29 seconds
Started Dec 27 12:42:26 PM PST 23
Finished Dec 27 01:07:11 PM PST 23
Peak memory 271596 kb
Host smart-17ef7087-170d-4f9b-9c28-df164ab354f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700536272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1700536272
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.168053852
Short name T306
Test name
Test status
Simulation time 38692264690 ps
CPU time 344.4 seconds
Started Dec 27 12:42:27 PM PST 23
Finished Dec 27 12:48:52 PM PST 23
Peak memory 247564 kb
Host smart-dab46aac-3e9e-40e6-96c5-426f9c7f7f82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168053852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.168053852
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2706070863
Short name T624
Test name
Test status
Simulation time 293724807 ps
CPU time 8.07 seconds
Started Dec 27 12:42:21 PM PST 23
Finished Dec 27 12:43:12 PM PST 23
Peak memory 248600 kb
Host smart-3c7f2964-5b24-4433-b300-7a9d2aeda17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27060
70863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2706070863
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3710710827
Short name T507
Test name
Test status
Simulation time 399384734 ps
CPU time 17.4 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 246876 kb
Host smart-0814009d-ad78-491c-8dc1-9d71f9d60fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107
10827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3710710827
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2223951452
Short name T281
Test name
Test status
Simulation time 2335403711 ps
CPU time 41.08 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:43:42 PM PST 23
Peak memory 256292 kb
Host smart-9bf8c3f6-1b70-48df-b298-249c1a2f4146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239
51452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2223951452
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1847181780
Short name T22
Test name
Test status
Simulation time 62023698 ps
CPU time 2.77 seconds
Started Dec 27 12:42:34 PM PST 23
Finished Dec 27 12:43:13 PM PST 23
Peak memory 240368 kb
Host smart-9bbf7480-033f-4a31-ac9f-f536adb5fc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18471
81780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1847181780
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2624664203
Short name T118
Test name
Test status
Simulation time 5129452871 ps
CPU time 70.22 seconds
Started Dec 27 12:42:31 PM PST 23
Finished Dec 27 12:44:19 PM PST 23
Peak memory 249576 kb
Host smart-5e4fe575-c9d0-4cbc-a92b-e4419e460a60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624664203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2624664203
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.986174700
Short name T103
Test name
Test status
Simulation time 19806122999 ps
CPU time 1754.66 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 01:12:16 PM PST 23
Peak memory 289384 kb
Host smart-0b610a74-13c8-4a2f-bd73-30bc8c355ab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986174700 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.986174700
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2900649822
Short name T456
Test name
Test status
Simulation time 126601549817 ps
CPU time 2122.14 seconds
Started Dec 27 12:42:15 PM PST 23
Finished Dec 27 01:18:23 PM PST 23
Peak memory 273264 kb
Host smart-5559bb4a-543e-4b8e-8c12-0dda35f0eb5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900649822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2900649822
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2318157449
Short name T411
Test name
Test status
Simulation time 470241068 ps
CPU time 37.76 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 12:43:36 PM PST 23
Peak memory 255292 kb
Host smart-743e7915-56ca-4c64-85e1-26d4feed72ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
57449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2318157449
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1872607406
Short name T655
Test name
Test status
Simulation time 145044112 ps
CPU time 5.61 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:04 PM PST 23
Peak memory 251984 kb
Host smart-175c3c39-0fe3-4842-870b-94d07cf36f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18726
07406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1872607406
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.406555847
Short name T340
Test name
Test status
Simulation time 24997590286 ps
CPU time 985.18 seconds
Started Dec 27 12:42:38 PM PST 23
Finished Dec 27 12:59:39 PM PST 23
Peak memory 272520 kb
Host smart-bb91d5ef-234d-4fa5-9e00-d4ea7dcad4b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406555847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.406555847
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.339049561
Short name T125
Test name
Test status
Simulation time 120007255888 ps
CPU time 1846.13 seconds
Started Dec 27 12:42:17 PM PST 23
Finished Dec 27 01:13:48 PM PST 23
Peak memory 283488 kb
Host smart-74f2296a-c60d-4e9e-b83a-e6c0a8bda08c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339049561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.339049561
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3097080490
Short name T419
Test name
Test status
Simulation time 1617397643 ps
CPU time 44.35 seconds
Started Dec 27 12:42:21 PM PST 23
Finished Dec 27 12:43:48 PM PST 23
Peak memory 248504 kb
Host smart-d833e3d0-bceb-4262-8592-5054d99742c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30970
80490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3097080490
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2875821832
Short name T381
Test name
Test status
Simulation time 355362173 ps
CPU time 26.52 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:43:28 PM PST 23
Peak memory 254252 kb
Host smart-c3281e2e-d694-4d03-a54a-b039af94026e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28758
21832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2875821832
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3332798706
Short name T509
Test name
Test status
Simulation time 266672554 ps
CPU time 9.26 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:07 PM PST 23
Peak memory 248592 kb
Host smart-95887802-1279-403d-9266-dbcc37f7f394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33327
98706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3332798706
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1560294712
Short name T546
Test name
Test status
Simulation time 966689646 ps
CPU time 19.38 seconds
Started Dec 27 12:42:17 PM PST 23
Finished Dec 27 12:43:21 PM PST 23
Peak memory 248552 kb
Host smart-39221432-580f-4dc7-8e70-929d411d3479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15602
94712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1560294712
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2050899160
Short name T528
Test name
Test status
Simulation time 28753674659 ps
CPU time 3045.26 seconds
Started Dec 27 12:42:26 PM PST 23
Finished Dec 27 01:33:52 PM PST 23
Peak memory 322364 kb
Host smart-2dfdfccd-d50f-4bfb-be5b-7b822b21bc2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050899160 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2050899160
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.286638743
Short name T423
Test name
Test status
Simulation time 41317665749 ps
CPU time 1361.67 seconds
Started Dec 27 12:42:12 PM PST 23
Finished Dec 27 01:05:41 PM PST 23
Peak memory 266968 kb
Host smart-6464642f-a885-4061-9c5f-bc89000f8211
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286638743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.286638743
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3069984082
Short name T239
Test name
Test status
Simulation time 4624905335 ps
CPU time 72 seconds
Started Dec 27 12:42:33 PM PST 23
Finished Dec 27 12:44:22 PM PST 23
Peak memory 248092 kb
Host smart-27eb9365-0a2d-43af-a693-884d21b71ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30699
84082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3069984082
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2305210972
Short name T715
Test name
Test status
Simulation time 169741351 ps
CPU time 3.9 seconds
Started Dec 27 12:42:14 PM PST 23
Finished Dec 27 12:43:04 PM PST 23
Peak memory 238644 kb
Host smart-763fc8df-6620-424c-8a6e-6eaf1fe3dd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
10972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2305210972
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2133475370
Short name T729
Test name
Test status
Simulation time 46014392206 ps
CPU time 2559.7 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 01:25:41 PM PST 23
Peak memory 287656 kb
Host smart-e51ea0fa-6e6d-4756-9a00-f37ed5a50b95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133475370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2133475370
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3311685298
Short name T233
Test name
Test status
Simulation time 11399975431 ps
CPU time 104.02 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:44:45 PM PST 23
Peak memory 247168 kb
Host smart-fb345646-8a2a-46bd-b07a-7e2f1bebe7e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311685298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3311685298
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.928380672
Short name T65
Test name
Test status
Simulation time 810481941 ps
CPU time 26.18 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:28 PM PST 23
Peak memory 248804 kb
Host smart-0ca17f82-ff23-4bc1-b256-4ca9d9732a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92838
0672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.928380672
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1108971360
Short name T375
Test name
Test status
Simulation time 259872883 ps
CPU time 12.78 seconds
Started Dec 27 12:42:35 PM PST 23
Finished Dec 27 12:43:24 PM PST 23
Peak memory 254884 kb
Host smart-f00a876a-008e-4e49-a979-5728909edf50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
71360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1108971360
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.125237075
Short name T403
Test name
Test status
Simulation time 2396450893 ps
CPU time 29.92 seconds
Started Dec 27 12:42:14 PM PST 23
Finished Dec 27 12:43:30 PM PST 23
Peak memory 248696 kb
Host smart-5d240cc8-21d2-47b7-ab47-cb3938cd130a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523
7075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.125237075
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1725529532
Short name T48
Test name
Test status
Simulation time 187669078 ps
CPU time 19.32 seconds
Started Dec 27 12:42:26 PM PST 23
Finished Dec 27 12:43:26 PM PST 23
Peak memory 248620 kb
Host smart-ad932769-f815-405f-ac92-14cac7b75bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17255
29532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1725529532
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2265166236
Short name T488
Test name
Test status
Simulation time 28157282543 ps
CPU time 1242.04 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 01:03:40 PM PST 23
Peak memory 286388 kb
Host smart-6659ee5f-70e2-47b2-b9f7-130c577a010b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265166236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2265166236
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3156116156
Short name T664
Test name
Test status
Simulation time 4172313384 ps
CPU time 236.87 seconds
Started Dec 27 12:42:29 PM PST 23
Finished Dec 27 12:47:05 PM PST 23
Peak memory 250628 kb
Host smart-e4e188a1-ce07-4c14-811a-05fa62ca5c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31561
16156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3156116156
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.729849134
Short name T93
Test name
Test status
Simulation time 1535865816 ps
CPU time 8.33 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 248524 kb
Host smart-5c73f42f-a8c3-417d-83e3-b5d26c872dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72984
9134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.729849134
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2380537606
Short name T580
Test name
Test status
Simulation time 346576751112 ps
CPU time 2226.85 seconds
Started Dec 27 12:42:24 PM PST 23
Finished Dec 27 01:20:13 PM PST 23
Peak memory 287404 kb
Host smart-52ab8899-396e-46bf-bed8-321a96d1b3ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380537606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2380537606
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2752573150
Short name T317
Test name
Test status
Simulation time 16103932563 ps
CPU time 613.47 seconds
Started Dec 27 12:42:28 PM PST 23
Finished Dec 27 12:53:21 PM PST 23
Peak memory 247248 kb
Host smart-cd8f233e-cc1a-4221-a4ff-d1fe730e7c7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752573150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2752573150
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.562106926
Short name T680
Test name
Test status
Simulation time 2066690957 ps
CPU time 10.68 seconds
Started Dec 27 12:42:31 PM PST 23
Finished Dec 27 12:43:20 PM PST 23
Peak memory 248624 kb
Host smart-343bc98e-53dd-41ae-b225-5b23fe2fbca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56210
6926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.562106926
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1161639053
Short name T385
Test name
Test status
Simulation time 961547274 ps
CPU time 51 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:51 PM PST 23
Peak memory 248228 kb
Host smart-aea53510-33f7-4f52-be05-2805595637e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
39053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1161639053
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.399829114
Short name T627
Test name
Test status
Simulation time 134502377 ps
CPU time 13.25 seconds
Started Dec 27 12:42:20 PM PST 23
Finished Dec 27 12:43:17 PM PST 23
Peak memory 248584 kb
Host smart-7fb4a7e3-17bd-4991-8d8b-9a6fdd4c9032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39982
9114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.399829114
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3958591009
Short name T388
Test name
Test status
Simulation time 931019470 ps
CPU time 20.25 seconds
Started Dec 27 12:42:16 PM PST 23
Finished Dec 27 12:43:22 PM PST 23
Peak memory 248604 kb
Host smart-1a6f3338-8d04-4022-a9fa-50c4b61c5bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
91009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3958591009
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.240102681
Short name T301
Test name
Test status
Simulation time 26848931329 ps
CPU time 1760.08 seconds
Started Dec 27 12:42:17 PM PST 23
Finished Dec 27 01:12:22 PM PST 23
Peak memory 272240 kb
Host smart-0692af60-4e8a-4d21-b529-31ce28a6f9cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240102681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.240102681
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3584886276
Short name T500
Test name
Test status
Simulation time 3874624209 ps
CPU time 60.5 seconds
Started Dec 27 12:42:11 PM PST 23
Finished Dec 27 12:43:58 PM PST 23
Peak memory 255892 kb
Host smart-e3cf9230-9f7c-446c-bc2d-0c750c965647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35848
86276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3584886276
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.276217996
Short name T426
Test name
Test status
Simulation time 463422356 ps
CPU time 13.55 seconds
Started Dec 27 12:42:25 PM PST 23
Finished Dec 27 12:43:20 PM PST 23
Peak memory 246824 kb
Host smart-1ecd47cc-0299-40b9-bf8d-53369808a95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27621
7996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.276217996
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1035261462
Short name T584
Test name
Test status
Simulation time 12970566250 ps
CPU time 1063.93 seconds
Started Dec 27 12:42:25 PM PST 23
Finished Dec 27 01:00:50 PM PST 23
Peak memory 272752 kb
Host smart-df1ca604-c8fd-4ac2-a37a-ef2632f040d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035261462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1035261462
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1035093317
Short name T89
Test name
Test status
Simulation time 12179720298 ps
CPU time 885.23 seconds
Started Dec 27 12:42:34 PM PST 23
Finished Dec 27 12:57:56 PM PST 23
Peak memory 272136 kb
Host smart-61d94def-acbb-450a-922e-c4e4c79be0b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035093317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1035093317
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.4029551738
Short name T324
Test name
Test status
Simulation time 6353484866 ps
CPU time 255.64 seconds
Started Dec 27 12:42:20 PM PST 23
Finished Dec 27 12:47:19 PM PST 23
Peak memory 247372 kb
Host smart-482f5537-2c99-4d4b-b4d6-9876cfdda857
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029551738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4029551738
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1011388436
Short name T647
Test name
Test status
Simulation time 810898487 ps
CPU time 13.08 seconds
Started Dec 27 12:42:13 PM PST 23
Finished Dec 27 12:43:12 PM PST 23
Peak memory 253888 kb
Host smart-d2e2ce55-6680-49aa-b82b-ecc8c8f1ed18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10113
88436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1011388436
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2034780227
Short name T548
Test name
Test status
Simulation time 1057626944 ps
CPU time 58.32 seconds
Started Dec 27 12:42:23 PM PST 23
Finished Dec 27 12:44:04 PM PST 23
Peak memory 255192 kb
Host smart-d246e19a-5ec8-4048-a4e0-414e0f3f6088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20347
80227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2034780227
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1262996207
Short name T566
Test name
Test status
Simulation time 303958656 ps
CPU time 10.65 seconds
Started Dec 27 12:42:08 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 254096 kb
Host smart-e4f7f1a3-b430-48f6-b7e8-905f9c43bded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12629
96207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1262996207
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3516357959
Short name T453
Test name
Test status
Simulation time 960166569 ps
CPU time 50.11 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 12:43:47 PM PST 23
Peak memory 248512 kb
Host smart-cab09cd5-3b31-455b-bea9-15469faf8cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35163
57959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3516357959
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1142570730
Short name T241
Test name
Test status
Simulation time 49717474523 ps
CPU time 2738.33 seconds
Started Dec 27 12:42:10 PM PST 23
Finished Dec 27 01:28:35 PM PST 23
Peak memory 289464 kb
Host smart-527557a3-859d-40dc-a8d9-b296c3a71b41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142570730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1142570730
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.905812807
Short name T418
Test name
Test status
Simulation time 40716909418 ps
CPU time 4489.89 seconds
Started Dec 27 12:42:52 PM PST 23
Finished Dec 27 01:58:17 PM PST 23
Peak memory 338816 kb
Host smart-a2801581-e1bc-4fcd-9ded-74dfa1c6be98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905812807 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.905812807
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2774059621
Short name T226
Test name
Test status
Simulation time 14724428 ps
CPU time 2.45 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 248808 kb
Host smart-b8a7ddff-7fc6-4f0d-a759-820af0af17fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2774059621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2774059621
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2795484201
Short name T578
Test name
Test status
Simulation time 52702148530 ps
CPU time 930.81 seconds
Started Dec 27 12:41:25 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 270004 kb
Host smart-55618ede-de1e-454c-85b2-feea4ed2f06f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795484201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2795484201
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.731959220
Short name T530
Test name
Test status
Simulation time 115214404 ps
CPU time 7.11 seconds
Started Dec 27 12:41:27 PM PST 23
Finished Dec 27 12:42:35 PM PST 23
Peak memory 240384 kb
Host smart-d14697e1-c4a3-4a6e-aa17-b7d4071701b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=731959220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.731959220
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2249161985
Short name T510
Test name
Test status
Simulation time 2537073632 ps
CPU time 60.92 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:43:34 PM PST 23
Peak memory 248504 kb
Host smart-7f0b517d-4e9d-429f-a8ca-3cdce614b46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22491
61985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2249161985
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3231789026
Short name T51
Test name
Test status
Simulation time 147670577 ps
CPU time 4.8 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 238752 kb
Host smart-63c5b19e-8dc8-48af-b0ac-f746420573d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32317
89026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3231789026
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1086736649
Short name T344
Test name
Test status
Simulation time 17787078969 ps
CPU time 1503.21 seconds
Started Dec 27 12:40:58 PM PST 23
Finished Dec 27 01:07:06 PM PST 23
Peak memory 281416 kb
Host smart-e63c40cb-157a-44a2-b1f4-831cc96a91da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086736649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1086736649
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.118653131
Short name T526
Test name
Test status
Simulation time 149462264884 ps
CPU time 2103.68 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 01:17:23 PM PST 23
Peak memory 283968 kb
Host smart-3e761284-2590-4102-982e-d4509f2f88d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118653131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.118653131
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1054500747
Short name T320
Test name
Test status
Simulation time 34369749493 ps
CPU time 239.22 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:46:07 PM PST 23
Peak memory 247440 kb
Host smart-2745ea02-bb03-46cc-8469-840b9310e149
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054500747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1054500747
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.4084147486
Short name T71
Test name
Test status
Simulation time 194666861 ps
CPU time 10.86 seconds
Started Dec 27 12:41:21 PM PST 23
Finished Dec 27 12:42:34 PM PST 23
Peak memory 248616 kb
Host smart-7f88c675-9621-4298-a10d-13809ffc71c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40841
47486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.4084147486
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.545160747
Short name T477
Test name
Test status
Simulation time 2437249285 ps
CPU time 33.44 seconds
Started Dec 27 12:41:22 PM PST 23
Finished Dec 27 12:42:57 PM PST 23
Peak memory 254172 kb
Host smart-10c246ec-7a05-4c8a-bd27-ac0f9908ac4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54516
0747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.545160747
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.869770061
Short name T120
Test name
Test status
Simulation time 2374458832 ps
CPU time 33.64 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:40 PM PST 23
Peak memory 255076 kb
Host smart-0b594c3d-6a6e-4923-a753-66eae44e48bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86977
0061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.869770061
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1293193935
Short name T660
Test name
Test status
Simulation time 1776639846 ps
CPU time 46.5 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:43:01 PM PST 23
Peak memory 248552 kb
Host smart-072d81a9-1c91-4c2c-bcad-4c5e696c1001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12931
93935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1293193935
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3450327015
Short name T273
Test name
Test status
Simulation time 94119887203 ps
CPU time 1950.66 seconds
Started Dec 27 12:41:03 PM PST 23
Finished Dec 27 01:14:38 PM PST 23
Peak memory 273112 kb
Host smart-e7015ead-2c9d-48e1-b5c9-e2b7e3f398be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450327015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3450327015
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.845651611
Short name T134
Test name
Test status
Simulation time 39750450 ps
CPU time 3.25 seconds
Started Dec 27 12:41:06 PM PST 23
Finished Dec 27 12:42:13 PM PST 23
Peak memory 248812 kb
Host smart-2e93eb93-0646-4726-b60b-5a16879ef1cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=845651611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.845651611
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1305485453
Short name T424
Test name
Test status
Simulation time 29536358582 ps
CPU time 1111.59 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 01:00:43 PM PST 23
Peak memory 272500 kb
Host smart-25385fce-0fa3-4f64-a2a3-979d59122179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305485453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1305485453
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.710088070
Short name T672
Test name
Test status
Simulation time 360612799 ps
CPU time 6.35 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 240416 kb
Host smart-554367e2-4684-4953-9e42-a8df773f0128
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=710088070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.710088070
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1060192502
Short name T369
Test name
Test status
Simulation time 1290345214 ps
CPU time 92.87 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:43:41 PM PST 23
Peak memory 249492 kb
Host smart-095e828f-5f09-440a-806b-ecab49485cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601
92502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1060192502
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2330527381
Short name T435
Test name
Test status
Simulation time 343992820 ps
CPU time 20.59 seconds
Started Dec 27 12:41:13 PM PST 23
Finished Dec 27 12:42:38 PM PST 23
Peak memory 254204 kb
Host smart-33e60c0a-f8b5-4c31-9d99-25d24a7c86cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23305
27381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2330527381
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2969747465
Short name T347
Test name
Test status
Simulation time 69764294821 ps
CPU time 1995.72 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 01:15:29 PM PST 23
Peak memory 273200 kb
Host smart-0d3bfe3e-7dc7-47c0-b408-e5f7b717e0be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969747465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2969747465
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.745776503
Short name T682
Test name
Test status
Simulation time 32493737696 ps
CPU time 1328.58 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 01:04:29 PM PST 23
Peak memory 288752 kb
Host smart-c481389b-dcb9-4d57-9361-5ba23212c49e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745776503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.745776503
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3767895366
Short name T334
Test name
Test status
Simulation time 3244075802 ps
CPU time 132.6 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:44:37 PM PST 23
Peak memory 247584 kb
Host smart-a1b66744-6616-48d5-8e75-c193fac699a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767895366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3767895366
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1866607822
Short name T2
Test name
Test status
Simulation time 2969620578 ps
CPU time 51.31 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 255668 kb
Host smart-17b84d7d-9861-4ab8-8418-88173d4e1121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666
07822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1866607822
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1240734508
Short name T582
Test name
Test status
Simulation time 583368778 ps
CPU time 31.87 seconds
Started Dec 27 12:41:33 PM PST 23
Finished Dec 27 12:43:05 PM PST 23
Peak memory 253616 kb
Host smart-7d079a81-3dc4-4bab-b8df-e23b1a70e5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12407
34508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1240734508
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1682730134
Short name T462
Test name
Test status
Simulation time 219469165 ps
CPU time 15.33 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 12:42:27 PM PST 23
Peak memory 255356 kb
Host smart-3bd739ed-7280-4d38-aa27-00de586b4ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
30134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1682730134
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3913986715
Short name T601
Test name
Test status
Simulation time 576917833 ps
CPU time 13.43 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:34 PM PST 23
Peak memory 256768 kb
Host smart-99b86715-8726-4e35-a468-82e280c14c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39139
86715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3913986715
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1877445399
Short name T496
Test name
Test status
Simulation time 442643480978 ps
CPU time 1509 seconds
Started Dec 27 12:41:13 PM PST 23
Finished Dec 27 01:07:26 PM PST 23
Peak memory 272856 kb
Host smart-c5f12880-b236-4dca-948d-097e1992f05b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877445399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1877445399
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2340258832
Short name T519
Test name
Test status
Simulation time 61064473510 ps
CPU time 3438.92 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 01:39:39 PM PST 23
Peak memory 333012 kb
Host smart-f30cde85-1899-4f2c-9b6c-046ac43e39c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340258832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2340258832
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.176891969
Short name T215
Test name
Test status
Simulation time 31504906 ps
CPU time 2.36 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:08 PM PST 23
Peak memory 248848 kb
Host smart-aa8cb352-0258-4fd4-bbe6-c0ae125119d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=176891969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.176891969
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2362134609
Short name T444
Test name
Test status
Simulation time 41028404839 ps
CPU time 1178.13 seconds
Started Dec 27 12:41:36 PM PST 23
Finished Dec 27 01:02:14 PM PST 23
Peak memory 289384 kb
Host smart-64dfd9af-9718-4dfe-b3d6-21eb87a06aaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362134609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2362134609
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4169594875
Short name T240
Test name
Test status
Simulation time 2247069971 ps
CPU time 48.17 seconds
Started Dec 27 12:41:11 PM PST 23
Finished Dec 27 12:43:03 PM PST 23
Peak memory 240400 kb
Host smart-592bfacc-1397-4475-97cc-dc001b270216
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4169594875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4169594875
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3570721831
Short name T430
Test name
Test status
Simulation time 58291479290 ps
CPU time 227.14 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:46:06 PM PST 23
Peak memory 256748 kb
Host smart-ffa9f586-2d99-42ae-b218-5f069bb09c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35707
21831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3570721831
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1688405387
Short name T373
Test name
Test status
Simulation time 1774110484 ps
CPU time 12.47 seconds
Started Dec 27 12:41:05 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 254636 kb
Host smart-3fa70581-563f-4f3b-8d4f-2880ff7f56dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
05387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1688405387
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1148573996
Short name T541
Test name
Test status
Simulation time 23400940938 ps
CPU time 1265.97 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 01:03:27 PM PST 23
Peak memory 272652 kb
Host smart-e25dcb05-4a96-4110-8e5f-0ffc5166bd3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148573996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1148573996
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1406692189
Short name T438
Test name
Test status
Simulation time 42934638927 ps
CPU time 1931.61 seconds
Started Dec 27 12:41:06 PM PST 23
Finished Dec 27 01:14:22 PM PST 23
Peak memory 286224 kb
Host smart-ed2bb5fa-14b5-4c79-ae5c-02d4202495f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406692189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1406692189
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1794106621
Short name T336
Test name
Test status
Simulation time 65636218559 ps
CPU time 623.21 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:52:53 PM PST 23
Peak memory 247500 kb
Host smart-6f10995c-c60e-40cd-b42a-e7e80f48edfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794106621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1794106621
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1012063562
Short name T416
Test name
Test status
Simulation time 1809185737 ps
CPU time 21.81 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:44 PM PST 23
Peak memory 255496 kb
Host smart-6152fc32-de89-4ffe-86d3-caaea1838bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10120
63562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1012063562
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2378693606
Short name T376
Test name
Test status
Simulation time 295798013 ps
CPU time 6.19 seconds
Started Dec 27 12:41:26 PM PST 23
Finished Dec 27 12:42:34 PM PST 23
Peak memory 249316 kb
Host smart-2269cc00-025b-4d9b-87bc-821a58470e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786
93606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2378693606
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.803869388
Short name T533
Test name
Test status
Simulation time 2851338861 ps
CPU time 42.31 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 12:43:09 PM PST 23
Peak memory 255284 kb
Host smart-12bc0e98-69e4-4e92-b178-b160cacafcd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80386
9388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.803869388
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2479301761
Short name T401
Test name
Test status
Simulation time 277544635 ps
CPU time 17.86 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 12:42:38 PM PST 23
Peak memory 248676 kb
Host smart-d7624cd9-9a11-460d-8e8a-998bb08f2597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24793
01761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2479301761
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2521073104
Short name T288
Test name
Test status
Simulation time 16242992121 ps
CPU time 329.37 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:47:48 PM PST 23
Peak memory 256724 kb
Host smart-fe9c26fd-b610-4529-98b2-d4d7110a5765
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521073104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2521073104
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3899905925
Short name T588
Test name
Test status
Simulation time 121453291834 ps
CPU time 5197.88 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 02:09:00 PM PST 23
Peak memory 322404 kb
Host smart-5eac773b-33de-4c24-b68e-f7ae552d17fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899905925 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3899905925
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1503444063
Short name T229
Test name
Test status
Simulation time 22721765 ps
CPU time 2.1 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 248768 kb
Host smart-0117539f-be4f-4892-b0ef-885f95e3c221
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1503444063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1503444063
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1624305607
Short name T487
Test name
Test status
Simulation time 7081674809 ps
CPU time 780.94 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:55:23 PM PST 23
Peak memory 272860 kb
Host smart-42c40865-3c11-4a5e-b6b2-dbce63f6fb07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624305607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1624305607
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1531462193
Short name T410
Test name
Test status
Simulation time 651057686 ps
CPU time 15.31 seconds
Started Dec 27 12:41:05 PM PST 23
Finished Dec 27 12:42:24 PM PST 23
Peak memory 240432 kb
Host smart-47915e35-81db-43d9-88e0-3e288ff3c462
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1531462193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1531462193
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1836776650
Short name T532
Test name
Test status
Simulation time 3590578418 ps
CPU time 64.4 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:43:29 PM PST 23
Peak memory 248480 kb
Host smart-9d2b07ab-6304-4854-bd3f-8e4370298b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18367
76650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1836776650
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3122870038
Short name T562
Test name
Test status
Simulation time 4640903507 ps
CPU time 62.37 seconds
Started Dec 27 12:41:27 PM PST 23
Finished Dec 27 12:43:31 PM PST 23
Peak memory 248776 kb
Host smart-9aa9ae31-a8f8-40a0-8804-bcc4c86995e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31228
70038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3122870038
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3126276750
Short name T249
Test name
Test status
Simulation time 35474168646 ps
CPU time 1144.54 seconds
Started Dec 27 12:41:20 PM PST 23
Finished Dec 27 01:01:27 PM PST 23
Peak memory 264792 kb
Host smart-22bc36a1-1685-48c5-8b46-f687c337422f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126276750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3126276750
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3805959510
Short name T466
Test name
Test status
Simulation time 48147307109 ps
CPU time 1349.28 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 01:04:46 PM PST 23
Peak memory 272352 kb
Host smart-fb3ac6df-1040-42c5-b1a3-243e6c221b21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805959510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3805959510
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1525875703
Short name T561
Test name
Test status
Simulation time 29846801283 ps
CPU time 169.05 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 12:45:09 PM PST 23
Peak memory 247504 kb
Host smart-6542f247-3498-4d53-8da9-31ac44c288aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525875703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1525875703
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1985488112
Short name T479
Test name
Test status
Simulation time 56336226 ps
CPU time 6.86 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:31 PM PST 23
Peak memory 253532 kb
Host smart-534fe520-7308-472e-977d-1ec7e5a1f611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19854
88112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1985488112
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2742966971
Short name T127
Test name
Test status
Simulation time 1216236463 ps
CPU time 34.72 seconds
Started Dec 27 12:41:11 PM PST 23
Finished Dec 27 12:42:49 PM PST 23
Peak memory 255024 kb
Host smart-2c31807a-e4db-4cf9-905c-0fb02cfbd498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27429
66971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2742966971
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2266104259
Short name T295
Test name
Test status
Simulation time 871858481 ps
CPU time 17.57 seconds
Started Dec 27 12:41:24 PM PST 23
Finished Dec 27 12:42:43 PM PST 23
Peak memory 248552 kb
Host smart-79cba533-5d26-46e0-a2ab-1a396c8615ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22661
04259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2266104259
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2427087966
Short name T21
Test name
Test status
Simulation time 716666410 ps
CPU time 41.59 seconds
Started Dec 27 12:41:32 PM PST 23
Finished Dec 27 12:43:14 PM PST 23
Peak memory 248580 kb
Host smart-67b2f56e-ef06-47e7-81c3-931d18a5c776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24270
87966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2427087966
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3346001737
Short name T105
Test name
Test status
Simulation time 22646001317 ps
CPU time 467.01 seconds
Started Dec 27 12:41:51 PM PST 23
Finished Dec 27 12:50:33 PM PST 23
Peak memory 267880 kb
Host smart-17392232-8487-4433-967a-03fbd2b5b30f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346001737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3346001737
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3111242350
Short name T133
Test name
Test status
Simulation time 74939430200 ps
CPU time 3584.37 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 01:42:03 PM PST 23
Peak memory 297936 kb
Host smart-094e778e-3050-4a15-8cab-d1147a414d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111242350 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3111242350
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1607376927
Short name T216
Test name
Test status
Simulation time 17197639 ps
CPU time 2.31 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:23 PM PST 23
Peak memory 248692 kb
Host smart-794957c6-9791-4776-9e77-a889565c94f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1607376927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1607376927
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.573729199
Short name T513
Test name
Test status
Simulation time 210509829451 ps
CPU time 3066 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 01:33:28 PM PST 23
Peak memory 288236 kb
Host smart-dac8c944-8d1a-4ac8-9ee6-05727fc70cc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573729199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.573729199
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2977496296
Short name T598
Test name
Test status
Simulation time 803139402 ps
CPU time 10.02 seconds
Started Dec 27 12:41:13 PM PST 23
Finished Dec 27 12:42:27 PM PST 23
Peak memory 240500 kb
Host smart-ce056565-3aec-4f06-b14c-a0d11f6dd07f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2977496296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2977496296
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2230644108
Short name T108
Test name
Test status
Simulation time 1309382421 ps
CPU time 27.89 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 12:42:45 PM PST 23
Peak memory 248796 kb
Host smart-6ff1bf69-33ec-42df-9ea9-5209037959a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22306
44108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2230644108
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1151622360
Short name T716
Test name
Test status
Simulation time 280352246 ps
CPU time 24.3 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:42:32 PM PST 23
Peak memory 254928 kb
Host smart-ca5635d9-b32d-4b89-86a6-240acc879372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11516
22360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1151622360
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2937482132
Short name T8
Test name
Test status
Simulation time 58573707430 ps
CPU time 1139.32 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 01:01:19 PM PST 23
Peak memory 283252 kb
Host smart-08aea78c-a2ab-4af1-9a66-3aa9f121cbfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937482132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2937482132
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2792434384
Short name T520
Test name
Test status
Simulation time 16406574786 ps
CPU time 625.24 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:52:47 PM PST 23
Peak memory 272536 kb
Host smart-c537c9b6-3c17-498e-8e63-01fcf9cc48d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792434384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2792434384
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.915448607
Short name T329
Test name
Test status
Simulation time 11324899491 ps
CPU time 467.81 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 12:50:08 PM PST 23
Peak memory 247188 kb
Host smart-5e323996-c3ed-445e-bbc8-0d799e32e242
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915448607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.915448607
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2304550751
Short name T667
Test name
Test status
Simulation time 400676149 ps
CPU time 19.49 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 248648 kb
Host smart-6b5bac9f-dd28-450b-813e-63caffe58c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23045
50751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2304550751
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.448262894
Short name T265
Test name
Test status
Simulation time 356686893 ps
CPU time 10.07 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:31 PM PST 23
Peak memory 246884 kb
Host smart-39e0c362-e871-44b4-a911-05099ef8ee5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44826
2894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.448262894
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3486656651
Short name T274
Test name
Test status
Simulation time 522748586 ps
CPU time 32.45 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:42:51 PM PST 23
Peak memory 248004 kb
Host smart-1ba05dcc-3987-4bfe-9668-8f7e4f1cb308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34866
56651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3486656651
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4030586203
Short name T451
Test name
Test status
Simulation time 406100538 ps
CPU time 23.83 seconds
Started Dec 27 12:41:17 PM PST 23
Finished Dec 27 12:42:44 PM PST 23
Peak memory 248512 kb
Host smart-15b8505d-757e-4867-a681-4094aae8c32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40305
86203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4030586203
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.95471368
Short name T441
Test name
Test status
Simulation time 14006200949 ps
CPU time 1260.97 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 01:03:23 PM PST 23
Peak memory 285092 kb
Host smart-84d1b150-5f9b-40f5-8b54-80b4ac3f4880
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95471368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handl
er_stress_all.95471368
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2586242724
Short name T257
Test name
Test status
Simulation time 78214626013 ps
CPU time 1268.98 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 01:03:21 PM PST 23
Peak memory 284368 kb
Host smart-888c73b1-4e1e-47ce-9cc7-52532908d2d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586242724 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2586242724
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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