Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	103653	1			T13	9		T52	10		T25	2564
class_i[0x1]	34553	1			T52	48		T26	6		T5	11
class_i[0x2]	70777	1			T25	19		T6	9		T27	358
class_i[0x3]	56466	1			T52	3		T5	2126		T39	3

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	67060	1			T52	19		T25	634		T26	1256
alert[0x1]	67534	1			T13	8		T52	12		T25	649
alert[0x2]	66153	1			T52	21		T25	655		T26	1166
alert[0x3]	64702	1			T13	1		T52	9		T25	645

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

265193

1

T13

9

T52

61

T25

2583

esc_ping_fail

256

1

T90

6

T123

2

T38

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	66982	1			T52	19		T25	634		T26	1256
esc_integrity_fail	alert[0x1]	67474	1			T13	8		T52	12		T25	649
esc_integrity_fail	alert[0x2]	66094	1			T52	21		T25	655		T26	1166
esc_integrity_fail	alert[0x3]	64643	1			T13	1		T52	9		T25	645
esc_ping_fail	alert[0x0]	78	1			T90	1		T38	1		T49	2
esc_ping_fail	alert[0x1]	60	1			T90	1		T123	1		T38	3
esc_ping_fail	alert[0x2]	59	1			T90	1		T38	2		T77	1
esc_ping_fail	alert[0x3]	59	1			T90	3		T123	1		T38	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	103568	1			T13	9		T52	10		T25	2564
esc_integrity_fail	class_i[0x1]	34481	1			T52	48		T26	6		T5	11
esc_integrity_fail	class_i[0x2]	70711	1			T25	19		T6	9		T27	358
esc_integrity_fail	class_i[0x3]	56433	1			T52	3		T5	2126		T39	3
esc_ping_fail	class_i[0x0]	85	1			T123	1		T293	2		T289	6
esc_ping_fail	class_i[0x1]	72	1			T123	1		T38	7		T49	5
esc_ping_fail	class_i[0x2]	66	1			T77	6		T236	1		T294	9
esc_ping_fail	class_i[0x3]	33	1			T90	6		T236	1		T283	3