Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	187	1			T3	1		T81	1		T5	1
index[0x1]	242	1			T3	1		T7	1		T32	1
index[0x2]	186	1			T3	1		T13	1		T52	1
index[0x3]	198	1			T34	1		T8	1		T33	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	233	1			T3	3		T50	1		T5	3
lens_less_than_1000[1]	145	1			T32	1		T33	1		T25	1
lens_less_than_1000[2]	109	1			T7	1		T37	1		T5	5
lens_less_than_1000[3]	87	1			T52	1		T53	1		T54	1
lens_less_than_1000[4]	79	1			T8	1		T5	1		T43	1
lens_less_than_1000[5]	48	1			T13	1		T6	1		T27	1
lens_less_than_1000[6]	46	1			T27	10		T28	1		T253	2
lens_less_than_1000[7]	30	1			T81	1		T28	1		T55	1
lens_less_than_1000[8]	13	1			T34	1		T27	1		T62	1
lens_less_than_1000[9]	5	1			T67	1		T115	2		T254	1
len_2	18	1			T48	1		T60	2		T255	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T3	1		T27	1		T35	1
index[0x0]	lens_less_than_1000[1]	33	1			T6	1		T40	2		T60	2
index[0x0]	lens_less_than_1000[2]	27	1			T112	1		T57	1		T60	1
index[0x0]	lens_less_than_1000[3]	18	1			T256	1		T40	1		T100	1
index[0x0]	lens_less_than_1000[4]	13	1			T5	1		T74	1		T40	1
index[0x0]	lens_less_than_1000[5]	11	1			T27	1		T106	1		T62	1
index[0x0]	lens_less_than_1000[6]	8	1			T253	1		T257	1		T258	1
index[0x0]	lens_less_than_1000[7]	8	1			T81	1		T55	1		T105	1
index[0x0]	lens_less_than_1000[8]	1	1			T259	1		-	-		-	-
index[0x0]	len_2	6	1			T48	1		T238	1		T260	1
index[0x1]	lens_less_than_1000[0]	58	1			T3	1		T50	1		T5	1
index[0x1]	lens_less_than_1000[1]	44	1			T32	1		T25	1		T5	1
index[0x1]	lens_less_than_1000[2]	31	1			T7	1		T37	1		T5	5
index[0x1]	lens_less_than_1000[3]	16	1			T35	1		T95	1		T31	1
index[0x1]	lens_less_than_1000[4]	34	1			T75	1		T92	1		T95	2
index[0x1]	lens_less_than_1000[5]	22	1			T235	1		T261	1		T262	1
index[0x1]	lens_less_than_1000[6]	22	1			T27	10		T28	1		T99	1
index[0x1]	lens_less_than_1000[7]	7	1			T28	1		T95	1		T96	2
index[0x1]	lens_less_than_1000[8]	3	1			T62	1		T238	1		T67	1
index[0x1]	lens_less_than_1000[9]	3	1			T67	1		T115	2		-	-
index[0x1]	len_2	2	1			T263	1		T264	1		-	-
index[0x2]	lens_less_than_1000[0]	56	1			T3	1		T89	1		T40	1
index[0x2]	lens_less_than_1000[1]	29	1			T40	1		T92	1		T221	1
index[0x2]	lens_less_than_1000[2]	19	1			T36	1		T58	1		T235	1
index[0x2]	lens_less_than_1000[3]	29	1			T52	1		T54	1		T6	1
index[0x2]	lens_less_than_1000[4]	16	1			T43	1		T30	1		T234	1
index[0x2]	lens_less_than_1000[5]	9	1			T13	1		T106	1		T67	1
index[0x2]	lens_less_than_1000[6]	13	1			T253	1		T265	1		T64	1
index[0x2]	lens_less_than_1000[7]	6	1			T62	1		T266	1		T267	1
index[0x2]	lens_less_than_1000[8]	4	1			T27	1		T268	1		T269	1
index[0x2]	len_2	5	1			T60	2		T255	1		T238	1
index[0x3]	lens_less_than_1000[0]	57	1			T5	2		T48	1		T91	1
index[0x3]	lens_less_than_1000[1]	39	1			T33	1		T5	5		T6	1
index[0x3]	lens_less_than_1000[2]	32	1			T39	1		T35	1		T40	1
index[0x3]	lens_less_than_1000[3]	24	1			T53	1		T95	1		T270	1
index[0x3]	lens_less_than_1000[4]	16	1			T8	1		T30	1		T95	1
index[0x3]	lens_less_than_1000[5]	6	1			T6	1		T271	1		T272	1
index[0x3]	lens_less_than_1000[6]	3	1			T71	1		T273	1		T274	1
index[0x3]	lens_less_than_1000[7]	9	1			T60	2		T275	1		T273	1
index[0x3]	lens_less_than_1000[8]	5	1			T34	1		T276	1		T277	1
index[0x3]	lens_less_than_1000[9]	2	1			T254	1		T278	1		-	-
index[0x3]	len_2	5	1			T279	1		T130	3		T280	1