Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	0	40	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	0	40	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	98	1			T5	2		T6	1		T48	1
class_index[0x1]	87	1			T5	1		T6	1		T27	3
class_index[0x2]	74	1			T5	6		T27	3		T73	1
class_index[0x3]	93	1			T5	6		T27	1		T28	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	125	1			T27	1		T73	1		T36	1
intr_timeout_cnt[1]	82	1			T5	9		T6	1		T93	1
intr_timeout_cnt[2]	47	1			T5	2		T6	1		T27	4
intr_timeout_cnt[3]	20	1			T5	1		T60	2		T99	1
intr_timeout_cnt[4]	14	1			T30	1		T99	1		T62	1
intr_timeout_cnt[5]	14	1			T48	1		T95	2		T60	3
intr_timeout_cnt[6]	18	1			T5	2		T28	1		T57	1
intr_timeout_cnt[7]	10	1			T5	1		T27	1		T30	1
intr_timeout_cnt[8]	10	1			T95	1		T97	2		T69	1
intr_timeout_cnt[9]	12	1			T27	1		T95	1		T311	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	0	40	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	42	1			T55	1		T94	1		T57	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T6	1		T60	2		T62	1
class_index[0x0]	intr_timeout_cnt[2]	13	1			T98	1		T312	1		T313	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T5	1		T68	1		T314	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T99	1		T315	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	5	1			T48	1		T60	3		T104	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T259	1		T316	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T5	1		T317	1		T111	1
class_index[0x0]	intr_timeout_cnt[8]	5	1			T69	1		T267	1		T318	2
class_index[0x0]	intr_timeout_cnt[9]	2	1			T319	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	26	1			T36	1		T46	1		T48	1
class_index[0x1]	intr_timeout_cnt[1]	22	1			T98	2		T64	1		T320	1
class_index[0x1]	intr_timeout_cnt[2]	12	1			T5	1		T6	1		T27	2
class_index[0x1]	intr_timeout_cnt[3]	6	1			T60	2		T321	1		T322	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T30	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	6	1			T95	1		T323	1		T267	1
class_index[0x1]	intr_timeout_cnt[6]	6	1			T57	1		T104	1		T314	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T324	2		T325	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T318	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	4	1			T27	1		T326	1		T259	1
class_index[0x2]	intr_timeout_cnt[0]	25	1			T27	1		T73	1		T100	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T5	3		T93	1		T60	1
class_index[0x2]	intr_timeout_cnt[2]	13	1			T5	1		T27	1		T101	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T99	1		T62	1		T327	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T62	1		T328	1		T329	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T95	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T5	2		T317	1		T330	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T27	1		T331	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T97	2		T332	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T333	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	32	1			T48	1		T40	1		T97	2
class_index[0x3]	intr_timeout_cnt[1]	24	1			T5	6		T95	1		T100	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T27	1		T334	1		T68	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T335	2		T336	1		T330	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T319	3		T337	1		T267	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T247	1		T338	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	5	1			T28	1		T339	1		T270	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T30	1		T340	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T95	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	5	1			T95	1		T311	1		T327	2