Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	368704	1			T15	8		T19	1		T23	8
all_values[1]	368704	1			T15	8		T19	1		T23	8
all_values[2]	368704	1			T15	8		T19	1		T23	8
all_values[3]	368704	1			T15	8		T19	1		T23	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

734322

1

T15

16

T19

4

T23

24

auto[1]

740494

1

T15

16

T23

8

T124

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

872157

1

T15

20

T19

4

T23

14

auto[1]

602659

1

T15

12

T23

18

T124

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104675	1			T15	5		T19	1		T23	2
all_values[0]	auto[0]	auto[1]	78516	1			T15	1		T23	4		T124	2
all_values[0]	auto[1]	auto[0]	106356	1			T15	2		T124	5		T125	1
all_values[0]	auto[1]	auto[1]	79157	1			T23	2		T125	1		T363	2
all_values[1]	auto[0]	auto[0]	110138	1			T15	2		T19	1		T23	2
all_values[1]	auto[0]	auto[1]	73812	1			T15	2		T23	4		T124	3
all_values[1]	auto[1]	auto[0]	111287	1			T15	3		T124	4		T363	4
all_values[1]	auto[1]	auto[1]	73467	1			T15	1		T23	2		T125	1
all_values[2]	auto[0]	auto[0]	109157	1			T15	2		T19	1		T23	5
all_values[2]	auto[0]	auto[1]	74540	1			T15	1		T23	1		T124	5
all_values[2]	auto[1]	auto[0]	110357	1			T15	1		T23	2		T124	1
all_values[2]	auto[1]	auto[1]	74650	1			T15	4		T124	2		T125	3
all_values[3]	auto[0]	auto[0]	109454	1			T15	2		T19	1		T23	2
all_values[3]	auto[0]	auto[1]	74030	1			T15	1		T23	4		T364	4
all_values[3]	auto[1]	auto[0]	110733	1			T15	3		T23	1		T124	2
all_values[3]	auto[1]	auto[1]	74487	1			T15	2		T23	1		T124	2