Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	368704	1			T15	8		T19	1		T23	8
all_pins[1]	368704	1			T15	8		T19	1		T23	8
all_pins[2]	368704	1			T15	8		T19	1		T23	8
all_pins[3]	368704	1			T15	8		T19	1		T23	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1173055	1			T15	25		T19	4		T23	27
values[0x1]	301761	1			T15	7		T23	5		T124	4
transitions[0x0=>0x1]	200582	1			T15	4		T23	5		T124	4
transitions[0x1=>0x0]	200833	1			T15	4		T23	5		T124	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	289547	1			T15	8		T19	1		T23	6
all_pins[0]	values[0x1]	79157	1			T23	2		T125	1		T363	2
all_pins[0]	transitions[0x0=>0x1]	78497	1			T23	2		T125	1		T363	2
all_pins[0]	transitions[0x1=>0x0]	74078	1			T15	2		T23	1		T124	2
all_pins[1]	values[0x0]	295237	1			T15	7		T19	1		T23	6
all_pins[1]	values[0x1]	73467	1			T15	1		T23	2		T125	1
all_pins[1]	transitions[0x0=>0x1]	39907	1			T15	1		T23	2		T364	3
all_pins[1]	transitions[0x1=>0x0]	45597	1			T23	2		T363	2		T248	4
all_pins[2]	values[0x0]	294054	1			T15	4		T19	1		T23	8
all_pins[2]	values[0x1]	74650	1			T15	4		T124	2		T125	3
all_pins[2]	transitions[0x0=>0x1]	41542	1			T15	3		T124	2		T125	3
all_pins[2]	transitions[0x1=>0x0]	40359	1			T23	2		T125	1		T364	3
all_pins[3]	values[0x0]	294217	1			T15	6		T19	1		T23	7
all_pins[3]	values[0x1]	74487	1			T15	2		T23	1		T124	2
all_pins[3]	transitions[0x0=>0x1]	40636	1			T23	1		T124	2		T363	1
all_pins[3]	transitions[0x1=>0x0]	40799	1			T15	2		T124	2		T125	1