Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T15	7		T23	7		T124	7
all_values[1]	284	1			T15	7		T23	7		T124	7
all_values[2]	284	1			T15	7		T23	7		T124	7
all_values[3]	284	1			T15	7		T23	7		T124	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T15

16

T23

20

T124

20

auto[1]

504

1

T15

12

T23

8

T124

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

458

1

T15

8

T23

8

T124

10

auto[1]

678

1

T15

20

T23

20

T124

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

672

1

T15

12

T23

16

T124

12

auto[1]

464

1

T15

16

T23

12

T124

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

61

1

T15

2

T124

2

T363

2

all_values[0]

auto[0]

auto[0]

auto[1]

29

1

T23

2

T125

1

T364

2

all_values[0]

auto[0]

auto[1]

auto[0]

35

1

T124

1

T125

1

T365

1

all_values[0]

auto[0]

auto[1]

auto[1]

34

1

T363

1

T365

1

T248

2

all_values[0]

auto[1]

auto[0]

auto[1]

67

1

T15

3

T23

2

T124

3

all_values[0]

auto[1]

auto[1]

auto[1]

58

1

T15

2

T23

3

T124

1

all_values[1]

auto[0]

auto[0]

auto[0]

66

1

T15

2

T23

1

T124

1

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T23

2

T124

1

T125

1

all_values[1]

auto[0]

auto[1]

auto[0]

49

1

T15

1

T124

2

T363

2

all_values[1]

auto[0]

auto[1]

auto[1]

21

1

T15

1

T364

1

T366

2

all_values[1]

auto[1]

auto[0]

auto[1]

70

1

T15

2

T23

2

T124

3

all_values[1]

auto[1]

auto[1]

auto[1]

51

1

T15

1

T23

2

T364

2

all_values[2]

auto[0]

auto[0]

auto[0]

76

1

T23

3

T363

3

T365

1

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T23

1

T364

1

T365

1

all_values[2]

auto[0]

auto[1]

auto[0]

56

1

T23

2

T364

1

T366

3

all_values[2]

auto[0]

auto[1]

auto[1]

21

1

T15

1

T124

1

T125

1

all_values[2]

auto[1]

auto[0]

auto[1]

61

1

T15

3

T23

1

T124

6

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T15

3

T125

3

T363

1

all_values[3]

auto[0]

auto[0]

auto[0]

67

1

T15

2

T23

2

T124

3

all_values[3]

auto[0]

auto[0]

auto[1]

30

1

T15

1

T23

3

T364

2

all_values[3]

auto[0]

auto[1]

auto[0]

48

1

T15

1

T124

1

T125

2

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T15

1

T125

1

T364

1

all_values[3]

auto[1]

auto[0]

auto[1]

54

1

T15

1

T23

1

T124

1

all_values[3]

auto[1]

auto[1]

auto[1]

57

1

T15

1

T23

1

T124

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal