Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87939	1			T3	200		T37	963		T25	366
accum_cnt_1000	238949	1			T3	627		T8	2015		T33	80
accum_cnt_100	33223	1			T3	31		T32	2		T50	10
accum_cnt_50	71979	1			T2	68		T3	31		T13	2
accum_cnt_10	210211	1			T1	6		T2	29		T3	934
accum_cnt_0	407011	1			T1	66		T2	3		T3	1813

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	271421	1			T1	18		T2	25		T3	909
class_index[0x1]	271419	1			T1	18		T2	25		T3	909
class_index[0x2]	271417	1			T1	18		T2	25		T3	909
class_index[0x3]	271417	1			T1	18		T2	25		T3	909

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24451	1			T37	316		T25	207		T26	245
class_index[0x0]	accum_cnt_1000	67950	1			T8	935		T33	38		T37	518
class_index[0x0]	accum_cnt_100	8640	1			T32	2		T50	10		T8	162
class_index[0x0]	accum_cnt_50	17450	1			T2	14		T32	17		T50	9
class_index[0x0]	accum_cnt_10	45826	1			T1	6		T2	8		T3	3
class_index[0x0]	accum_cnt_0	95208	1			T1	12		T2	3		T3	906
class_index[0x1]	accum_cnt_2000	22503	1			T37	383		T26	640		T39	581
class_index[0x1]	accum_cnt_1000	54006	1			T33	17		T37	347		T26	688
class_index[0x1]	accum_cnt_100	6306	1			T33	23		T53	16		T37	20
class_index[0x1]	accum_cnt_50	16390	1			T2	22		T33	19		T53	18
class_index[0x1]	accum_cnt_10	57706	1			T2	3		T3	909		T7	1241
class_index[0x1]	accum_cnt_0	107232	1			T1	18		T9	3		T7	12
class_index[0x2]	accum_cnt_2000	17147	1			T37	264		T25	159		T6	289
class_index[0x2]	accum_cnt_1000	56809	1			T33	25		T37	559		T25	168
class_index[0x2]	accum_cnt_100	9423	1			T33	19		T37	34		T25	9
class_index[0x2]	accum_cnt_50	17584	1			T2	18		T13	2		T32	18
class_index[0x2]	accum_cnt_10	53676	1			T2	7		T3	3		T7	1
class_index[0x2]	accum_cnt_0	107715	1			T1	18		T3	906		T9	3
class_index[0x3]	accum_cnt_2000	23838	1			T3	200		T26	636		T5	250
class_index[0x3]	accum_cnt_1000	60184	1			T3	627		T8	1080		T54	33
class_index[0x3]	accum_cnt_100	8854	1			T3	31		T8	80		T53	12
class_index[0x3]	accum_cnt_50	20555	1			T2	14		T3	31		T8	57
class_index[0x3]	accum_cnt_10	53003	1			T2	11		T3	19		T9	1
class_index[0x3]	accum_cnt_0	96856	1			T1	18		T3	1		T9	2