Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	9189	1			T25	244		T26	3763		T90	1
alert[0x1]	6670	1			T13	2		T123	1		T40	13
alert[0x2]	8070	1			T25	121		T26	1291		T5	4
alert[0x3]	3000	1			T25	68		T5	5		T27	1
alert[0x4]	5098	1			T26	291		T5	4		T27	26
alert[0x5]	7538	1			T25	770		T27	2		T35	203
alert[0x6]	1966	1			T122	2		T35	85		T30	1
alert[0x7]	4405	1			T25	14		T27	40		T122	1
alert[0x8]	2514	1			T5	1		T27	22		T49	1
alert[0x9]	4185	1			T25	1		T30	7		T40	336
alert[0xa]	4970	1			T26	58		T39	3		T90	1
alert[0xb]	6815	1			T25	56		T26	42		T5	27
alert[0xc]	3862	1			T123	1		T38	1		T49	1
alert[0xd]	4499	1			T26	360		T27	15		T35	1
alert[0xe]	11206	1			T25	41		T6	3		T27	84
alert[0xf]	4393	1			T26	364		T6	8		T27	15
alert[0x10]	3487	1			T27	5		T90	1		T123	1
alert[0x11]	3670	1			T39	5		T40	241		T92	15
alert[0x12]	1774	1			T5	11		T49	1		T57	8
alert[0x13]	5813	1			T25	15		T5	86		T90	1
alert[0x14]	2294	1			T26	2		T27	446		T123	1
alert[0x15]	5378	1			T25	836		T27	28		T35	130
alert[0x16]	3053	1			T25	180		T5	1		T39	1
alert[0x17]	4997	1			T52	31		T5	20		T82	16
alert[0x18]	4741	1			T52	15		T26	66		T27	70
alert[0x19]	5025	1			T25	13		T26	417		T5	7
alert[0x1a]	2099	1			T52	2		T25	11		T26	92
alert[0x1b]	1466	1			T27	6		T38	2		T30	16
alert[0x1c]	5012	1			T25	642		T27	328		T90	2
alert[0x1d]	5708	1			T26	16		T5	2		T27	16
alert[0x1e]	5453	1			T25	20		T30	4		T40	326
alert[0x1f]	3265	1			T52	14		T25	16		T26	229
alert[0x20]	6136	1			T25	4		T27	26		T40	33
alert[0x21]	5990	1			T13	31		T27	361		T40	395
alert[0x22]	7345	1			T26	134		T5	1		T27	37
alert[0x23]	7095	1			T90	1		T82	3		T35	1
alert[0x24]	3359	1			T39	1		T27	130		T35	47
alert[0x25]	4060	1			T25	26		T27	50		T35	1
alert[0x26]	3341	1			T6	4		T90	1		T38	1
alert[0x27]	2709	1			T13	1		T25	85		T27	2
alert[0x28]	2680	1			T5	1		T27	80		T90	1
alert[0x29]	3294	1			T38	1		T49	1		T40	1
alert[0x2a]	5171	1			T52	5		T5	2		T27	6
alert[0x2b]	3206	1			T90	1		T49	1		T30	83
alert[0x2c]	11153	1			T39	3		T27	18		T35	19
alert[0x2d]	4376	1			T25	14		T26	53		T5	3
alert[0x2e]	2154	1			T26	3		T5	4		T82	2
alert[0x2f]	3864	1			T25	105		T26	36		T27	6
alert[0x30]	2934	1			T25	46		T26	273		T5	17
alert[0x31]	2475	1			T35	1		T49	1		T30	5
alert[0x32]	1740	1			T25	6		T27	10		T55	28
alert[0x33]	4223	1			T52	14		T25	998		T26	138
alert[0x34]	3770	1			T52	5		T25	20		T39	3
alert[0x35]	6219	1			T26	37		T5	4		T35	5
alert[0x36]	8224	1			T26	84		T38	1		T30	11
alert[0x37]	4209	1			T27	2		T82	4		T38	1
alert[0x38]	3573	1			T26	52		T27	24		T49	1
alert[0x39]	5205	1			T27	7		T38	1		T49	1
alert[0x3a]	3362	1			T25	30		T82	1		T38	1
alert[0x3b]	8066	1			T26	199		T123	1		T49	1
alert[0x3c]	2529	1			T25	13		T26	4		T90	1
alert[0x3d]	5728	1			T25	2		T26	5		T5	8
alert[0x3e]	5321	1			T52	5		T25	18		T26	5
alert[0x3f]	3964	1			T25	23		T26	132		T27	4
alert[0x40]	2226	1			T25	40		T49	1		T30	7

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	80520	1			T13	34		T52	5		T25	26
class_i[0x1]	53197	1			T52	70		T5	5		T39	151
class_i[0x2]	90208	1			T52	16		T25	4452		T26	8128
class_i[0x3]	77391	1			T5	5		T6	28		T27	881

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

300657

1

T13

34

T52

91

T25

4478

alert_ping_fail

659

1

T90

14

T122

5

T123

10

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	9178	1			T25	244		T26	3763		T40	2824
alert_integrity_fail	alert[0x1]	6662	1			T13	2		T40	13		T55	163
alert_integrity_fail	alert[0x2]	8058	1			T25	121		T26	1291		T5	4
alert_integrity_fail	alert[0x3]	2993	1			T25	68		T5	5		T27	1
alert_integrity_fail	alert[0x4]	5088	1			T26	291		T5	4		T27	26
alert_integrity_fail	alert[0x5]	7528	1			T25	770		T27	2		T35	203
alert_integrity_fail	alert[0x6]	1954	1			T35	85		T30	1		T55	499
alert_integrity_fail	alert[0x7]	4397	1			T25	14		T27	40		T40	12
alert_integrity_fail	alert[0x8]	2499	1			T5	1		T27	22		T105	14
alert_integrity_fail	alert[0x9]	4174	1			T25	1		T30	7		T40	336
alert_integrity_fail	alert[0xa]	4950	1			T26	58		T39	3		T55	165
alert_integrity_fail	alert[0xb]	6805	1			T25	56		T26	42		T5	27
alert_integrity_fail	alert[0xc]	3854	1			T55	9		T95	27		T105	10
alert_integrity_fail	alert[0xd]	4490	1			T26	360		T27	15		T35	1
alert_integrity_fail	alert[0xe]	11199	1			T25	41		T6	3		T27	84
alert_integrity_fail	alert[0xf]	4379	1			T26	364		T6	8		T27	15
alert_integrity_fail	alert[0x10]	3478	1			T27	5		T40	9		T14	10
alert_integrity_fail	alert[0x11]	3664	1			T39	5		T40	241		T92	15
alert_integrity_fail	alert[0x12]	1766	1			T5	11		T57	8		T61	17
alert_integrity_fail	alert[0x13]	5801	1			T25	15		T5	86		T40	7
alert_integrity_fail	alert[0x14]	2273	1			T26	2		T27	446		T113	1
alert_integrity_fail	alert[0x15]	5366	1			T25	836		T27	28		T35	130
alert_integrity_fail	alert[0x16]	3044	1			T25	180		T5	1		T39	1
alert_integrity_fail	alert[0x17]	4989	1			T52	31		T5	20		T82	16
alert_integrity_fail	alert[0x18]	4724	1			T52	15		T26	66		T27	70
alert_integrity_fail	alert[0x19]	5017	1			T25	13		T26	417		T5	7
alert_integrity_fail	alert[0x1a]	2096	1			T52	2		T25	11		T26	92
alert_integrity_fail	alert[0x1b]	1456	1			T27	6		T30	16		T94	1
alert_integrity_fail	alert[0x1c]	5001	1			T25	642		T27	328		T30	5
alert_integrity_fail	alert[0x1d]	5699	1			T26	16		T5	2		T27	16
alert_integrity_fail	alert[0x1e]	5443	1			T25	20		T30	4		T40	326
alert_integrity_fail	alert[0x1f]	3250	1			T52	14		T25	16		T26	229
alert_integrity_fail	alert[0x20]	6126	1			T25	4		T27	26		T40	33
alert_integrity_fail	alert[0x21]	5981	1			T13	31		T27	361		T40	395
alert_integrity_fail	alert[0x22]	7332	1			T26	134		T5	1		T27	37
alert_integrity_fail	alert[0x23]	7087	1			T82	3		T35	1		T40	637
alert_integrity_fail	alert[0x24]	3351	1			T39	1		T27	130		T35	47
alert_integrity_fail	alert[0x25]	4053	1			T25	26		T27	50		T35	1
alert_integrity_fail	alert[0x26]	3327	1			T6	4		T30	115		T40	40
alert_integrity_fail	alert[0x27]	2699	1			T13	1		T25	85		T27	2
alert_integrity_fail	alert[0x28]	2667	1			T5	1		T27	80		T40	282
alert_integrity_fail	alert[0x29]	3285	1			T40	1		T95	209		T253	18
alert_integrity_fail	alert[0x2a]	5157	1			T52	5		T5	2		T27	6
alert_integrity_fail	alert[0x2b]	3193	1			T30	83		T40	113		T94	20
alert_integrity_fail	alert[0x2c]	11141	1			T39	3		T27	18		T35	19
alert_integrity_fail	alert[0x2d]	4370	1			T25	14		T26	53		T5	3
alert_integrity_fail	alert[0x2e]	2145	1			T26	3		T5	4		T82	2
alert_integrity_fail	alert[0x2f]	3849	1			T25	105		T26	36		T27	6
alert_integrity_fail	alert[0x30]	2922	1			T25	46		T26	273		T5	17
alert_integrity_fail	alert[0x31]	2465	1			T35	1		T30	5		T40	4
alert_integrity_fail	alert[0x32]	1734	1			T25	6		T27	10		T55	28
alert_integrity_fail	alert[0x33]	4214	1			T52	14		T25	998		T26	138
alert_integrity_fail	alert[0x34]	3759	1			T52	5		T25	20		T39	3
alert_integrity_fail	alert[0x35]	6214	1			T26	37		T5	4		T35	5
alert_integrity_fail	alert[0x36]	8217	1			T26	84		T30	11		T57	32
alert_integrity_fail	alert[0x37]	4200	1			T27	2		T82	4		T40	146
alert_integrity_fail	alert[0x38]	3563	1			T26	52		T27	24		T40	6
alert_integrity_fail	alert[0x39]	5201	1			T27	7		T40	56		T95	28
alert_integrity_fail	alert[0x3a]	3348	1			T25	30		T82	1		T48	2
alert_integrity_fail	alert[0x3b]	8054	1			T26	199		T30	4		T40	25
alert_integrity_fail	alert[0x3c]	2518	1			T25	13		T26	4		T82	1
alert_integrity_fail	alert[0x3d]	5717	1			T25	2		T26	5		T5	8
alert_integrity_fail	alert[0x3e]	5313	1			T52	5		T25	18		T26	5
alert_integrity_fail	alert[0x3f]	3960	1			T25	23		T26	132		T27	4
alert_integrity_fail	alert[0x40]	2220	1			T25	40		T30	7		T40	477
alert_ping_fail	alert[0x0]	11	1			T90	1		T283	1		T284	1
alert_ping_fail	alert[0x1]	8	1			T123	1		T285	1		T286	2
alert_ping_fail	alert[0x2]	12	1			T49	1		T77	1		T287	1
alert_ping_fail	alert[0x3]	7	1			T90	1		T49	2		T284	1
alert_ping_fail	alert[0x4]	10	1			T123	1		T38	1		T288	1
alert_ping_fail	alert[0x5]	10	1			T49	1		T289	1		T290	1
alert_ping_fail	alert[0x6]	12	1			T122	2		T287	1		T282	1
alert_ping_fail	alert[0x7]	8	1			T122	1		T291	1		T292	2
alert_ping_fail	alert[0x8]	15	1			T49	1		T77	1		T80	1
alert_ping_fail	alert[0x9]	11	1			T293	1		T283	1		T271	1
alert_ping_fail	alert[0xa]	20	1			T90	1		T38	1		T294	1
alert_ping_fail	alert[0xb]	10	1			T77	1		T295	1		T296	1
alert_ping_fail	alert[0xc]	8	1			T123	1		T38	1		T49	1
alert_ping_fail	alert[0xd]	9	1			T123	1		T287	1		T271	1
alert_ping_fail	alert[0xe]	7	1			T294	1		T297	1		T298	1
alert_ping_fail	alert[0xf]	14	1			T49	1		T289	1		T299	1
alert_ping_fail	alert[0x10]	9	1			T90	1		T123	1		T38	1
alert_ping_fail	alert[0x11]	6	1			T289	1		T283	1		T271	1
alert_ping_fail	alert[0x12]	8	1			T49	1		T294	1		T299	1
alert_ping_fail	alert[0x13]	12	1			T90	1		T287	1		T300	1
alert_ping_fail	alert[0x14]	21	1			T123	1		T282	1		T295	1
alert_ping_fail	alert[0x15]	12	1			T284	1		T301	1		T302	1
alert_ping_fail	alert[0x16]	9	1			T283	1		T303	1		T271	1
alert_ping_fail	alert[0x17]	8	1			T289	1		T283	1		T304	1
alert_ping_fail	alert[0x18]	17	1			T38	1		T77	1		T299	1
alert_ping_fail	alert[0x19]	8	1			T90	1		T294	1		T305	1
alert_ping_fail	alert[0x1a]	3	1			T299	1		T243	1		T302	1
alert_ping_fail	alert[0x1b]	10	1			T38	2		T77	1		T306	1
alert_ping_fail	alert[0x1c]	11	1			T90	2		T289	1		T305	1
alert_ping_fail	alert[0x1d]	9	1			T122	2		T299	1		T231	1
alert_ping_fail	alert[0x1e]	10	1			T289	1		T295	1		T299	1
alert_ping_fail	alert[0x1f]	15	1			T123	1		T287	1		T307	1
alert_ping_fail	alert[0x20]	10	1			T283	1		T284	2		T297	1
alert_ping_fail	alert[0x21]	9	1			T271	1		T243	2		T286	2
alert_ping_fail	alert[0x22]	13	1			T77	2		T293	1		T289	1
alert_ping_fail	alert[0x23]	8	1			T90	1		T294	1		T295	1
alert_ping_fail	alert[0x24]	8	1			T38	1		T284	1		T271	1
alert_ping_fail	alert[0x25]	7	1			T38	1		T49	1		T77	1
alert_ping_fail	alert[0x26]	14	1			T90	1		T38	1		T49	1
alert_ping_fail	alert[0x27]	10	1			T38	1		T294	1		T296	1
alert_ping_fail	alert[0x28]	13	1			T90	1		T49	3		T296	1
alert_ping_fail	alert[0x29]	9	1			T38	1		T49	1		T294	1
alert_ping_fail	alert[0x2a]	14	1			T123	1		T38	1		T49	1
alert_ping_fail	alert[0x2b]	13	1			T90	1		T49	1		T293	1
alert_ping_fail	alert[0x2c]	12	1			T49	1		T299	1		T290	1
alert_ping_fail	alert[0x2d]	6	1			T38	1		T236	1		T283	1
alert_ping_fail	alert[0x2e]	9	1			T77	1		T283	1		T271	1
alert_ping_fail	alert[0x2f]	15	1			T38	1		T283	1		T299	1
alert_ping_fail	alert[0x30]	12	1			T90	1		T289	1		T294	1
alert_ping_fail	alert[0x31]	10	1			T49	1		T289	1		T287	1
alert_ping_fail	alert[0x32]	6	1			T295	1		T297	1		T308	1
alert_ping_fail	alert[0x33]	9	1			T123	1		T283	1		T299	1
alert_ping_fail	alert[0x34]	11	1			T38	1		T236	2		T284	1
alert_ping_fail	alert[0x35]	5	1			T38	1		T299	1		T290	2
alert_ping_fail	alert[0x36]	7	1			T38	1		T77	1		T297	1
alert_ping_fail	alert[0x37]	9	1			T38	1		T77	1		T289	1
alert_ping_fail	alert[0x38]	10	1			T49	1		T236	1		T294	1
alert_ping_fail	alert[0x39]	4	1			T38	1		T49	1		T309	1
alert_ping_fail	alert[0x3a]	14	1			T38	1		T49	1		T297	2
alert_ping_fail	alert[0x3b]	12	1			T123	1		T49	1		T289	1
alert_ping_fail	alert[0x3c]	11	1			T90	1		T299	1		T297	1
alert_ping_fail	alert[0x3d]	11	1			T38	1		T287	1		T236	2
alert_ping_fail	alert[0x3e]	8	1			T299	1		T284	1		T302	1
alert_ping_fail	alert[0x3f]	4	1			T287	1		T294	1		T297	1
alert_ping_fail	alert[0x40]	6	1			T49	1		T290	1		T310	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	80375	1			T13	34		T52	5		T25	26
alert_integrity_fail	class_i[0x1]	53112	1			T52	70		T5	5		T39	151
alert_integrity_fail	class_i[0x2]	89993	1			T52	16		T25	4452		T26	8128
alert_integrity_fail	class_i[0x3]	77177	1			T5	5		T6	28		T27	881
alert_ping_fail	class_i[0x0]	145	1			T90	1		T123	1		T49	1
alert_ping_fail	class_i[0x1]	85	1			T122	5		T293	2		T282	3
alert_ping_fail	class_i[0x2]	215	1			T90	13		T123	1		T38	22
alert_ping_fail	class_i[0x3]	214	1			T123	8		T49	22		T289	12