Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.49 99.99 98.68 91.69 100.00 100.00 99.38 99.72


Total test records in report: 847
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T141 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2094831456 Dec 31 12:44:13 PM PST 23 Dec 31 12:49:15 PM PST 23 6324132288 ps
T775 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3137952950 Dec 31 12:44:18 PM PST 23 Dec 31 12:44:23 PM PST 23 16105738 ps
T776 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.437848213 Dec 31 12:44:25 PM PST 23 Dec 31 12:44:38 PM PST 23 70465263 ps
T777 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.939789251 Dec 31 12:44:17 PM PST 23 Dec 31 12:44:24 PM PST 23 97834192 ps
T778 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4290530678 Dec 31 12:44:22 PM PST 23 Dec 31 12:44:27 PM PST 23 7758898 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1878166690 Dec 31 12:44:14 PM PST 23 Dec 31 12:49:51 PM PST 23 18538475937 ps
T780 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3558512492 Dec 31 12:44:00 PM PST 23 Dec 31 12:44:22 PM PST 23 344310220 ps
T250 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3870442024 Dec 31 12:44:30 PM PST 23 Dec 31 12:44:57 PM PST 23 162149479 ps
T781 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3610973560 Dec 31 12:44:05 PM PST 23 Dec 31 12:44:24 PM PST 23 126300876 ps
T782 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3946746876 Dec 31 12:44:04 PM PST 23 Dec 31 12:44:22 PM PST 23 253161429 ps
T783 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3323143003 Dec 31 12:44:10 PM PST 23 Dec 31 12:44:26 PM PST 23 314784349 ps
T784 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1275156472 Dec 31 12:44:40 PM PST 23 Dec 31 12:44:46 PM PST 23 7923892 ps
T191 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1405748597 Dec 31 12:43:56 PM PST 23 Dec 31 12:45:32 PM PST 23 1302360620 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2458640842 Dec 31 12:44:14 PM PST 23 Dec 31 12:44:20 PM PST 23 13346844 ps
T142 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2341775189 Dec 31 12:44:00 PM PST 23 Dec 31 12:46:48 PM PST 23 4177695226 ps
T786 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1164723506 Dec 31 12:44:09 PM PST 23 Dec 31 12:44:19 PM PST 23 6914335 ps
T165 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2421985689 Dec 31 12:43:45 PM PST 23 Dec 31 12:55:02 PM PST 23 4951564752 ps
T787 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3326554990 Dec 31 12:44:23 PM PST 23 Dec 31 12:44:30 PM PST 23 29454399 ps
T189 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3059489740 Dec 31 12:44:11 PM PST 23 Dec 31 12:44:25 PM PST 23 138626904 ps
T788 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1314215321 Dec 31 12:44:08 PM PST 23 Dec 31 12:44:28 PM PST 23 91578441 ps
T789 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.831521688 Dec 31 12:44:12 PM PST 23 Dec 31 12:46:16 PM PST 23 6813829801 ps
T790 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2562827712 Dec 31 12:44:40 PM PST 23 Dec 31 12:44:46 PM PST 23 7078038 ps
T791 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.145706749 Dec 31 12:44:31 PM PST 23 Dec 31 12:44:43 PM PST 23 76192723 ps
T792 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1546968168 Dec 31 12:44:41 PM PST 23 Dec 31 12:44:46 PM PST 23 13126883 ps
T793 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3954478658 Dec 31 12:44:21 PM PST 23 Dec 31 12:44:30 PM PST 23 72273724 ps
T794 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2455966360 Dec 31 12:44:31 PM PST 23 Dec 31 12:44:38 PM PST 23 21583908 ps
T169 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2237435967 Dec 31 12:44:21 PM PST 23 Dec 31 12:59:47 PM PST 23 49991229223 ps
T795 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1215012776 Dec 31 12:44:57 PM PST 23 Dec 31 12:45:06 PM PST 23 52984057 ps
T796 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2830659774 Dec 31 12:44:19 PM PST 23 Dec 31 12:44:24 PM PST 23 7683230 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.814639759 Dec 31 12:44:08 PM PST 23 Dec 31 12:44:22 PM PST 23 75093497 ps
T798 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1089354555 Dec 31 12:44:28 PM PST 23 Dec 31 12:44:35 PM PST 23 9788933 ps
T799 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1002329377 Dec 31 12:43:51 PM PST 23 Dec 31 12:43:59 PM PST 23 120994688 ps
T800 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.346756212 Dec 31 12:44:12 PM PST 23 Dec 31 12:44:30 PM PST 23 303315943 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.999891897 Dec 31 12:44:49 PM PST 23 Dec 31 12:45:05 PM PST 23 256682989 ps
T802 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3736356722 Dec 31 12:44:12 PM PST 23 Dec 31 12:44:20 PM PST 23 8634044 ps
T803 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3489438099 Dec 31 12:44:26 PM PST 23 Dec 31 12:44:32 PM PST 23 20147750 ps
T168 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3718820049 Dec 31 12:44:05 PM PST 23 Dec 31 12:49:17 PM PST 23 2325519469 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3875882740 Dec 31 12:43:52 PM PST 23 Dec 31 12:44:01 PM PST 23 6376645 ps
T805 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3075656094 Dec 31 12:43:35 PM PST 23 Dec 31 12:43:41 PM PST 23 29207043 ps
T806 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1367301326 Dec 31 12:44:15 PM PST 23 Dec 31 12:44:42 PM PST 23 628224025 ps
T807 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.344628752 Dec 31 12:44:05 PM PST 23 Dec 31 12:44:16 PM PST 23 32776906 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.272284432 Dec 31 12:44:01 PM PST 23 Dec 31 12:44:33 PM PST 23 1030560018 ps
T809 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3882926760 Dec 31 12:44:09 PM PST 23 Dec 31 12:44:24 PM PST 23 150596794 ps
T810 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2184151148 Dec 31 12:43:57 PM PST 23 Dec 31 12:44:13 PM PST 23 44852240 ps
T368 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1694374171 Dec 31 12:44:17 PM PST 23 Dec 31 12:53:37 PM PST 23 16977999748 ps
T179 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3557897016 Dec 31 12:44:25 PM PST 23 Dec 31 12:52:11 PM PST 23 18360314786 ps
T811 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1669523721 Dec 31 12:44:21 PM PST 23 Dec 31 12:45:02 PM PST 23 8388773065 ps
T812 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1127996993 Dec 31 12:44:01 PM PST 23 Dec 31 12:44:25 PM PST 23 96937074 ps
T187 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4013111695 Dec 31 12:43:59 PM PST 23 Dec 31 12:44:13 PM PST 23 59117671 ps
T813 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.887278147 Dec 31 12:44:24 PM PST 23 Dec 31 12:44:33 PM PST 23 63214658 ps
T814 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.222118798 Dec 31 12:44:20 PM PST 23 Dec 31 12:44:25 PM PST 23 10308495 ps
T815 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3696977867 Dec 31 12:44:18 PM PST 23 Dec 31 12:44:26 PM PST 23 46174222 ps
T816 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4269606076 Dec 31 12:44:42 PM PST 23 Dec 31 12:44:50 PM PST 23 23007280 ps
T190 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3616741663 Dec 31 12:43:49 PM PST 23 Dec 31 12:45:13 PM PST 23 1431474666 ps
T817 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2801449205 Dec 31 12:44:19 PM PST 23 Dec 31 12:44:24 PM PST 23 6087497 ps
T818 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.250107986 Dec 31 12:44:08 PM PST 23 Dec 31 12:44:29 PM PST 23 167593827 ps
T819 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4116141355 Dec 31 12:44:40 PM PST 23 Dec 31 12:44:46 PM PST 23 10026414 ps
T820 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4133721850 Dec 31 12:44:16 PM PST 23 Dec 31 12:44:21 PM PST 23 13597325 ps
T821 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3119009790 Dec 31 12:44:04 PM PST 23 Dec 31 12:44:20 PM PST 23 35073275 ps
T822 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4135084350 Dec 31 12:43:49 PM PST 23 Dec 31 12:43:56 PM PST 23 165156417 ps
T823 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3881135660 Dec 31 12:44:17 PM PST 23 Dec 31 12:44:26 PM PST 23 124679151 ps
T172 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.186959866 Dec 31 12:44:02 PM PST 23 Dec 31 12:48:56 PM PST 23 14521363598 ps
T162 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.726295239 Dec 31 12:44:07 PM PST 23 Dec 31 12:49:44 PM PST 23 5687721566 ps
T824 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2097872686 Dec 31 12:44:36 PM PST 23 Dec 31 12:44:43 PM PST 23 14735684 ps
T825 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1337863664 Dec 31 12:44:41 PM PST 23 Dec 31 12:44:46 PM PST 23 8366438 ps
T826 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.870304752 Dec 31 12:44:18 PM PST 23 Dec 31 12:44:33 PM PST 23 166566285 ps
T827 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3033718655 Dec 31 12:44:25 PM PST 23 Dec 31 12:44:29 PM PST 23 46903739 ps
T178 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1422051986 Dec 31 12:44:22 PM PST 23 Dec 31 12:49:01 PM PST 23 2509123608 ps
T176 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1500252315 Dec 31 12:44:14 PM PST 23 Dec 31 12:53:12 PM PST 23 7787294164 ps
T828 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.444109350 Dec 31 12:44:18 PM PST 23 Dec 31 12:44:27 PM PST 23 99304896 ps
T163 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2009992734 Dec 31 12:43:56 PM PST 23 Dec 31 12:54:39 PM PST 23 23458589636 ps
T167 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2267298341 Dec 31 12:44:08 PM PST 23 Dec 31 12:47:47 PM PST 23 5894412175 ps
T829 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.121031688 Dec 31 12:44:00 PM PST 23 Dec 31 12:44:13 PM PST 23 33009411 ps
T370 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.22202472 Dec 31 12:44:15 PM PST 23 Dec 31 01:01:05 PM PST 23 83766586671 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2360497056 Dec 31 12:44:24 PM PST 23 Dec 31 12:47:36 PM PST 23 3142780946 ps
T831 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3668138994 Dec 31 12:44:27 PM PST 23 Dec 31 12:44:33 PM PST 23 11415932 ps
T832 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1916917603 Dec 31 12:44:07 PM PST 23 Dec 31 12:44:21 PM PST 23 130588153 ps
T833 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.436860858 Dec 31 12:44:17 PM PST 23 Dec 31 12:44:22 PM PST 23 9662599 ps
T177 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2371920030 Dec 31 12:43:59 PM PST 23 Dec 31 12:47:25 PM PST 23 6660330081 ps
T834 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1988384437 Dec 31 12:43:46 PM PST 23 Dec 31 12:43:49 PM PST 23 9313588 ps
T192 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1327525320 Dec 31 12:43:34 PM PST 23 Dec 31 12:43:40 PM PST 23 216711655 ps
T835 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.443255917 Dec 31 12:44:21 PM PST 23 Dec 31 12:44:34 PM PST 23 93036510 ps
T836 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1950142644 Dec 31 12:44:13 PM PST 23 Dec 31 12:44:22 PM PST 23 22422185 ps
T837 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2380925820 Dec 31 12:44:23 PM PST 23 Dec 31 12:44:28 PM PST 23 9832722 ps
T170 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.577123486 Dec 31 12:44:05 PM PST 23 Dec 31 12:47:04 PM PST 23 29587983477 ps
T838 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3193752800 Dec 31 12:44:42 PM PST 23 Dec 31 12:45:17 PM PST 23 5125938591 ps
T839 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2551012831 Dec 31 12:44:34 PM PST 23 Dec 31 12:44:43 PM PST 23 168647818 ps
T369 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.451129364 Dec 31 12:44:09 PM PST 23 Dec 31 12:52:26 PM PST 23 33172322832 ps
T840 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3646408858 Dec 31 12:44:14 PM PST 23 Dec 31 12:44:24 PM PST 23 59548872 ps
T841 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.523856134 Dec 31 12:43:41 PM PST 23 Dec 31 12:43:55 PM PST 23 419798790 ps
T842 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.957210136 Dec 31 12:43:49 PM PST 23 Dec 31 12:49:41 PM PST 23 22833600695 ps
T197 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3916719574 Dec 31 12:43:47 PM PST 23 Dec 31 12:43:51 PM PST 23 50188313 ps
T843 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2065142728 Dec 31 12:44:07 PM PST 23 Dec 31 12:44:19 PM PST 23 8231891 ps
T844 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.597449648 Dec 31 12:44:30 PM PST 23 Dec 31 12:44:37 PM PST 23 8752099 ps
T845 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4048256987 Dec 31 12:44:03 PM PST 23 Dec 31 12:44:32 PM PST 23 312123490 ps
T846 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1524805888 Dec 31 12:44:16 PM PST 23 Dec 31 12:44:21 PM PST 23 20276586 ps
T847 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4205243372 Dec 31 12:43:56 PM PST 23 Dec 31 12:44:18 PM PST 23 274352287 ps

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.718090901
Short name T15
Test name
Test status
Simulation time 11257518 ps
CPU time 1.31 seconds
Started Dec 31 12:44:26 PM PST 23
Finished Dec 31 12:44:32 PM PST 23
Peak memory 235552 kb
Host smart-2a4a1509-a314-4aaf-8f55-51ac0c3a9b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=718090901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.718090901
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.372312015
Short name T7
Test name
Test status
Simulation time 35289455656 ps
CPU time 2122 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 02:08:15 PM PST 23
Peak memory 289008 kb
Host smart-2f81f858-8212-4a9f-a062-dc2fa2c4e33b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372312015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.372312015
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.282106369
Short name T143
Test name
Test status
Simulation time 498057424 ps
CPU time 34.97 seconds
Started Dec 31 12:44:33 PM PST 23
Finished Dec 31 12:45:14 PM PST 23
Peak memory 239188 kb
Host smart-4e1f876c-5603-4ca5-ace0-c0750f4f4a46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=282106369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.282106369
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1090603293
Short name T27
Test name
Test status
Simulation time 44473408596 ps
CPU time 2395.4 seconds
Started Dec 31 01:33:36 PM PST 23
Finished Dec 31 02:13:32 PM PST 23
Peak memory 289624 kb
Host smart-cdf57a38-5b14-41de-9f91-3acfe39ae9a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090603293 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1090603293
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.120709675
Short name T21
Test name
Test status
Simulation time 3325170958 ps
CPU time 177.38 seconds
Started Dec 31 12:44:26 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 265284 kb
Host smart-2fd1021d-c797-4cd7-a8ab-a7f6384251af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=120709675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.120709675
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3097927075
Short name T4
Test name
Test status
Simulation time 8173381603 ps
CPU time 18.09 seconds
Started Dec 31 01:31:30 PM PST 23
Finished Dec 31 01:31:49 PM PST 23
Peak memory 240472 kb
Host smart-3beac267-848a-463a-89ad-3c2934286dd6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3097927075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3097927075
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2772207909
Short name T25
Test name
Test status
Simulation time 50561464754 ps
CPU time 1405.54 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:56:27 PM PST 23
Peak memory 266016 kb
Host smart-b36502da-62d5-4478-9bc4-d4767a2880d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772207909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2772207909
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.877991605
Short name T10
Test name
Test status
Simulation time 553359017 ps
CPU time 13.27 seconds
Started Dec 31 01:31:29 PM PST 23
Finished Dec 31 01:31:43 PM PST 23
Peak memory 273456 kb
Host smart-a25f6e56-48e0-4e7c-90f0-931451ce602b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=877991605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.877991605
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3949854731
Short name T144
Test name
Test status
Simulation time 32836127631 ps
CPU time 1148 seconds
Started Dec 31 12:43:52 PM PST 23
Finished Dec 31 01:03:07 PM PST 23
Peak memory 265456 kb
Host smart-29f65e18-af70-4c63-893b-363a127a607e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949854731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3949854731
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.23374441
Short name T122
Test name
Test status
Simulation time 42313986518 ps
CPU time 2326.31 seconds
Started Dec 31 01:33:00 PM PST 23
Finished Dec 31 02:11:47 PM PST 23
Peak memory 289212 kb
Host smart-57ff94e6-4751-492c-8090-cfc872168992
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23374441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.23374441
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.944320195
Short name T3
Test name
Test status
Simulation time 33381851513 ps
CPU time 1830.39 seconds
Started Dec 31 01:34:26 PM PST 23
Finished Dec 31 02:04:59 PM PST 23
Peak memory 272288 kb
Host smart-0e72065c-250e-448e-8497-b87728c61da2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944320195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.944320195
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1035492052
Short name T150
Test name
Test status
Simulation time 6825674422 ps
CPU time 201.64 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 265284 kb
Host smart-2a2c6a01-920f-4d9d-bdd3-9442b7afca75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1035492052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1035492052
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.134206211
Short name T5
Test name
Test status
Simulation time 366303421741 ps
CPU time 1703.17 seconds
Started Dec 31 01:34:52 PM PST 23
Finished Dec 31 02:03:20 PM PST 23
Peak memory 269276 kb
Host smart-f67aea18-6291-436e-b086-0665868bcea5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134206211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.134206211
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.178767802
Short name T60
Test name
Test status
Simulation time 140527049988 ps
CPU time 3698.68 seconds
Started Dec 31 01:33:36 PM PST 23
Finished Dec 31 02:35:16 PM PST 23
Peak memory 303716 kb
Host smart-03002ab4-0d6f-4678-b5be-d95565cdb0f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178767802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.178767802
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3217119762
Short name T159
Test name
Test status
Simulation time 16300227304 ps
CPU time 1114.56 seconds
Started Dec 31 12:44:03 PM PST 23
Finished Dec 31 01:02:48 PM PST 23
Peak memory 265348 kb
Host smart-8c73ce90-9236-4d18-a17e-d94c82722c05
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217119762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3217119762
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3881450105
Short name T307
Test name
Test status
Simulation time 37069814548 ps
CPU time 1926.83 seconds
Started Dec 31 01:31:19 PM PST 23
Finished Dec 31 02:03:30 PM PST 23
Peak memory 282980 kb
Host smart-135514f2-b716-427f-aeed-a95d01f7fce7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881450105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3881450105
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1106362961
Short name T38
Test name
Test status
Simulation time 14762709858 ps
CPU time 575.88 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 01:43:43 PM PST 23
Peak memory 247244 kb
Host smart-52cff846-1769-4c00-9ca8-8ae6a4c734b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106362961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1106362961
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3148947365
Short name T183
Test name
Test status
Simulation time 574891683 ps
CPU time 31.61 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 240300 kb
Host smart-453f1523-6845-4495-9eca-ca00de1de592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3148947365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3148947365
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3453391596
Short name T95
Test name
Test status
Simulation time 169748302093 ps
CPU time 2121.75 seconds
Started Dec 31 01:34:09 PM PST 23
Finished Dec 31 02:09:33 PM PST 23
Peak memory 289708 kb
Host smart-398dd336-e4b3-4109-a49b-f78271917944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453391596 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3453391596
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2000337000
Short name T341
Test name
Test status
Simulation time 128314628525 ps
CPU time 2912.7 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 02:21:37 PM PST 23
Peak memory 287316 kb
Host smart-713a5b59-36c1-4504-a273-3bd5f3c2de80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000337000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2000337000
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3198476433
Short name T153
Test name
Test status
Simulation time 23798086008 ps
CPU time 931.99 seconds
Started Dec 31 12:43:56 PM PST 23
Finished Dec 31 12:59:41 PM PST 23
Peak memory 265552 kb
Host smart-fbf69c15-f8b0-4191-b145-5c87d094a06b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198476433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3198476433
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4123476950
Short name T49
Test name
Test status
Simulation time 62432126136 ps
CPU time 627.47 seconds
Started Dec 31 01:32:22 PM PST 23
Finished Dec 31 01:42:54 PM PST 23
Peak memory 246576 kb
Host smart-bc5ed228-9edf-47e1-b46a-438dc1ea472f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123476950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4123476950
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2267298341
Short name T167
Test name
Test status
Simulation time 5894412175 ps
CPU time 210.14 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 266372 kb
Host smart-6a92c4c6-c2f7-4531-9243-2733fbdc1a2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2267298341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2267298341
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3554215297
Short name T67
Test name
Test status
Simulation time 134221142665 ps
CPU time 3536.39 seconds
Started Dec 31 01:32:54 PM PST 23
Finished Dec 31 02:31:51 PM PST 23
Peak memory 353876 kb
Host smart-5b070a4e-a73b-44d8-871d-f180eb1d2bb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554215297 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3554215297
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3026092819
Short name T297
Test name
Test status
Simulation time 19141573294 ps
CPU time 516.56 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:41:40 PM PST 23
Peak memory 247556 kb
Host smart-8ada9a75-0a8c-4348-9d6b-24f59efeb37c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026092819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3026092819
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2557069719
Short name T148
Test name
Test status
Simulation time 23305008482 ps
CPU time 954.76 seconds
Started Dec 31 12:44:07 PM PST 23
Finished Dec 31 01:00:14 PM PST 23
Peak memory 265444 kb
Host smart-94154c8a-d4aa-4f6e-8e09-6517ce0ae070
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557069719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2557069719
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3021552340
Short name T26
Test name
Test status
Simulation time 53298754193 ps
CPU time 2741.37 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 02:19:42 PM PST 23
Peak memory 288668 kb
Host smart-d1cd4823-8dc8-4731-8856-182be62c40d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021552340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3021552340
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3031402862
Short name T300
Test name
Test status
Simulation time 122726796014 ps
CPU time 1696.2 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 02:01:46 PM PST 23
Peak memory 272152 kb
Host smart-0029eede-28a4-4529-a3c0-21b2da2c168c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031402862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3031402862
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4294271314
Short name T585
Test name
Test status
Simulation time 7215983690 ps
CPU time 294.03 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:39:00 PM PST 23
Peak memory 247588 kb
Host smart-0788deb0-39f8-434d-a81d-2e409fadfb15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294271314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4294271314
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2211523018
Short name T40
Test name
Test status
Simulation time 13686835545 ps
CPU time 1236.54 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 01:54:19 PM PST 23
Peak memory 288892 kb
Host smart-c7b32663-4560-4d64-af0e-94f041d0c759
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211523018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2211523018
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.818554697
Short name T348
Test name
Test status
Simulation time 45417108178 ps
CPU time 2379.5 seconds
Started Dec 31 01:32:22 PM PST 23
Finished Dec 31 02:12:07 PM PST 23
Peak memory 273124 kb
Host smart-cdbe5e51-4e7c-4dd6-a25c-7dddb41df50f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818554697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.818554697
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2346005718
Short name T151
Test name
Test status
Simulation time 5114182472 ps
CPU time 318.71 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:49:46 PM PST 23
Peak memory 265248 kb
Host smart-152a87c9-f175-416f-a5e3-e53121ca3d04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2346005718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2346005718
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.875203905
Short name T302
Test name
Test status
Simulation time 16340024589 ps
CPU time 322.48 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:39:07 PM PST 23
Peak memory 248320 kb
Host smart-861ab12e-f142-4bfa-a80c-9a61e4105488
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875203905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.875203905
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1611901565
Short name T495
Test name
Test status
Simulation time 177451358664 ps
CPU time 3830.35 seconds
Started Dec 31 01:33:07 PM PST 23
Finished Dec 31 02:36:59 PM PST 23
Peak memory 322632 kb
Host smart-b3533d21-fd9d-43e4-aeea-2fa7271e7a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611901565 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1611901565
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2666023229
Short name T23
Test name
Test status
Simulation time 19868563 ps
CPU time 1.34 seconds
Started Dec 31 12:44:03 PM PST 23
Finished Dec 31 12:44:14 PM PST 23
Peak memory 235524 kb
Host smart-f9a037a1-767b-43e4-a352-68e28e4cbeea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2666023229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2666023229
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.675454475
Short name T267
Test name
Test status
Simulation time 74116106880 ps
CPU time 4084.21 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 02:41:08 PM PST 23
Peak memory 305792 kb
Host smart-4f09f77e-1833-4183-b7d1-5bdfcf7dc5f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675454475 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.675454475
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2824066755
Short name T152
Test name
Test status
Simulation time 3251104704 ps
CPU time 325.56 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:49:48 PM PST 23
Peak memory 265264 kb
Host smart-317a6125-a23f-4d7e-b917-6d0b6077970b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824066755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2824066755
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.22202472
Short name T370
Test name
Test status
Simulation time 83766586671 ps
CPU time 1005.64 seconds
Started Dec 31 12:44:15 PM PST 23
Finished Dec 31 01:01:05 PM PST 23
Peak memory 265520 kb
Host smart-ff1938c0-2590-40e7-ac9d-1a6c3181858c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22202472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.22202472
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2107892480
Short name T282
Test name
Test status
Simulation time 29138050348 ps
CPU time 1641.96 seconds
Started Dec 31 01:32:48 PM PST 23
Finished Dec 31 02:00:10 PM PST 23
Peak memory 273300 kb
Host smart-881ba7ae-374f-4b9c-a565-ac3cea03bad3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107892480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2107892480
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3488370991
Short name T119
Test name
Test status
Simulation time 201150634327 ps
CPU time 2963.16 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 02:21:39 PM PST 23
Peak memory 304924 kb
Host smart-1a629a7d-1bc0-43d8-b204-55c1fb9ec969
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488370991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3488370991
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.988370117
Short name T71
Test name
Test status
Simulation time 256750784976 ps
CPU time 3584.12 seconds
Started Dec 31 01:32:59 PM PST 23
Finished Dec 31 02:32:45 PM PST 23
Peak memory 297840 kb
Host smart-2e839e08-249a-4d45-8ad4-3ae2a488e217
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988370117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.988370117
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2405602575
Short name T130
Test name
Test status
Simulation time 614498159567 ps
CPU time 6834.33 seconds
Started Dec 31 01:33:22 PM PST 23
Finished Dec 31 03:27:17 PM PST 23
Peak memory 355032 kb
Host smart-2235a4c1-5a73-4e02-aa99-a3fdf20601b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405602575 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2405602575
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.428127205
Short name T22
Test name
Test status
Simulation time 176141872 ps
CPU time 3.31 seconds
Started Dec 31 12:43:49 PM PST 23
Finished Dec 31 12:43:57 PM PST 23
Peak memory 236356 kb
Host smart-364c3566-6a60-4899-a233-ef36d7059cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=428127205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.428127205
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3016658293
Short name T132
Test name
Test status
Simulation time 46248640584 ps
CPU time 4556.97 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 02:50:13 PM PST 23
Peak memory 338984 kb
Host smart-8ff85b6b-50d8-4ced-98d4-0638f5cbf65a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016658293 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3016658293
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2065614070
Short name T19
Test name
Test status
Simulation time 399995282 ps
CPU time 5.06 seconds
Started Dec 31 12:43:50 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 240400 kb
Host smart-ea7c01b8-d4b9-4b68-9bb1-27f5c71e660f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065614070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2065614070
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2821878093
Short name T210
Test name
Test status
Simulation time 14455024 ps
CPU time 2.35 seconds
Started Dec 31 01:31:09 PM PST 23
Finished Dec 31 01:31:20 PM PST 23
Peak memory 248804 kb
Host smart-12a4068c-509f-4fa4-ae93-aa62eab5c8d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2821878093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2821878093
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1539925545
Short name T211
Test name
Test status
Simulation time 67605686 ps
CPU time 2.84 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 01:32:09 PM PST 23
Peak memory 248852 kb
Host smart-d6698234-4fe9-4799-b02e-c74e3b5168bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1539925545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1539925545
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3908691243
Short name T205
Test name
Test status
Simulation time 114488401 ps
CPU time 2.67 seconds
Started Dec 31 01:32:24 PM PST 23
Finished Dec 31 01:32:29 PM PST 23
Peak memory 248604 kb
Host smart-4c68029e-f09b-472f-8311-a6b77fda28ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3908691243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3908691243
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4081659536
Short name T202
Test name
Test status
Simulation time 32824446 ps
CPU time 3.15 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:33:48 PM PST 23
Peak memory 248872 kb
Host smart-edff03e0-4b06-4281-bc36-76dc4af99bdc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4081659536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4081659536
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3363851477
Short name T371
Test name
Test status
Simulation time 19929281 ps
CPU time 1.9 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 236376 kb
Host smart-fd16b438-b236-48d8-a7e5-fef7ced2a410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363851477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3363851477
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3152635157
Short name T316
Test name
Test status
Simulation time 41251174209 ps
CPU time 2449.05 seconds
Started Dec 31 01:31:29 PM PST 23
Finished Dec 31 02:12:19 PM PST 23
Peak memory 285908 kb
Host smart-a957e0b5-0ecb-408c-b3a0-0719e981d5b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152635157 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3152635157
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.561576502
Short name T30
Test name
Test status
Simulation time 97226618952 ps
CPU time 5431.6 seconds
Started Dec 31 01:34:18 PM PST 23
Finished Dec 31 03:04:51 PM PST 23
Peak memory 298008 kb
Host smart-8697144d-aabb-480e-a270-22d1cf9a9504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561576502 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.561576502
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3504794883
Short name T359
Test name
Test status
Simulation time 28569447148 ps
CPU time 1522.19 seconds
Started Dec 31 01:34:16 PM PST 23
Finished Dec 31 01:59:40 PM PST 23
Peak memory 288548 kb
Host smart-0e2ec791-02e2-4007-b478-05790eb4cdc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504794883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3504794883
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2641222982
Short name T330
Test name
Test status
Simulation time 134580357802 ps
CPU time 2809.51 seconds
Started Dec 31 01:32:19 PM PST 23
Finished Dec 31 02:19:14 PM PST 23
Peak memory 289016 kb
Host smart-d114b793-17cf-4bf2-a21d-6d5c54e68347
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641222982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2641222982
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.902713363
Short name T99
Test name
Test status
Simulation time 3606527418 ps
CPU time 31.15 seconds
Started Dec 31 01:33:25 PM PST 23
Finished Dec 31 01:33:57 PM PST 23
Peak memory 248612 kb
Host smart-693ab098-1f23-41ea-9116-fd52d1dbe0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90271
3363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.902713363
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2506745810
Short name T289
Test name
Test status
Simulation time 34589940771 ps
CPU time 348.5 seconds
Started Dec 31 01:34:22 PM PST 23
Finished Dec 31 01:40:13 PM PST 23
Peak memory 247580 kb
Host smart-c4fbf2b0-f697-4c2e-85b6-cdadb2c8efb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506745810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2506745810
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2921529808
Short name T318
Test name
Test status
Simulation time 78580909301 ps
CPU time 3936.81 seconds
Started Dec 31 01:33:06 PM PST 23
Finished Dec 31 02:38:43 PM PST 23
Peak memory 304864 kb
Host smart-e5857e00-d15b-4580-8cd3-9e82a8ca5e34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921529808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2921529808
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1121166725
Short name T14
Test name
Test status
Simulation time 22372072829 ps
CPU time 1094.25 seconds
Started Dec 31 01:30:51 PM PST 23
Finished Dec 31 01:49:11 PM PST 23
Peak memory 272832 kb
Host smart-d5080a77-f489-4e75-aef8-4d76ddc5bdee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121166725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1121166725
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2211476893
Short name T117
Test name
Test status
Simulation time 6358468538 ps
CPU time 522.44 seconds
Started Dec 31 01:34:17 PM PST 23
Finished Dec 31 01:43:01 PM PST 23
Peak memory 269968 kb
Host smart-d75efa0d-931b-4c49-a563-9cab87bc56b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211476893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2211476893
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2539022302
Short name T277
Test name
Test status
Simulation time 15000650113 ps
CPU time 710.41 seconds
Started Dec 31 01:33:35 PM PST 23
Finished Dec 31 01:45:26 PM PST 23
Peak memory 273088 kb
Host smart-34b0f007-e8c7-453f-b265-30348952d7e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539022302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2539022302
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2237435967
Short name T169
Test name
Test status
Simulation time 49991229223 ps
CPU time 922.09 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:59:47 PM PST 23
Peak memory 265336 kb
Host smart-cffc4abd-7f45-4950-8f30-b166fb277532
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237435967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2237435967
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1569000186
Short name T155
Test name
Test status
Simulation time 18481226359 ps
CPU time 285.94 seconds
Started Dec 31 12:44:13 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 265240 kb
Host smart-417c3a49-4dd4-42ee-b2d1-49cf780793ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1569000186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1569000186
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1327525320
Short name T192
Test name
Test status
Simulation time 216711655 ps
CPU time 3.85 seconds
Started Dec 31 12:43:34 PM PST 23
Finished Dec 31 12:43:40 PM PST 23
Peak memory 236348 kb
Host smart-0cec7227-18b6-4ec5-83f2-2d9699b0d5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1327525320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1327525320
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1694374171
Short name T368
Test name
Test status
Simulation time 16977999748 ps
CPU time 557.22 seconds
Started Dec 31 12:44:17 PM PST 23
Finished Dec 31 12:53:37 PM PST 23
Peak memory 265228 kb
Host smart-e7f3157a-c1fd-44c3-9455-953a40f21ee3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694374171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1694374171
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2030071853
Short name T264
Test name
Test status
Simulation time 7151066084 ps
CPU time 729.53 seconds
Started Dec 31 01:34:08 PM PST 23
Finished Dec 31 01:46:19 PM PST 23
Peak memory 272504 kb
Host smart-bfbf2e4e-9e85-4c5b-95df-22402ed8fe58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030071853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2030071853
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.194906864
Short name T528
Test name
Test status
Simulation time 20739075468 ps
CPU time 1950.28 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 02:06:38 PM PST 23
Peak memory 306092 kb
Host smart-bd3f04ba-063e-4d1b-93ba-d3d2fc6b6a58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194906864 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.194906864
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.804775055
Short name T319
Test name
Test status
Simulation time 3125701342 ps
CPU time 46.64 seconds
Started Dec 31 01:33:05 PM PST 23
Finished Dec 31 01:33:52 PM PST 23
Peak memory 248524 kb
Host smart-8cb3cfc2-bc33-4d3b-b581-ea92cc1946e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80477
5055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.804775055
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2906016631
Short name T8
Test name
Test status
Simulation time 80506436622 ps
CPU time 1288.26 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:55:34 PM PST 23
Peak memory 288648 kb
Host smart-11402ff5-7f71-4560-a500-0c3f6c2bfad7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906016631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2906016631
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.183848487
Short name T278
Test name
Test status
Simulation time 19550642492 ps
CPU time 1929.61 seconds
Started Dec 31 01:34:22 PM PST 23
Finished Dec 31 02:06:34 PM PST 23
Peak memory 305936 kb
Host smart-78144d61-68f3-4be3-99bb-bf1fffa3ef22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183848487 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.183848487
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2274729628
Short name T259
Test name
Test status
Simulation time 177822199394 ps
CPU time 2558.5 seconds
Started Dec 31 01:34:42 PM PST 23
Finished Dec 31 02:17:23 PM PST 23
Peak memory 297804 kb
Host smart-d0b05fa4-de67-4c6d-b0b5-e6fe94450231
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274729628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2274729628
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4170563841
Short name T324
Test name
Test status
Simulation time 1087885970 ps
CPU time 31.9 seconds
Started Dec 31 01:32:55 PM PST 23
Finished Dec 31 01:33:27 PM PST 23
Peak memory 255008 kb
Host smart-321aaac7-280c-4144-b50a-7e2cceeb78f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41705
63841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4170563841
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.106637413
Short name T338
Test name
Test status
Simulation time 4390132125 ps
CPU time 392.57 seconds
Started Dec 31 01:33:02 PM PST 23
Finished Dec 31 01:39:35 PM PST 23
Peak memory 265096 kb
Host smart-23a9fb76-9166-4746-979f-eb0df0e3a174
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106637413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.106637413
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2384918134
Short name T346
Test name
Test status
Simulation time 59057269786 ps
CPU time 1470.89 seconds
Started Dec 31 01:34:28 PM PST 23
Finished Dec 31 01:59:01 PM PST 23
Peak memory 271428 kb
Host smart-68738d01-6412-4767-ae65-a14ccbe4b46f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384918134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2384918134
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.834514423
Short name T333
Test name
Test status
Simulation time 152374443627 ps
CPU time 4434.98 seconds
Started Dec 31 01:33:24 PM PST 23
Finished Dec 31 02:47:20 PM PST 23
Peak memory 317580 kb
Host smart-b7ba29a8-8d59-4371-a4f9-65ad6212be03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834514423 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.834514423
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.241402091
Short name T332
Test name
Test status
Simulation time 201368786364 ps
CPU time 3106.82 seconds
Started Dec 31 01:32:55 PM PST 23
Finished Dec 31 02:24:43 PM PST 23
Peak memory 305204 kb
Host smart-6003887d-ff56-4c8b-93a0-f124e2c78008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241402091 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.241402091
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1185776006
Short name T134
Test name
Test status
Simulation time 717006208 ps
CPU time 22.86 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:32:43 PM PST 23
Peak memory 246884 kb
Host smart-8b045faa-5eed-4a89-be66-800fc7dc5538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11857
76006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1185776006
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1214494169
Short name T36
Test name
Test status
Simulation time 1084719467 ps
CPU time 19.33 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:32:39 PM PST 23
Peak memory 254640 kb
Host smart-8f5a1fc4-98b1-4d3a-b47f-9a7a91896acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
94169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1214494169
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1405748597
Short name T191
Test name
Test status
Simulation time 1302360620 ps
CPU time 82.74 seconds
Started Dec 31 12:43:56 PM PST 23
Finished Dec 31 12:45:32 PM PST 23
Peak memory 239412 kb
Host smart-e7fcec20-b63c-45ad-b0ed-3988b920e2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1405748597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1405748597
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.726295239
Short name T162
Test name
Test status
Simulation time 5687721566 ps
CPU time 327.17 seconds
Started Dec 31 12:44:07 PM PST 23
Finished Dec 31 12:49:44 PM PST 23
Peak memory 265284 kb
Host smart-1cf4aa0c-4d00-4d1c-9158-664a03109f49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=726295239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.726295239
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3754414079
Short name T127
Test name
Test status
Simulation time 122523431 ps
CPU time 3.02 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:55 PM PST 23
Peak memory 237392 kb
Host smart-97eec4ec-26fa-4ebb-a9b3-13661b21c808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3754414079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3754414079
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.351343437
Short name T188
Test name
Test status
Simulation time 65735759 ps
CPU time 4.38 seconds
Started Dec 31 12:44:22 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 236384 kb
Host smart-bdccb0ce-8968-4d8b-8fd6-382982fe358e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=351343437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.351343437
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2086596037
Short name T196
Test name
Test status
Simulation time 3694520691 ps
CPU time 60.8 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:45:25 PM PST 23
Peak memory 248596 kb
Host smart-aaaced71-904d-45f3-b849-f8feadcb4bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2086596037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2086596037
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2274887730
Short name T126
Test name
Test status
Simulation time 79279153 ps
CPU time 4.63 seconds
Started Dec 31 12:44:27 PM PST 23
Finished Dec 31 12:44:35 PM PST 23
Peak memory 236780 kb
Host smart-be54f8e9-d5a8-48ec-b206-e7108991843c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2274887730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2274887730
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4013111695
Short name T187
Test name
Test status
Simulation time 59117671 ps
CPU time 3.72 seconds
Started Dec 31 12:43:59 PM PST 23
Finished Dec 31 12:44:13 PM PST 23
Peak memory 236376 kb
Host smart-cd1a721b-da18-4848-b73f-c87b3907b533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4013111695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4013111695
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3711909402
Short name T193
Test name
Test status
Simulation time 49704131 ps
CPU time 3.34 seconds
Started Dec 31 12:44:32 PM PST 23
Finished Dec 31 12:44:41 PM PST 23
Peak memory 235464 kb
Host smart-6ad7f283-93e1-4510-8eb9-bf200e177117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3711909402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3711909402
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3916719574
Short name T197
Test name
Test status
Simulation time 50188313 ps
CPU time 2.96 seconds
Started Dec 31 12:43:47 PM PST 23
Finished Dec 31 12:43:51 PM PST 23
Peak memory 236660 kb
Host smart-34ada7f2-cebb-4d69-bbad-561ee7342405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3916719574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3916719574
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2649970364
Short name T195
Test name
Test status
Simulation time 1126611533 ps
CPU time 71.16 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:45:28 PM PST 23
Peak memory 244872 kb
Host smart-c327deda-1324-4714-a25c-c0ac8a777952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2649970364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2649970364
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4067361926
Short name T31
Test name
Test status
Simulation time 51923003429 ps
CPU time 2585.86 seconds
Started Dec 31 01:32:19 PM PST 23
Finished Dec 31 02:15:31 PM PST 23
Peak memory 289328 kb
Host smart-0ca2e6df-0268-41b3-bb67-395dd47168d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067361926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4067361926
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.432599571
Short name T761
Test name
Test status
Simulation time 987046352 ps
CPU time 71.25 seconds
Started Dec 31 12:44:10 PM PST 23
Finished Dec 31 12:45:30 PM PST 23
Peak memory 236368 kb
Host smart-50068801-554b-4214-bd4e-016b04da3b4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=432599571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.432599571
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.957210136
Short name T842
Test name
Test status
Simulation time 22833600695 ps
CPU time 349.2 seconds
Started Dec 31 12:43:49 PM PST 23
Finished Dec 31 12:49:41 PM PST 23
Peak memory 240404 kb
Host smart-9cf6dfe2-ebf7-448d-b4a6-e55c0782a04b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=957210136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.957210136
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2183666586
Short name T744
Test name
Test status
Simulation time 73887403 ps
CPU time 5.87 seconds
Started Dec 31 12:43:51 PM PST 23
Finished Dec 31 12:44:00 PM PST 23
Peak memory 240328 kb
Host smart-529df53c-46ad-4728-8476-71ca0fe09cbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2183666586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2183666586
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2055453221
Short name T754
Test name
Test status
Simulation time 53478700 ps
CPU time 3.28 seconds
Started Dec 31 12:43:34 PM PST 23
Finished Dec 31 12:43:40 PM PST 23
Peak memory 239516 kb
Host smart-57c4de87-6cfa-451e-a79f-f296d8ad1331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055453221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2055453221
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.523856134
Short name T841
Test name
Test status
Simulation time 419798790 ps
CPU time 8 seconds
Started Dec 31 12:43:41 PM PST 23
Finished Dec 31 12:43:55 PM PST 23
Peak memory 235512 kb
Host smart-dc2125fc-f2fe-4d9a-a6dc-0ea8ec027d37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=523856134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.523856134
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2065142728
Short name T843
Test name
Test status
Simulation time 8231891 ps
CPU time 1.45 seconds
Started Dec 31 12:44:07 PM PST 23
Finished Dec 31 12:44:19 PM PST 23
Peak memory 236488 kb
Host smart-0af701f8-d134-4f81-9e04-1378280dc71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065142728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2065142728
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.458156339
Short name T740
Test name
Test status
Simulation time 660284945 ps
CPU time 19.96 seconds
Started Dec 31 12:43:45 PM PST 23
Finished Dec 31 12:44:06 PM PST 23
Peak memory 240336 kb
Host smart-c1f40e57-6ced-4bd7-a0b5-53627b9986cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=458156339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.458156339
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3820978098
Short name T156
Test name
Test status
Simulation time 2115507891 ps
CPU time 138.73 seconds
Started Dec 31 12:44:06 PM PST 23
Finished Dec 31 12:46:36 PM PST 23
Peak memory 265172 kb
Host smart-12ff25b4-3946-4874-9bf9-12af4850096c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3820978098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3820978098
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1500252315
Short name T176
Test name
Test status
Simulation time 7787294164 ps
CPU time 533.21 seconds
Started Dec 31 12:44:14 PM PST 23
Finished Dec 31 12:53:12 PM PST 23
Peak memory 265312 kb
Host smart-b3216fdf-b65a-4103-83e7-409a8f6f0670
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500252315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1500252315
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.717445794
Short name T198
Test name
Test status
Simulation time 21077705820 ps
CPU time 294.48 seconds
Started Dec 31 12:43:42 PM PST 23
Finished Dec 31 12:48:38 PM PST 23
Peak memory 237476 kb
Host smart-7314e74c-6cfb-415c-a76f-b46fcbcdf309
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=717445794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.717445794
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2441589321
Short name T751
Test name
Test status
Simulation time 2857410863 ps
CPU time 175.99 seconds
Started Dec 31 12:43:36 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 236396 kb
Host smart-a7edb865-36f5-484a-8f43-41c5b5c73d65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2441589321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2441589321
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.145706749
Short name T791
Test name
Test status
Simulation time 76192723 ps
CPU time 6.31 seconds
Started Dec 31 12:44:31 PM PST 23
Finished Dec 31 12:44:43 PM PST 23
Peak memory 240372 kb
Host smart-790aa58e-0cb6-46bf-aae5-598c331dba37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=145706749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.145706749
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3075656094
Short name T805
Test name
Test status
Simulation time 29207043 ps
CPU time 3.27 seconds
Started Dec 31 12:43:35 PM PST 23
Finished Dec 31 12:43:41 PM PST 23
Peak memory 240348 kb
Host smart-9c359fbf-765b-4f73-af70-36b4e57f4a75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075656094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3075656094
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3435129756
Short name T753
Test name
Test status
Simulation time 48605457 ps
CPU time 4.52 seconds
Started Dec 31 12:43:50 PM PST 23
Finished Dec 31 12:43:58 PM PST 23
Peak memory 235480 kb
Host smart-8e1658c5-7a1a-4622-a2e3-e72c4afa93ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3435129756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3435129756
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3875882740
Short name T804
Test name
Test status
Simulation time 6376645 ps
CPU time 1.38 seconds
Started Dec 31 12:43:52 PM PST 23
Finished Dec 31 12:44:01 PM PST 23
Peak memory 236392 kb
Host smart-fe9b15da-7525-407e-bba2-83b77899a9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875882740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3875882740
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3572189214
Short name T171
Test name
Test status
Simulation time 92954939 ps
CPU time 12.4 seconds
Started Dec 31 12:43:42 PM PST 23
Finished Dec 31 12:43:56 PM PST 23
Peak memory 240292 kb
Host smart-0c8b9266-4082-43d4-bea8-1cd923d37b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3572189214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3572189214
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.577123486
Short name T170
Test name
Test status
Simulation time 29587983477 ps
CPU time 168.67 seconds
Started Dec 31 12:44:05 PM PST 23
Finished Dec 31 12:47:04 PM PST 23
Peak memory 265440 kb
Host smart-7b87958b-1bc6-4177-ac24-1e7a4331b8e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=577123486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.577123486
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.808873589
Short name T24
Test name
Test status
Simulation time 1035594881 ps
CPU time 11.11 seconds
Started Dec 31 12:43:28 PM PST 23
Finished Dec 31 12:43:40 PM PST 23
Peak memory 251884 kb
Host smart-85104dfb-3a01-458b-b247-ce54edb31f98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=808873589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.808873589
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3894143232
Short name T772
Test name
Test status
Simulation time 245770658 ps
CPU time 4.56 seconds
Started Dec 31 12:43:55 PM PST 23
Finished Dec 31 12:44:14 PM PST 23
Peak memory 240400 kb
Host smart-3b87715c-b2eb-47db-bc4f-301ce6ebc82e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894143232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3894143232
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.887473519
Short name T774
Test name
Test status
Simulation time 471908621 ps
CPU time 7.95 seconds
Started Dec 31 12:44:06 PM PST 23
Finished Dec 31 12:44:25 PM PST 23
Peak memory 235496 kb
Host smart-7927d0fd-6593-4f04-be70-d14175dccdbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=887473519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.887473519
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2801449205
Short name T817
Test name
Test status
Simulation time 6087497 ps
CPU time 1.38 seconds
Started Dec 31 12:44:19 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 236304 kb
Host smart-49638a56-f952-4c61-9e93-6ab395d56482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2801449205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2801449205
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3558512492
Short name T780
Test name
Test status
Simulation time 344310220 ps
CPU time 12.47 seconds
Started Dec 31 12:44:00 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 240296 kb
Host smart-ec086f21-510c-4d32-9acf-7fa32d15d6f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3558512492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3558512492
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.787696234
Short name T139
Test name
Test status
Simulation time 5312486568 ps
CPU time 160.49 seconds
Started Dec 31 12:44:02 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 257176 kb
Host smart-bca710c7-4f79-48a1-b020-0c1db55fac3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=787696234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.787696234
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3718820049
Short name T168
Test name
Test status
Simulation time 2325519469 ps
CPU time 301.88 seconds
Started Dec 31 12:44:05 PM PST 23
Finished Dec 31 12:49:17 PM PST 23
Peak memory 269844 kb
Host smart-c7510c51-8c93-4834-832b-459360298ea5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718820049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3718820049
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3224731563
Short name T763
Test name
Test status
Simulation time 535165157 ps
CPU time 16.6 seconds
Started Dec 31 12:44:01 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 247136 kb
Host smart-fa21bb80-21b2-4936-bd4f-2033abb68bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3224731563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3224731563
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.444109350
Short name T828
Test name
Test status
Simulation time 99304896 ps
CPU time 5.46 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:27 PM PST 23
Peak memory 256716 kb
Host smart-32d48509-0c56-4e9d-a856-aa2b68d11a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444109350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.444109350
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1313288386
Short name T174
Test name
Test status
Simulation time 22608222 ps
CPU time 3.48 seconds
Started Dec 31 12:44:03 PM PST 23
Finished Dec 31 12:44:17 PM PST 23
Peak memory 236312 kb
Host smart-4957ec1d-1ec2-42b0-94b7-a3e7ace94cb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1313288386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1313288386
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2830659774
Short name T796
Test name
Test status
Simulation time 7683230 ps
CPU time 1.43 seconds
Started Dec 31 12:44:19 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 235484 kb
Host smart-ccadf105-0b55-41e4-ad32-32e1f76b7e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2830659774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2830659774
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3465952918
Short name T746
Test name
Test status
Simulation time 1070750650 ps
CPU time 17.65 seconds
Started Dec 31 12:43:49 PM PST 23
Finished Dec 31 12:44:10 PM PST 23
Peak memory 240380 kb
Host smart-7742db66-e200-4a0e-bdfe-526e9b9a5588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3465952918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3465952918
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1127996993
Short name T812
Test name
Test status
Simulation time 96937074 ps
CPU time 12 seconds
Started Dec 31 12:44:01 PM PST 23
Finished Dec 31 12:44:25 PM PST 23
Peak memory 248344 kb
Host smart-2edb17e2-da6d-4abf-89e8-b6f29de0b1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1127996993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1127996993
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4135084350
Short name T822
Test name
Test status
Simulation time 165156417 ps
CPU time 3.86 seconds
Started Dec 31 12:43:49 PM PST 23
Finished Dec 31 12:43:56 PM PST 23
Peak memory 240440 kb
Host smart-24f99328-2715-4781-b53d-d226c4ae18c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135084350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4135084350
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3326554990
Short name T787
Test name
Test status
Simulation time 29454399 ps
CPU time 3.23 seconds
Started Dec 31 12:44:23 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 236332 kb
Host smart-791b2bbc-14ca-40e3-bcf3-d38f9fb37d68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3326554990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3326554990
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.222118798
Short name T814
Test name
Test status
Simulation time 10308495 ps
CPU time 1.47 seconds
Started Dec 31 12:44:20 PM PST 23
Finished Dec 31 12:44:25 PM PST 23
Peak memory 235540 kb
Host smart-0d8987b7-c1e6-446b-88e7-80b3c556ecef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=222118798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.222118798
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3698391049
Short name T769
Test name
Test status
Simulation time 770251710 ps
CPU time 22.45 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 244592 kb
Host smart-6bb202ed-4268-4035-954b-ec1366928bce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3698391049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3698391049
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2341775189
Short name T142
Test name
Test status
Simulation time 4177695226 ps
CPU time 157.85 seconds
Started Dec 31 12:44:00 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 265812 kb
Host smart-6c09493d-9ad9-46c7-aeb6-4e79bf3dc7ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2341775189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2341775189
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.250107986
Short name T818
Test name
Test status
Simulation time 167593827 ps
CPU time 11.09 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:44:29 PM PST 23
Peak memory 248164 kb
Host smart-02d4bce8-a120-458e-801b-75a31d1364f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=250107986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.250107986
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3381970431
Short name T251
Test name
Test status
Simulation time 159866897 ps
CPU time 18.77 seconds
Started Dec 31 12:44:02 PM PST 23
Finished Dec 31 12:44:32 PM PST 23
Peak memory 248500 kb
Host smart-77d6ee7b-2ba4-4d74-8a1b-296bbb0deb23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3381970431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3381970431
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1301101642
Short name T20
Test name
Test status
Simulation time 235264663 ps
CPU time 5.23 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:44:33 PM PST 23
Peak memory 251360 kb
Host smart-c3675dc1-338c-416a-aab1-ee338dfec63d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301101642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1301101642
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3474591510
Short name T745
Test name
Test status
Simulation time 542320462 ps
CPU time 7.22 seconds
Started Dec 31 12:43:42 PM PST 23
Finished Dec 31 12:43:51 PM PST 23
Peak memory 236228 kb
Host smart-229cabbf-f46a-409f-94d2-0a011b368f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3474591510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3474591510
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.121031688
Short name T829
Test name
Test status
Simulation time 33009411 ps
CPU time 2.37 seconds
Started Dec 31 12:44:00 PM PST 23
Finished Dec 31 12:44:13 PM PST 23
Peak memory 236324 kb
Host smart-98c72a54-e532-4cd0-b25e-d0f087443b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=121031688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.121031688
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.870304752
Short name T826
Test name
Test status
Simulation time 166566285 ps
CPU time 11.76 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:33 PM PST 23
Peak memory 240296 kb
Host smart-49faa1b6-fa78-496c-ab09-c9dcfdf31817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=870304752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.870304752
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2094831456
Short name T141
Test name
Test status
Simulation time 6324132288 ps
CPU time 295.76 seconds
Started Dec 31 12:44:13 PM PST 23
Finished Dec 31 12:49:15 PM PST 23
Peak memory 265292 kb
Host smart-d58545aa-a8e0-414e-b05f-19f4abb85e0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2094831456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2094831456
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3181298995
Short name T18
Test name
Test status
Simulation time 59961139412 ps
CPU time 987.65 seconds
Started Dec 31 12:44:11 PM PST 23
Finished Dec 31 01:00:46 PM PST 23
Peak memory 272556 kb
Host smart-f1d44d07-a7ac-48a7-99ef-f927fed5fba1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181298995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3181298995
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3294574218
Short name T758
Test name
Test status
Simulation time 57472870 ps
CPU time 4.36 seconds
Started Dec 31 12:44:07 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 248684 kb
Host smart-e264054a-d3e9-43f4-94c9-09e66c78027c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3294574218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3294574218
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1353206117
Short name T252
Test name
Test status
Simulation time 113972162 ps
CPU time 5.79 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:44:23 PM PST 23
Peak memory 236368 kb
Host smart-a387f941-94a1-4441-84fa-32e0e094f001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1353206117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1353206117
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3283500985
Short name T194
Test name
Test status
Simulation time 56466138 ps
CPU time 5.57 seconds
Started Dec 31 12:44:14 PM PST 23
Finished Dec 31 12:44:25 PM PST 23
Peak memory 252128 kb
Host smart-f7d1dced-0d36-4e1a-a704-296f4ee44825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283500985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3283500985
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1002329377
Short name T799
Test name
Test status
Simulation time 120994688 ps
CPU time 4.57 seconds
Started Dec 31 12:43:51 PM PST 23
Finished Dec 31 12:43:59 PM PST 23
Peak memory 235476 kb
Host smart-26959a2a-f8ed-4766-8be5-f665e42926f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1002329377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1002329377
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1988384437
Short name T834
Test name
Test status
Simulation time 9313588 ps
CPU time 1.6 seconds
Started Dec 31 12:43:46 PM PST 23
Finished Dec 31 12:43:49 PM PST 23
Peak memory 236472 kb
Host smart-91cd4434-e4b6-4c66-849d-2b593d3d362f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1988384437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1988384437
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3320434644
Short name T738
Test name
Test status
Simulation time 169276102 ps
CPU time 22.24 seconds
Started Dec 31 12:43:45 PM PST 23
Finished Dec 31 12:44:08 PM PST 23
Peak memory 248528 kb
Host smart-387de4c1-d996-4be8-a8d8-924ef9dfa5a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3320434644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3320434644
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2371920030
Short name T177
Test name
Test status
Simulation time 6660330081 ps
CPU time 195.67 seconds
Started Dec 31 12:43:59 PM PST 23
Finished Dec 31 12:47:25 PM PST 23
Peak memory 265288 kb
Host smart-7819ed83-302d-4b28-bc0c-43aa6d3c8e99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2371920030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2371920030
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.417314398
Short name T149
Test name
Test status
Simulation time 2391163216 ps
CPU time 343.67 seconds
Started Dec 31 12:44:11 PM PST 23
Finished Dec 31 12:50:02 PM PST 23
Peak memory 265288 kb
Host smart-07a336f0-e6c1-4438-a9b1-fab718f918e4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417314398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.417314398
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.346756212
Short name T800
Test name
Test status
Simulation time 303315943 ps
CPU time 11.25 seconds
Started Dec 31 12:44:12 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 248496 kb
Host smart-05cce2fb-1563-4673-83f2-0f95bab5b2ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=346756212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.346756212
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1916917603
Short name T832
Test name
Test status
Simulation time 130588153 ps
CPU time 3.72 seconds
Started Dec 31 12:44:07 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 236436 kb
Host smart-8bc80373-c2c4-45d0-9dda-aa58f545567b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916917603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1916917603
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1151878901
Short name T367
Test name
Test status
Simulation time 176105311 ps
CPU time 7.68 seconds
Started Dec 31 12:44:22 PM PST 23
Finished Dec 31 12:44:34 PM PST 23
Peak memory 240248 kb
Host smart-cb020336-8f7b-4ffe-adcf-787ed626b96f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1151878901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1151878901
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.912566143
Short name T768
Test name
Test status
Simulation time 6334933278 ps
CPU time 35.09 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:44:52 PM PST 23
Peak memory 244596 kb
Host smart-111742ae-56fa-4265-917e-cbb67f6bff7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=912566143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.912566143
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.343030236
Short name T147
Test name
Test status
Simulation time 1863613958 ps
CPU time 140.63 seconds
Started Dec 31 12:44:00 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 264808 kb
Host smart-60478cec-12ce-4e80-9bd9-8e6a87aeaeb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=343030236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.343030236
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3557897016
Short name T179
Test name
Test status
Simulation time 18360314786 ps
CPU time 462.63 seconds
Started Dec 31 12:44:25 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 269300 kb
Host smart-3e48edef-ae31-40b9-b2c2-85e3210122c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557897016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3557897016
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.443255917
Short name T835
Test name
Test status
Simulation time 93036510 ps
CPU time 10.11 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:44:34 PM PST 23
Peak memory 248592 kb
Host smart-fac45adb-0795-4f94-b70f-a0af60f9d45b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=443255917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.443255917
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.939789251
Short name T777
Test name
Test status
Simulation time 97834192 ps
CPU time 3.6 seconds
Started Dec 31 12:44:17 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 237452 kb
Host smart-af33e4a1-4c07-49e4-a8c3-b6b5cfc494f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939789251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.939789251
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3646408858
Short name T840
Test name
Test status
Simulation time 59548872 ps
CPU time 4.59 seconds
Started Dec 31 12:44:14 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 235504 kb
Host smart-d8771f75-6e70-4206-a231-00362f4dc840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3646408858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3646408858
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1524805888
Short name T846
Test name
Test status
Simulation time 20276586 ps
CPU time 1.38 seconds
Started Dec 31 12:44:16 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 235600 kb
Host smart-3c685d2b-2bcc-40de-9d1e-92d3580804b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1524805888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1524805888
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1314215321
Short name T788
Test name
Test status
Simulation time 91578441 ps
CPU time 10.86 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:44:28 PM PST 23
Peak memory 243656 kb
Host smart-c0cb1160-4c45-45a9-835a-9ccc6bb97276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1314215321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1314215321
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1321510032
Short name T145
Test name
Test status
Simulation time 14040355622 ps
CPU time 167.93 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:47:16 PM PST 23
Peak memory 265028 kb
Host smart-438f4fa1-f348-4873-a677-1ddbb2d8fffb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1321510032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1321510032
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.451129364
Short name T369
Test name
Test status
Simulation time 33172322832 ps
CPU time 488.11 seconds
Started Dec 31 12:44:09 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 265276 kb
Host smart-d7aa1ba8-b965-4f18-b40f-57d0e1401a31
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451129364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.451129364
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2091059915
Short name T180
Test name
Test status
Simulation time 277785474 ps
CPU time 13.42 seconds
Started Dec 31 12:44:19 PM PST 23
Finished Dec 31 12:44:36 PM PST 23
Peak memory 247696 kb
Host smart-399c53f7-cb7c-4c7c-ba59-f6ade771defe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2091059915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2091059915
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3059489740
Short name T189
Test name
Test status
Simulation time 138626904 ps
CPU time 6.79 seconds
Started Dec 31 12:44:11 PM PST 23
Finished Dec 31 12:44:25 PM PST 23
Peak memory 235512 kb
Host smart-d41f5cbd-1739-4a53-aa6c-f884abebcbdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3059489740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3059489740
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4269606076
Short name T816
Test name
Test status
Simulation time 23007280 ps
CPU time 4.18 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 256748 kb
Host smart-78b72a48-39fd-4ad9-9a00-8976f6c2b6e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269606076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4269606076
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1816240423
Short name T741
Test name
Test status
Simulation time 512385943 ps
CPU time 9.19 seconds
Started Dec 31 12:44:13 PM PST 23
Finished Dec 31 12:44:28 PM PST 23
Peak memory 240268 kb
Host smart-403a33e3-d7e0-4e63-9829-3a1cdc9b890f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1816240423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1816240423
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.258809148
Short name T125
Test name
Test status
Simulation time 16614411 ps
CPU time 1.31 seconds
Started Dec 31 12:44:16 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 235512 kb
Host smart-7880fb56-358e-4b16-be73-63bf0ba53815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=258809148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.258809148
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3569685223
Short name T737
Test name
Test status
Simulation time 91645662 ps
CPU time 11.84 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:57 PM PST 23
Peak memory 244568 kb
Host smart-21b7a448-b092-446f-9cf2-bb6d222cc226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3569685223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3569685223
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3263511742
Short name T157
Test name
Test status
Simulation time 2645064577 ps
CPU time 172.7 seconds
Started Dec 31 12:44:36 PM PST 23
Finished Dec 31 12:47:35 PM PST 23
Peak memory 266728 kb
Host smart-a012880d-a08b-4527-8af9-eca0063096f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3263511742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3263511742
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1060952836
Short name T749
Test name
Test status
Simulation time 51621028 ps
CPU time 6.04 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 247692 kb
Host smart-05edf5be-bb2f-4801-a240-f697ebfc80c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1060952836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1060952836
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3053023479
Short name T249
Test name
Test status
Simulation time 22785066 ps
CPU time 2.3 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 236760 kb
Host smart-61ce0151-6829-4888-ae43-f836e5916aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3053023479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3053023479
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.437848213
Short name T776
Test name
Test status
Simulation time 70465263 ps
CPU time 7.1 seconds
Started Dec 31 12:44:25 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 251768 kb
Host smart-e3d88faa-3966-4f3c-a729-a632d2537989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437848213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.437848213
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3946746876
Short name T782
Test name
Test status
Simulation time 253161429 ps
CPU time 8.82 seconds
Started Dec 31 12:44:04 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 236384 kb
Host smart-135fa4fa-30ce-4506-a704-43e103012554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3946746876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3946746876
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2380925820
Short name T837
Test name
Test status
Simulation time 9832722 ps
CPU time 1.49 seconds
Started Dec 31 12:44:23 PM PST 23
Finished Dec 31 12:44:28 PM PST 23
Peak memory 235520 kb
Host smart-1dd03438-2bd2-4099-a3ed-dba18ef436a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2380925820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2380925820
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1367301326
Short name T806
Test name
Test status
Simulation time 628224025 ps
CPU time 22.51 seconds
Started Dec 31 12:44:15 PM PST 23
Finished Dec 31 12:44:42 PM PST 23
Peak memory 239980 kb
Host smart-7911f4b9-6d46-40ce-9e34-96255eef5804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1367301326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1367301326
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.966444010
Short name T762
Test name
Test status
Simulation time 397729671 ps
CPU time 7.58 seconds
Started Dec 31 12:44:34 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 247612 kb
Host smart-b7b69566-b830-43e3-b10d-6f77ab6e7c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=966444010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.966444010
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.814639759
Short name T797
Test name
Test status
Simulation time 75093497 ps
CPU time 4.54 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 240356 kb
Host smart-9c891159-8f05-433b-bded-9bb0da6b6d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814639759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.814639759
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3323143003
Short name T783
Test name
Test status
Simulation time 314784349 ps
CPU time 7.69 seconds
Started Dec 31 12:44:10 PM PST 23
Finished Dec 31 12:44:26 PM PST 23
Peak memory 240400 kb
Host smart-039fb36b-3bff-47e7-a551-2fe071776d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3323143003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3323143003
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.74287995
Short name T742
Test name
Test status
Simulation time 14710642 ps
CPU time 1.26 seconds
Started Dec 31 12:44:54 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 236388 kb
Host smart-602633f8-4bed-47fd-95b0-4644b6bf116b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74287995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.74287995
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3197340405
Short name T173
Test name
Test status
Simulation time 1278019334 ps
CPU time 38.9 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:45:00 PM PST 23
Peak memory 248612 kb
Host smart-46bd1819-56e1-4a25-94ae-4101ce905e27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3197340405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3197340405
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1809936163
Short name T164
Test name
Test status
Simulation time 10981421098 ps
CPU time 140.75 seconds
Started Dec 31 12:44:06 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 257080 kb
Host smart-260b61fc-85fb-43d4-9d29-a48eb503045b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1809936163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1809936163
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1646348256
Short name T760
Test name
Test status
Simulation time 597040537 ps
CPU time 11.82 seconds
Started Dec 31 12:44:22 PM PST 23
Finished Dec 31 12:44:37 PM PST 23
Peak memory 247476 kb
Host smart-292afea5-3b50-46fc-bccc-ccac4a4784a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1646348256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1646348256
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3870442024
Short name T250
Test name
Test status
Simulation time 162149479 ps
CPU time 21.36 seconds
Started Dec 31 12:44:30 PM PST 23
Finished Dec 31 12:44:57 PM PST 23
Peak memory 236528 kb
Host smart-9c25d0a0-3637-4779-bb5f-def1757c43d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3870442024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3870442024
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3938978271
Short name T748
Test name
Test status
Simulation time 735180688 ps
CPU time 69.96 seconds
Started Dec 31 12:43:46 PM PST 23
Finished Dec 31 12:44:57 PM PST 23
Peak memory 240288 kb
Host smart-73e6eff6-7a81-48ce-8608-1f68c4fa5156
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3938978271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3938978271
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1798502418
Short name T175
Test name
Test status
Simulation time 874286318 ps
CPU time 109.13 seconds
Started Dec 31 12:43:56 PM PST 23
Finished Dec 31 12:45:58 PM PST 23
Peak memory 240644 kb
Host smart-9bcf7e4b-8905-4acc-8c5a-2a7d814432e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1798502418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1798502418
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3321250929
Short name T756
Test name
Test status
Simulation time 135509418 ps
CPU time 5.27 seconds
Started Dec 31 12:43:41 PM PST 23
Finished Dec 31 12:43:47 PM PST 23
Peak memory 240428 kb
Host smart-b70c09bd-cad7-4453-a1bb-44666ee4f462
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3321250929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3321250929
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1547659459
Short name T245
Test name
Test status
Simulation time 138351948 ps
CPU time 4.28 seconds
Started Dec 31 12:44:06 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 238748 kb
Host smart-d10a2242-a630-4d19-ae08-df88852efaac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547659459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1547659459
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1339195419
Short name T743
Test name
Test status
Simulation time 183528579 ps
CPU time 7 seconds
Started Dec 31 12:43:25 PM PST 23
Finished Dec 31 12:43:33 PM PST 23
Peak memory 240408 kb
Host smart-86cddcf4-cc78-4ba4-bb0b-65f6fe3055ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1339195419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1339195419
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2644448048
Short name T736
Test name
Test status
Simulation time 15361712 ps
CPU time 1.32 seconds
Started Dec 31 12:44:02 PM PST 23
Finished Dec 31 12:44:14 PM PST 23
Peak memory 236384 kb
Host smart-5e354da7-a52c-4e18-b0a1-2ee848d16d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2644448048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2644448048
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.272284432
Short name T808
Test name
Test status
Simulation time 1030560018 ps
CPU time 20.03 seconds
Started Dec 31 12:44:01 PM PST 23
Finished Dec 31 12:44:33 PM PST 23
Peak memory 240332 kb
Host smart-3bc87d9e-d392-4b2c-b89c-323b04be630e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=272284432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.272284432
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2500986451
Short name T138
Test name
Test status
Simulation time 2272707988 ps
CPU time 150.96 seconds
Started Dec 31 12:43:53 PM PST 23
Finished Dec 31 12:46:35 PM PST 23
Peak memory 273120 kb
Host smart-eaa54d36-2678-4303-a978-39d87f08157d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500986451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2500986451
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2009992734
Short name T163
Test name
Test status
Simulation time 23458589636 ps
CPU time 630.14 seconds
Started Dec 31 12:43:56 PM PST 23
Finished Dec 31 12:54:39 PM PST 23
Peak memory 265260 kb
Host smart-0e3f08c9-cb05-4db7-977d-ec3896804fd4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009992734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2009992734
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.378363903
Short name T186
Test name
Test status
Simulation time 174034071 ps
CPU time 11.22 seconds
Started Dec 31 12:44:04 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 248308 kb
Host smart-497f7b80-1eb7-4df6-9885-f64a8a339dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=378363903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.378363903
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1089354555
Short name T798
Test name
Test status
Simulation time 9788933 ps
CPU time 1.57 seconds
Started Dec 31 12:44:28 PM PST 23
Finished Dec 31 12:44:35 PM PST 23
Peak memory 235684 kb
Host smart-1a25deea-aca3-4657-9151-e0adc37307b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1089354555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1089354555
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1275156472
Short name T784
Test name
Test status
Simulation time 7923892 ps
CPU time 1.33 seconds
Started Dec 31 12:44:40 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 235508 kb
Host smart-793eb4d3-5b96-4155-9d55-bc3cb7118d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1275156472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1275156472
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.436860858
Short name T833
Test name
Test status
Simulation time 9662599 ps
CPU time 1.35 seconds
Started Dec 31 12:44:17 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 233788 kb
Host smart-10e92602-6f9d-4553-bc77-935273315568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=436860858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.436860858
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3489438099
Short name T803
Test name
Test status
Simulation time 20147750 ps
CPU time 1.38 seconds
Started Dec 31 12:44:26 PM PST 23
Finished Dec 31 12:44:32 PM PST 23
Peak memory 235516 kb
Host smart-db5cd190-df1f-4ab8-8a88-3f21dfe5ffbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489438099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3489438099
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3607133656
Short name T759
Test name
Test status
Simulation time 11826566 ps
CPU time 1.54 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:44:42 PM PST 23
Peak memory 236416 kb
Host smart-0b5be455-87a0-4d80-b9b8-7806a285917f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3607133656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3607133656
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2562827712
Short name T790
Test name
Test status
Simulation time 7078038 ps
CPU time 1.38 seconds
Started Dec 31 12:44:40 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 236388 kb
Host smart-0af7fc37-4316-4285-9c0e-7594dea91c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562827712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2562827712
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3736356722
Short name T802
Test name
Test status
Simulation time 8634044 ps
CPU time 1.55 seconds
Started Dec 31 12:44:12 PM PST 23
Finished Dec 31 12:44:20 PM PST 23
Peak memory 236480 kb
Host smart-d997395a-e211-4ec7-9b34-7e8052031848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3736356722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3736356722
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3615295154
Short name T771
Test name
Test status
Simulation time 27267267 ps
CPU time 1.39 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:54 PM PST 23
Peak memory 236448 kb
Host smart-dbedb531-71f3-416f-ae65-5d4da9638181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3615295154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3615295154
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.704708128
Short name T755
Test name
Test status
Simulation time 19066774 ps
CPU time 1.33 seconds
Started Dec 31 12:44:05 PM PST 23
Finished Dec 31 12:44:17 PM PST 23
Peak memory 236588 kb
Host smart-f70bf017-b98a-4803-8747-5a7a3b0387c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=704708128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.704708128
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.831521688
Short name T789
Test name
Test status
Simulation time 6813829801 ps
CPU time 117.74 seconds
Started Dec 31 12:44:12 PM PST 23
Finished Dec 31 12:46:16 PM PST 23
Peak memory 236480 kb
Host smart-9185c610-c909-4345-8b30-89cb34238040
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=831521688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.831521688
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3846182534
Short name T739
Test name
Test status
Simulation time 6531363942 ps
CPU time 199 seconds
Started Dec 31 12:43:41 PM PST 23
Finished Dec 31 12:47:01 PM PST 23
Peak memory 240408 kb
Host smart-67de3b00-b3c2-42a3-9380-58ea932d34a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3846182534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3846182534
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1950142644
Short name T836
Test name
Test status
Simulation time 22422185 ps
CPU time 3.63 seconds
Started Dec 31 12:44:13 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 240348 kb
Host smart-cf77fd1b-3b98-4c00-9ee0-1e0fc396dcfe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1950142644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1950142644
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3882926760
Short name T809
Test name
Test status
Simulation time 150596794 ps
CPU time 6.8 seconds
Started Dec 31 12:44:09 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 251108 kb
Host smart-c443b6da-6aaa-460e-a2d1-1a2f7c324905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882926760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3882926760
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1146172469
Short name T146
Test name
Test status
Simulation time 135405596 ps
CPU time 4.55 seconds
Started Dec 31 12:43:59 PM PST 23
Finished Dec 31 12:44:18 PM PST 23
Peak memory 236364 kb
Host smart-513e0d17-2f66-44f6-9629-b9e79ad77707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1146172469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1146172469
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3055105806
Short name T773
Test name
Test status
Simulation time 9479947 ps
CPU time 1.3 seconds
Started Dec 31 12:43:51 PM PST 23
Finished Dec 31 12:43:56 PM PST 23
Peak memory 236420 kb
Host smart-8f87fd24-c1de-4f27-8c6f-e1d7713192b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3055105806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3055105806
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1122319501
Short name T181
Test name
Test status
Simulation time 1179036591 ps
CPU time 23.5 seconds
Started Dec 31 12:44:07 PM PST 23
Finished Dec 31 12:44:41 PM PST 23
Peak memory 240308 kb
Host smart-cd33d385-b725-410a-91d5-143301d0f10c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1122319501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1122319501
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.416801387
Short name T764
Test name
Test status
Simulation time 314736669 ps
CPU time 10.85 seconds
Started Dec 31 12:44:15 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 254616 kb
Host smart-db69f3aa-5f6a-4752-806b-f1ffd1ae11a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=416801387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.416801387
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1164723506
Short name T786
Test name
Test status
Simulation time 6914335 ps
CPU time 1.27 seconds
Started Dec 31 12:44:09 PM PST 23
Finished Dec 31 12:44:19 PM PST 23
Peak memory 234576 kb
Host smart-9d2a0dcc-bd80-42f5-929e-9fc7b8918808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1164723506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1164723506
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1278308855
Short name T767
Test name
Test status
Simulation time 12648169 ps
CPU time 1.3 seconds
Started Dec 31 12:44:15 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 236428 kb
Host smart-4ecefbad-f8ea-4cec-8421-48eba23e8c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1278308855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1278308855
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4290530678
Short name T778
Test name
Test status
Simulation time 7758898 ps
CPU time 1.28 seconds
Started Dec 31 12:44:22 PM PST 23
Finished Dec 31 12:44:27 PM PST 23
Peak memory 234484 kb
Host smart-c08e2a8d-46e1-4215-9b26-ff4c13d96e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4290530678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4290530678
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.488618603
Short name T124
Test name
Test status
Simulation time 6849447 ps
CPU time 1.4 seconds
Started Dec 31 12:44:05 PM PST 23
Finished Dec 31 12:44:16 PM PST 23
Peak memory 235768 kb
Host smart-6b5b88a1-69b3-48e2-aca8-e9da45334e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=488618603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.488618603
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1006558889
Short name T747
Test name
Test status
Simulation time 21203752 ps
CPU time 1.37 seconds
Started Dec 31 12:44:26 PM PST 23
Finished Dec 31 12:44:31 PM PST 23
Peak memory 236340 kb
Host smart-28ca5f7b-de8f-4812-8e07-7a36b6cb85bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1006558889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1006558889
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2097872686
Short name T824
Test name
Test status
Simulation time 14735684 ps
CPU time 1.34 seconds
Started Dec 31 12:44:36 PM PST 23
Finished Dec 31 12:44:43 PM PST 23
Peak memory 236384 kb
Host smart-b4da103e-d18b-400d-8de6-97ac97e918b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2097872686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2097872686
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2509836420
Short name T363
Test name
Test status
Simulation time 7780999 ps
CPU time 1.29 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 234476 kb
Host smart-9a2b531c-4750-48f7-a850-883ea2f86e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2509836420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2509836420
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1337863664
Short name T825
Test name
Test status
Simulation time 8366438 ps
CPU time 1.29 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 235620 kb
Host smart-2dd7f5e2-c7b8-4e0c-a902-0cf8d83d57b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1337863664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1337863664
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3033718655
Short name T827
Test name
Test status
Simulation time 46903739 ps
CPU time 1.22 seconds
Started Dec 31 12:44:25 PM PST 23
Finished Dec 31 12:44:29 PM PST 23
Peak memory 236340 kb
Host smart-0b838b1b-3e67-4bcb-ab9a-69df5734d2ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3033718655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3033718655
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3137952950
Short name T775
Test name
Test status
Simulation time 16105738 ps
CPU time 1.26 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:23 PM PST 23
Peak memory 234420 kb
Host smart-2bf5f0f9-12f7-448d-9c3c-24f4631b4172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3137952950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3137952950
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1878166690
Short name T779
Test name
Test status
Simulation time 18538475937 ps
CPU time 332.23 seconds
Started Dec 31 12:44:14 PM PST 23
Finished Dec 31 12:49:51 PM PST 23
Peak memory 240376 kb
Host smart-1ae741bc-83e6-4ab9-9870-7b6582daaaf3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1878166690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1878166690
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2360497056
Short name T830
Test name
Test status
Simulation time 3142780946 ps
CPU time 189.01 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:47:36 PM PST 23
Peak memory 240400 kb
Host smart-921b00b8-b1de-4406-8faf-07a025a7f484
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2360497056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2360497056
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3337244352
Short name T128
Test name
Test status
Simulation time 146645138 ps
CPU time 5.77 seconds
Started Dec 31 12:44:02 PM PST 23
Finished Dec 31 12:44:19 PM PST 23
Peak memory 240312 kb
Host smart-2ed8aa24-71b0-4087-b226-b48894ceda60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3337244352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3337244352
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1986130640
Short name T246
Test name
Test status
Simulation time 63014276 ps
CPU time 6.33 seconds
Started Dec 31 12:43:53 PM PST 23
Finished Dec 31 12:44:10 PM PST 23
Peak memory 251772 kb
Host smart-67295fa0-ba27-41e5-a2dc-3966b4664d7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986130640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1986130640
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3696977867
Short name T815
Test name
Test status
Simulation time 46174222 ps
CPU time 3.56 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:26 PM PST 23
Peak memory 236348 kb
Host smart-691989e5-b008-483b-9cd1-6d9f3138ff57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3696977867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3696977867
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2458640842
Short name T785
Test name
Test status
Simulation time 13346844 ps
CPU time 1.3 seconds
Started Dec 31 12:44:14 PM PST 23
Finished Dec 31 12:44:20 PM PST 23
Peak memory 234536 kb
Host smart-01b726b2-0455-47e2-a06b-a441be98713a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2458640842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2458640842
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3783429229
Short name T16
Test name
Test status
Simulation time 1996483128 ps
CPU time 36.91 seconds
Started Dec 31 12:43:57 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 244516 kb
Host smart-f3b52eb2-d473-4f2a-9c2d-8a84f4bd340e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3783429229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3783429229
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1419618277
Short name T161
Test name
Test status
Simulation time 705256577 ps
CPU time 85.92 seconds
Started Dec 31 12:44:06 PM PST 23
Finished Dec 31 12:45:43 PM PST 23
Peak memory 257040 kb
Host smart-2c65e22c-105d-458b-9ee0-5d0659150ad8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1419618277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1419618277
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1626201549
Short name T185
Test name
Test status
Simulation time 611084598 ps
CPU time 9.85 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:32 PM PST 23
Peak memory 248508 kb
Host smart-649810e2-bb68-4ae3-8c06-b2a15f4e4717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1626201549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1626201549
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3616741663
Short name T190
Test name
Test status
Simulation time 1431474666 ps
CPU time 79.74 seconds
Started Dec 31 12:43:49 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 244660 kb
Host smart-79345f6e-697f-4ced-80bc-1840eb8d0f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3616741663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3616741663
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.331609887
Short name T770
Test name
Test status
Simulation time 6803638 ps
CPU time 1.39 seconds
Started Dec 31 12:44:27 PM PST 23
Finished Dec 31 12:44:33 PM PST 23
Peak memory 235536 kb
Host smart-1633b90b-7cca-4cca-9686-17978fc6af9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331609887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.331609887
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2405154862
Short name T766
Test name
Test status
Simulation time 7991392 ps
CPU time 1.34 seconds
Started Dec 31 12:44:26 PM PST 23
Finished Dec 31 12:44:31 PM PST 23
Peak memory 235476 kb
Host smart-33ec4217-5553-4b2b-8d95-49a0ba34417a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2405154862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2405154862
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3136766387
Short name T248
Test name
Test status
Simulation time 10054844 ps
CPU time 1.55 seconds
Started Dec 31 12:44:39 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 236360 kb
Host smart-b20adc82-ac2d-4435-bbcb-d7010eea7756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3136766387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3136766387
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3668138994
Short name T831
Test name
Test status
Simulation time 11415932 ps
CPU time 1.31 seconds
Started Dec 31 12:44:27 PM PST 23
Finished Dec 31 12:44:33 PM PST 23
Peak memory 235472 kb
Host smart-5bddf16b-c6fa-45f6-9696-e5518fa7ec91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3668138994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3668138994
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3964641681
Short name T752
Test name
Test status
Simulation time 7575094 ps
CPU time 1.36 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:44:55 PM PST 23
Peak memory 234604 kb
Host smart-9a369cb9-6412-4dab-a1a6-f84b2077784f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3964641681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3964641681
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4116141355
Short name T819
Test name
Test status
Simulation time 10026414 ps
CPU time 1.56 seconds
Started Dec 31 12:44:40 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 235588 kb
Host smart-00c936a5-3c1b-4d91-82cf-08bff9cf251e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4116141355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4116141355
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2455966360
Short name T794
Test name
Test status
Simulation time 21583908 ps
CPU time 1.32 seconds
Started Dec 31 12:44:31 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 236372 kb
Host smart-3c13b791-cba4-487e-a7ea-33dcd3082680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2455966360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2455966360
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1384283290
Short name T366
Test name
Test status
Simulation time 9078497 ps
CPU time 1.5 seconds
Started Dec 31 12:44:33 PM PST 23
Finished Dec 31 12:44:40 PM PST 23
Peak memory 235604 kb
Host smart-759b4045-4069-45c9-bfb8-0a80c3e0f528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1384283290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1384283290
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4133721850
Short name T820
Test name
Test status
Simulation time 13597325 ps
CPU time 1.64 seconds
Started Dec 31 12:44:16 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 235616 kb
Host smart-6b57a991-6bb7-4843-89ee-a030fe5096af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4133721850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4133721850
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2551012831
Short name T839
Test name
Test status
Simulation time 168647818 ps
CPU time 3.97 seconds
Started Dec 31 12:44:34 PM PST 23
Finished Dec 31 12:44:43 PM PST 23
Peak memory 236920 kb
Host smart-c6ac5f91-bcaf-4d2e-a5e2-c88963483e9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551012831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2551012831
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.887278147
Short name T813
Test name
Test status
Simulation time 63214658 ps
CPU time 4.95 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:44:33 PM PST 23
Peak memory 238420 kb
Host smart-774cbcf7-e047-4adf-bf8f-e84993d6f6b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=887278147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.887278147
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.344628752
Short name T807
Test name
Test status
Simulation time 32776906 ps
CPU time 1.27 seconds
Started Dec 31 12:44:05 PM PST 23
Finished Dec 31 12:44:16 PM PST 23
Peak memory 235516 kb
Host smart-b6289d6e-6239-4b64-a521-c435c6613326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=344628752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.344628752
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.167690787
Short name T735
Test name
Test status
Simulation time 2731249314 ps
CPU time 42.13 seconds
Started Dec 31 12:44:22 PM PST 23
Finished Dec 31 12:45:07 PM PST 23
Peak memory 244640 kb
Host smart-e7bf2b0e-a204-4158-87a5-c622fadc8598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=167690787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.167690787
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.186959866
Short name T172
Test name
Test status
Simulation time 14521363598 ps
CPU time 282.72 seconds
Started Dec 31 12:44:02 PM PST 23
Finished Dec 31 12:48:56 PM PST 23
Peak memory 266480 kb
Host smart-709796a0-6cf2-47b4-9966-64dc0d3bff20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=186959866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.186959866
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2421985689
Short name T165
Test name
Test status
Simulation time 4951564752 ps
CPU time 675.99 seconds
Started Dec 31 12:43:45 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 265324 kb
Host smart-a55bab85-c627-48d0-b9dd-b595da2bfbcf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421985689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2421985689
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.965267785
Short name T184
Test name
Test status
Simulation time 906639129 ps
CPU time 16.22 seconds
Started Dec 31 12:44:00 PM PST 23
Finished Dec 31 12:44:25 PM PST 23
Peak memory 248708 kb
Host smart-c0ae0273-4e47-4172-b0a8-6bee84b9e32f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=965267785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.965267785
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.183654111
Short name T757
Test name
Test status
Simulation time 62151583 ps
CPU time 1.99 seconds
Started Dec 31 12:44:08 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 236548 kb
Host smart-3a1ab409-15de-456d-8d36-62a37915f9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=183654111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.183654111
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1215012776
Short name T795
Test name
Test status
Simulation time 52984057 ps
CPU time 5.92 seconds
Started Dec 31 12:44:57 PM PST 23
Finished Dec 31 12:45:06 PM PST 23
Peak memory 241788 kb
Host smart-fea2bbc5-7ced-4f2c-894b-3825b630ebff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215012776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1215012776
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2501984012
Short name T182
Test name
Test status
Simulation time 481547707 ps
CPU time 7.94 seconds
Started Dec 31 12:44:38 PM PST 23
Finished Dec 31 12:44:52 PM PST 23
Peak memory 240324 kb
Host smart-5934e2f8-dbfa-49fd-b696-693cfbdf7353
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2501984012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2501984012
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.597449648
Short name T844
Test name
Test status
Simulation time 8752099 ps
CPU time 1.47 seconds
Started Dec 31 12:44:30 PM PST 23
Finished Dec 31 12:44:37 PM PST 23
Peak memory 236452 kb
Host smart-9dc5c6ca-10af-49f7-8a6e-3bd332d6935c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=597449648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.597449648
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1669523721
Short name T811
Test name
Test status
Simulation time 8388773065 ps
CPU time 36.21 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:45:02 PM PST 23
Peak memory 244600 kb
Host smart-2a14e2a8-ce59-4d9e-98c0-fb8651700265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1669523721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1669523721
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1592445705
Short name T140
Test name
Test status
Simulation time 8706099394 ps
CPU time 179 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 265280 kb
Host smart-e25b0ade-1d62-4df6-b1e2-41689682e250
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1592445705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1592445705
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2650183977
Short name T160
Test name
Test status
Simulation time 59975293775 ps
CPU time 958.01 seconds
Started Dec 31 12:44:30 PM PST 23
Finished Dec 31 01:00:34 PM PST 23
Peak memory 266260 kb
Host smart-6c0a03da-fef0-49bf-be19-e378613cc952
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650183977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2650183977
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2983733879
Short name T765
Test name
Test status
Simulation time 89038047 ps
CPU time 11.59 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:33 PM PST 23
Peak memory 250156 kb
Host smart-1f62c766-d8e3-46f4-b965-19cdd60db87f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983733879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2983733879
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3954478658
Short name T793
Test name
Test status
Simulation time 72273724 ps
CPU time 4.2 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 240300 kb
Host smart-2f797e23-9f76-4331-b334-6f7b705de135
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954478658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3954478658
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3881135660
Short name T823
Test name
Test status
Simulation time 124679151 ps
CPU time 5.27 seconds
Started Dec 31 12:44:17 PM PST 23
Finished Dec 31 12:44:26 PM PST 23
Peak memory 235644 kb
Host smart-114f0bf0-aec9-4d87-a3f2-a2e5b378494e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3881135660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3881135660
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2758433978
Short name T365
Test name
Test status
Simulation time 10418336 ps
CPU time 1.31 seconds
Started Dec 31 12:44:20 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 236240 kb
Host smart-deb62c49-409d-4b75-96b5-ea16f7a4239f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2758433978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2758433978
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1409136896
Short name T166
Test name
Test status
Simulation time 541672040 ps
CPU time 37.91 seconds
Started Dec 31 12:44:22 PM PST 23
Finished Dec 31 12:45:04 PM PST 23
Peak memory 244576 kb
Host smart-c81d3833-7f8a-4ad0-9a11-28b29f6ea9de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1409136896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1409136896
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1422051986
Short name T178
Test name
Test status
Simulation time 2509123608 ps
CPU time 274.81 seconds
Started Dec 31 12:44:22 PM PST 23
Finished Dec 31 12:49:01 PM PST 23
Peak memory 265276 kb
Host smart-c561775f-a0f4-48f4-aafa-2f922b8fe858
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422051986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1422051986
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.999891897
Short name T801
Test name
Test status
Simulation time 256682989 ps
CPU time 13.5 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:45:05 PM PST 23
Peak memory 248532 kb
Host smart-12e94c92-c957-4bcc-b62b-8b1847997da6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=999891897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.999891897
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2184151148
Short name T810
Test name
Test status
Simulation time 44852240 ps
CPU time 4.22 seconds
Started Dec 31 12:43:57 PM PST 23
Finished Dec 31 12:44:13 PM PST 23
Peak memory 239208 kb
Host smart-b1859eb7-1b6f-4d94-b3ea-bef8f7ffd1a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184151148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2184151148
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3252396679
Short name T17
Test name
Test status
Simulation time 20547059 ps
CPU time 3.62 seconds
Started Dec 31 12:44:02 PM PST 23
Finished Dec 31 12:44:17 PM PST 23
Peak memory 236376 kb
Host smart-81fb930f-0012-4b6c-b5b7-6d1398c97115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3252396679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3252396679
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3792417265
Short name T364
Test name
Test status
Simulation time 11630492 ps
CPU time 1.39 seconds
Started Dec 31 12:44:15 PM PST 23
Finished Dec 31 12:44:21 PM PST 23
Peak memory 236416 kb
Host smart-4e0931c5-0588-4580-9fae-e80f5674b22c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3792417265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3792417265
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1871816299
Short name T750
Test name
Test status
Simulation time 1441851514 ps
CPU time 48.42 seconds
Started Dec 31 12:44:01 PM PST 23
Finished Dec 31 12:45:01 PM PST 23
Peak memory 244528 kb
Host smart-51670218-512c-4909-9ea2-e84e90aaffe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1871816299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1871816299
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4194775888
Short name T154
Test name
Test status
Simulation time 109961400619 ps
CPU time 892.88 seconds
Started Dec 31 12:44:20 PM PST 23
Finished Dec 31 12:59:17 PM PST 23
Peak memory 265192 kb
Host smart-f7763ac9-2690-4e22-b417-c7026362981e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194775888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.4194775888
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3193752800
Short name T838
Test name
Test status
Simulation time 5125938591 ps
CPU time 31 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:45:17 PM PST 23
Peak memory 248584 kb
Host smart-f4acca35-4a4e-4bc6-9f4f-9cd8ce0dfebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193752800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3193752800
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3119009790
Short name T821
Test name
Test status
Simulation time 35073275 ps
CPU time 6.52 seconds
Started Dec 31 12:44:04 PM PST 23
Finished Dec 31 12:44:20 PM PST 23
Peak memory 252032 kb
Host smart-4c99462e-1315-425e-a44e-68a65fa9a1af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119009790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3119009790
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3610973560
Short name T781
Test name
Test status
Simulation time 126300876 ps
CPU time 8.75 seconds
Started Dec 31 12:44:05 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 236336 kb
Host smart-96bdbc00-4f26-46e9-b0ee-9deab7e9e6b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3610973560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3610973560
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1546968168
Short name T792
Test name
Test status
Simulation time 13126883 ps
CPU time 1.41 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 236356 kb
Host smart-8f1d5790-f4df-4c56-982e-cb726e033056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546968168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1546968168
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4048256987
Short name T845
Test name
Test status
Simulation time 312123490 ps
CPU time 19.11 seconds
Started Dec 31 12:44:03 PM PST 23
Finished Dec 31 12:44:32 PM PST 23
Peak memory 244556 kb
Host smart-75b19304-a55f-4367-8c5b-88bac9cd4283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048256987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4048256987
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3099827534
Short name T158
Test name
Test status
Simulation time 2230351419 ps
CPU time 271.2 seconds
Started Dec 31 12:44:04 PM PST 23
Finished Dec 31 12:48:45 PM PST 23
Peak memory 265364 kb
Host smart-57628fd9-0b94-4b87-8324-e99d3000b17e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099827534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3099827534
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4205243372
Short name T847
Test name
Test status
Simulation time 274352287 ps
CPU time 9.8 seconds
Started Dec 31 12:43:56 PM PST 23
Finished Dec 31 12:44:18 PM PST 23
Peak memory 253372 kb
Host smart-c5fe7f1c-e1fc-448a-8895-b5279a12d7a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4205243372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4205243372
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2223760271
Short name T137
Test name
Test status
Simulation time 773239702 ps
CPU time 31.68 seconds
Started Dec 31 01:31:15 PM PST 23
Finished Dec 31 01:31:54 PM PST 23
Peak memory 240356 kb
Host smart-d1f530af-a5bd-441f-a59c-e29aaa1307b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2223760271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2223760271
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4213518554
Short name T225
Test name
Test status
Simulation time 6146326492 ps
CPU time 188.65 seconds
Started Dec 31 01:31:11 PM PST 23
Finished Dec 31 01:34:28 PM PST 23
Peak memory 256904 kb
Host smart-0a6bc0d8-ff09-4fa6-aaf6-2deeb1da3a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
18554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4213518554
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3398591677
Short name T312
Test name
Test status
Simulation time 1090670924 ps
CPU time 16.3 seconds
Started Dec 31 01:31:09 PM PST 23
Finished Dec 31 01:31:33 PM PST 23
Peak memory 253840 kb
Host smart-74bbdc81-48d0-457a-9550-0b3d11cfba67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
91677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3398591677
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2904681256
Short name T698
Test name
Test status
Simulation time 41522482927 ps
CPU time 2337.31 seconds
Started Dec 31 01:31:09 PM PST 23
Finished Dec 31 02:10:15 PM PST 23
Peak memory 272800 kb
Host smart-94f1d27c-669f-48af-858e-2cf1295d3616
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904681256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2904681256
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1946091339
Short name T90
Test name
Test status
Simulation time 17462560730 ps
CPU time 403.62 seconds
Started Dec 31 01:31:11 PM PST 23
Finished Dec 31 01:38:03 PM PST 23
Peak memory 246576 kb
Host smart-ecc1da8b-5f15-40d3-96b7-f6481317a9b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946091339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1946091339
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3524225099
Short name T673
Test name
Test status
Simulation time 114179301 ps
CPU time 7.95 seconds
Started Dec 31 01:31:09 PM PST 23
Finished Dec 31 01:31:26 PM PST 23
Peak memory 248564 kb
Host smart-884b6a6d-44d9-4832-a4ce-82b64891835a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35242
25099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3524225099
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3388408765
Short name T541
Test name
Test status
Simulation time 119230152 ps
CPU time 4.5 seconds
Started Dec 31 01:31:19 PM PST 23
Finished Dec 31 01:31:28 PM PST 23
Peak memory 238432 kb
Host smart-81fb942d-fd98-4c25-b835-dd1d1f783843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33884
08765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3388408765
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2549794919
Short name T12
Test name
Test status
Simulation time 599717851 ps
CPU time 26.66 seconds
Started Dec 31 01:31:09 PM PST 23
Finished Dec 31 01:31:43 PM PST 23
Peak memory 265180 kb
Host smart-e4c0f4d2-f62b-412e-bc53-a22c8ad2e0a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2549794919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2549794919
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4199640134
Short name T94
Test name
Test status
Simulation time 1582872511 ps
CPU time 21.14 seconds
Started Dec 31 01:31:03 PM PST 23
Finished Dec 31 01:31:31 PM PST 23
Peak memory 246880 kb
Host smart-b904f134-f0f4-4bb6-b05a-daa7441fde5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41996
40134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4199640134
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2522923103
Short name T436
Test name
Test status
Simulation time 224897040 ps
CPU time 19.64 seconds
Started Dec 31 01:31:02 PM PST 23
Finished Dec 31 01:31:29 PM PST 23
Peak memory 256808 kb
Host smart-42ec7aea-5653-4219-b0df-d6535d670c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25229
23103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2522923103
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1380924222
Short name T538
Test name
Test status
Simulation time 115300450701 ps
CPU time 970.92 seconds
Started Dec 31 01:31:15 PM PST 23
Finished Dec 31 01:47:33 PM PST 23
Peak memory 281156 kb
Host smart-a1849c53-d57c-4239-afab-b6c3f06663ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380924222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1380924222
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.329704822
Short name T253
Test name
Test status
Simulation time 28939549439 ps
CPU time 1604.7 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:58:13 PM PST 23
Peak memory 273308 kb
Host smart-eadf8c97-d80e-4787-a596-71ab2c03c7f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329704822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.329704822
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3062138909
Short name T429
Test name
Test status
Simulation time 600130038 ps
CPU time 9.72 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:31:39 PM PST 23
Peak memory 240352 kb
Host smart-04716f13-2d68-4475-95b1-c0f369dc8d95
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3062138909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3062138909
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1670833480
Short name T272
Test name
Test status
Simulation time 2060558035 ps
CPU time 89.55 seconds
Started Dec 31 01:32:01 PM PST 23
Finished Dec 31 01:33:32 PM PST 23
Peak memory 256032 kb
Host smart-270cdd04-db29-467e-9702-002d88d10634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16708
33480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1670833480
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2400530818
Short name T638
Test name
Test status
Simulation time 1684583106 ps
CPU time 52.01 seconds
Started Dec 31 01:31:58 PM PST 23
Finished Dec 31 01:32:53 PM PST 23
Peak memory 248676 kb
Host smart-0b48fcef-2c6f-4a0a-9426-17bd3b82f5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24005
30818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2400530818
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4093485650
Short name T420
Test name
Test status
Simulation time 25049749628 ps
CPU time 1102.09 seconds
Started Dec 31 01:31:26 PM PST 23
Finished Dec 31 01:49:50 PM PST 23
Peak memory 281920 kb
Host smart-abb1d324-5a32-4b32-a522-3090b52ea6d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093485650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4093485650
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3449207821
Short name T403
Test name
Test status
Simulation time 283853681067 ps
CPU time 1342.26 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:53:51 PM PST 23
Peak memory 273176 kb
Host smart-b82a6d6d-bcb3-42da-b8c7-509d84a2af28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449207821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3449207821
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2860548970
Short name T271
Test name
Test status
Simulation time 24805681817 ps
CPU time 450.28 seconds
Started Dec 31 01:31:24 PM PST 23
Finished Dec 31 01:38:56 PM PST 23
Peak memory 247576 kb
Host smart-e2cadc78-20f9-4c96-be10-e59297f25443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860548970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2860548970
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1218163539
Short name T527
Test name
Test status
Simulation time 80956114 ps
CPU time 9.99 seconds
Started Dec 31 01:31:31 PM PST 23
Finished Dec 31 01:31:42 PM PST 23
Peak memory 248596 kb
Host smart-bf4e2fee-63a5-4962-98fd-a2dc31835e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12181
63539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1218163539
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.618402134
Short name T467
Test name
Test status
Simulation time 410371564 ps
CPU time 27.49 seconds
Started Dec 31 01:31:23 PM PST 23
Finished Dec 31 01:31:52 PM PST 23
Peak memory 255472 kb
Host smart-c66c68a0-e32c-49ad-aa0b-e24e444d1b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61840
2134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.618402134
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.625926299
Short name T222
Test name
Test status
Simulation time 96413425 ps
CPU time 5.56 seconds
Started Dec 31 01:31:15 PM PST 23
Finished Dec 31 01:31:28 PM PST 23
Peak memory 240360 kb
Host smart-057d7845-5d46-483a-b99b-5a59d92773de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62592
6299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.625926299
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1865182613
Short name T548
Test name
Test status
Simulation time 1078318388 ps
CPU time 34.16 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:32:02 PM PST 23
Peak memory 248628 kb
Host smart-e0b76434-eed2-4695-96d6-6394d8ba16e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18651
82613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1865182613
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.498679372
Short name T133
Test name
Test status
Simulation time 238320611968 ps
CPU time 1548.45 seconds
Started Dec 31 01:31:25 PM PST 23
Finished Dec 31 01:57:15 PM PST 23
Peak memory 288976 kb
Host smart-daf7239e-bad2-4029-bc6a-4b646d3d5bf0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498679372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.498679372
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3021621634
Short name T547
Test name
Test status
Simulation time 97106363348 ps
CPU time 8029.55 seconds
Started Dec 31 01:31:04 PM PST 23
Finished Dec 31 03:45:02 PM PST 23
Peak memory 354320 kb
Host smart-9ef56b6f-8363-4d4a-b116-5ee6a5581be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021621634 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3021621634
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2952494269
Short name T207
Test name
Test status
Simulation time 153534184 ps
CPU time 3.57 seconds
Started Dec 31 01:33:48 PM PST 23
Finished Dec 31 01:33:52 PM PST 23
Peak memory 248852 kb
Host smart-13e637d7-2121-4620-a26f-8188e48edebc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2952494269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2952494269
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2175139084
Short name T275
Test name
Test status
Simulation time 9729901166 ps
CPU time 850.15 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 01:47:41 PM PST 23
Peak memory 271004 kb
Host smart-cdd70bab-5eff-475a-9357-de464ccfb079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175139084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2175139084
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2374785851
Short name T457
Test name
Test status
Simulation time 522613174 ps
CPU time 13.3 seconds
Started Dec 31 01:33:48 PM PST 23
Finished Dec 31 01:34:02 PM PST 23
Peak memory 240368 kb
Host smart-5efabbe8-26ec-42b6-a857-408e27866dbd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2374785851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2374785851
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2224058951
Short name T568
Test name
Test status
Simulation time 933989314 ps
CPU time 76.89 seconds
Started Dec 31 01:32:15 PM PST 23
Finished Dec 31 01:33:33 PM PST 23
Peak memory 247972 kb
Host smart-6a79d1b2-ac11-47b8-bb4b-01f975e56691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
58951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2224058951
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1443062720
Short name T396
Test name
Test status
Simulation time 4078683218 ps
CPU time 56.63 seconds
Started Dec 31 01:33:05 PM PST 23
Finished Dec 31 01:34:02 PM PST 23
Peak memory 248132 kb
Host smart-43446f59-a21f-4778-b790-04a9f02a387b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14430
62720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1443062720
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2975812095
Short name T37
Test name
Test status
Simulation time 36280414529 ps
CPU time 909.92 seconds
Started Dec 31 01:33:38 PM PST 23
Finished Dec 31 01:48:49 PM PST 23
Peak memory 273220 kb
Host smart-ef36cb3e-4168-4d87-a6ce-b384b1a5b4e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975812095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2975812095
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2198729519
Short name T628
Test name
Test status
Simulation time 47250193045 ps
CPU time 505.14 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 01:42:04 PM PST 23
Peak memory 247572 kb
Host smart-cc88dd9b-279e-4539-a430-e18f8349f19c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198729519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2198729519
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3409705418
Short name T615
Test name
Test status
Simulation time 220341124 ps
CPU time 17.58 seconds
Started Dec 31 01:32:55 PM PST 23
Finished Dec 31 01:33:14 PM PST 23
Peak memory 248596 kb
Host smart-aa5ea96c-9ddb-4c9e-8149-82fe516da080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
05418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3409705418
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2238019221
Short name T665
Test name
Test status
Simulation time 604554419 ps
CPU time 30.47 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:34:15 PM PST 23
Peak memory 254516 kb
Host smart-6eeb07b1-a822-4c47-997e-3a6d06c3a22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380
19221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2238019221
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3424865441
Short name T474
Test name
Test status
Simulation time 308922279 ps
CPU time 6.96 seconds
Started Dec 31 01:32:50 PM PST 23
Finished Dec 31 01:32:58 PM PST 23
Peak memory 250340 kb
Host smart-a958a66d-71d9-4dfb-95d2-428a1c18d580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
65441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3424865441
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1315577094
Short name T690
Test name
Test status
Simulation time 909199996 ps
CPU time 25.39 seconds
Started Dec 31 01:33:02 PM PST 23
Finished Dec 31 01:33:28 PM PST 23
Peak memory 248688 kb
Host smart-c5540beb-13bf-4a7a-83b0-8bddd0dbc085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13155
77094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1315577094
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2037903127
Short name T612
Test name
Test status
Simulation time 29353143152 ps
CPU time 1422.02 seconds
Started Dec 31 01:33:25 PM PST 23
Finished Dec 31 01:57:07 PM PST 23
Peak memory 289644 kb
Host smart-1d2e4383-4325-4333-91cc-b8040ebff9e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037903127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2037903127
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1972356422
Short name T598
Test name
Test status
Simulation time 85468978200 ps
CPU time 6571.86 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 03:23:17 PM PST 23
Peak memory 321896 kb
Host smart-9d543193-0bd8-49c2-b35b-b65354ab9849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972356422 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1972356422
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1088125523
Short name T217
Test name
Test status
Simulation time 49013314 ps
CPU time 2.26 seconds
Started Dec 31 01:32:02 PM PST 23
Finished Dec 31 01:32:05 PM PST 23
Peak memory 248776 kb
Host smart-67cc8af2-2d6c-4869-927e-9d2efdbefdaa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1088125523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1088125523
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.834260209
Short name T320
Test name
Test status
Simulation time 73390661159 ps
CPU time 1260.62 seconds
Started Dec 31 01:34:18 PM PST 23
Finished Dec 31 01:55:20 PM PST 23
Peak memory 286960 kb
Host smart-887424ef-95b7-45fe-8ddb-d58677e5a35c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834260209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.834260209
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2933639749
Short name T684
Test name
Test status
Simulation time 334804442 ps
CPU time 9.79 seconds
Started Dec 31 01:34:04 PM PST 23
Finished Dec 31 01:34:17 PM PST 23
Peak memory 240640 kb
Host smart-8fd4dfe2-4764-47ed-a361-36b9b34a70b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2933639749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2933639749
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.319898521
Short name T461
Test name
Test status
Simulation time 7375988407 ps
CPU time 141.96 seconds
Started Dec 31 01:34:09 PM PST 23
Finished Dec 31 01:36:33 PM PST 23
Peak memory 250624 kb
Host smart-1a4c074a-3160-47fa-b591-db8d91f1dea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
8521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.319898521
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.439056011
Short name T79
Test name
Test status
Simulation time 448249483 ps
CPU time 29.3 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 01:34:22 PM PST 23
Peak memory 254684 kb
Host smart-0eb07d3a-d6c4-4eb2-b1dc-7808afc39535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43905
6011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.439056011
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1075786430
Short name T616
Test name
Test status
Simulation time 67203612048 ps
CPU time 1968.1 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 02:06:32 PM PST 23
Peak memory 289176 kb
Host smart-83c3b7e2-4e9e-44aa-9635-daf052e6389b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075786430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1075786430
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.609561426
Short name T715
Test name
Test status
Simulation time 341259258031 ps
CPU time 1955.15 seconds
Started Dec 31 01:33:34 PM PST 23
Finished Dec 31 02:06:10 PM PST 23
Peak memory 272648 kb
Host smart-c4db6402-b455-4ccd-b876-a77c49744f31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609561426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.609561426
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4098667146
Short name T243
Test name
Test status
Simulation time 97074253470 ps
CPU time 466.93 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 01:41:50 PM PST 23
Peak memory 247264 kb
Host smart-becdab17-0bce-4891-bf71-9c047db28316
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098667146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4098667146
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2720331944
Short name T81
Test name
Test status
Simulation time 1629937400 ps
CPU time 47.05 seconds
Started Dec 31 01:33:46 PM PST 23
Finished Dec 31 01:34:34 PM PST 23
Peak memory 248604 kb
Host smart-e9e3f296-02d8-47df-97ce-02c8c629668b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27203
31944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2720331944
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3691715095
Short name T91
Test name
Test status
Simulation time 3439014805 ps
CPU time 49.47 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 01:34:19 PM PST 23
Peak memory 247128 kb
Host smart-6507e40f-b92f-4805-a819-955758cf2558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
15095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3691715095
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3478493516
Short name T311
Test name
Test status
Simulation time 206316855 ps
CPU time 8.12 seconds
Started Dec 31 01:32:59 PM PST 23
Finished Dec 31 01:33:08 PM PST 23
Peak memory 246848 kb
Host smart-16e69aa5-0c5a-4ca6-853e-6ca967ec0f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34784
93516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3478493516
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1364207035
Short name T441
Test name
Test status
Simulation time 581676644 ps
CPU time 17.15 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:33:57 PM PST 23
Peak memory 248604 kb
Host smart-1bf8e379-93c6-47c0-9434-b1ae75a235d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13642
07035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1364207035
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1560677190
Short name T62
Test name
Test status
Simulation time 164564894752 ps
CPU time 2230.26 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 02:09:25 PM PST 23
Peak memory 289524 kb
Host smart-9b292522-e9aa-4b56-83fa-dd6a9f9e9884
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560677190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1560677190
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2933859626
Short name T327
Test name
Test status
Simulation time 150026843039 ps
CPU time 1579.43 seconds
Started Dec 31 01:31:32 PM PST 23
Finished Dec 31 01:57:52 PM PST 23
Peak memory 281572 kb
Host smart-5ba59f39-8c3a-422a-9980-92ddb98ccddf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933859626 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2933859626
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.4191451439
Short name T216
Test name
Test status
Simulation time 223426124 ps
CPU time 3.35 seconds
Started Dec 31 01:32:18 PM PST 23
Finished Dec 31 01:32:23 PM PST 23
Peak memory 248804 kb
Host smart-3590055e-bce2-45f2-881d-da07e66adcaa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4191451439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.4191451439
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3804807770
Short name T517
Test name
Test status
Simulation time 20803263579 ps
CPU time 1261.75 seconds
Started Dec 31 01:32:03 PM PST 23
Finished Dec 31 01:53:06 PM PST 23
Peak memory 273040 kb
Host smart-275567bd-a02c-4294-8497-11bc0923386f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804807770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3804807770
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3853684742
Short name T540
Test name
Test status
Simulation time 891121950 ps
CPU time 10.31 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 01:32:15 PM PST 23
Peak memory 240416 kb
Host smart-d7c147ae-460b-4daa-bbf8-a096ddc75804
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3853684742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3853684742
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2315099164
Short name T507
Test name
Test status
Simulation time 2845459758 ps
CPU time 159.71 seconds
Started Dec 31 01:31:30 PM PST 23
Finished Dec 31 01:34:10 PM PST 23
Peak memory 256192 kb
Host smart-54e3bcb4-26a2-4e73-b98d-2e344ce5edf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23150
99164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2315099164
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2910710732
Short name T73
Test name
Test status
Simulation time 91430176 ps
CPU time 9.34 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:32:29 PM PST 23
Peak memory 247732 kb
Host smart-d14f900f-f6a1-40d6-97d0-42c3d4b4d5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29107
10732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2910710732
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.4015637803
Short name T347
Test name
Test status
Simulation time 50299145729 ps
CPU time 596.96 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:41:26 PM PST 23
Peak memory 265096 kb
Host smart-68a06fe9-1f91-47e7-9fc6-af529625295e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015637803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.4015637803
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3426000753
Short name T625
Test name
Test status
Simulation time 115518757618 ps
CPU time 1668.14 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 02:00:50 PM PST 23
Peak memory 272248 kb
Host smart-4e84949b-574b-4aac-bcc5-1df89b6749da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426000753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3426000753
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2157792518
Short name T292
Test name
Test status
Simulation time 100933486176 ps
CPU time 577.55 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 01:41:53 PM PST 23
Peak memory 247272 kb
Host smart-1d6cce98-b433-4c25-891d-cd9e95c6d1a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157792518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2157792518
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3451277702
Short name T78
Test name
Test status
Simulation time 169010778 ps
CPU time 13.7 seconds
Started Dec 31 01:32:06 PM PST 23
Finished Dec 31 01:32:20 PM PST 23
Peak memory 248616 kb
Host smart-b3974a01-e5b4-427d-8930-54d710022206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34512
77702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3451277702
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.649324430
Short name T569
Test name
Test status
Simulation time 230032964 ps
CPU time 19.19 seconds
Started Dec 31 01:31:30 PM PST 23
Finished Dec 31 01:31:50 PM PST 23
Peak memory 247140 kb
Host smart-ab831a85-e1d8-4387-b847-ae879a020215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64932
4430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.649324430
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.248903004
Short name T375
Test name
Test status
Simulation time 766319175 ps
CPU time 46.5 seconds
Started Dec 31 01:32:49 PM PST 23
Finished Dec 31 01:33:36 PM PST 23
Peak memory 255284 kb
Host smart-502149fc-dea9-46c8-9682-bd64eb100870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24890
3004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.248903004
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3371620138
Short name T83
Test name
Test status
Simulation time 672150529 ps
CPU time 29.66 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 01:32:56 PM PST 23
Peak memory 248608 kb
Host smart-b99ec197-6191-4859-bdb2-f59c820b7336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33716
20138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3371620138
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.769009727
Short name T566
Test name
Test status
Simulation time 93466340507 ps
CPU time 1532.46 seconds
Started Dec 31 01:32:54 PM PST 23
Finished Dec 31 01:58:27 PM PST 23
Peak memory 281560 kb
Host smart-7569dd04-4941-49d4-92d8-b40224a33c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769009727 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.769009727
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2675827336
Short name T204
Test name
Test status
Simulation time 39301434 ps
CPU time 3.41 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 01:32:30 PM PST 23
Peak memory 248884 kb
Host smart-eeff3370-1d64-4762-8dcc-1b671dd79743
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2675827336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2675827336
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1934803280
Short name T115
Test name
Test status
Simulation time 53077950106 ps
CPU time 1354.16 seconds
Started Dec 31 01:33:26 PM PST 23
Finished Dec 31 01:56:00 PM PST 23
Peak memory 288644 kb
Host smart-5f9954d3-4923-43a4-ae56-7f1bf6028da8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934803280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1934803280
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3343248888
Short name T608
Test name
Test status
Simulation time 2395402189 ps
CPU time 50.55 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:33:16 PM PST 23
Peak memory 240384 kb
Host smart-5fcc912f-cc6a-4bec-ab91-f9f13dda6ca1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3343248888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3343248888
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.41834775
Short name T634
Test name
Test status
Simulation time 7740291370 ps
CPU time 235.22 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:36:21 PM PST 23
Peak memory 249724 kb
Host smart-2acdbe37-ef21-4a50-8d4a-a6046918eadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41834
775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.41834775
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2801631390
Short name T648
Test name
Test status
Simulation time 112069208 ps
CPU time 13.52 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 01:33:06 PM PST 23
Peak memory 248112 kb
Host smart-90d06560-f89f-4f2a-8927-a5b8eef63fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28016
31390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2801631390
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3063592805
Short name T75
Test name
Test status
Simulation time 134832054246 ps
CPU time 1814.22 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 02:02:34 PM PST 23
Peak memory 272452 kb
Host smart-5ace5292-1523-4a23-a4da-f39948dfb122
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063592805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3063592805
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.381607493
Short name T455
Test name
Test status
Simulation time 20738130792 ps
CPU time 568.01 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 01:42:20 PM PST 23
Peak memory 271872 kb
Host smart-c13efff0-f360-4f7d-b632-393f93603802
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381607493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.381607493
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3738414893
Short name T284
Test name
Test status
Simulation time 116282369791 ps
CPU time 427.59 seconds
Started Dec 31 01:32:03 PM PST 23
Finished Dec 31 01:39:12 PM PST 23
Peak memory 248672 kb
Host smart-7fe0c57a-9e21-4f04-bac2-c921e22014ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738414893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3738414893
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.999844930
Short name T435
Test name
Test status
Simulation time 261975178 ps
CPU time 24.42 seconds
Started Dec 31 01:32:03 PM PST 23
Finished Dec 31 01:32:29 PM PST 23
Peak memory 248588 kb
Host smart-23e6b510-6b95-4d76-bc2b-b4a1784029c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99984
4930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.999844930
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2955578261
Short name T280
Test name
Test status
Simulation time 569597665 ps
CPU time 38.16 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 01:32:53 PM PST 23
Peak memory 254328 kb
Host smart-46c0d429-ce18-476e-a578-9daac773dba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
78261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2955578261
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.545193554
Short name T376
Test name
Test status
Simulation time 122398534 ps
CPU time 4.5 seconds
Started Dec 31 01:31:58 PM PST 23
Finished Dec 31 01:32:06 PM PST 23
Peak memory 249832 kb
Host smart-4e662c1e-1352-420c-bdcd-8becf2547701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54519
3554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.545193554
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.382568692
Short name T410
Test name
Test status
Simulation time 1747004208 ps
CPU time 31.98 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 01:32:37 PM PST 23
Peak memory 248568 kb
Host smart-b7844330-56a9-47a1-b862-e4f58fed8f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
8692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.382568692
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3360417498
Short name T515
Test name
Test status
Simulation time 97974763016 ps
CPU time 1498.65 seconds
Started Dec 31 01:32:01 PM PST 23
Finished Dec 31 01:57:01 PM PST 23
Peak memory 289728 kb
Host smart-fba3d27d-114d-407e-ba5c-4bd18d5f7091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360417498 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3360417498
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.641028847
Short name T208
Test name
Test status
Simulation time 63846191 ps
CPU time 3.24 seconds
Started Dec 31 01:32:48 PM PST 23
Finished Dec 31 01:32:53 PM PST 23
Peak memory 248852 kb
Host smart-94d3c496-7cc7-40a7-81f2-57743d5d1611
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=641028847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.641028847
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1083418430
Short name T534
Test name
Test status
Simulation time 159372474573 ps
CPU time 2327.96 seconds
Started Dec 31 01:32:08 PM PST 23
Finished Dec 31 02:10:57 PM PST 23
Peak memory 289292 kb
Host smart-f755c15c-a0cf-46b6-b03c-a9c15f0027a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083418430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1083418430
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.261164057
Short name T400
Test name
Test status
Simulation time 4403790496 ps
CPU time 51.83 seconds
Started Dec 31 01:32:58 PM PST 23
Finished Dec 31 01:33:50 PM PST 23
Peak memory 240552 kb
Host smart-7bc2a4ee-25a4-414d-bea4-061e36a34f88
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=261164057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.261164057
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1111108587
Short name T443
Test name
Test status
Simulation time 12850762566 ps
CPU time 219.45 seconds
Started Dec 31 01:32:15 PM PST 23
Finished Dec 31 01:35:56 PM PST 23
Peak memory 256456 kb
Host smart-210af2ea-ef1a-44e7-abdf-cd2ba6823590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11111
08587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1111108587
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1023540297
Short name T525
Test name
Test status
Simulation time 8514515466 ps
CPU time 69.43 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:33:29 PM PST 23
Peak memory 254608 kb
Host smart-cdc650a0-cfee-40ec-a5b3-8018cf1f723e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10235
40297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1023540297
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.553670886
Short name T642
Test name
Test status
Simulation time 200743907 ps
CPU time 13.95 seconds
Started Dec 31 01:32:15 PM PST 23
Finished Dec 31 01:32:30 PM PST 23
Peak memory 248620 kb
Host smart-cf10f25b-0a09-4574-9030-cfc1752d87c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55367
0886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.553670886
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4191043825
Short name T70
Test name
Test status
Simulation time 195257010 ps
CPU time 20.4 seconds
Started Dec 31 01:32:02 PM PST 23
Finished Dec 31 01:32:23 PM PST 23
Peak memory 248272 kb
Host smart-da008538-b6f9-4f0e-bdbc-cbd1098096ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41910
43825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4191043825
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2839053560
Short name T471
Test name
Test status
Simulation time 2468623561 ps
CPU time 39.48 seconds
Started Dec 31 01:32:48 PM PST 23
Finished Dec 31 01:33:29 PM PST 23
Peak memory 255004 kb
Host smart-495b2b5a-52e6-4644-96d5-55fe250ceff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
53560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2839053560
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3115227162
Short name T731
Test name
Test status
Simulation time 2196957616 ps
CPU time 41.29 seconds
Started Dec 31 01:32:01 PM PST 23
Finished Dec 31 01:32:44 PM PST 23
Peak memory 248752 kb
Host smart-484f66ea-b208-442c-8fce-e62d7a3c45b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31152
27162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3115227162
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4064052763
Short name T597
Test name
Test status
Simulation time 134493736434 ps
CPU time 1810.59 seconds
Started Dec 31 01:32:02 PM PST 23
Finished Dec 31 02:02:14 PM PST 23
Peak memory 273224 kb
Host smart-3dd77a04-36e7-4c9d-bff2-919d5a90351f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064052763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4064052763
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2237941757
Short name T118
Test name
Test status
Simulation time 54102788286 ps
CPU time 2464.34 seconds
Started Dec 31 01:32:54 PM PST 23
Finished Dec 31 02:13:59 PM PST 23
Peak memory 330744 kb
Host smart-14c1c276-e04b-4620-9a30-1f719ec85007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237941757 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2237941757
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.4192416999
Short name T213
Test name
Test status
Simulation time 194242692 ps
CPU time 4.36 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:33:49 PM PST 23
Peak memory 248804 kb
Host smart-d56658bb-69a5-4f94-af86-4d76c6617a6d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4192416999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4192416999
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3826712064
Short name T632
Test name
Test status
Simulation time 108090663922 ps
CPU time 930.93 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:48:58 PM PST 23
Peak memory 268092 kb
Host smart-822e1e4d-9a2c-43a0-b635-71be07388bf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826712064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3826712064
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1626430866
Short name T424
Test name
Test status
Simulation time 1008715170 ps
CPU time 45.68 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:34:29 PM PST 23
Peak memory 240096 kb
Host smart-bf46063e-4434-440c-ad0b-4c46bac1e96f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1626430866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1626430866
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.74193060
Short name T692
Test name
Test status
Simulation time 1826835234 ps
CPU time 59.64 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 01:34:42 PM PST 23
Peak memory 247996 kb
Host smart-5a055c84-c446-4c6c-a969-ba00fef4c745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74193
060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.74193060
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.4187135038
Short name T93
Test name
Test status
Simulation time 96231490 ps
CPU time 4.91 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:33:50 PM PST 23
Peak memory 238688 kb
Host smart-2d45a427-dadb-465e-9487-b92e0df18b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871
35038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4187135038
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1090400368
Short name T353
Test name
Test status
Simulation time 10540138340 ps
CPU time 856.39 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:47:19 PM PST 23
Peak memory 271376 kb
Host smart-78c3b0ed-7b3a-47b3-9da4-383835af4394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090400368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1090400368
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1867555628
Short name T584
Test name
Test status
Simulation time 12887603385 ps
CPU time 779.6 seconds
Started Dec 31 01:34:21 PM PST 23
Finished Dec 31 01:47:22 PM PST 23
Peak memory 272728 kb
Host smart-d84a4f68-9deb-4110-89c7-22b1f872f4b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867555628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1867555628
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4017165096
Short name T231
Test name
Test status
Simulation time 43402185160 ps
CPU time 429.96 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 01:40:52 PM PST 23
Peak memory 246780 kb
Host smart-24ea5038-81e7-474e-ab7e-7fa093c9d050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017165096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4017165096
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4047010633
Short name T45
Test name
Test status
Simulation time 178865079 ps
CPU time 18.74 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:33:47 PM PST 23
Peak memory 248564 kb
Host smart-5cd386aa-a4d8-4b41-b135-4d002b8f135b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40470
10633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4047010633
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1767299563
Short name T102
Test name
Test status
Simulation time 229956619 ps
CPU time 29.28 seconds
Started Dec 31 01:32:59 PM PST 23
Finished Dec 31 01:33:29 PM PST 23
Peak memory 255416 kb
Host smart-be022315-a3a8-4405-955b-1261aafeaec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17672
99563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1767299563
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3371361849
Short name T52
Test name
Test status
Simulation time 3484752354 ps
CPU time 53.73 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:34:54 PM PST 23
Peak memory 255092 kb
Host smart-72aef361-16e3-41b5-833c-32e1ea5c6c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
61849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3371361849
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3265112913
Short name T224
Test name
Test status
Simulation time 718494918 ps
CPU time 7.45 seconds
Started Dec 31 01:32:51 PM PST 23
Finished Dec 31 01:33:00 PM PST 23
Peak memory 248592 kb
Host smart-5d6f1592-e969-4e6b-91d7-e392b23f3a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651
12913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3265112913
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.336144478
Short name T451
Test name
Test status
Simulation time 2094387253 ps
CPU time 148.42 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 01:36:36 PM PST 23
Peak memory 256816 kb
Host smart-f18392ec-4b41-4f2e-8aa0-39991c0e93fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336144478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.336144478
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2045212647
Short name T92
Test name
Test status
Simulation time 186289218375 ps
CPU time 2676.94 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 02:16:43 PM PST 23
Peak memory 318272 kb
Host smart-cb637782-770d-4367-8085-9dc02c3314a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045212647 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2045212647
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2131484295
Short name T438
Test name
Test status
Simulation time 70225419497 ps
CPU time 1105.35 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 01:50:30 PM PST 23
Peak memory 272736 kb
Host smart-2c1e45b5-ef5f-4e07-9afd-ec2ec5730ad1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131484295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2131484295
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1391644413
Short name T561
Test name
Test status
Simulation time 269340174 ps
CPU time 9.87 seconds
Started Dec 31 01:32:57 PM PST 23
Finished Dec 31 01:33:08 PM PST 23
Peak memory 240468 kb
Host smart-5dec1d5e-0b98-43f8-9e69-bc0e9407615b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1391644413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1391644413
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1114570745
Short name T714
Test name
Test status
Simulation time 2738842032 ps
CPU time 54.48 seconds
Started Dec 31 01:32:48 PM PST 23
Finished Dec 31 01:33:44 PM PST 23
Peak memory 248088 kb
Host smart-ee51c418-df48-45f5-b0ab-296653bd0ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11145
70745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1114570745
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3606976054
Short name T542
Test name
Test status
Simulation time 274571876 ps
CPU time 19.78 seconds
Started Dec 31 01:32:18 PM PST 23
Finished Dec 31 01:32:40 PM PST 23
Peak memory 253756 kb
Host smart-4a91d1d0-9f66-4b9f-aff0-21fea184b299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36069
76054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3606976054
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1994837997
Short name T512
Test name
Test status
Simulation time 19202947064 ps
CPU time 1058.09 seconds
Started Dec 31 01:32:03 PM PST 23
Finished Dec 31 01:49:43 PM PST 23
Peak memory 272448 kb
Host smart-dbd14979-a08b-4c04-a93d-44ee4f33dc94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994837997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1994837997
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.446372467
Short name T577
Test name
Test status
Simulation time 225709158535 ps
CPU time 2286.78 seconds
Started Dec 31 01:32:00 PM PST 23
Finished Dec 31 02:10:09 PM PST 23
Peak memory 281284 kb
Host smart-1c8f7cd2-07ff-42de-8503-b6e7a33b8dc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446372467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.446372467
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1909458622
Short name T236
Test name
Test status
Simulation time 9912249442 ps
CPU time 252.47 seconds
Started Dec 31 01:32:50 PM PST 23
Finished Dec 31 01:37:03 PM PST 23
Peak memory 246476 kb
Host smart-07800f98-6094-4060-85a1-48238e4a71f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909458622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1909458622
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4119924961
Short name T480
Test name
Test status
Simulation time 873972206 ps
CPU time 48.56 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:33:08 PM PST 23
Peak memory 255424 kb
Host smart-b8cbb073-35aa-4d50-80a2-a84d9a8b1994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41199
24961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4119924961
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2357635158
Short name T722
Test name
Test status
Simulation time 133391308 ps
CPU time 12.93 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 01:32:31 PM PST 23
Peak memory 252736 kb
Host smart-3a7876c3-f6e0-410a-97b8-f3e6e3b0bcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23576
35158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2357635158
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2382932491
Short name T708
Test name
Test status
Simulation time 4413234547 ps
CPU time 79.58 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 01:33:38 PM PST 23
Peak memory 247516 kb
Host smart-a32aad75-a3ee-4ca6-a9f8-9155f625450c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23829
32491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2382932491
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.871615733
Short name T414
Test name
Test status
Simulation time 3703687599 ps
CPU time 63.14 seconds
Started Dec 31 01:32:06 PM PST 23
Finished Dec 31 01:33:10 PM PST 23
Peak memory 248724 kb
Host smart-6cd276f4-94fa-459f-8ceb-2074e13c04f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87161
5733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.871615733
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1891403663
Short name T504
Test name
Test status
Simulation time 61060543134 ps
CPU time 1336.81 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 01:54:32 PM PST 23
Peak memory 289564 kb
Host smart-82a2c6a7-c5b7-4d15-93ba-23fd74df6aa4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891403663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1891403663
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.61500201
Short name T218
Test name
Test status
Simulation time 16932112 ps
CPU time 2.45 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 01:34:04 PM PST 23
Peak memory 248900 kb
Host smart-95c28e4d-b78b-43c5-866c-e494062569a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=61500201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.61500201
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3965482119
Short name T113
Test name
Test status
Simulation time 99655496046 ps
CPU time 524.21 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 01:42:22 PM PST 23
Peak memory 272192 kb
Host smart-439583e5-03c8-4ced-83b4-7ad204bc5214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965482119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3965482119
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3424307137
Short name T582
Test name
Test status
Simulation time 221663220 ps
CPU time 9.07 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 01:33:46 PM PST 23
Peak memory 240408 kb
Host smart-30da559f-5591-4d38-8219-4aff45adbc5c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3424307137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3424307137
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2019113527
Short name T522
Test name
Test status
Simulation time 11996614006 ps
CPU time 183.28 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:36:43 PM PST 23
Peak memory 256500 kb
Host smart-393319ac-d530-4862-9dd6-30a15e3b68f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20191
13527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2019113527
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3248755853
Short name T322
Test name
Test status
Simulation time 3026124077 ps
CPU time 73.59 seconds
Started Dec 31 01:32:19 PM PST 23
Finished Dec 31 01:33:38 PM PST 23
Peak memory 248456 kb
Host smart-e2655c7f-ca53-40d9-ad4b-f9887684e87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32487
55853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3248755853
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3572528371
Short name T687
Test name
Test status
Simulation time 534197894608 ps
CPU time 1488.34 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:58:29 PM PST 23
Peak memory 272596 kb
Host smart-3d591f3b-81f7-4c7a-87c6-dfc57d518dc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572528371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3572528371
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1547886689
Short name T498
Test name
Test status
Simulation time 846337804013 ps
CPU time 2974.96 seconds
Started Dec 31 01:33:05 PM PST 23
Finished Dec 31 02:22:41 PM PST 23
Peak memory 288972 kb
Host smart-a96aecf6-4cdb-4ce9-8f5e-72d31e9a768e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547886689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1547886689
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2630256322
Short name T306
Test name
Test status
Simulation time 19461950411 ps
CPU time 108.25 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 01:35:19 PM PST 23
Peak memory 247268 kb
Host smart-fb3b67fd-028f-467b-8364-c307c4adf32f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630256322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2630256322
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.259260680
Short name T484
Test name
Test status
Simulation time 2060675195 ps
CPU time 19.51 seconds
Started Dec 31 01:33:06 PM PST 23
Finished Dec 31 01:33:26 PM PST 23
Peak memory 248616 kb
Host smart-cf7a28cc-3423-40c2-ad2c-4d7977a959fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25926
0680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.259260680
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2993995699
Short name T459
Test name
Test status
Simulation time 459856598 ps
CPU time 24.44 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 01:33:21 PM PST 23
Peak memory 246908 kb
Host smart-dce34784-6883-48d1-9c55-9007ce998473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29939
95699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2993995699
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1417232763
Short name T82
Test name
Test status
Simulation time 218078107 ps
CPU time 26.55 seconds
Started Dec 31 01:33:38 PM PST 23
Finished Dec 31 01:34:05 PM PST 23
Peak memory 246920 kb
Host smart-7b08aca2-42f6-408c-bcf8-7c72ba45fab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14172
32763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1417232763
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2264592372
Short name T1
Test name
Test status
Simulation time 654641676 ps
CPU time 35.38 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 01:33:02 PM PST 23
Peak memory 248580 kb
Host smart-cff5ed45-c48d-4063-a82e-de60eba7fa0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22645
92372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2264592372
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1151131228
Short name T387
Test name
Test status
Simulation time 81340636 ps
CPU time 6.62 seconds
Started Dec 31 01:34:04 PM PST 23
Finished Dec 31 01:34:14 PM PST 23
Peak memory 256828 kb
Host smart-fda06381-6602-41ea-961b-1f9f16a273cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151131228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1151131228
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1080465024
Short name T201
Test name
Test status
Simulation time 35581571 ps
CPU time 2.63 seconds
Started Dec 31 01:33:48 PM PST 23
Finished Dec 31 01:33:52 PM PST 23
Peak memory 248816 kb
Host smart-1d9fc85b-9db4-4bf9-af68-ad9082e67f10
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1080465024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1080465024
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.924600136
Short name T508
Test name
Test status
Simulation time 983540261 ps
CPU time 11.19 seconds
Started Dec 31 01:34:13 PM PST 23
Finished Dec 31 01:34:26 PM PST 23
Peak memory 248568 kb
Host smart-64fcf7f8-8f4e-4cd8-98ff-a8aa5cc276c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=924600136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.924600136
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2357051795
Short name T9
Test name
Test status
Simulation time 228036348 ps
CPU time 6.16 seconds
Started Dec 31 01:34:11 PM PST 23
Finished Dec 31 01:34:19 PM PST 23
Peak memory 253632 kb
Host smart-8c3205c8-16af-475a-ae7a-18d5b81ba30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23570
51795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2357051795
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.476549070
Short name T724
Test name
Test status
Simulation time 1793289963 ps
CPU time 29.42 seconds
Started Dec 31 01:34:02 PM PST 23
Finished Dec 31 01:34:36 PM PST 23
Peak memory 254780 kb
Host smart-ad78e7d2-e5cf-4363-b306-931fb5bf2687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47654
9070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.476549070
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3675548897
Short name T723
Test name
Test status
Simulation time 56024622168 ps
CPU time 1573.95 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 02:00:20 PM PST 23
Peak memory 282168 kb
Host smart-a7384d4d-30fd-4fa5-ad28-50a6410dffc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675548897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3675548897
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1853793873
Short name T583
Test name
Test status
Simulation time 936633846 ps
CPU time 21.72 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 01:34:09 PM PST 23
Peak memory 248684 kb
Host smart-ff516c60-0464-4ef1-b30a-f611d542fc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18537
93873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1853793873
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3935155762
Short name T59
Test name
Test status
Simulation time 416323378 ps
CPU time 9.27 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:33:55 PM PST 23
Peak memory 246872 kb
Host smart-071db4c2-a832-4122-9160-7fa1b1718e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39351
55762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3935155762
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2162482183
Short name T382
Test name
Test status
Simulation time 225426616 ps
CPU time 8.16 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:33:48 PM PST 23
Peak memory 253360 kb
Host smart-7f20dbe0-527b-419b-9c10-e1c2a6bd1620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21624
82183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2162482183
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.513128374
Short name T96
Test name
Test status
Simulation time 3778496610 ps
CPU time 57.8 seconds
Started Dec 31 01:33:34 PM PST 23
Finished Dec 31 01:34:33 PM PST 23
Peak memory 248672 kb
Host smart-ab60eb5a-f908-4242-acb2-7e5b8fa055d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51312
8374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.513128374
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3654511192
Short name T392
Test name
Test status
Simulation time 3968727337 ps
CPU time 92.25 seconds
Started Dec 31 01:31:59 PM PST 23
Finished Dec 31 01:33:34 PM PST 23
Peak memory 256896 kb
Host smart-89d9b8cb-2128-4557-9b6b-bb459c6b22b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654511192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3654511192
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2276053999
Short name T700
Test name
Test status
Simulation time 212070679346 ps
CPU time 4056.96 seconds
Started Dec 31 01:34:10 PM PST 23
Finished Dec 31 02:41:49 PM PST 23
Peak memory 305880 kb
Host smart-35e6391f-5daf-4ce2-9b43-7fa5221868de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276053999 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2276053999
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1436834774
Short name T215
Test name
Test status
Simulation time 198335732 ps
CPU time 3.57 seconds
Started Dec 31 01:33:40 PM PST 23
Finished Dec 31 01:33:45 PM PST 23
Peak memory 248912 kb
Host smart-d6f2a319-29e3-49d8-b2ae-fad5ae6f1e43
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1436834774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1436834774
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1507919565
Short name T61
Test name
Test status
Simulation time 80269274274 ps
CPU time 1299.29 seconds
Started Dec 31 01:33:47 PM PST 23
Finished Dec 31 01:55:27 PM PST 23
Peak memory 272524 kb
Host smart-3c354609-4d22-4022-b236-98c7f698a1e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507919565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1507919565
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.4001675998
Short name T454
Test name
Test status
Simulation time 1844314793 ps
CPU time 22.65 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:33:27 PM PST 23
Peak memory 240412 kb
Host smart-bbd36c8a-da0d-4609-8e77-e55d1f5507cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4001675998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4001675998
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1445102877
Short name T131
Test name
Test status
Simulation time 13134469491 ps
CPU time 187.93 seconds
Started Dec 31 01:34:13 PM PST 23
Finished Dec 31 01:37:22 PM PST 23
Peak memory 255908 kb
Host smart-8233fc91-d672-4527-beb5-1e7326443638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14451
02877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1445102877
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3851507121
Short name T622
Test name
Test status
Simulation time 68274208 ps
CPU time 2.87 seconds
Started Dec 31 01:34:21 PM PST 23
Finished Dec 31 01:34:26 PM PST 23
Peak memory 238744 kb
Host smart-a135cdbe-bb9f-4d66-9752-4dfad2974d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515
07121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3851507121
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.4076765702
Short name T494
Test name
Test status
Simulation time 9388962373 ps
CPU time 745.2 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:45:29 PM PST 23
Peak memory 272592 kb
Host smart-96aa2a17-7cac-48e4-960d-f0e1781e7c20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076765702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.4076765702
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2593813753
Short name T706
Test name
Test status
Simulation time 154049766811 ps
CPU time 2472.15 seconds
Started Dec 31 01:34:03 PM PST 23
Finished Dec 31 02:15:19 PM PST 23
Peak memory 289116 kb
Host smart-ddb4a4b0-6d62-487f-9914-a24dcedfd334
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593813753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2593813753
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2009464154
Short name T293
Test name
Test status
Simulation time 2541072606 ps
CPU time 102.66 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 01:35:47 PM PST 23
Peak memory 254544 kb
Host smart-1097b03b-e64a-4df6-aef8-49bffb67a898
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009464154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2009464154
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.528504608
Short name T586
Test name
Test status
Simulation time 1213787438 ps
CPU time 22.73 seconds
Started Dec 31 01:34:19 PM PST 23
Finished Dec 31 01:34:43 PM PST 23
Peak memory 248992 kb
Host smart-28a0a0c3-aee7-457c-bba7-f622a2b83257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52850
4608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.528504608
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.726723507
Short name T452
Test name
Test status
Simulation time 659761742 ps
CPU time 45.48 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 01:35:01 PM PST 23
Peak memory 247388 kb
Host smart-627aadb9-46fe-4cda-a9a3-a4cff91d4ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72672
3507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.726723507
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2443005944
Short name T48
Test name
Test status
Simulation time 1171925043 ps
CPU time 67.1 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:34:52 PM PST 23
Peak memory 255016 kb
Host smart-1b9537be-3a2a-4dff-b2d8-0d35356a7e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
05944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2443005944
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.4199570092
Short name T466
Test name
Test status
Simulation time 297189830 ps
CPU time 5.59 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:34:06 PM PST 23
Peak memory 240464 kb
Host smart-92902732-b543-4668-854e-1d40c3507cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995
70092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.4199570092
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3180735850
Short name T69
Test name
Test status
Simulation time 3153456392 ps
CPU time 79.77 seconds
Started Dec 31 01:34:02 PM PST 23
Finished Dec 31 01:35:26 PM PST 23
Peak memory 256864 kb
Host smart-91a2c3da-9687-46d6-aea6-e54365b320f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180735850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3180735850
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3231879937
Short name T64
Test name
Test status
Simulation time 49288472199 ps
CPU time 2983.2 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 02:23:44 PM PST 23
Peak memory 305820 kb
Host smart-955712a9-9762-480e-a964-4dbb276a00e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231879937 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3231879937
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1463370781
Short name T203
Test name
Test status
Simulation time 33082688 ps
CPU time 3.25 seconds
Started Dec 31 01:32:02 PM PST 23
Finished Dec 31 01:32:06 PM PST 23
Peak memory 248876 kb
Host smart-5d4e68ce-6ad8-4128-9c60-3f3597c59891
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1463370781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1463370781
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3011466931
Short name T609
Test name
Test status
Simulation time 50759210843 ps
CPU time 996.18 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:48:04 PM PST 23
Peak memory 281944 kb
Host smart-09dabfd6-c14d-44bc-abbe-b08d6cc4ecfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011466931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3011466931
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1735868852
Short name T462
Test name
Test status
Simulation time 459589266 ps
CPU time 12.33 seconds
Started Dec 31 01:31:59 PM PST 23
Finished Dec 31 01:32:14 PM PST 23
Peak memory 248668 kb
Host smart-3d77eb2c-e971-433b-9832-3febb74f3753
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1735868852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1735868852
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1417669668
Short name T239
Test name
Test status
Simulation time 1131847701 ps
CPU time 92.12 seconds
Started Dec 31 01:31:19 PM PST 23
Finished Dec 31 01:32:55 PM PST 23
Peak memory 255888 kb
Host smart-624aa1cb-5aa9-431e-bcab-ef5e87d0c83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14176
69668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1417669668
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.991097113
Short name T412
Test name
Test status
Simulation time 282418064 ps
CPU time 22.78 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:31:52 PM PST 23
Peak memory 248168 kb
Host smart-b6cb4794-5d7b-43aa-b486-df5d1d8819e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99109
7113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.991097113
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3737810909
Short name T667
Test name
Test status
Simulation time 42187908832 ps
CPU time 2300.47 seconds
Started Dec 31 01:31:31 PM PST 23
Finished Dec 31 02:09:53 PM PST 23
Peak memory 289516 kb
Host smart-b5705c95-1a9b-4028-8514-c5a8c517a24e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737810909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3737810909
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4161441069
Short name T523
Test name
Test status
Simulation time 15240862739 ps
CPU time 1256.4 seconds
Started Dec 31 01:31:29 PM PST 23
Finished Dec 31 01:52:27 PM PST 23
Peak memory 288880 kb
Host smart-64001249-9539-446e-8de3-82af8887acf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161441069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4161441069
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.272306123
Short name T286
Test name
Test status
Simulation time 47438477156 ps
CPU time 479.28 seconds
Started Dec 31 01:31:24 PM PST 23
Finished Dec 31 01:39:25 PM PST 23
Peak memory 247576 kb
Host smart-c52565cc-c531-4d10-8778-a9c05f030424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272306123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.272306123
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1362903467
Short name T519
Test name
Test status
Simulation time 1055817147 ps
CPU time 26.09 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:31:55 PM PST 23
Peak memory 248624 kb
Host smart-129b2a8a-bfe4-4ae9-98a0-0acec0abd3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
03467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1362903467
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.930989606
Short name T256
Test name
Test status
Simulation time 165164984 ps
CPU time 6.19 seconds
Started Dec 31 01:31:26 PM PST 23
Finished Dec 31 01:31:33 PM PST 23
Peak memory 239640 kb
Host smart-3f5f8f7d-2192-41b3-b17f-87ce9f85e582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93098
9606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.930989606
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.312146649
Short name T41
Test name
Test status
Simulation time 1389560963 ps
CPU time 33.49 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:32:01 PM PST 23
Peak memory 273284 kb
Host smart-448ad549-a9ae-4642-8ed2-c3601d9075bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=312146649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.312146649
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2820495610
Short name T401
Test name
Test status
Simulation time 591825913 ps
CPU time 30.65 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:31:59 PM PST 23
Peak memory 248604 kb
Host smart-1a0eb2a3-a6e7-4a7f-9a37-901223dc296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28204
95610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2820495610
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2777436819
Short name T664
Test name
Test status
Simulation time 11036748269 ps
CPU time 635.37 seconds
Started Dec 31 01:31:32 PM PST 23
Finished Dec 31 01:42:08 PM PST 23
Peak memory 256848 kb
Host smart-a714487b-ef09-47ec-bb03-e68f8b2bc750
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777436819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2777436819
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1359701329
Short name T702
Test name
Test status
Simulation time 31477162909 ps
CPU time 1020.47 seconds
Started Dec 31 01:31:26 PM PST 23
Finished Dec 31 01:48:28 PM PST 23
Peak memory 273244 kb
Host smart-fa99e60a-52d5-4cbc-888a-dbe7aca9a913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359701329 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1359701329
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1689483246
Short name T487
Test name
Test status
Simulation time 71059034895 ps
CPU time 1113.65 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:52:40 PM PST 23
Peak memory 265256 kb
Host smart-440093ca-4add-4ece-8061-ced450390e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689483246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1689483246
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.441784106
Short name T556
Test name
Test status
Simulation time 1292989411 ps
CPU time 17.71 seconds
Started Dec 31 01:34:10 PM PST 23
Finished Dec 31 01:34:29 PM PST 23
Peak memory 255440 kb
Host smart-312080ab-f7ee-485a-ab85-d1e4b225078e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44178
4106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.441784106
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3670260761
Short name T232
Test name
Test status
Simulation time 118373344 ps
CPU time 7.92 seconds
Started Dec 31 01:34:14 PM PST 23
Finished Dec 31 01:34:23 PM PST 23
Peak memory 249820 kb
Host smart-e126460d-69a3-488f-a9d2-0bb0f714e7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36702
60761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3670260761
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4206411880
Short name T362
Test name
Test status
Simulation time 46684817119 ps
CPU time 802.41 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 01:47:01 PM PST 23
Peak memory 272516 kb
Host smart-054f0f41-dfe2-47ab-b71d-70f0671b19c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206411880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4206411880
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.730310165
Short name T565
Test name
Test status
Simulation time 31238966116 ps
CPU time 1742.23 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 02:03:03 PM PST 23
Peak memory 287996 kb
Host smart-720aafa7-c0cf-4de8-b684-f80d5af54978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730310165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.730310165
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2353888308
Short name T291
Test name
Test status
Simulation time 4463817424 ps
CPU time 163.13 seconds
Started Dec 31 01:33:38 PM PST 23
Finished Dec 31 01:36:22 PM PST 23
Peak memory 248436 kb
Host smart-d87ca0a2-abaa-467a-917a-fc58ad615921
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353888308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2353888308
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3308651847
Short name T514
Test name
Test status
Simulation time 265140806 ps
CPU time 24.57 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:34:25 PM PST 23
Peak memory 254784 kb
Host smart-8589f009-7e3e-4993-bfa5-2ef064ded865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
51847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3308651847
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3360729863
Short name T263
Test name
Test status
Simulation time 178875401 ps
CPU time 11.21 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:34:20 PM PST 23
Peak memory 254760 kb
Host smart-9a9db5ee-5abb-4730-a97e-a4de040fb48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
29863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3360729863
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.962756357
Short name T592
Test name
Test status
Simulation time 5319208262 ps
CPU time 46.76 seconds
Started Dec 31 01:33:46 PM PST 23
Finished Dec 31 01:34:33 PM PST 23
Peak memory 248636 kb
Host smart-3fc51cbb-fb15-4bbb-9e0f-5d5b29e22152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96275
6357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.962756357
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2367893131
Short name T120
Test name
Test status
Simulation time 21476290818 ps
CPU time 389.37 seconds
Started Dec 31 01:33:58 PM PST 23
Finished Dec 31 01:40:31 PM PST 23
Peak memory 273280 kb
Host smart-1d136863-6c8a-4d38-93a8-ce4f43f06e58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367893131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2367893131
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2135675498
Short name T717
Test name
Test status
Simulation time 174816798110 ps
CPU time 2484.09 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 02:15:32 PM PST 23
Peak memory 288880 kb
Host smart-d2a3bd61-ea90-444e-9dd2-80908e7953ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135675498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2135675498
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2751343857
Short name T571
Test name
Test status
Simulation time 17500531016 ps
CPU time 260.34 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:38:05 PM PST 23
Peak memory 256376 kb
Host smart-4e7afcda-e76b-4fd5-b5ac-5d061d5c395d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
43857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2751343857
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2007287576
Short name T545
Test name
Test status
Simulation time 699549593 ps
CPU time 43.82 seconds
Started Dec 31 01:34:04 PM PST 23
Finished Dec 31 01:34:51 PM PST 23
Peak memory 254936 kb
Host smart-800ec27c-50a4-488c-8987-10e1c1d4accb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20072
87576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2007287576
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.33355421
Short name T423
Test name
Test status
Simulation time 96145476660 ps
CPU time 2344.59 seconds
Started Dec 31 01:32:08 PM PST 23
Finished Dec 31 02:11:14 PM PST 23
Peak memory 289384 kb
Host smart-87bb048d-a0a9-4004-aff3-ff6d972f5cb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33355421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.33355421
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3189143424
Short name T298
Test name
Test status
Simulation time 163870438333 ps
CPU time 472.99 seconds
Started Dec 31 01:34:33 PM PST 23
Finished Dec 31 01:42:31 PM PST 23
Peak memory 247572 kb
Host smart-91b2524e-e89e-4b41-b4a6-681f60b4aa70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189143424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3189143424
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2611207981
Short name T520
Test name
Test status
Simulation time 648686610 ps
CPU time 21.86 seconds
Started Dec 31 01:33:57 PM PST 23
Finished Dec 31 01:34:22 PM PST 23
Peak memory 248652 kb
Host smart-e0f6b8cd-712c-4167-b3bc-19a5fb8b66ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
07981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2611207981
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1439553694
Short name T393
Test name
Test status
Simulation time 2384803063 ps
CPU time 20.16 seconds
Started Dec 31 01:33:23 PM PST 23
Finished Dec 31 01:33:43 PM PST 23
Peak memory 253520 kb
Host smart-3366f856-b1f2-483a-81bc-f7587fd6ccd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14395
53694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1439553694
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1311173870
Short name T395
Test name
Test status
Simulation time 314061978 ps
CPU time 11.95 seconds
Started Dec 31 01:34:10 PM PST 23
Finished Dec 31 01:34:24 PM PST 23
Peak memory 248772 kb
Host smart-c89844c5-6308-4c68-b7c5-66646b3e8e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111
73870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1311173870
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3644056428
Short name T701
Test name
Test status
Simulation time 1631081336 ps
CPU time 8.01 seconds
Started Dec 31 01:33:42 PM PST 23
Finished Dec 31 01:33:51 PM PST 23
Peak memory 248592 kb
Host smart-d2d121f3-4d3e-4de6-95a6-3316d91c21f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
56428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3644056428
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4000002616
Short name T111
Test name
Test status
Simulation time 135087444103 ps
CPU time 3880.99 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 02:37:07 PM PST 23
Peak memory 305552 kb
Host smart-75ee1173-fcfe-4948-8280-3e26f15e5061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000002616 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4000002616
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3478946945
Short name T418
Test name
Test status
Simulation time 86550062185 ps
CPU time 2495.48 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 02:15:05 PM PST 23
Peak memory 284256 kb
Host smart-ef4209fe-b9a7-4457-b4a4-c77325eecad1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478946945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3478946945
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3549272644
Short name T76
Test name
Test status
Simulation time 2903015382 ps
CPU time 64.91 seconds
Started Dec 31 01:32:12 PM PST 23
Finished Dec 31 01:33:18 PM PST 23
Peak memory 256224 kb
Host smart-ab1a518d-6cba-405a-aa08-f01fb6ed5cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35492
72644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3549272644
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2652634433
Short name T357
Test name
Test status
Simulation time 278560580459 ps
CPU time 1314.36 seconds
Started Dec 31 01:33:40 PM PST 23
Finished Dec 31 01:55:36 PM PST 23
Peak memory 281308 kb
Host smart-80cdc53f-452e-44dd-ba12-76f9eae081e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652634433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2652634433
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1167831978
Short name T610
Test name
Test status
Simulation time 14994964499 ps
CPU time 1245.5 seconds
Started Dec 31 01:32:57 PM PST 23
Finished Dec 31 01:53:43 PM PST 23
Peak memory 286360 kb
Host smart-4358f91a-ed95-4e93-beeb-429118eb1074
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167831978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1167831978
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.267100730
Short name T733
Test name
Test status
Simulation time 9720596673 ps
CPU time 342.54 seconds
Started Dec 31 01:33:25 PM PST 23
Finished Dec 31 01:39:08 PM PST 23
Peak memory 254108 kb
Host smart-715f24ee-9f9d-47a6-8a43-de9ee6f46029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267100730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.267100730
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3116955225
Short name T650
Test name
Test status
Simulation time 214351661 ps
CPU time 6.75 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 01:32:34 PM PST 23
Peak memory 256816 kb
Host smart-1aabd188-eef1-4362-8972-1eae7ea28d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
55225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3116955225
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.947453096
Short name T237
Test name
Test status
Simulation time 954696951 ps
CPU time 54.65 seconds
Started Dec 31 01:32:24 PM PST 23
Finished Dec 31 01:33:21 PM PST 23
Peak memory 248004 kb
Host smart-071630a9-16b5-433f-8eaf-4c3befd1262a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94745
3096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.947453096
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.944462624
Short name T573
Test name
Test status
Simulation time 2115630464 ps
CPU time 38.86 seconds
Started Dec 31 01:32:49 PM PST 23
Finished Dec 31 01:33:28 PM PST 23
Peak memory 254920 kb
Host smart-38719273-2c87-4e19-af6f-2a30a11455b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94446
2624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.944462624
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1390580138
Short name T559
Test name
Test status
Simulation time 263815588 ps
CPU time 15.52 seconds
Started Dec 31 01:32:18 PM PST 23
Finished Dec 31 01:32:36 PM PST 23
Peak memory 248656 kb
Host smart-9df28054-48f7-4107-ae59-2b5ca8d366b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13905
80138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1390580138
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3857836698
Short name T100
Test name
Test status
Simulation time 40414734472 ps
CPU time 2281.45 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 02:11:44 PM PST 23
Peak memory 289744 kb
Host smart-6490014f-d8cb-47d0-b2c1-cd02389f20e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857836698 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3857836698
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1957003769
Short name T465
Test name
Test status
Simulation time 70336126889 ps
CPU time 862.24 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 01:47:56 PM PST 23
Peak memory 282100 kb
Host smart-5ade8e54-7764-4740-a1cf-4baad81f4b32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957003769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1957003769
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1592515546
Short name T488
Test name
Test status
Simulation time 4652806951 ps
CPU time 122.4 seconds
Started Dec 31 01:33:26 PM PST 23
Finished Dec 31 01:35:29 PM PST 23
Peak memory 248312 kb
Host smart-1baecfd1-8594-4155-b5b2-5e1601df2de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15925
15546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1592515546
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1538156711
Short name T421
Test name
Test status
Simulation time 51534995 ps
CPU time 6.3 seconds
Started Dec 31 01:33:05 PM PST 23
Finished Dec 31 01:33:12 PM PST 23
Peak memory 253492 kb
Host smart-85fced19-5682-42bc-b54c-9ae4dc57d288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15381
56711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1538156711
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1440781755
Short name T709
Test name
Test status
Simulation time 301685655476 ps
CPU time 2364.75 seconds
Started Dec 31 01:33:50 PM PST 23
Finished Dec 31 02:13:16 PM PST 23
Peak memory 287308 kb
Host smart-643caaba-e5e9-4176-8025-74a287d762a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440781755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1440781755
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.806432066
Short name T600
Test name
Test status
Simulation time 249549815674 ps
CPU time 1230.81 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:54:31 PM PST 23
Peak memory 272904 kb
Host smart-58b4df2a-0aff-4412-b0cc-133a83c94dcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806432066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.806432066
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.760479527
Short name T668
Test name
Test status
Simulation time 32455579528 ps
CPU time 108.09 seconds
Started Dec 31 01:34:14 PM PST 23
Finished Dec 31 01:36:03 PM PST 23
Peak memory 247424 kb
Host smart-fd5ef95c-212e-4d55-a79b-f92753a778bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760479527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.760479527
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3961054380
Short name T602
Test name
Test status
Simulation time 2204163545 ps
CPU time 64.64 seconds
Started Dec 31 01:32:51 PM PST 23
Finished Dec 31 01:33:57 PM PST 23
Peak memory 255464 kb
Host smart-81e43e21-5291-4e11-8c32-96ed8826a3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39610
54380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3961054380
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.946474714
Short name T555
Test name
Test status
Simulation time 1818743581 ps
CPU time 51.67 seconds
Started Dec 31 01:33:24 PM PST 23
Finished Dec 31 01:34:16 PM PST 23
Peak memory 254776 kb
Host smart-a82bbbcc-13da-483a-b109-9d56b3226506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94647
4714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.946474714
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2104220476
Short name T437
Test name
Test status
Simulation time 2240534171 ps
CPU time 29.31 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 01:33:26 PM PST 23
Peak memory 248476 kb
Host smart-b4b46443-b8da-4a86-8ad7-3e0c87bcca98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042
20476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2104220476
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1716466132
Short name T497
Test name
Test status
Simulation time 4623526540 ps
CPU time 40.47 seconds
Started Dec 31 01:34:04 PM PST 23
Finished Dec 31 01:34:47 PM PST 23
Peak memory 256900 kb
Host smart-8dd21973-f64d-4043-a3b8-4772466454a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716466132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1716466132
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2288212685
Short name T331
Test name
Test status
Simulation time 585294346276 ps
CPU time 8068.96 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 03:48:14 PM PST 23
Peak memory 354208 kb
Host smart-d551a918-63ea-4061-aaf0-208a674366ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288212685 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2288212685
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2890703540
Short name T713
Test name
Test status
Simulation time 275045125811 ps
CPU time 1543.19 seconds
Started Dec 31 01:34:10 PM PST 23
Finished Dec 31 01:59:55 PM PST 23
Peak memory 273212 kb
Host smart-90a1ff7b-29d0-4a8b-bc80-1f800a4f0ebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890703540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2890703540
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1677728247
Short name T614
Test name
Test status
Simulation time 5295975563 ps
CPU time 73.83 seconds
Started Dec 31 01:34:16 PM PST 23
Finished Dec 31 01:35:30 PM PST 23
Peak memory 256188 kb
Host smart-65aaca56-2e59-4873-ab34-42c317f417aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16777
28247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1677728247
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1282816251
Short name T434
Test name
Test status
Simulation time 3212922549 ps
CPU time 45.23 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:34:51 PM PST 23
Peak memory 255724 kb
Host smart-13fc0060-d231-4153-8bf4-53d9f2455cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12828
16251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1282816251
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2597389859
Short name T493
Test name
Test status
Simulation time 81151909438 ps
CPU time 1331.02 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 01:55:08 PM PST 23
Peak memory 286120 kb
Host smart-7b778ed0-2f58-4242-960f-5cbd2ad389cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597389859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2597389859
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3697484358
Short name T694
Test name
Test status
Simulation time 5103577295 ps
CPU time 115.61 seconds
Started Dec 31 01:34:04 PM PST 23
Finished Dec 31 01:36:03 PM PST 23
Peak memory 247584 kb
Host smart-7544fbf4-82a5-44c2-9e97-26114046b9ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697484358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3697484358
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4215979521
Short name T380
Test name
Test status
Simulation time 570701511 ps
CPU time 17.53 seconds
Started Dec 31 01:34:08 PM PST 23
Finished Dec 31 01:34:28 PM PST 23
Peak memory 248624 kb
Host smart-25e70db8-3456-42eb-ad6d-b8a420c007c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42159
79521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4215979521
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3819193126
Short name T2
Test name
Test status
Simulation time 362881113 ps
CPU time 29.72 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 01:34:30 PM PST 23
Peak memory 246680 kb
Host smart-31282991-2f76-4911-a61c-bcc7ca5d6e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38191
93126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3819193126
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4237532591
Short name T373
Test name
Test status
Simulation time 2032732918 ps
CPU time 33 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 01:34:49 PM PST 23
Peak memory 247728 kb
Host smart-d33abdd5-a9b7-4668-9a12-06e63335693f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375
32591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4237532591
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3138893739
Short name T88
Test name
Test status
Simulation time 666057814 ps
CPU time 37.5 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:34:43 PM PST 23
Peak memory 248660 kb
Host smart-f4b543e2-d0ab-451d-ada3-0b3043e364cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31388
93739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3138893739
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2357038706
Short name T680
Test name
Test status
Simulation time 32583194642 ps
CPU time 902.25 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:49:11 PM PST 23
Peak memory 273344 kb
Host smart-e3f17941-1767-4da9-b37a-a872fa5759fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357038706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2357038706
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3128835982
Short name T104
Test name
Test status
Simulation time 49289917978 ps
CPU time 1619.25 seconds
Started Dec 31 01:34:09 PM PST 23
Finished Dec 31 02:01:11 PM PST 23
Peak memory 287472 kb
Host smart-78861f13-37d7-4a1f-96a0-2c83bd3a9456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128835982 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3128835982
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2488361292
Short name T653
Test name
Test status
Simulation time 22915240230 ps
CPU time 1416.96 seconds
Started Dec 31 01:33:02 PM PST 23
Finished Dec 31 01:56:40 PM PST 23
Peak memory 268176 kb
Host smart-17d598cf-6340-4b99-bb1c-e3c367e67287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488361292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2488361292
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2807506054
Short name T580
Test name
Test status
Simulation time 3592477986 ps
CPU time 68.3 seconds
Started Dec 31 01:32:18 PM PST 23
Finished Dec 31 01:33:29 PM PST 23
Peak memory 256144 kb
Host smart-e67fcd43-5c09-4a5b-9ad9-1f66462bd126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28075
06054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2807506054
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1365081592
Short name T606
Test name
Test status
Simulation time 742469685 ps
CPU time 30.46 seconds
Started Dec 31 01:32:03 PM PST 23
Finished Dec 31 01:32:34 PM PST 23
Peak memory 248396 kb
Host smart-40114935-dee7-4697-82da-c9107b8b6d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13650
81592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1365081592
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3677037047
Short name T728
Test name
Test status
Simulation time 8724541121 ps
CPU time 809.8 seconds
Started Dec 31 01:32:54 PM PST 23
Finished Dec 31 01:46:24 PM PST 23
Peak memory 272388 kb
Host smart-16426c43-37da-4f9d-980c-ee38acdc3364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677037047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3677037047
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.4081202921
Short name T460
Test name
Test status
Simulation time 66217675255 ps
CPU time 1805.55 seconds
Started Dec 31 01:32:06 PM PST 23
Finished Dec 31 02:02:12 PM PST 23
Peak memory 273316 kb
Host smart-b24e44d3-d05b-4e04-9e34-999db372d54c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081202921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.4081202921
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1374040149
Short name T691
Test name
Test status
Simulation time 15463571489 ps
CPU time 319.22 seconds
Started Dec 31 01:34:18 PM PST 23
Finished Dec 31 01:39:38 PM PST 23
Peak memory 246604 kb
Host smart-4cd21bbf-d0d5-4567-a87c-f190627a50d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374040149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1374040149
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.4282265020
Short name T550
Test name
Test status
Simulation time 678724380 ps
CPU time 37.11 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:34:45 PM PST 23
Peak memory 248564 kb
Host smart-db8061ad-b1fe-47b9-baad-ea19e237b6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42822
65020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4282265020
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.289405543
Short name T574
Test name
Test status
Simulation time 1202349761 ps
CPU time 31.11 seconds
Started Dec 31 01:34:29 PM PST 23
Finished Dec 31 01:35:02 PM PST 23
Peak memory 256224 kb
Host smart-d73e636e-6843-4a34-945e-0f1fb4331eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28940
5543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.289405543
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2765162257
Short name T526
Test name
Test status
Simulation time 34973383 ps
CPU time 4.6 seconds
Started Dec 31 01:34:13 PM PST 23
Finished Dec 31 01:34:20 PM PST 23
Peak memory 238684 kb
Host smart-9c9de0d7-042e-4c6c-a2b3-70517a5ef44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
62257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2765162257
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2734871438
Short name T442
Test name
Test status
Simulation time 757992113 ps
CPU time 20.89 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:34:27 PM PST 23
Peak memory 248716 kb
Host smart-008f56b4-9442-4a1c-9b0b-141313d5caf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
71438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2734871438
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3366630149
Short name T617
Test name
Test status
Simulation time 112031089635 ps
CPU time 2683.86 seconds
Started Dec 31 01:32:18 PM PST 23
Finished Dec 31 02:17:04 PM PST 23
Peak memory 288980 kb
Host smart-cf8357b4-4003-45b9-bfdd-105b8862fbe2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366630149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3366630149
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1733166451
Short name T28
Test name
Test status
Simulation time 31825991568 ps
CPU time 1332.41 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 01:55:55 PM PST 23
Peak memory 305276 kb
Host smart-dc33e542-258d-4596-a717-7239b76a046c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733166451 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1733166451
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.430956534
Short name T732
Test name
Test status
Simulation time 135388053617 ps
CPU time 1854.75 seconds
Started Dec 31 01:34:07 PM PST 23
Finished Dec 31 02:05:04 PM PST 23
Peak memory 272988 kb
Host smart-0e281742-7239-46ff-91e1-37a0d12f9cbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430956534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.430956534
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1398547001
Short name T439
Test name
Test status
Simulation time 3133883181 ps
CPU time 42.49 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:34:51 PM PST 23
Peak memory 254304 kb
Host smart-59f61069-22c1-41a2-bf98-51c7dfcd8e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13985
47001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1398547001
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.719358526
Short name T516
Test name
Test status
Simulation time 281912025 ps
CPU time 14.49 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 01:34:15 PM PST 23
Peak memory 254288 kb
Host smart-d0587c79-e352-483b-b70e-09ecf474c2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71935
8526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.719358526
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.633841677
Short name T344
Test name
Test status
Simulation time 89228319184 ps
CPU time 1324.91 seconds
Started Dec 31 01:33:50 PM PST 23
Finished Dec 31 01:55:56 PM PST 23
Peak memory 272372 kb
Host smart-8ce80d28-f771-4b5d-9cf9-ff945a66f312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633841677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.633841677
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1120612531
Short name T599
Test name
Test status
Simulation time 15762638987 ps
CPU time 1326.54 seconds
Started Dec 31 01:33:47 PM PST 23
Finished Dec 31 01:55:54 PM PST 23
Peak memory 286796 kb
Host smart-f35c2ebe-448a-4512-bdd6-7467ae04ada6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120612531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1120612531
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2214191588
Short name T309
Test name
Test status
Simulation time 6246731664 ps
CPU time 141.63 seconds
Started Dec 31 01:34:07 PM PST 23
Finished Dec 31 01:36:30 PM PST 23
Peak memory 246268 kb
Host smart-6e62a8d2-394b-40c6-8979-631942c900c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214191588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2214191588
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2859929408
Short name T530
Test name
Test status
Simulation time 145323732 ps
CPU time 5.28 seconds
Started Dec 31 01:33:52 PM PST 23
Finished Dec 31 01:33:58 PM PST 23
Peak memory 240480 kb
Host smart-16083a19-12cc-47db-95ae-b4e731fd6b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28599
29408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2859929408
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2822877638
Short name T43
Test name
Test status
Simulation time 419283259 ps
CPU time 17.99 seconds
Started Dec 31 01:34:25 PM PST 23
Finished Dec 31 01:34:44 PM PST 23
Peak memory 255112 kb
Host smart-b0964356-51c4-45a3-adc3-6886f1606da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28228
77638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2822877638
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3624294214
Short name T335
Test name
Test status
Simulation time 703152307 ps
CPU time 19.13 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:34:24 PM PST 23
Peak memory 255464 kb
Host smart-a52cede7-9e4b-4a30-8fb8-15cb7b8a8920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36242
94214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3624294214
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1888240824
Short name T704
Test name
Test status
Simulation time 3490552538 ps
CPU time 35.57 seconds
Started Dec 31 01:34:25 PM PST 23
Finished Dec 31 01:35:03 PM PST 23
Peak memory 248736 kb
Host smart-31d89d3f-3884-4320-af29-ed4f257261a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18882
40824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1888240824
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2917764317
Short name T729
Test name
Test status
Simulation time 33766460802 ps
CPU time 1988.94 seconds
Started Dec 31 01:34:23 PM PST 23
Finished Dec 31 02:07:34 PM PST 23
Peak memory 289408 kb
Host smart-a5f86c7a-9e60-4a3e-82bd-18fbde3cc7a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917764317 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2917764317
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3291417856
Short name T506
Test name
Test status
Simulation time 93388193471 ps
CPU time 2423.68 seconds
Started Dec 31 01:34:03 PM PST 23
Finished Dec 31 02:14:31 PM PST 23
Peak memory 281488 kb
Host smart-209483d4-0fd8-4181-af6b-b6903df548eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291417856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3291417856
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1082094345
Short name T72
Test name
Test status
Simulation time 542678397 ps
CPU time 24.72 seconds
Started Dec 31 01:34:26 PM PST 23
Finished Dec 31 01:34:52 PM PST 23
Peak memory 255356 kb
Host smart-1fa065b6-01ca-49fd-a617-96e0f33dade6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
94345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1082094345
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3321827013
Short name T334
Test name
Test status
Simulation time 324691090 ps
CPU time 17.14 seconds
Started Dec 31 01:34:12 PM PST 23
Finished Dec 31 01:34:30 PM PST 23
Peak memory 251616 kb
Host smart-3fb409b4-c4c4-4d27-85af-86739096595e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
27013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3321827013
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2010525662
Short name T355
Test name
Test status
Simulation time 203474345848 ps
CPU time 2186.75 seconds
Started Dec 31 01:34:24 PM PST 23
Finished Dec 31 02:10:53 PM PST 23
Peak memory 288804 kb
Host smart-ddcc3ccf-ac1b-4e2b-9ab2-ce7adf4a63cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010525662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2010525662
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1954165862
Short name T87
Test name
Test status
Simulation time 155792112181 ps
CPU time 1655.86 seconds
Started Dec 31 01:34:08 PM PST 23
Finished Dec 31 02:01:45 PM PST 23
Peak memory 281480 kb
Host smart-c6188036-7d12-4e79-b498-0c71c485bc25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954165862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1954165862
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3620281339
Short name T529
Test name
Test status
Simulation time 2580160353 ps
CPU time 106.21 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 01:35:47 PM PST 23
Peak memory 248616 kb
Host smart-c7da2f84-7b08-40a6-9aab-9c3040090150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620281339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3620281339
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1941115774
Short name T244
Test name
Test status
Simulation time 79609206 ps
CPU time 6.21 seconds
Started Dec 31 01:33:58 PM PST 23
Finished Dec 31 01:34:08 PM PST 23
Peak memory 240436 kb
Host smart-bd63c1ea-8506-4c0f-80d6-6098297b6436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19411
15774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1941115774
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1520090363
Short name T432
Test name
Test status
Simulation time 245668875 ps
CPU time 15.5 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:34:24 PM PST 23
Peak memory 246616 kb
Host smart-b240c90f-4796-48f6-a188-8bd5bcfbb2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15200
90363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1520090363
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.241367067
Short name T314
Test name
Test status
Simulation time 2247931882 ps
CPU time 30.92 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 01:34:47 PM PST 23
Peak memory 248656 kb
Host smart-57dcac73-1aa9-450d-b101-526898b59efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24136
7067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.241367067
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3065580906
Short name T611
Test name
Test status
Simulation time 1423926391 ps
CPU time 38.43 seconds
Started Dec 31 01:32:19 PM PST 23
Finished Dec 31 01:33:03 PM PST 23
Peak memory 248708 kb
Host smart-1be081d5-3f4a-4896-aad9-a7e115ea7288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30655
80906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3065580906
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3191641405
Short name T618
Test name
Test status
Simulation time 37007002368 ps
CPU time 1293.05 seconds
Started Dec 31 01:34:13 PM PST 23
Finished Dec 31 01:55:47 PM PST 23
Peak memory 289448 kb
Host smart-b333f62d-686e-43fe-ab9e-ce7660c45482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191641405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3191641405
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.566391950
Short name T255
Test name
Test status
Simulation time 2455188647 ps
CPU time 132.31 seconds
Started Dec 31 01:32:53 PM PST 23
Finished Dec 31 01:35:06 PM PST 23
Peak memory 256200 kb
Host smart-1901e86d-35fa-4e9d-80f5-f046e9fcd0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56639
1950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.566391950
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3408703880
Short name T394
Test name
Test status
Simulation time 1178392324 ps
CPU time 48.31 seconds
Started Dec 31 01:32:00 PM PST 23
Finished Dec 31 01:32:50 PM PST 23
Peak memory 254300 kb
Host smart-bc7600a1-ac48-4402-8bd0-f1c5eeb6eaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
03880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3408703880
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1872520384
Short name T44
Test name
Test status
Simulation time 45724960617 ps
CPU time 2533.84 seconds
Started Dec 31 01:33:46 PM PST 23
Finished Dec 31 02:16:00 PM PST 23
Peak memory 288688 kb
Host smart-2aad0373-7ab2-486d-8996-d39aad67bb45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872520384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1872520384
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2457425480
Short name T308
Test name
Test status
Simulation time 6001813445 ps
CPU time 247.63 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:38:08 PM PST 23
Peak memory 247452 kb
Host smart-0580e4a7-ac77-41d1-a618-cdf1db792fba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457425480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2457425480
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3113845626
Short name T613
Test name
Test status
Simulation time 520572254 ps
CPU time 9.69 seconds
Started Dec 31 01:32:59 PM PST 23
Finished Dec 31 01:33:09 PM PST 23
Peak memory 248596 kb
Host smart-523c93ee-4e91-4a5f-accb-952671d33526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
45626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3113845626
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1092669733
Short name T389
Test name
Test status
Simulation time 2458811092 ps
CPU time 35.27 seconds
Started Dec 31 01:32:57 PM PST 23
Finished Dec 31 01:33:33 PM PST 23
Peak memory 255180 kb
Host smart-500b4a70-436b-4983-b03b-5fab36ca0b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10926
69733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1092669733
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3170040519
Short name T440
Test name
Test status
Simulation time 163045076 ps
CPU time 12.16 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:32:32 PM PST 23
Peak memory 253312 kb
Host smart-76539ee9-bb3b-4ac2-a758-c43ad8231bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31700
40519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3170040519
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1578011347
Short name T469
Test name
Test status
Simulation time 1535185570 ps
CPU time 60.72 seconds
Started Dec 31 01:32:07 PM PST 23
Finished Dec 31 01:33:08 PM PST 23
Peak memory 248600 kb
Host smart-42cc9aba-e508-4f9f-aa99-34a40b330775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780
11347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1578011347
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2510504634
Short name T323
Test name
Test status
Simulation time 44735485869 ps
CPU time 2601.45 seconds
Started Dec 31 01:33:50 PM PST 23
Finished Dec 31 02:17:12 PM PST 23
Peak memory 289496 kb
Host smart-b7a78dd1-3265-4c6d-8507-3b9fb0f6e15c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510504634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2510504634
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2903669393
Short name T468
Test name
Test status
Simulation time 173971175880 ps
CPU time 2824.76 seconds
Started Dec 31 01:33:53 PM PST 23
Finished Dec 31 02:21:04 PM PST 23
Peak memory 289312 kb
Host smart-c3a62d2f-5a18-42d9-9af2-79ba9d4c64a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903669393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2903669393
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.582810448
Short name T678
Test name
Test status
Simulation time 2941682944 ps
CPU time 52.64 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:34:53 PM PST 23
Peak memory 255884 kb
Host smart-32cb15ed-d202-4309-9617-edc3ee294335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58281
0448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.582810448
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1596889064
Short name T425
Test name
Test status
Simulation time 2119993426 ps
CPU time 20.44 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:34:21 PM PST 23
Peak memory 254352 kb
Host smart-d7df2571-b02b-4d50-af4f-3a3bab7275c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15968
89064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1596889064
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3920760757
Short name T281
Test name
Test status
Simulation time 24495475511 ps
CPU time 1341.34 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 01:56:29 PM PST 23
Peak memory 271012 kb
Host smart-c2351b66-46fc-49e7-a114-278fed115a0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920760757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3920760757
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1325039329
Short name T419
Test name
Test status
Simulation time 11613143200 ps
CPU time 1288.91 seconds
Started Dec 31 01:33:50 PM PST 23
Finished Dec 31 01:55:21 PM PST 23
Peak memory 288992 kb
Host smart-84c9fde3-c329-43e1-9576-58a89b007f22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325039329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1325039329
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4116971248
Short name T501
Test name
Test status
Simulation time 12156035760 ps
CPU time 227.94 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:37:53 PM PST 23
Peak memory 247284 kb
Host smart-7accf094-b924-4c75-9957-3d455ba04182
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116971248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4116971248
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3035626439
Short name T430
Test name
Test status
Simulation time 8049989651 ps
CPU time 63.99 seconds
Started Dec 31 01:33:52 PM PST 23
Finished Dec 31 01:35:01 PM PST 23
Peak memory 255320 kb
Host smart-1d9c77ba-b292-4d7e-995c-18817d915aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356
26439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3035626439
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2193468132
Short name T505
Test name
Test status
Simulation time 798281500 ps
CPU time 46.41 seconds
Started Dec 31 01:34:11 PM PST 23
Finished Dec 31 01:34:59 PM PST 23
Peak memory 248140 kb
Host smart-7c11dec1-6ea1-4824-bea5-d69beac7da34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21934
68132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2193468132
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.840635264
Short name T413
Test name
Test status
Simulation time 17430027922 ps
CPU time 57.54 seconds
Started Dec 31 01:33:40 PM PST 23
Finished Dec 31 01:34:39 PM PST 23
Peak memory 254476 kb
Host smart-22e66725-f538-470c-bddc-dd1d2e5f457b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84063
5264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.840635264
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2287130556
Short name T549
Test name
Test status
Simulation time 34113710 ps
CPU time 4.3 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 01:34:12 PM PST 23
Peak memory 240488 kb
Host smart-836344b9-1600-4d0a-aca7-ad0c4c2a2184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22871
30556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2287130556
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.942136692
Short name T270
Test name
Test status
Simulation time 717606324840 ps
CPU time 2518.56 seconds
Started Dec 31 01:33:51 PM PST 23
Finished Dec 31 02:15:52 PM PST 23
Peak memory 288912 kb
Host smart-292e75f2-29b7-4c46-b192-f81c63b88c37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942136692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.942136692
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2090023483
Short name T105
Test name
Test status
Simulation time 17348132184 ps
CPU time 1358 seconds
Started Dec 31 01:34:13 PM PST 23
Finished Dec 31 01:56:52 PM PST 23
Peak memory 289824 kb
Host smart-389b13e9-303a-4c2d-b6cc-03a9ad286730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090023483 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2090023483
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2566860376
Short name T212
Test name
Test status
Simulation time 73559441 ps
CPU time 2.88 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:31:31 PM PST 23
Peak memory 248808 kb
Host smart-6b00264d-94e5-49d0-bfc0-05c55f420622
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2566860376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2566860376
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2704742695
Short name T518
Test name
Test status
Simulation time 207156778297 ps
CPU time 1309.11 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:53:17 PM PST 23
Peak memory 265072 kb
Host smart-a93dea9e-28c7-47d3-9c95-27662ff11fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704742695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2704742695
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1089070905
Short name T659
Test name
Test status
Simulation time 9255796020 ps
CPU time 21.77 seconds
Started Dec 31 01:31:56 PM PST 23
Finished Dec 31 01:32:20 PM PST 23
Peak memory 240440 kb
Host smart-0c51ab3e-8b66-44c2-bcbb-e3fe74b82459
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1089070905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1089070905
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3252082084
Short name T649
Test name
Test status
Simulation time 6875624020 ps
CPU time 131.42 seconds
Started Dec 31 01:31:31 PM PST 23
Finished Dec 31 01:33:43 PM PST 23
Peak memory 256380 kb
Host smart-027d097b-17e9-45d9-a9fe-738feb5b3cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
82084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3252082084
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1767887908
Short name T531
Test name
Test status
Simulation time 146150662 ps
CPU time 11.64 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:31:41 PM PST 23
Peak memory 248680 kb
Host smart-6020b9a9-1790-44da-a686-033eec24d590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17678
87908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1767887908
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3640235841
Short name T301
Test name
Test status
Simulation time 17078892535 ps
CPU time 1065.43 seconds
Started Dec 31 01:32:02 PM PST 23
Finished Dec 31 01:49:48 PM PST 23
Peak memory 272760 kb
Host smart-b1ac169b-4db4-41fe-b2fd-635368bb224b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640235841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3640235841
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.958026017
Short name T381
Test name
Test status
Simulation time 22923272332 ps
CPU time 1350.63 seconds
Started Dec 31 01:31:29 PM PST 23
Finished Dec 31 01:54:01 PM PST 23
Peak memory 271128 kb
Host smart-73581354-998c-4df6-a59d-7aad69424cde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958026017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.958026017
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2351712537
Short name T299
Test name
Test status
Simulation time 13911794860 ps
CPU time 584.53 seconds
Started Dec 31 01:31:31 PM PST 23
Finished Dec 31 01:41:16 PM PST 23
Peak memory 247268 kb
Host smart-c0eaa20a-c809-4574-8aaa-4b7b4e85d345
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351712537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2351712537
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1973710989
Short name T448
Test name
Test status
Simulation time 739051722 ps
CPU time 43.05 seconds
Started Dec 31 01:31:26 PM PST 23
Finished Dec 31 01:32:10 PM PST 23
Peak memory 248564 kb
Host smart-e1567526-3bbe-481b-b4b3-281443e79b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19737
10989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1973710989
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1213676779
Short name T56
Test name
Test status
Simulation time 1313662979 ps
CPU time 28.46 seconds
Started Dec 31 01:31:35 PM PST 23
Finished Dec 31 01:32:05 PM PST 23
Peak memory 254304 kb
Host smart-b4a5291a-752f-435a-928b-45cc138b5aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12136
76779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1213676779
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1877995029
Short name T42
Test name
Test status
Simulation time 1391826250 ps
CPU time 55.76 seconds
Started Dec 31 01:31:26 PM PST 23
Finished Dec 31 01:32:23 PM PST 23
Peak memory 270388 kb
Host smart-5ab01836-e454-4f69-b634-6ac880bfd435
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1877995029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1877995029
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2556541524
Short name T593
Test name
Test status
Simulation time 78562701 ps
CPU time 10.51 seconds
Started Dec 31 01:31:59 PM PST 23
Finished Dec 31 01:32:12 PM PST 23
Peak memory 246872 kb
Host smart-7aef935f-ca39-43f2-91a1-40cec8cf33db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25565
41524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2556541524
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3626761083
Short name T570
Test name
Test status
Simulation time 495918070 ps
CPU time 9.75 seconds
Started Dec 31 01:31:26 PM PST 23
Finished Dec 31 01:31:38 PM PST 23
Peak memory 248608 kb
Host smart-6d900d1b-35b2-4046-91c2-3c24607af5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36267
61083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3626761083
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2958606129
Short name T482
Test name
Test status
Simulation time 14789403777 ps
CPU time 1333.25 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:53:41 PM PST 23
Peak memory 288532 kb
Host smart-8d91a133-de0d-4bd9-96c4-5c81bbf83f38
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958606129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2958606129
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2430341847
Short name T326
Test name
Test status
Simulation time 88403961669 ps
CPU time 5504.35 seconds
Started Dec 31 01:31:26 PM PST 23
Finished Dec 31 03:03:12 PM PST 23
Peak memory 331172 kb
Host smart-81dde7f7-4755-4853-8a77-99ac981cf60b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430341847 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2430341847
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3582458546
Short name T226
Test name
Test status
Simulation time 74952420794 ps
CPU time 1468.6 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 01:58:06 PM PST 23
Peak memory 288500 kb
Host smart-b7c9876a-0bb8-442a-8524-6ac86a2c00dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582458546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3582458546
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3269346310
Short name T374
Test name
Test status
Simulation time 1728656191 ps
CPU time 147.11 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:36:28 PM PST 23
Peak memory 256756 kb
Host smart-7b325f92-9154-4d6b-bbd0-21e338be0cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32693
46310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3269346310
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.889683101
Short name T121
Test name
Test status
Simulation time 1601308630 ps
CPU time 19.57 seconds
Started Dec 31 01:34:02 PM PST 23
Finished Dec 31 01:34:26 PM PST 23
Peak memory 254604 kb
Host smart-2e2aa974-f49a-4317-8114-a4ca11b26d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88968
3101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.889683101
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.640175794
Short name T260
Test name
Test status
Simulation time 17648470190 ps
CPU time 1089.54 seconds
Started Dec 31 01:33:58 PM PST 23
Finished Dec 31 01:52:11 PM PST 23
Peak memory 265108 kb
Host smart-d889279b-7d31-4c64-802c-7964559927d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640175794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.640175794
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.732172732
Short name T399
Test name
Test status
Simulation time 80511028420 ps
CPU time 1403.72 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 01:57:40 PM PST 23
Peak memory 288948 kb
Host smart-182804f8-af28-42a0-b653-0cf1c08eef9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732172732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.732172732
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.445089127
Short name T578
Test name
Test status
Simulation time 6771490062 ps
CPU time 266.93 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 01:38:32 PM PST 23
Peak memory 254676 kb
Host smart-fd79f3ea-052c-4942-9977-9ac2db7b1a43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445089127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.445089127
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3703278720
Short name T532
Test name
Test status
Simulation time 2137478578 ps
CPU time 61.34 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:35:07 PM PST 23
Peak memory 248692 kb
Host smart-a8295f45-78c1-40d4-bbe6-9c4a7924fecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37032
78720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3703278720
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1001396737
Short name T241
Test name
Test status
Simulation time 628200057 ps
CPU time 9.63 seconds
Started Dec 31 01:34:07 PM PST 23
Finished Dec 31 01:34:18 PM PST 23
Peak memory 249032 kb
Host smart-a1b06439-6793-468f-bcf1-ae83af633572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
96737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1001396737
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1542160509
Short name T579
Test name
Test status
Simulation time 1149782811 ps
CPU time 20.62 seconds
Started Dec 31 01:33:58 PM PST 23
Finished Dec 31 01:34:22 PM PST 23
Peak memory 253708 kb
Host smart-a2da27b5-cbf1-46c4-a190-e6f1cec54168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
60509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1542160509
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.576199371
Short name T721
Test name
Test status
Simulation time 1117599847 ps
CPU time 59.68 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 01:34:42 PM PST 23
Peak memory 248592 kb
Host smart-fccd8397-b3ca-4ec0-a102-b64f8cd78837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57619
9371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.576199371
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2794063476
Short name T106
Test name
Test status
Simulation time 50345584058 ps
CPU time 4703.08 seconds
Started Dec 31 01:34:09 PM PST 23
Finished Dec 31 02:52:35 PM PST 23
Peak memory 350172 kb
Host smart-893ca864-bda6-4fed-b1b1-3e5ae4fcd5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794063476 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2794063476
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2177906356
Short name T114
Test name
Test status
Simulation time 33659292299 ps
CPU time 1265.43 seconds
Started Dec 31 01:33:38 PM PST 23
Finished Dec 31 01:54:44 PM PST 23
Peak memory 288884 kb
Host smart-cfaae5e6-3678-421d-8518-c73313ac2cb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177906356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2177906356
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.480746200
Short name T688
Test name
Test status
Simulation time 2016095384 ps
CPU time 72.61 seconds
Started Dec 31 01:34:08 PM PST 23
Finished Dec 31 01:35:22 PM PST 23
Peak memory 255848 kb
Host smart-7faeaf2d-68a8-4053-8fdd-67325e92a55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48074
6200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.480746200
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1072772214
Short name T734
Test name
Test status
Simulation time 699804244 ps
CPU time 35.9 seconds
Started Dec 31 01:33:54 PM PST 23
Finished Dec 31 01:34:36 PM PST 23
Peak memory 248568 kb
Host smart-af84e95b-2503-4472-a7b9-5bef48136c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10727
72214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1072772214
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1489711435
Short name T74
Test name
Test status
Simulation time 26401190971 ps
CPU time 1569.85 seconds
Started Dec 31 01:33:20 PM PST 23
Finished Dec 31 01:59:31 PM PST 23
Peak memory 273192 kb
Host smart-4e1260a6-ef69-4ab7-84b1-7264056291ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489711435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1489711435
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2431931381
Short name T716
Test name
Test status
Simulation time 47952716110 ps
CPU time 2255.57 seconds
Started Dec 31 01:33:57 PM PST 23
Finished Dec 31 02:11:36 PM PST 23
Peak memory 282908 kb
Host smart-1ad93c92-bc46-4dd7-9a79-75a115c8b939
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431931381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2431931381
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2517724880
Short name T544
Test name
Test status
Simulation time 1827970895 ps
CPU time 58.42 seconds
Started Dec 31 01:34:14 PM PST 23
Finished Dec 31 01:35:14 PM PST 23
Peak memory 256852 kb
Host smart-1d5d73e2-6562-4179-923b-efe81ee654f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25177
24880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2517724880
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2310922456
Short name T718
Test name
Test status
Simulation time 48268294 ps
CPU time 4.57 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:34:10 PM PST 23
Peak memory 239988 kb
Host smart-f5e0d54a-08e7-46f7-8a69-1a6466facdd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
22456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2310922456
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.505998832
Short name T386
Test name
Test status
Simulation time 230362181 ps
CPU time 22.92 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:34:08 PM PST 23
Peak memory 248632 kb
Host smart-4570eb51-3e7a-4c68-a773-a4d9bfed73f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50599
8832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.505998832
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2598536471
Short name T470
Test name
Test status
Simulation time 1785535996 ps
CPU time 51.95 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 01:35:08 PM PST 23
Peak memory 248660 kb
Host smart-7a82fb09-010e-4a9f-a2e0-1c24ebd8e851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25985
36471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2598536471
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2293298344
Short name T329
Test name
Test status
Simulation time 61201294089 ps
CPU time 3001.86 seconds
Started Dec 31 01:34:03 PM PST 23
Finished Dec 31 02:24:09 PM PST 23
Peak memory 289536 kb
Host smart-91bc031c-5d76-4bfa-8d12-08d267b28631
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293298344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2293298344
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.81216631
Short name T453
Test name
Test status
Simulation time 124262836767 ps
CPU time 727.11 seconds
Started Dec 31 01:34:08 PM PST 23
Finished Dec 31 01:46:17 PM PST 23
Peak memory 268036 kb
Host smart-6f0e36bc-9e6e-4077-84e1-b34b17d6cde7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81216631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.81216631
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3232675513
Short name T54
Test name
Test status
Simulation time 2743775834 ps
CPU time 151.9 seconds
Started Dec 31 01:34:07 PM PST 23
Finished Dec 31 01:36:41 PM PST 23
Peak memory 249628 kb
Host smart-ed0ddf1a-ac18-454d-9a51-3b842b9cf237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32326
75513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3232675513
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1358675536
Short name T652
Test name
Test status
Simulation time 900317941 ps
CPU time 50.78 seconds
Started Dec 31 01:33:49 PM PST 23
Finished Dec 31 01:34:40 PM PST 23
Peak memory 254980 kb
Host smart-a29bd50a-a568-452a-820e-426a8d2207ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13586
75536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1358675536
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2353762908
Short name T352
Test name
Test status
Simulation time 24487296612 ps
CPU time 1204.97 seconds
Started Dec 31 01:34:18 PM PST 23
Finished Dec 31 01:54:24 PM PST 23
Peak memory 289136 kb
Host smart-eb66c25d-bd38-481e-ba09-c86e591d9869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353762908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2353762908
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.542958532
Short name T415
Test name
Test status
Simulation time 13283108732 ps
CPU time 1262.79 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:55:09 PM PST 23
Peak memory 288680 kb
Host smart-fadf7c26-9e4c-43a1-be3b-75f4290ed8df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542958532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.542958532
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1135686022
Short name T674
Test name
Test status
Simulation time 6666690975 ps
CPU time 288.58 seconds
Started Dec 31 01:34:20 PM PST 23
Finished Dec 31 01:39:10 PM PST 23
Peak memory 247288 kb
Host smart-9268dd25-49b7-437e-8da3-664907ebb4e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135686022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1135686022
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1577148528
Short name T65
Test name
Test status
Simulation time 742833914 ps
CPU time 42.74 seconds
Started Dec 31 01:33:42 PM PST 23
Finished Dec 31 01:34:25 PM PST 23
Peak memory 248608 kb
Host smart-7498b695-26e5-4e56-8384-3f73453e28eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15771
48528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1577148528
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.976410705
Short name T472
Test name
Test status
Simulation time 1092578732 ps
CPU time 10.09 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:33:54 PM PST 23
Peak memory 247720 kb
Host smart-f3865aae-ea6a-4573-96f1-d88f54e77c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97641
0705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.976410705
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.994956517
Short name T682
Test name
Test status
Simulation time 48273581 ps
CPU time 4.63 seconds
Started Dec 31 01:34:14 PM PST 23
Finished Dec 31 01:34:20 PM PST 23
Peak memory 238724 kb
Host smart-2d10eb24-7a1a-45aa-9bb0-1e53b647cb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99495
6517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.994956517
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3000675685
Short name T428
Test name
Test status
Simulation time 276722990 ps
CPU time 24.26 seconds
Started Dec 31 01:34:14 PM PST 23
Finished Dec 31 01:34:40 PM PST 23
Peak memory 248612 kb
Host smart-b5cecb6e-0fd5-477b-8048-0591d7a2fa51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006
75685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3000675685
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1860873279
Short name T273
Test name
Test status
Simulation time 92220413135 ps
CPU time 2437.23 seconds
Started Dec 31 01:34:12 PM PST 23
Finished Dec 31 02:14:51 PM PST 23
Peak memory 287940 kb
Host smart-97918d7d-efb0-455a-9601-e0f595685c61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860873279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1860873279
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.320148535
Short name T683
Test name
Test status
Simulation time 26306051919 ps
CPU time 2672.15 seconds
Started Dec 31 01:34:23 PM PST 23
Finished Dec 31 02:18:57 PM PST 23
Peak memory 319452 kb
Host smart-30fba7fa-d9d6-4978-b421-cf96688f6f46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320148535 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.320148535
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3764009405
Short name T537
Test name
Test status
Simulation time 50489480608 ps
CPU time 2784.93 seconds
Started Dec 31 01:34:20 PM PST 23
Finished Dec 31 02:20:47 PM PST 23
Peak memory 289304 kb
Host smart-677c49e7-40b5-45af-8326-3f30824b3471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764009405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3764009405
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.173275995
Short name T404
Test name
Test status
Simulation time 20555465267 ps
CPU time 278.12 seconds
Started Dec 31 01:34:08 PM PST 23
Finished Dec 31 01:38:49 PM PST 23
Peak memory 256876 kb
Host smart-f1314d58-735b-4d34-9b33-6fa71eea9813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17327
5995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.173275995
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2457009507
Short name T621
Test name
Test status
Simulation time 364406730 ps
CPU time 22.97 seconds
Started Dec 31 01:34:02 PM PST 23
Finished Dec 31 01:34:29 PM PST 23
Peak memory 248428 kb
Host smart-856c36b6-717e-4d2f-81c0-c885d05e5ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24570
09507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2457009507
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3198012723
Short name T345
Test name
Test status
Simulation time 137587552360 ps
CPU time 1051.64 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:51:37 PM PST 23
Peak memory 272736 kb
Host smart-a43e2cd4-0743-432c-b0b1-2ff5127056a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198012723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3198012723
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1502231428
Short name T509
Test name
Test status
Simulation time 23209151907 ps
CPU time 660.97 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:44:04 PM PST 23
Peak memory 265028 kb
Host smart-49eac3dd-a155-49da-817f-5f35c3b29475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502231428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1502231428
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3667090586
Short name T513
Test name
Test status
Simulation time 11850643363 ps
CPU time 451.2 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:41:38 PM PST 23
Peak memory 248568 kb
Host smart-699d5b87-2b4a-4cad-8e24-a6f35ac4df0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667090586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3667090586
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2349909524
Short name T447
Test name
Test status
Simulation time 2759807335 ps
CPU time 36.61 seconds
Started Dec 31 01:34:07 PM PST 23
Finished Dec 31 01:34:45 PM PST 23
Peak memory 248716 kb
Host smart-3b4ddffa-1f41-41c6-952b-43569d13a59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23499
09524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2349909524
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2271979732
Short name T591
Test name
Test status
Simulation time 349680007 ps
CPU time 26.15 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 01:34:42 PM PST 23
Peak memory 247208 kb
Host smart-55630c85-d7e2-4903-ada2-55ef1f0ca049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22719
79732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2271979732
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1206143870
Short name T619
Test name
Test status
Simulation time 3163228235 ps
CPU time 37.85 seconds
Started Dec 31 01:34:22 PM PST 23
Finished Dec 31 01:35:02 PM PST 23
Peak memory 248600 kb
Host smart-8dbbd735-e5d1-4cc0-98bc-1655a8d3d5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
43870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1206143870
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2980989762
Short name T266
Test name
Test status
Simulation time 792923292 ps
CPU time 32.32 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:34:41 PM PST 23
Peak memory 248672 kb
Host smart-8f4c5522-255c-4849-88cc-97d38767ac32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809
89762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2980989762
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1310786386
Short name T422
Test name
Test status
Simulation time 27168449966 ps
CPU time 1278.86 seconds
Started Dec 31 01:33:02 PM PST 23
Finished Dec 31 01:54:21 PM PST 23
Peak memory 288716 kb
Host smart-3bfabc42-7c26-4325-bde0-62b17f6fdecf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310786386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1310786386
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2339456203
Short name T279
Test name
Test status
Simulation time 129887926950 ps
CPU time 1837.53 seconds
Started Dec 31 01:34:37 PM PST 23
Finished Dec 31 02:05:20 PM PST 23
Peak memory 270096 kb
Host smart-f393e8c0-8e89-4873-be6c-f4f70b886945
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339456203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2339456203
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.4244582615
Short name T489
Test name
Test status
Simulation time 935578123 ps
CPU time 69.23 seconds
Started Dec 31 01:34:35 PM PST 23
Finished Dec 31 01:35:48 PM PST 23
Peak memory 249592 kb
Host smart-7e557bed-69ae-4b25-b413-4efa3a7a8a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
82615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4244582615
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3662560299
Short name T229
Test name
Test status
Simulation time 1614962681 ps
CPU time 24.49 seconds
Started Dec 31 01:34:33 PM PST 23
Finished Dec 31 01:35:02 PM PST 23
Peak memory 254460 kb
Host smart-8f127e50-e729-4e84-be5f-f32b3cc6b47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36625
60299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3662560299
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1438625013
Short name T360
Test name
Test status
Simulation time 222035419914 ps
CPU time 3059.44 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 02:24:02 PM PST 23
Peak memory 289052 kb
Host smart-213b1edf-73db-45e1-b97f-fa78403cdb10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438625013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1438625013
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2014591204
Short name T627
Test name
Test status
Simulation time 45952057094 ps
CPU time 2376.61 seconds
Started Dec 31 01:33:33 PM PST 23
Finished Dec 31 02:13:10 PM PST 23
Peak memory 284940 kb
Host smart-d9743ae8-6e94-4795-9c1b-615df6d862aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014591204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2014591204
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.620631327
Short name T288
Test name
Test status
Simulation time 6426547542 ps
CPU time 133.46 seconds
Started Dec 31 01:34:43 PM PST 23
Finished Dec 31 01:36:58 PM PST 23
Peak memory 246452 kb
Host smart-b20a7798-f6b5-46dd-a7cb-af18c4a25a50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620631327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.620631327
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3657742242
Short name T265
Test name
Test status
Simulation time 655916772 ps
CPU time 41.47 seconds
Started Dec 31 01:34:29 PM PST 23
Finished Dec 31 01:35:19 PM PST 23
Peak memory 248688 kb
Host smart-59e4dcaa-4d89-4afb-9f82-286c2e660fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36577
42242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3657742242
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3183253798
Short name T604
Test name
Test status
Simulation time 279267861 ps
CPU time 30.18 seconds
Started Dec 31 01:34:16 PM PST 23
Finished Dec 31 01:34:48 PM PST 23
Peak memory 248628 kb
Host smart-2ca10e56-b261-479b-b23f-1788d9881c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832
53798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3183253798
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.222664087
Short name T340
Test name
Test status
Simulation time 367443605 ps
CPU time 24.43 seconds
Started Dec 31 01:34:35 PM PST 23
Finished Dec 31 01:35:03 PM PST 23
Peak memory 255068 kb
Host smart-84e3e3dc-06b3-4abe-a15d-b82aad8a69a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22266
4087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.222664087
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2340770985
Short name T378
Test name
Test status
Simulation time 386287675 ps
CPU time 23.65 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:34:29 PM PST 23
Peak memory 248536 kb
Host smart-2598990d-01ea-4540-b109-3a59c580a3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
70985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2340770985
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4240782767
Short name T631
Test name
Test status
Simulation time 35112533891 ps
CPU time 1085.92 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:51:35 PM PST 23
Peak memory 283168 kb
Host smart-688f7bd7-8e3f-4450-af21-6ef15e252d7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240782767 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4240782767
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3526689368
Short name T58
Test name
Test status
Simulation time 36747767623 ps
CPU time 873.34 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:47:00 PM PST 23
Peak memory 288428 kb
Host smart-a3aa7e24-6acb-4ae0-b8e0-9e04c3938dd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526689368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3526689368
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3941940851
Short name T456
Test name
Test status
Simulation time 31979460696 ps
CPU time 261.95 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:36:47 PM PST 23
Peak memory 256348 kb
Host smart-79da0c22-d564-436f-958b-717e11d42416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39419
40851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3941940851
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1794949560
Short name T699
Test name
Test status
Simulation time 737359166 ps
CPU time 22.09 seconds
Started Dec 31 01:32:58 PM PST 23
Finished Dec 31 01:33:20 PM PST 23
Peak memory 254084 kb
Host smart-adfec276-3be1-4142-81f8-27cf7e3a7c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
49560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1794949560
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1566331624
Short name T343
Test name
Test status
Simulation time 13688075394 ps
CPU time 1216.38 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:53:18 PM PST 23
Peak memory 289060 kb
Host smart-0a99c4a7-98bb-4e8d-b77e-da8f74c7b78f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566331624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1566331624
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4145541302
Short name T539
Test name
Test status
Simulation time 22468401104 ps
CPU time 562.21 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:42:51 PM PST 23
Peak memory 265072 kb
Host smart-c3bc29ae-12c3-4517-a2c7-5ea0faa50f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145541302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4145541302
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1972144615
Short name T595
Test name
Test status
Simulation time 9694394162 ps
CPU time 394.71 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 01:39:31 PM PST 23
Peak memory 247672 kb
Host smart-7e6dc695-5b7c-4689-a4f3-7a89dec0fba6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972144615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1972144615
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1850985750
Short name T669
Test name
Test status
Simulation time 119856135 ps
CPU time 13.07 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 01:33:42 PM PST 23
Peak memory 248680 kb
Host smart-d33b8521-53fc-40d4-8dec-793e72da4a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18509
85750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1850985750
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2827293849
Short name T388
Test name
Test status
Simulation time 167991885 ps
CPU time 15.49 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 01:33:08 PM PST 23
Peak memory 254260 kb
Host smart-97d03a9e-c1e3-469e-97aa-7393e8e4c29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28272
93849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2827293849
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2053454162
Short name T696
Test name
Test status
Simulation time 2676944277 ps
CPU time 46.66 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 01:33:39 PM PST 23
Peak memory 256860 kb
Host smart-bac658f6-3fb4-47f2-a21e-ac729684ee6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20534
54162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2053454162
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1672373585
Short name T567
Test name
Test status
Simulation time 10789188281 ps
CPU time 1211.7 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 01:54:16 PM PST 23
Peak memory 289832 kb
Host smart-79d9858b-100e-4737-a80e-4ebc464f9fd1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672373585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1672373585
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.709722875
Short name T685
Test name
Test status
Simulation time 45824284426 ps
CPU time 1999.83 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 02:06:25 PM PST 23
Peak memory 272784 kb
Host smart-ba4a9862-f5fc-4213-8e52-e70df8dc68c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709722875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.709722875
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2244011601
Short name T446
Test name
Test status
Simulation time 2755931933 ps
CPU time 47.28 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:34:32 PM PST 23
Peak memory 256260 kb
Host smart-68488a28-36f8-40bb-b24a-5668c88a2401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
11601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2244011601
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2134876160
Short name T677
Test name
Test status
Simulation time 129602689 ps
CPU time 13.29 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:33:58 PM PST 23
Peak memory 254316 kb
Host smart-804f278f-28f9-48d1-8170-f25531213344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21348
76160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2134876160
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1679516415
Short name T358
Test name
Test status
Simulation time 37513530262 ps
CPU time 1414.09 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:56:00 PM PST 23
Peak memory 287976 kb
Host smart-5074e054-fded-40f6-a6ad-1a43cd746b81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679516415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1679516415
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1547964032
Short name T407
Test name
Test status
Simulation time 9255014003 ps
CPU time 1280.67 seconds
Started Dec 31 01:33:05 PM PST 23
Finished Dec 31 01:54:26 PM PST 23
Peak memory 286752 kb
Host smart-0091c999-0bab-412a-bba2-369fec6b571a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547964032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1547964032
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2966428975
Short name T77
Test name
Test status
Simulation time 35982011617 ps
CPU time 369 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:39:11 PM PST 23
Peak memory 246852 kb
Host smart-9d9f829a-4da8-4b18-9b4b-12339d5f3535
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966428975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2966428975
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2242324342
Short name T66
Test name
Test status
Simulation time 664691651 ps
CPU time 21.31 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:34:01 PM PST 23
Peak memory 248576 kb
Host smart-a87c6482-ea35-4c14-ad64-8f1054c0f20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
24342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2242324342
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2760736683
Short name T594
Test name
Test status
Simulation time 51277305 ps
CPU time 4.39 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 01:34:09 PM PST 23
Peak memory 238692 kb
Host smart-d4d27229-43ac-4255-bc4d-f7e6cadd7215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27607
36683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2760736683
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1846553011
Short name T444
Test name
Test status
Simulation time 869496596 ps
CPU time 26.39 seconds
Started Dec 31 01:32:53 PM PST 23
Finished Dec 31 01:33:20 PM PST 23
Peak memory 248660 kb
Host smart-cc1972ea-120a-47d1-a441-75e5ea8f5ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
53011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1846553011
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1106908759
Short name T129
Test name
Test status
Simulation time 2506595838 ps
CPU time 136.12 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 01:35:13 PM PST 23
Peak memory 250652 kb
Host smart-416550df-0b3d-4393-b243-50080928457e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106908759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1106908759
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3314399488
Short name T29
Test name
Test status
Simulation time 388510484181 ps
CPU time 2188.16 seconds
Started Dec 31 01:32:19 PM PST 23
Finished Dec 31 02:08:53 PM PST 23
Peak memory 287824 kb
Host smart-44072cf6-974d-4311-921f-4258e32e1d24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314399488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3314399488
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2769357238
Short name T661
Test name
Test status
Simulation time 6772191945 ps
CPU time 189.76 seconds
Started Dec 31 01:32:57 PM PST 23
Finished Dec 31 01:36:07 PM PST 23
Peak memory 249612 kb
Host smart-92d9f5a7-fa90-420a-822b-ded1f571c2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27693
57238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2769357238
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.748718036
Short name T85
Test name
Test status
Simulation time 1299662109 ps
CPU time 34.68 seconds
Started Dec 31 01:32:51 PM PST 23
Finished Dec 31 01:33:27 PM PST 23
Peak memory 254316 kb
Host smart-414245de-a6d5-4240-93b7-0cf08630b0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74871
8036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.748718036
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3947921838
Short name T478
Test name
Test status
Simulation time 137566694713 ps
CPU time 1843.36 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 02:04:28 PM PST 23
Peak memory 273344 kb
Host smart-c053b4fe-831c-4ac0-84d5-c9a693e0fe3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947921838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3947921838
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1477347073
Short name T283
Test name
Test status
Simulation time 53446769180 ps
CPU time 246.2 seconds
Started Dec 31 01:33:33 PM PST 23
Finished Dec 31 01:37:39 PM PST 23
Peak memory 247312 kb
Host smart-08971ad9-60a8-4a2e-973f-5e8eda4ba35d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477347073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1477347073
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3523928679
Short name T676
Test name
Test status
Simulation time 600005539 ps
CPU time 25.78 seconds
Started Dec 31 01:32:24 PM PST 23
Finished Dec 31 01:32:53 PM PST 23
Peak memory 248644 kb
Host smart-142e4b4c-cd84-43c5-a446-60d7b5511633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35239
28679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3523928679
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.855085107
Short name T719
Test name
Test status
Simulation time 365789061 ps
CPU time 32.65 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 01:32:50 PM PST 23
Peak memory 253948 kb
Host smart-e32942db-c2c0-411a-a853-19779e305a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85508
5107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.855085107
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.84520915
Short name T707
Test name
Test status
Simulation time 318890814 ps
CPU time 25.53 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 01:34:05 PM PST 23
Peak memory 248640 kb
Host smart-9a87cad4-c211-4a54-b3d4-3b7b14c7b6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84520
915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.84520915
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.192376834
Short name T135
Test name
Test status
Simulation time 352805064587 ps
CPU time 1736.57 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 02:02:01 PM PST 23
Peak memory 305520 kb
Host smart-9f4c5a63-5a66-4acf-963e-a38d38acfe48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192376834 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.192376834
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.229823111
Short name T581
Test name
Test status
Simulation time 9277815253 ps
CPU time 733.02 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:45:57 PM PST 23
Peak memory 265024 kb
Host smart-8ea65f22-dbee-40a4-a427-d14230bb8ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229823111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.229823111
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1206752802
Short name T536
Test name
Test status
Simulation time 16753568756 ps
CPU time 233.05 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 01:36:57 PM PST 23
Peak memory 256908 kb
Host smart-f1171e71-f3ab-4118-b29b-7f180a3f2988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067
52802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1206752802
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3748264180
Short name T483
Test name
Test status
Simulation time 285709863 ps
CPU time 27.77 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:32:48 PM PST 23
Peak memory 255124 kb
Host smart-4b5b05c8-c459-4e7f-8ec3-8b3970968575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37482
64180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3748264180
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.139788413
Short name T479
Test name
Test status
Simulation time 182523138520 ps
CPU time 2375.65 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 02:13:04 PM PST 23
Peak memory 281268 kb
Host smart-7dff2405-f604-43ab-b0f0-bb4fb74a3a0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139788413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.139788413
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2629628930
Short name T268
Test name
Test status
Simulation time 598041889 ps
CPU time 19.02 seconds
Started Dec 31 01:33:25 PM PST 23
Finished Dec 31 01:33:45 PM PST 23
Peak memory 248568 kb
Host smart-b2a49a2c-28ed-49a3-8872-3032cb239861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26296
28930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2629628930
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.881974977
Short name T499
Test name
Test status
Simulation time 1354210317 ps
CPU time 72.35 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 01:33:39 PM PST 23
Peak memory 254816 kb
Host smart-269b6183-87e4-49f6-8755-e622fbeb5385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88197
4977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.881974977
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2089885132
Short name T337
Test name
Test status
Simulation time 2101990229 ps
CPU time 33.12 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:32:53 PM PST 23
Peak memory 254888 kb
Host smart-171083e6-d608-41ef-a0eb-581673e9a679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
85132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2089885132
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3833543797
Short name T543
Test name
Test status
Simulation time 688139114 ps
CPU time 39.77 seconds
Started Dec 31 01:32:19 PM PST 23
Finished Dec 31 01:33:04 PM PST 23
Peak memory 248800 kb
Host smart-30d8025e-16b3-4c00-b870-34ec746fba62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38335
43797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3833543797
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2988163925
Short name T317
Test name
Test status
Simulation time 44344435308 ps
CPU time 2538.44 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 02:15:56 PM PST 23
Peak memory 305348 kb
Host smart-ee26c5f1-f975-4218-a33d-85b80b23d8dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988163925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2988163925
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1701181798
Short name T325
Test name
Test status
Simulation time 21451995663 ps
CPU time 1957.98 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 02:06:06 PM PST 23
Peak memory 305568 kb
Host smart-9a556595-dd98-4ec2-a0e4-b333c3416df6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701181798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1701181798
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.821506748
Short name T230
Test name
Test status
Simulation time 43836227730 ps
CPU time 1390.68 seconds
Started Dec 31 01:32:54 PM PST 23
Finished Dec 31 01:56:05 PM PST 23
Peak memory 272936 kb
Host smart-646e7721-9f0f-40ed-90cd-873a5d394d73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821506748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.821506748
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2495870532
Short name T623
Test name
Test status
Simulation time 4074953229 ps
CPU time 194.7 seconds
Started Dec 31 01:32:47 PM PST 23
Finished Dec 31 01:36:02 PM PST 23
Peak memory 256096 kb
Host smart-55a2d1d5-77f6-42b1-9bf0-acd6a08a29b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24958
70532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2495870532
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3963189683
Short name T558
Test name
Test status
Simulation time 1027788344 ps
CPU time 22.9 seconds
Started Dec 31 01:33:02 PM PST 23
Finished Dec 31 01:33:25 PM PST 23
Peak memory 255076 kb
Host smart-113dc0c8-2330-404c-97c2-4dbd40290cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39631
89683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3963189683
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.781214691
Short name T242
Test name
Test status
Simulation time 39470871492 ps
CPU time 1072.44 seconds
Started Dec 31 01:33:23 PM PST 23
Finished Dec 31 01:51:16 PM PST 23
Peak memory 283504 kb
Host smart-c3fb9011-c22a-4f0e-b785-44c9e8082d09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781214691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.781214691
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4169051092
Short name T689
Test name
Test status
Simulation time 33190542220 ps
CPU time 444.42 seconds
Started Dec 31 01:32:47 PM PST 23
Finished Dec 31 01:40:12 PM PST 23
Peak memory 247508 kb
Host smart-df0e990d-3681-41b4-a917-7f6d27dad90e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169051092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4169051092
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3846864614
Short name T50
Test name
Test status
Simulation time 7127713962 ps
CPU time 47.1 seconds
Started Dec 31 01:33:57 PM PST 23
Finished Dec 31 01:34:48 PM PST 23
Peak memory 255748 kb
Host smart-67bfc608-c1a2-4746-bab1-8c949078412c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38468
64614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3846864614
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1433862236
Short name T274
Test name
Test status
Simulation time 439807113 ps
CPU time 43.75 seconds
Started Dec 31 01:33:40 PM PST 23
Finished Dec 31 01:34:25 PM PST 23
Peak memory 247188 kb
Host smart-fa2492ab-28fe-4614-9209-97b6b75d6ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14338
62236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1433862236
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3651023022
Short name T588
Test name
Test status
Simulation time 1025473524 ps
CPU time 38.15 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:33:40 PM PST 23
Peak memory 247464 kb
Host smart-72f2345d-bb5a-4d62-9f30-1a2dc323e8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36510
23022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3651023022
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2843616220
Short name T657
Test name
Test status
Simulation time 388547795 ps
CPU time 26.06 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:34:31 PM PST 23
Peak memory 248664 kb
Host smart-2534ba1c-1bd8-429c-a18e-2a881b68c334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28436
16220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2843616220
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.49542350
Short name T223
Test name
Test status
Simulation time 1758797617 ps
CPU time 100.65 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 01:34:07 PM PST 23
Peak memory 256456 kb
Host smart-3e007d88-790c-40f6-a73c-ad7ca5b0ff73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49542350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_hand
ler_stress_all.49542350
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.751790839
Short name T57
Test name
Test status
Simulation time 41360439123 ps
CPU time 4296.23 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 02:43:55 PM PST 23
Peak memory 338344 kb
Host smart-0c8cc8c2-acf0-40ab-8421-53a890d324be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751790839 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.751790839
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3125211354
Short name T431
Test name
Test status
Simulation time 45944719199 ps
CPU time 2552.29 seconds
Started Dec 31 01:32:48 PM PST 23
Finished Dec 31 02:15:22 PM PST 23
Peak memory 289456 kb
Host smart-bf0c3b81-2b42-4523-88e0-d692113721fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125211354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3125211354
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1878557889
Short name T136
Test name
Test status
Simulation time 338205262 ps
CPU time 9.94 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:33:13 PM PST 23
Peak memory 240484 kb
Host smart-63f64f87-078e-4d65-8c0e-f7ecc4620a6b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1878557889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1878557889
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2534093138
Short name T666
Test name
Test status
Simulation time 3711787833 ps
CPU time 195.09 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:36:17 PM PST 23
Peak memory 249884 kb
Host smart-5cce2c24-0144-4931-805a-f0cc5937175b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25340
93138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2534093138
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4212293515
Short name T449
Test name
Test status
Simulation time 1050144974 ps
CPU time 59.68 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 01:33:18 PM PST 23
Peak memory 255128 kb
Host smart-162d4c6b-50fe-409f-b9df-5f7d521b9410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
93515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4212293515
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3995270693
Short name T620
Test name
Test status
Simulation time 18389529847 ps
CPU time 1420.95 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 01:56:08 PM PST 23
Peak memory 288964 kb
Host smart-7ec1810b-e7ac-4db2-acf6-c15e9ede867d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995270693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3995270693
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1071979701
Short name T607
Test name
Test status
Simulation time 26842711306 ps
CPU time 1546.87 seconds
Started Dec 31 01:33:07 PM PST 23
Finished Dec 31 01:58:55 PM PST 23
Peak memory 271692 kb
Host smart-801d14a2-d882-4028-8456-17d542edea4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071979701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1071979701
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3859337817
Short name T305
Test name
Test status
Simulation time 6339686434 ps
CPU time 240.49 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 01:36:57 PM PST 23
Peak memory 247604 kb
Host smart-06c5f396-032a-4193-a3b4-82327bf67e08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859337817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3859337817
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3896323885
Short name T411
Test name
Test status
Simulation time 1171567349 ps
CPU time 11.78 seconds
Started Dec 31 01:32:47 PM PST 23
Finished Dec 31 01:32:59 PM PST 23
Peak memory 255468 kb
Host smart-1e062e0a-b462-48d0-b5e8-d354cbc1fb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38963
23885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3896323885
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1631701519
Short name T101
Test name
Test status
Simulation time 834740842 ps
CPU time 20.46 seconds
Started Dec 31 01:32:19 PM PST 23
Finished Dec 31 01:32:46 PM PST 23
Peak memory 248276 kb
Host smart-323f353e-dc37-4478-9460-0dfec445d795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
01519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1631701519
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2004186837
Short name T11
Test name
Test status
Simulation time 759743046 ps
CPU time 22.95 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 01:31:52 PM PST 23
Peak memory 277648 kb
Host smart-014c2700-4c5c-45f4-a936-36c94ac542ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2004186837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2004186837
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1039887980
Short name T13
Test name
Test status
Simulation time 490123541 ps
CPU time 29.79 seconds
Started Dec 31 01:32:58 PM PST 23
Finished Dec 31 01:33:29 PM PST 23
Peak memory 255408 kb
Host smart-0e981ed5-acd7-4cf1-ba51-72b5b42fd683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
87980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1039887980
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.971331662
Short name T686
Test name
Test status
Simulation time 1977975911 ps
CPU time 30.24 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:32:00 PM PST 23
Peak memory 256708 kb
Host smart-53e7b024-d039-4ae4-87af-059483576431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97133
1662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.971331662
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3571815195
Short name T107
Test name
Test status
Simulation time 662552238 ps
CPU time 57.82 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:34:00 PM PST 23
Peak memory 248624 kb
Host smart-558dbf7c-03db-4750-a691-5a6267885e57
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571815195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3571815195
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.588451872
Short name T109
Test name
Test status
Simulation time 33548380702 ps
CPU time 2164.14 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 02:07:34 PM PST 23
Peak memory 286344 kb
Host smart-7da47a04-3b7c-4426-865f-0e8bf05497aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588451872 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.588451872
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.649866132
Short name T402
Test name
Test status
Simulation time 45384866710 ps
CPU time 2443.63 seconds
Started Dec 31 01:32:51 PM PST 23
Finished Dec 31 02:13:36 PM PST 23
Peak memory 284060 kb
Host smart-b90d4368-f22c-49db-b60c-3eae98dbd576
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649866132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.649866132
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1968754429
Short name T546
Test name
Test status
Simulation time 954826223 ps
CPU time 53.61 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:33:55 PM PST 23
Peak memory 254896 kb
Host smart-823b4880-5ffa-4608-8ae1-19acd795b852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19687
54429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1968754429
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3470831323
Short name T560
Test name
Test status
Simulation time 94703030 ps
CPU time 7.36 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 01:32:26 PM PST 23
Peak memory 239932 kb
Host smart-54d07207-ae5f-46d4-b50b-e5858fe9b18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34708
31323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3470831323
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1356181265
Short name T361
Test name
Test status
Simulation time 78475028850 ps
CPU time 1555.86 seconds
Started Dec 31 01:33:06 PM PST 23
Finished Dec 31 01:59:02 PM PST 23
Peak memory 288604 kb
Host smart-fde8da99-c77f-4f8f-b743-731e40fe0939
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356181265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1356181265
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3524824706
Short name T503
Test name
Test status
Simulation time 53613796274 ps
CPU time 858.74 seconds
Started Dec 31 01:32:49 PM PST 23
Finished Dec 31 01:47:08 PM PST 23
Peak memory 269168 kb
Host smart-756ba2bb-6df6-44b1-a85b-395d486a6159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524824706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3524824706
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1316478237
Short name T304
Test name
Test status
Simulation time 31267673742 ps
CPU time 251.13 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 01:37:49 PM PST 23
Peak memory 247496 kb
Host smart-03d03bf7-d22a-43ea-b327-1f8cd6125eca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316478237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1316478237
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2851631028
Short name T535
Test name
Test status
Simulation time 2578716982 ps
CPU time 71.34 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:33:31 PM PST 23
Peak memory 248664 kb
Host smart-a4d83b4d-2ec8-4f05-bc15-1967ac7f98b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516
31028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2851631028
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3070481622
Short name T587
Test name
Test status
Simulation time 54742287 ps
CPU time 5.21 seconds
Started Dec 31 01:33:24 PM PST 23
Finished Dec 31 01:33:30 PM PST 23
Peak memory 238740 kb
Host smart-cf28dbda-5b33-4184-bdcc-3b1ade78b564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30704
81622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3070481622
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1251016783
Short name T624
Test name
Test status
Simulation time 875384945 ps
CPU time 26.8 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 01:32:46 PM PST 23
Peak memory 254060 kb
Host smart-222f1155-022d-43b0-b5a5-bcf19bc7e475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12510
16783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1251016783
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2922529056
Short name T408
Test name
Test status
Simulation time 430864670 ps
CPU time 9.2 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 01:33:13 PM PST 23
Peak memory 240480 kb
Host smart-e30fa95e-8c9c-4f58-ba16-7bd8d299cde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29225
29056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2922529056
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3347273577
Short name T98
Test name
Test status
Simulation time 150369997572 ps
CPU time 2345.64 seconds
Started Dec 31 01:33:41 PM PST 23
Finished Dec 31 02:12:48 PM PST 23
Peak memory 289480 kb
Host smart-ae229d32-3ea1-4aeb-8349-46732f24ba05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347273577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3347273577
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4028100379
Short name T313
Test name
Test status
Simulation time 267694777019 ps
CPU time 3827.12 seconds
Started Dec 31 01:32:18 PM PST 23
Finished Dec 31 02:36:08 PM PST 23
Peak memory 306096 kb
Host smart-22d99fae-6fdf-403d-aae2-1f9baf8adcd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028100379 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4028100379
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.963040478
Short name T110
Test name
Test status
Simulation time 14389784232 ps
CPU time 1252.87 seconds
Started Dec 31 01:34:03 PM PST 23
Finished Dec 31 01:55:00 PM PST 23
Peak memory 289552 kb
Host smart-170d2714-baed-43f8-8215-11f065ea80d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963040478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.963040478
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1469278788
Short name T235
Test name
Test status
Simulation time 1785939418 ps
CPU time 128.37 seconds
Started Dec 31 01:33:58 PM PST 23
Finished Dec 31 01:36:09 PM PST 23
Peak memory 250572 kb
Host smart-b3649cdd-4ad8-44dd-8865-fdfbddcaf20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14692
78788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1469278788
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3046687085
Short name T379
Test name
Test status
Simulation time 53351200 ps
CPU time 8.42 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:33:10 PM PST 23
Peak memory 252272 kb
Host smart-facad5d7-f1c6-40fc-a53e-a1128531152c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30466
87085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3046687085
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3887858135
Short name T354
Test name
Test status
Simulation time 24684712192 ps
CPU time 1058.28 seconds
Started Dec 31 01:33:55 PM PST 23
Finished Dec 31 01:51:39 PM PST 23
Peak memory 289308 kb
Host smart-5ec599b7-ab42-44bc-accf-ff509d564d6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887858135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3887858135
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1318675704
Short name T477
Test name
Test status
Simulation time 117423394621 ps
CPU time 1537.23 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 01:59:38 PM PST 23
Peak memory 272260 kb
Host smart-5fe6c417-ce7a-45c2-aab1-fc9f8c0b9f44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318675704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1318675704
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2607590656
Short name T726
Test name
Test status
Simulation time 15205685083 ps
CPU time 486.6 seconds
Started Dec 31 01:33:46 PM PST 23
Finished Dec 31 01:41:54 PM PST 23
Peak memory 247604 kb
Host smart-3f1edcb4-4372-4d40-9983-b31f15b2f3f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607590656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2607590656
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3339212766
Short name T63
Test name
Test status
Simulation time 504816169 ps
CPU time 29.3 seconds
Started Dec 31 01:34:10 PM PST 23
Finished Dec 31 01:34:41 PM PST 23
Peak memory 248524 kb
Host smart-7597e08f-76c9-42fa-a35d-508739ca1ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33392
12766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3339212766
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3769485497
Short name T727
Test name
Test status
Simulation time 722139721 ps
CPU time 46.7 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:34:32 PM PST 23
Peak memory 248272 kb
Host smart-788f86da-fe7b-4859-8220-be2b89b7f9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37694
85497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3769485497
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.55688589
Short name T227
Test name
Test status
Simulation time 2598367416 ps
CPU time 24.6 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:34:09 PM PST 23
Peak memory 254512 kb
Host smart-b4e74836-bad2-4a90-80c7-777fe68b3ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55688
589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.55688589
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1959402142
Short name T643
Test name
Test status
Simulation time 657835909 ps
CPU time 25.05 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 01:34:26 PM PST 23
Peak memory 248612 kb
Host smart-fedf76ba-bc76-4c0a-9ec8-6545eba64fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
02142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1959402142
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1652685055
Short name T730
Test name
Test status
Simulation time 40917941804 ps
CPU time 211.79 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 01:37:37 PM PST 23
Peak memory 256820 kb
Host smart-f53c4407-0b87-4a7c-b6b3-e8b1d5fb0ed5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652685055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1652685055
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2665170990
Short name T336
Test name
Test status
Simulation time 162000361408 ps
CPU time 2682.1 seconds
Started Dec 31 01:33:59 PM PST 23
Finished Dec 31 02:18:47 PM PST 23
Peak memory 297736 kb
Host smart-a92b6188-961b-4fc0-9f1d-50ac74bec151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665170990 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2665170990
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3985748203
Short name T675
Test name
Test status
Simulation time 129308449077 ps
CPU time 1662.92 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 02:01:51 PM PST 23
Peak memory 273256 kb
Host smart-b82360e4-7baa-4ba0-9af6-8f95efa355be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985748203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3985748203
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2564393647
Short name T416
Test name
Test status
Simulation time 423120578 ps
CPU time 15.1 seconds
Started Dec 31 01:34:10 PM PST 23
Finished Dec 31 01:34:27 PM PST 23
Peak memory 252384 kb
Host smart-32135ff2-1fd3-4f94-8950-a4bdb978285e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25643
93647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2564393647
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.662372873
Short name T651
Test name
Test status
Simulation time 97189627 ps
CPU time 6.11 seconds
Started Dec 31 01:34:10 PM PST 23
Finished Dec 31 01:34:18 PM PST 23
Peak memory 238684 kb
Host smart-0f7ed885-ea06-49fa-baef-7f39f4d1405d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66237
2873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.662372873
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1035288304
Short name T427
Test name
Test status
Simulation time 924947490 ps
CPU time 47.85 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:34:56 PM PST 23
Peak memory 248652 kb
Host smart-67ed7b1f-1469-4dc9-947e-b1c0d5e88d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10352
88304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1035288304
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3077577076
Short name T276
Test name
Test status
Simulation time 3704185477 ps
CPU time 52.5 seconds
Started Dec 31 01:34:04 PM PST 23
Finished Dec 31 01:34:59 PM PST 23
Peak memory 256800 kb
Host smart-881823b1-298a-4d91-a60e-2aa577367db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
77076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3077577076
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2781773683
Short name T315
Test name
Test status
Simulation time 458300547 ps
CPU time 14.87 seconds
Started Dec 31 01:34:02 PM PST 23
Finished Dec 31 01:34:22 PM PST 23
Peak memory 248680 kb
Host smart-a0312256-e9b3-4e54-b2cb-a2220f146ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27817
73683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2781773683
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.248570825
Short name T671
Test name
Test status
Simulation time 1089336196 ps
CPU time 27.89 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:34:13 PM PST 23
Peak memory 248604 kb
Host smart-91f68930-6d60-4b6f-bca7-d61fe22d9811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24857
0825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.248570825
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3737291400
Short name T695
Test name
Test status
Simulation time 29643504460 ps
CPU time 555.62 seconds
Started Dec 31 01:34:08 PM PST 23
Finished Dec 31 01:43:26 PM PST 23
Peak memory 265068 kb
Host smart-cac182b5-83f3-41e7-9ccc-de08403230ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737291400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3737291400
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3803275935
Short name T257
Test name
Test status
Simulation time 99001172038 ps
CPU time 1629.34 seconds
Started Dec 31 01:33:34 PM PST 23
Finished Dec 31 02:00:44 PM PST 23
Peak memory 281572 kb
Host smart-d9a0da98-a562-46c1-9631-784c4555ce46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803275935 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3803275935
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2873911241
Short name T405
Test name
Test status
Simulation time 492795675638 ps
CPU time 2619.67 seconds
Started Dec 31 01:34:43 PM PST 23
Finished Dec 31 02:18:24 PM PST 23
Peak memory 289720 kb
Host smart-0fb5131a-713e-4fc0-9055-92ad3e1083e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873911241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2873911241
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3463360809
Short name T552
Test name
Test status
Simulation time 2000416498 ps
CPU time 75.94 seconds
Started Dec 31 01:34:11 PM PST 23
Finished Dec 31 01:35:28 PM PST 23
Peak memory 256816 kb
Host smart-384d3978-8c50-4f7f-880e-a25db2227170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34633
60809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3463360809
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1182624308
Short name T655
Test name
Test status
Simulation time 4099534458 ps
CPU time 28.53 seconds
Started Dec 31 01:34:06 PM PST 23
Finished Dec 31 01:34:37 PM PST 23
Peak memory 256948 kb
Host smart-417f2b63-9e59-4680-8399-d6ed60f9e400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11826
24308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1182624308
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3186483824
Short name T351
Test name
Test status
Simulation time 157072369262 ps
CPU time 2232.63 seconds
Started Dec 31 01:34:35 PM PST 23
Finished Dec 31 02:11:51 PM PST 23
Peak memory 289580 kb
Host smart-862ccc68-81fc-4fd4-ac82-db4e99350e30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186483824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3186483824
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2678424486
Short name T640
Test name
Test status
Simulation time 10219188685 ps
CPU time 1066.78 seconds
Started Dec 31 01:34:32 PM PST 23
Finished Dec 31 01:52:25 PM PST 23
Peak memory 273304 kb
Host smart-f257cd70-0987-4fc4-a07b-9e313174a7e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678424486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2678424486
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2142460760
Short name T123
Test name
Test status
Simulation time 88561706780 ps
CPU time 223.74 seconds
Started Dec 31 01:34:33 PM PST 23
Finished Dec 31 01:38:21 PM PST 23
Peak memory 247144 kb
Host smart-fd324cc4-2b9e-4926-815e-bcab8b50d36f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142460760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2142460760
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3276299623
Short name T34
Test name
Test status
Simulation time 274376759 ps
CPU time 18.08 seconds
Started Dec 31 01:34:07 PM PST 23
Finished Dec 31 01:34:27 PM PST 23
Peak memory 248548 kb
Host smart-4cd09f63-a5df-42df-acab-c53fb9ece666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
99623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3276299623
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3169716392
Short name T590
Test name
Test status
Simulation time 132713393 ps
CPU time 5.6 seconds
Started Dec 31 01:34:37 PM PST 23
Finished Dec 31 01:34:48 PM PST 23
Peak memory 252456 kb
Host smart-e7508505-68ee-414a-9c0b-830ef1a7cb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31697
16392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3169716392
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1308943689
Short name T417
Test name
Test status
Simulation time 3095098453 ps
CPU time 50.26 seconds
Started Dec 31 01:34:32 PM PST 23
Finished Dec 31 01:35:28 PM PST 23
Peak memory 255912 kb
Host smart-c5b7972e-e37d-4f16-978b-fea542395788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13089
43689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1308943689
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3144144603
Short name T575
Test name
Test status
Simulation time 1013232350 ps
CPU time 26.81 seconds
Started Dec 31 01:34:16 PM PST 23
Finished Dec 31 01:34:44 PM PST 23
Peak memory 248504 kb
Host smart-c7ad54b2-0af1-4a04-aab0-bc07cecb1788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31441
44603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3144144603
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.289123763
Short name T463
Test name
Test status
Simulation time 6990217398 ps
CPU time 255.81 seconds
Started Dec 31 01:33:40 PM PST 23
Finished Dec 31 01:37:57 PM PST 23
Peak memory 256880 kb
Host smart-72f95c8b-71a6-448d-accc-caa09c22fa5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289123763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.289123763
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1793390729
Short name T662
Test name
Test status
Simulation time 66571782755 ps
CPU time 2019.46 seconds
Started Dec 31 01:34:53 PM PST 23
Finished Dec 31 02:08:36 PM PST 23
Peak memory 271604 kb
Host smart-1611b857-87d4-4abc-8dad-53bac4ad5b23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793390729 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1793390729
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3416868121
Short name T605
Test name
Test status
Simulation time 132334143710 ps
CPU time 1855.88 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 02:04:25 PM PST 23
Peak memory 273072 kb
Host smart-1ad089bb-79e9-4708-b168-6b44163aef48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416868121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3416868121
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3618813510
Short name T589
Test name
Test status
Simulation time 1631690607 ps
CPU time 115.93 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:35:24 PM PST 23
Peak memory 256084 kb
Host smart-b08d5360-0b63-4b51-b09e-4719f0f5e75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36188
13510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3618813510
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1747057171
Short name T398
Test name
Test status
Simulation time 1246511608 ps
CPU time 19.06 seconds
Started Dec 31 01:34:33 PM PST 23
Finished Dec 31 01:34:57 PM PST 23
Peak memory 248064 kb
Host smart-2ebf1725-0062-44cc-97fc-b9de6f864bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17470
57171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1747057171
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.992420620
Short name T553
Test name
Test status
Simulation time 102300291383 ps
CPU time 1465.75 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 01:57:23 PM PST 23
Peak memory 265908 kb
Host smart-0bebd845-44c6-4371-b77c-afb89b3dcc01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992420620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.992420620
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3672393251
Short name T646
Test name
Test status
Simulation time 17242502395 ps
CPU time 1140.83 seconds
Started Dec 31 01:32:54 PM PST 23
Finished Dec 31 01:51:55 PM PST 23
Peak memory 265128 kb
Host smart-a0b217ed-74f2-40e0-ac87-5d4be9f9bf77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672393251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3672393251
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3901311422
Short name T670
Test name
Test status
Simulation time 10253360824 ps
CPU time 152.98 seconds
Started Dec 31 01:32:48 PM PST 23
Finished Dec 31 01:35:21 PM PST 23
Peak memory 248664 kb
Host smart-b1a2f648-d4d5-4c12-aed9-1f8b0134c4fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901311422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3901311422
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1989407660
Short name T47
Test name
Test status
Simulation time 1687945788 ps
CPU time 26.19 seconds
Started Dec 31 01:35:02 PM PST 23
Finished Dec 31 01:35:30 PM PST 23
Peak memory 248692 kb
Host smart-32c941fc-503d-486d-85a8-130a71f70a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19894
07660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1989407660
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3490142267
Short name T672
Test name
Test status
Simulation time 77821973 ps
CPU time 6.73 seconds
Started Dec 31 01:34:33 PM PST 23
Finished Dec 31 01:34:44 PM PST 23
Peak memory 248688 kb
Host smart-fd1f6db0-1d1d-4078-b19c-ae5c4c3bfad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901
42267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3490142267
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.190178275
Short name T710
Test name
Test status
Simulation time 335905995 ps
CPU time 13.87 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:33:41 PM PST 23
Peak memory 246760 kb
Host smart-7277b330-83b3-44b3-9cad-835c2d1edf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
8275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.190178275
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.72544257
Short name T450
Test name
Test status
Simulation time 326959602 ps
CPU time 29.3 seconds
Started Dec 31 01:34:31 PM PST 23
Finished Dec 31 01:35:06 PM PST 23
Peak memory 248688 kb
Host smart-c1872ca0-9b09-4327-a387-368ae8238613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72544
257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.72544257
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3634158017
Short name T654
Test name
Test status
Simulation time 53054191402 ps
CPU time 1210.33 seconds
Started Dec 31 01:33:05 PM PST 23
Finished Dec 31 01:53:16 PM PST 23
Peak memory 289368 kb
Host smart-aa1299b0-4104-425e-921c-380fcde71d22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634158017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3634158017
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.35847629
Short name T35
Test name
Test status
Simulation time 140345319922 ps
CPU time 2120.99 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 02:08:52 PM PST 23
Peak memory 289832 kb
Host smart-2e0e612f-7936-4bac-9aee-f712cd64df88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35847629 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.35847629
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.601583196
Short name T703
Test name
Test status
Simulation time 70788642558 ps
CPU time 1984.55 seconds
Started Dec 31 01:33:46 PM PST 23
Finished Dec 31 02:06:52 PM PST 23
Peak memory 272660 kb
Host smart-0b23bc23-9247-4235-930f-201c23ff80e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601583196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.601583196
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.109549031
Short name T32
Test name
Test status
Simulation time 4197640610 ps
CPU time 65.28 seconds
Started Dec 31 01:34:13 PM PST 23
Finished Dec 31 01:35:19 PM PST 23
Peak memory 256344 kb
Host smart-821da4f2-b9d0-451c-8331-0cd883bce6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10954
9031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.109549031
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3702764883
Short name T46
Test name
Test status
Simulation time 223312334 ps
CPU time 14.93 seconds
Started Dec 31 01:33:56 PM PST 23
Finished Dec 31 01:34:15 PM PST 23
Peak memory 248244 kb
Host smart-f4d5d4b5-c485-4e09-a2fb-d9e9e8cc48d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37027
64883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3702764883
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3459171135
Short name T84
Test name
Test status
Simulation time 136391567977 ps
CPU time 1982.02 seconds
Started Dec 31 01:33:35 PM PST 23
Finished Dec 31 02:06:38 PM PST 23
Peak memory 273344 kb
Host smart-5be34f3e-2a78-4eb8-b9d6-83d8890bbe4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459171135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3459171135
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3289231185
Short name T510
Test name
Test status
Simulation time 21083092348 ps
CPU time 1072.93 seconds
Started Dec 31 01:33:32 PM PST 23
Finished Dec 31 01:51:25 PM PST 23
Peak memory 285168 kb
Host smart-760b5f64-8d96-4c8b-a578-319eef3e1edf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289231185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3289231185
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3547932192
Short name T310
Test name
Test status
Simulation time 23317739502 ps
CPU time 251.72 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:37:51 PM PST 23
Peak memory 246540 kb
Host smart-cf822df4-4530-4c85-9228-b9b787647bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547932192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3547932192
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.982094995
Short name T464
Test name
Test status
Simulation time 1240681556 ps
CPU time 21.69 seconds
Started Dec 31 01:32:58 PM PST 23
Finished Dec 31 01:33:21 PM PST 23
Peak memory 248556 kb
Host smart-30445a1c-f9ab-4704-a401-9cfdcd4f7b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98209
4995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.982094995
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3750469419
Short name T500
Test name
Test status
Simulation time 1511381313 ps
CPU time 29.18 seconds
Started Dec 31 01:32:58 PM PST 23
Finished Dec 31 01:33:28 PM PST 23
Peak memory 254684 kb
Host smart-ffdb4e75-1f48-4c62-a29b-37b0c78257e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504
69419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3750469419
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3446183367
Short name T596
Test name
Test status
Simulation time 677354944 ps
CPU time 27.33 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 01:33:32 PM PST 23
Peak memory 256012 kb
Host smart-b8101c38-c561-4932-8c0c-1d1516b2b7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34461
83367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3446183367
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3718292128
Short name T637
Test name
Test status
Simulation time 59298087 ps
CPU time 2.42 seconds
Started Dec 31 01:33:31 PM PST 23
Finished Dec 31 01:33:34 PM PST 23
Peak memory 240376 kb
Host smart-3f2b71d2-7cac-43fc-9eef-09d94392e66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37182
92128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3718292128
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.360722950
Short name T68
Test name
Test status
Simulation time 434354606843 ps
CPU time 4141.64 seconds
Started Dec 31 01:33:25 PM PST 23
Finished Dec 31 02:42:33 PM PST 23
Peak memory 305532 kb
Host smart-d7386336-2261-40c1-9b89-9671e8564725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360722950 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.360722950
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3005806475
Short name T108
Test name
Test status
Simulation time 17929404931 ps
CPU time 1340.76 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:55:23 PM PST 23
Peak memory 289360 kb
Host smart-b402ee1c-89eb-40b5-9f73-01fc70a9740d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005806475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3005806475
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.957246137
Short name T660
Test name
Test status
Simulation time 1068971964 ps
CPU time 83.87 seconds
Started Dec 31 01:33:36 PM PST 23
Finished Dec 31 01:35:00 PM PST 23
Peak memory 249524 kb
Host smart-772cf096-b3a9-47dc-ad2a-5794ff3d3611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95724
6137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.957246137
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.184066780
Short name T603
Test name
Test status
Simulation time 724022786 ps
CPU time 8.99 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:34:15 PM PST 23
Peak memory 252348 kb
Host smart-bd997538-5a31-40eb-b25d-a9a98d30eb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18406
6780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.184066780
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.173708657
Short name T350
Test name
Test status
Simulation time 24669722659 ps
CPU time 1111.07 seconds
Started Dec 31 01:33:54 PM PST 23
Finished Dec 31 01:52:32 PM PST 23
Peak memory 273224 kb
Host smart-cd4b9c51-b9bd-4e47-ac43-dcec476547e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173708657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.173708657
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2598423905
Short name T663
Test name
Test status
Simulation time 28279303245 ps
CPU time 1486.4 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 01:57:51 PM PST 23
Peak memory 271304 kb
Host smart-29a1cce8-8284-4c02-8d0a-b023420ada44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598423905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2598423905
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3918428575
Short name T290
Test name
Test status
Simulation time 29054690662 ps
CPU time 582.58 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 01:43:24 PM PST 23
Peak memory 247496 kb
Host smart-233e7407-ea38-4dbf-b1b3-836d9e615920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918428575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3918428575
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3103933714
Short name T490
Test name
Test status
Simulation time 1181161622 ps
CPU time 28.29 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:33:32 PM PST 23
Peak memory 248620 kb
Host smart-03bc8759-b3da-4e0c-a380-513403b66888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31039
33714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3103933714
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1653453018
Short name T725
Test name
Test status
Simulation time 569701002 ps
CPU time 19.12 seconds
Started Dec 31 01:33:32 PM PST 23
Finished Dec 31 01:33:52 PM PST 23
Peak memory 254408 kb
Host smart-4e4a00c8-fe84-4441-a47e-20b3bc7d67b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534
53018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1653453018
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2501956403
Short name T328
Test name
Test status
Simulation time 258349008 ps
CPU time 28.38 seconds
Started Dec 31 01:33:42 PM PST 23
Finished Dec 31 01:34:11 PM PST 23
Peak memory 255012 kb
Host smart-2f6a8846-f93e-4d1e-bb7e-be0a677a7719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25019
56403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2501956403
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2456669857
Short name T551
Test name
Test status
Simulation time 311824540 ps
CPU time 16.14 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 01:33:47 PM PST 23
Peak memory 248648 kb
Host smart-77cecf00-500a-4b40-8cfa-1a8e092ba3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24566
69857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2456669857
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3880670400
Short name T633
Test name
Test status
Simulation time 10263599129 ps
CPU time 154.72 seconds
Started Dec 31 01:33:38 PM PST 23
Finished Dec 31 01:36:14 PM PST 23
Peak memory 256936 kb
Host smart-36510235-57ca-496a-930d-f26585863298
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880670400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3880670400
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.970223145
Short name T33
Test name
Test status
Simulation time 5655006809 ps
CPU time 99.36 seconds
Started Dec 31 01:32:53 PM PST 23
Finished Dec 31 01:34:33 PM PST 23
Peak memory 256796 kb
Host smart-580f86a8-4e6b-4d7c-b28a-aec21d1e2617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97022
3145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.970223145
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.853009507
Short name T426
Test name
Test status
Simulation time 2210230270 ps
CPU time 28.86 seconds
Started Dec 31 01:33:24 PM PST 23
Finished Dec 31 01:33:53 PM PST 23
Peak memory 254228 kb
Host smart-b56c6305-b228-4510-8a47-f574bc75cdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85300
9507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.853009507
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3143580196
Short name T533
Test name
Test status
Simulation time 17448131265 ps
CPU time 750.34 seconds
Started Dec 31 01:33:24 PM PST 23
Finished Dec 31 01:45:55 PM PST 23
Peak memory 265060 kb
Host smart-f71c9801-c72b-4b84-88ab-5d13a523ec8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143580196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3143580196
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3101568643
Short name T641
Test name
Test status
Simulation time 396608300272 ps
CPU time 1717.19 seconds
Started Dec 31 01:32:57 PM PST 23
Finished Dec 31 02:01:35 PM PST 23
Peak memory 272352 kb
Host smart-4d840be7-2c0d-4719-8c58-e9d7a543ba3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101568643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3101568643
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1385354722
Short name T656
Test name
Test status
Simulation time 51520473739 ps
CPU time 142.04 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:35:51 PM PST 23
Peak memory 255652 kb
Host smart-f7af1e3a-d5c8-48eb-b691-cedb37d4d198
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385354722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1385354722
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2435821839
Short name T630
Test name
Test status
Simulation time 54908840 ps
CPU time 4.97 seconds
Started Dec 31 01:34:15 PM PST 23
Finished Dec 31 01:34:21 PM PST 23
Peak memory 240400 kb
Host smart-8ab2e4cf-b68a-462b-bac6-a31033ba1cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24358
21839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2435821839
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2251009405
Short name T705
Test name
Test status
Simulation time 223093861 ps
CPU time 14.72 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 01:33:46 PM PST 23
Peak memory 253016 kb
Host smart-49498d1a-ead8-4d93-b66f-3bc49485715a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22510
09405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2251009405
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1853660194
Short name T339
Test name
Test status
Simulation time 2134650419 ps
CPU time 38.32 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:34:22 PM PST 23
Peak memory 247076 kb
Host smart-58272ca6-2296-4201-81d8-e362ee31be48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18536
60194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1853660194
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.54881671
Short name T658
Test name
Test status
Simulation time 119874577 ps
CPU time 13.7 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 01:33:43 PM PST 23
Peak memory 248756 kb
Host smart-d4c2e602-fceb-4e14-be3e-b39aff173497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54881
671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.54881671
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1910583804
Short name T219
Test name
Test status
Simulation time 65476972267 ps
CPU time 1237.94 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 01:54:09 PM PST 23
Peak memory 284744 kb
Host smart-4833ef28-131d-4852-b945-030286099d21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910583804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1910583804
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3876801288
Short name T712
Test name
Test status
Simulation time 23299232925 ps
CPU time 1422.31 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 01:56:48 PM PST 23
Peak memory 283060 kb
Host smart-4a3c63e6-6df6-4dcd-a1e6-092e2edad87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876801288 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3876801288
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1937280756
Short name T491
Test name
Test status
Simulation time 21864184485 ps
CPU time 1183.3 seconds
Started Dec 31 01:33:01 PM PST 23
Finished Dec 31 01:52:45 PM PST 23
Peak memory 286324 kb
Host smart-d6e821cc-c59f-40cb-a461-a4712c0746c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937280756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1937280756
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.902580171
Short name T383
Test name
Test status
Simulation time 3118451387 ps
CPU time 121.91 seconds
Started Dec 31 01:33:26 PM PST 23
Finished Dec 31 01:35:29 PM PST 23
Peak memory 249952 kb
Host smart-729db7a5-8e5d-4b17-ab74-910a7b8b7f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90258
0171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.902580171
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.541935697
Short name T629
Test name
Test status
Simulation time 2461281306 ps
CPU time 23.96 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 01:33:55 PM PST 23
Peak memory 255224 kb
Host smart-be3db5e6-f8e0-4642-ab6c-03e1121f5897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54193
5697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.541935697
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2408057104
Short name T349
Test name
Test status
Simulation time 62395101066 ps
CPU time 2760.4 seconds
Started Dec 31 01:32:55 PM PST 23
Finished Dec 31 02:18:57 PM PST 23
Peak memory 289236 kb
Host smart-0ea048e0-822c-447f-bf99-ee44c7440634
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408057104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2408057104
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3710045024
Short name T485
Test name
Test status
Simulation time 10897798376 ps
CPU time 1148.14 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 01:52:13 PM PST 23
Peak memory 289784 kb
Host smart-d26b64a9-a785-4e14-92e4-6a431bbb21b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710045024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3710045024
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1789213544
Short name T287
Test name
Test status
Simulation time 12856474148 ps
CPU time 279.11 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 01:37:32 PM PST 23
Peak memory 247512 kb
Host smart-a4d9d7fc-b0c7-4bd6-b4ed-c46ea21b1254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789213544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1789213544
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1807327173
Short name T572
Test name
Test status
Simulation time 1289678613 ps
CPU time 24.59 seconds
Started Dec 31 01:33:28 PM PST 23
Finished Dec 31 01:33:54 PM PST 23
Peak memory 248616 kb
Host smart-4d5e423d-c959-48be-9724-5f7a58aded34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18073
27173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1807327173
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1059997689
Short name T385
Test name
Test status
Simulation time 308098118 ps
CPU time 14.59 seconds
Started Dec 31 01:33:32 PM PST 23
Finished Dec 31 01:33:47 PM PST 23
Peak memory 253864 kb
Host smart-dcb666f1-690d-4fee-ab76-a46aea5116e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10599
97689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1059997689
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3328452171
Short name T576
Test name
Test status
Simulation time 638840368 ps
CPU time 8.5 seconds
Started Dec 31 01:33:32 PM PST 23
Finished Dec 31 01:33:41 PM PST 23
Peak memory 252076 kb
Host smart-2973072d-8835-4ee1-91ff-acf0f8f3f961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33284
52171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3328452171
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4210862520
Short name T220
Test name
Test status
Simulation time 409132041 ps
CPU time 35.27 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:33:39 PM PST 23
Peak memory 248660 kb
Host smart-8d53298e-fb91-422e-baad-9566e309e7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42108
62520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4210862520
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2827128585
Short name T6
Test name
Test status
Simulation time 179856463287 ps
CPU time 2628.98 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 02:17:20 PM PST 23
Peak memory 289216 kb
Host smart-a1c6eec0-1296-4703-8a59-44ee36025ef6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827128585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2827128585
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1003517287
Short name T221
Test name
Test status
Simulation time 46622500350 ps
CPU time 1155.69 seconds
Started Dec 31 01:33:48 PM PST 23
Finished Dec 31 01:53:04 PM PST 23
Peak memory 287224 kb
Host smart-e2083fa3-1e85-447d-9159-1ae988446eac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003517287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1003517287
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1256711620
Short name T563
Test name
Test status
Simulation time 6929140474 ps
CPU time 146.07 seconds
Started Dec 31 01:33:35 PM PST 23
Finished Dec 31 01:36:01 PM PST 23
Peak memory 256852 kb
Host smart-0fb4f2cd-a421-41b8-b259-effbbf50e9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12567
11620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1256711620
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1668086324
Short name T86
Test name
Test status
Simulation time 281091180 ps
CPU time 22.32 seconds
Started Dec 31 01:33:30 PM PST 23
Finished Dec 31 01:33:53 PM PST 23
Peak memory 248400 kb
Host smart-934b8ceb-988b-449e-8acc-ada55af965bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16680
86324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1668086324
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1541301346
Short name T645
Test name
Test status
Simulation time 81182859516 ps
CPU time 2291.44 seconds
Started Dec 31 01:33:39 PM PST 23
Finished Dec 31 02:11:51 PM PST 23
Peak memory 289252 kb
Host smart-665bbc90-faf5-40c0-8efe-4ad4b4e78bea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541301346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1541301346
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3918357330
Short name T89
Test name
Test status
Simulation time 66757826148 ps
CPU time 1847.41 seconds
Started Dec 31 01:34:09 PM PST 23
Finished Dec 31 02:04:58 PM PST 23
Peak memory 289008 kb
Host smart-278820c3-2ef4-4d6e-9960-523f856438bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918357330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3918357330
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2869292936
Short name T294
Test name
Test status
Simulation time 48423480250 ps
CPU time 535.06 seconds
Started Dec 31 01:33:48 PM PST 23
Finished Dec 31 01:42:43 PM PST 23
Peak memory 247272 kb
Host smart-f2e2ba40-e693-4008-83a3-b95827a8cd3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869292936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2869292936
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2744250834
Short name T445
Test name
Test status
Simulation time 673553245 ps
CPU time 27.26 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 01:33:20 PM PST 23
Peak memory 248604 kb
Host smart-6571ce32-67b3-4595-837d-0ab5bf503b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442
50834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2744250834
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.4245254373
Short name T720
Test name
Test status
Simulation time 120799387 ps
CPU time 8.27 seconds
Started Dec 31 01:33:23 PM PST 23
Finished Dec 31 01:33:32 PM PST 23
Peak memory 251416 kb
Host smart-5b26c673-80b0-4a0d-ac8c-f27fdb4331df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42452
54373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.4245254373
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4018288744
Short name T564
Test name
Test status
Simulation time 2807263854 ps
CPU time 31.65 seconds
Started Dec 31 01:32:50 PM PST 23
Finished Dec 31 01:33:23 PM PST 23
Peak memory 248592 kb
Host smart-c02175d2-d988-40ef-a767-52c959bd5b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40182
88744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4018288744
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1840800624
Short name T406
Test name
Test status
Simulation time 206424094 ps
CPU time 13.11 seconds
Started Dec 31 01:33:26 PM PST 23
Finished Dec 31 01:33:40 PM PST 23
Peak memory 248596 kb
Host smart-646d5ec6-7409-4548-b9d0-9752053bd38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18408
00624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1840800624
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2996015448
Short name T511
Test name
Test status
Simulation time 1671243141 ps
CPU time 139.01 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:36:04 PM PST 23
Peak memory 256468 kb
Host smart-f455317c-7eb5-4db7-aa80-bf99bb5eb3ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996015448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2996015448
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1521518338
Short name T269
Test name
Test status
Simulation time 10922280908 ps
CPU time 677.68 seconds
Started Dec 31 01:33:27 PM PST 23
Finished Dec 31 01:44:46 PM PST 23
Peak memory 272480 kb
Host smart-a8377b6d-bab2-4a4d-a351-c4da890a713c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521518338 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1521518338
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2378468730
Short name T209
Test name
Test status
Simulation time 42175798 ps
CPU time 3.49 seconds
Started Dec 31 01:32:24 PM PST 23
Finished Dec 31 01:32:30 PM PST 23
Peak memory 248644 kb
Host smart-0951069c-4be0-4e80-a895-9fb5c55d958c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2378468730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2378468730
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3770743400
Short name T39
Test name
Test status
Simulation time 396271748064 ps
CPU time 2383.41 seconds
Started Dec 31 01:32:02 PM PST 23
Finished Dec 31 02:11:47 PM PST 23
Peak memory 287640 kb
Host smart-52f788b7-828e-46b0-b072-963dca15c77a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770743400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3770743400
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3573527873
Short name T476
Test name
Test status
Simulation time 821423969 ps
CPU time 36.8 seconds
Started Dec 31 01:32:51 PM PST 23
Finished Dec 31 01:33:28 PM PST 23
Peak memory 240484 kb
Host smart-53dcb665-951d-4a05-af5f-3b94964edc01
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3573527873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3573527873
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2837478849
Short name T697
Test name
Test status
Simulation time 1566992285 ps
CPU time 95.72 seconds
Started Dec 31 01:31:58 PM PST 23
Finished Dec 31 01:33:37 PM PST 23
Peak memory 256080 kb
Host smart-51a58a74-00c1-4cd3-9057-4199dca6f177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
78849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2837478849
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3062882971
Short name T473
Test name
Test status
Simulation time 425205043 ps
CPU time 27.44 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:31:57 PM PST 23
Peak memory 248176 kb
Host smart-5dfacd34-84e4-48bf-94c3-93ad33a9a7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30628
82971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3062882971
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1529279351
Short name T693
Test name
Test status
Simulation time 108630260805 ps
CPU time 2785.6 seconds
Started Dec 31 01:32:17 PM PST 23
Finished Dec 31 02:18:45 PM PST 23
Peak memory 287084 kb
Host smart-3bc63f61-1b4c-48d5-9f6a-9b2f2239339a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529279351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1529279351
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2269683413
Short name T258
Test name
Test status
Simulation time 58277701095 ps
CPU time 1736.73 seconds
Started Dec 31 01:31:29 PM PST 23
Finished Dec 31 02:00:27 PM PST 23
Peak memory 288940 kb
Host smart-c9b734be-98f9-457f-86f1-a3380ca476d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269683413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2269683413
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.706325224
Short name T296
Test name
Test status
Simulation time 15467416494 ps
CPU time 184.19 seconds
Started Dec 31 01:32:03 PM PST 23
Finished Dec 31 01:35:09 PM PST 23
Peak memory 246556 kb
Host smart-5a00a163-71fc-4f8f-851e-0edb474c211b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706325224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.706325224
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1943380614
Short name T554
Test name
Test status
Simulation time 3237891468 ps
CPU time 32.04 seconds
Started Dec 31 01:32:02 PM PST 23
Finished Dec 31 01:32:35 PM PST 23
Peak memory 248604 kb
Host smart-5e9ca5f7-45f9-41ec-b41f-6960e53baad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19433
80614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1943380614
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.126542120
Short name T377
Test name
Test status
Simulation time 1296963376 ps
CPU time 72.72 seconds
Started Dec 31 01:32:00 PM PST 23
Finished Dec 31 01:33:15 PM PST 23
Peak memory 254732 kb
Host smart-3b595a04-07c8-4691-b4c1-0732faa380e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654
2120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.126542120
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.332467019
Short name T458
Test name
Test status
Simulation time 64655138 ps
CPU time 5.2 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 01:32:11 PM PST 23
Peak memory 240240 kb
Host smart-d0bf8986-9dee-491f-ae16-93e1529ebdb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33246
7019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.332467019
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3021437723
Short name T647
Test name
Test status
Simulation time 1460423196 ps
CPU time 17.54 seconds
Started Dec 31 01:32:03 PM PST 23
Finished Dec 31 01:32:22 PM PST 23
Peak memory 248820 kb
Host smart-c0bcd2c6-ad52-46ec-9b45-438fbaa7035d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214
37723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3021437723
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3617836968
Short name T321
Test name
Test status
Simulation time 58902958748 ps
CPU time 1278.23 seconds
Started Dec 31 01:33:05 PM PST 23
Finished Dec 31 01:54:24 PM PST 23
Peak memory 288692 kb
Host smart-2f12afc7-055e-41f4-aa58-67dce3cbe85d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617836968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3617836968
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4123281634
Short name T247
Test name
Test status
Simulation time 225681437380 ps
CPU time 1479.88 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:57:06 PM PST 23
Peak memory 281192 kb
Host smart-b9bf914a-aeb8-46d9-b03d-bc73a3da70ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123281634 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4123281634
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2545860782
Short name T206
Test name
Test status
Simulation time 56747276 ps
CPU time 3 seconds
Started Dec 31 01:32:50 PM PST 23
Finished Dec 31 01:32:54 PM PST 23
Peak memory 248748 kb
Host smart-8c62b19d-0ee0-4807-86c6-425a17fc9fd3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2545860782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2545860782
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2961682005
Short name T496
Test name
Test status
Simulation time 9435908947 ps
CPU time 713.54 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 01:44:12 PM PST 23
Peak memory 272860 kb
Host smart-20b7c88e-8873-4915-80ab-5759264fb92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961682005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2961682005
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2536417412
Short name T601
Test name
Test status
Simulation time 240833428 ps
CPU time 12.17 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:33:16 PM PST 23
Peak memory 240424 kb
Host smart-bb23ada7-f80d-4d8d-a482-3dd18169cfc4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2536417412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2536417412
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4219286093
Short name T372
Test name
Test status
Simulation time 5445863925 ps
CPU time 211.23 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 01:35:36 PM PST 23
Peak memory 256360 kb
Host smart-6ac632ba-be00-4386-8b6e-89fcd7784f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42192
86093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4219286093
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2980757551
Short name T262
Test name
Test status
Simulation time 6772622632 ps
CPU time 61.24 seconds
Started Dec 31 01:33:25 PM PST 23
Finished Dec 31 01:34:27 PM PST 23
Peak memory 256196 kb
Host smart-61395680-ea6c-4482-801a-52eb0733cced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807
57551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2980757551
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.881841121
Short name T303
Test name
Test status
Simulation time 30346583878 ps
CPU time 1679.57 seconds
Started Dec 31 01:31:59 PM PST 23
Finished Dec 31 02:00:02 PM PST 23
Peak memory 282528 kb
Host smart-8f182203-a8f4-4360-ac21-bd0f4fa22043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881841121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.881841121
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2428686357
Short name T261
Test name
Test status
Simulation time 14298930633 ps
CPU time 1236 seconds
Started Dec 31 01:32:54 PM PST 23
Finished Dec 31 01:53:31 PM PST 23
Peak memory 281492 kb
Host smart-3018dc0f-08da-4bea-a737-830ff644d348
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428686357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2428686357
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.277732305
Short name T295
Test name
Test status
Simulation time 33153329538 ps
CPU time 302.09 seconds
Started Dec 31 01:32:16 PM PST 23
Finished Dec 31 01:37:20 PM PST 23
Peak memory 247556 kb
Host smart-c82ea114-6d97-4be5-a54c-bd35b6127ee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277732305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.277732305
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1337832826
Short name T397
Test name
Test status
Simulation time 2545605607 ps
CPU time 35.37 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:33:02 PM PST 23
Peak memory 255116 kb
Host smart-9f3cacfa-d73b-4e83-ae93-eee7d1c8deda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13378
32826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1337832826
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3916618115
Short name T557
Test name
Test status
Simulation time 1667458359 ps
CPU time 32.6 seconds
Started Dec 31 01:32:52 PM PST 23
Finished Dec 31 01:33:26 PM PST 23
Peak memory 254752 kb
Host smart-5a401140-c7b4-44e5-96cf-19e9b30e40ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
18115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3916618115
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4201534375
Short name T391
Test name
Test status
Simulation time 357476025 ps
CPU time 23.96 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:31:54 PM PST 23
Peak memory 247756 kb
Host smart-54c32e41-78aa-4efc-abf2-abfd411864b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
34375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4201534375
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1081153788
Short name T233
Test name
Test status
Simulation time 1482303391 ps
CPU time 21.82 seconds
Started Dec 31 01:32:20 PM PST 23
Finished Dec 31 01:32:48 PM PST 23
Peak memory 248676 kb
Host smart-c105b8d5-a62a-4dfc-91dd-472c66814178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
53788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1081153788
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.958357730
Short name T199
Test name
Test status
Simulation time 68045749 ps
CPU time 3.36 seconds
Started Dec 31 01:31:57 PM PST 23
Finished Dec 31 01:32:04 PM PST 23
Peak memory 248852 kb
Host smart-dff5faa5-4d40-442c-90ef-6b8607f7c5c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=958357730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.958357730
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.723463044
Short name T524
Test name
Test status
Simulation time 226187293275 ps
CPU time 2562 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 02:14:11 PM PST 23
Peak memory 289376 kb
Host smart-49885c6e-5247-45f7-9b58-32db5eb05a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723463044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.723463044
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.300173793
Short name T626
Test name
Test status
Simulation time 8076875283 ps
CPU time 255.11 seconds
Started Dec 31 01:32:18 PM PST 23
Finished Dec 31 01:36:35 PM PST 23
Peak memory 256168 kb
Host smart-27cc13be-d661-46a9-a5f5-f9d754957a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30017
3793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.300173793
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1619305663
Short name T475
Test name
Test status
Simulation time 727563422 ps
CPU time 44.76 seconds
Started Dec 31 01:33:43 PM PST 23
Finished Dec 31 01:34:28 PM PST 23
Peak memory 253932 kb
Host smart-da714141-2d69-4293-8bd7-74d32999ca7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16193
05663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1619305663
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1122470232
Short name T80
Test name
Test status
Simulation time 16955867985 ps
CPU time 1331.46 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:53:41 PM PST 23
Peak memory 280828 kb
Host smart-90eb42c9-ff07-4999-9ec3-411ad2b6c043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122470232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1122470232
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1086727209
Short name T116
Test name
Test status
Simulation time 8932200770 ps
CPU time 942.08 seconds
Started Dec 31 01:31:30 PM PST 23
Finished Dec 31 01:47:13 PM PST 23
Peak memory 272296 kb
Host smart-af3f6a02-cc6b-47c7-ae8b-0c7768ae3bf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086727209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1086727209
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.794007032
Short name T681
Test name
Test status
Simulation time 9607402527 ps
CPU time 375.07 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 01:38:30 PM PST 23
Peak memory 246668 kb
Host smart-a33cb93c-6d04-446b-9457-cfbf3e748fd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794007032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.794007032
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.4145141095
Short name T562
Test name
Test status
Simulation time 2588983935 ps
CPU time 38.28 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:34:24 PM PST 23
Peak memory 248688 kb
Host smart-ddef3b94-dabc-4f37-966d-f235eab97e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41451
41095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4145141095
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1311160091
Short name T254
Test name
Test status
Simulation time 3970849553 ps
CPU time 32.39 seconds
Started Dec 31 01:33:49 PM PST 23
Finished Dec 31 01:34:22 PM PST 23
Peak memory 255152 kb
Host smart-ad9210d3-19e2-4e99-943a-6e12fb438c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111
60091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1311160091
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2248178947
Short name T679
Test name
Test status
Simulation time 317725517 ps
CPU time 12.04 seconds
Started Dec 31 01:31:37 PM PST 23
Finished Dec 31 01:31:50 PM PST 23
Peak memory 248696 kb
Host smart-fb231f81-e865-4dda-b54d-ad9554e41891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22481
78947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2248178947
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3621346788
Short name T521
Test name
Test status
Simulation time 1023355975 ps
CPU time 22.3 seconds
Started Dec 31 01:34:12 PM PST 23
Finished Dec 31 01:34:36 PM PST 23
Peak memory 255520 kb
Host smart-e3336611-b474-427d-b278-aae9b4034e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36213
46788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3621346788
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1362395701
Short name T238
Test name
Test status
Simulation time 38871233395 ps
CPU time 2359.48 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 02:11:35 PM PST 23
Peak memory 289400 kb
Host smart-a64d4452-6249-431a-808f-23dee14ddde0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362395701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1362395701
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1275189962
Short name T228
Test name
Test status
Simulation time 139328628169 ps
CPU time 3529.12 seconds
Started Dec 31 01:32:14 PM PST 23
Finished Dec 31 02:31:05 PM PST 23
Peak memory 331548 kb
Host smart-49e51581-6caa-4b47-ad5f-fe6b2203bdc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275189962 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1275189962
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.4106505968
Short name T214
Test name
Test status
Simulation time 47355971 ps
CPU time 3.5 seconds
Started Dec 31 01:34:13 PM PST 23
Finished Dec 31 01:34:17 PM PST 23
Peak memory 248856 kb
Host smart-b078e070-2136-4de0-8283-af406fce1695
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4106505968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.4106505968
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.683791178
Short name T644
Test name
Test status
Simulation time 914655074428 ps
CPU time 2466.01 seconds
Started Dec 31 01:33:38 PM PST 23
Finished Dec 31 02:14:51 PM PST 23
Peak memory 286972 kb
Host smart-8ac835fd-b60f-4dcf-83ba-9c364e7c73e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683791178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.683791178
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.936755077
Short name T492
Test name
Test status
Simulation time 80144358 ps
CPU time 5.87 seconds
Started Dec 31 01:33:58 PM PST 23
Finished Dec 31 01:34:07 PM PST 23
Peak memory 240452 kb
Host smart-c2b4e341-757b-48f5-a120-f94d6713f129
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=936755077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.936755077
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.510429570
Short name T384
Test name
Test status
Simulation time 2100739902 ps
CPU time 99.86 seconds
Started Dec 31 01:33:22 PM PST 23
Finished Dec 31 01:35:03 PM PST 23
Peak memory 256064 kb
Host smart-cbfada4d-e164-4a0d-83c8-8e155a4b86af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51042
9570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.510429570
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2437873132
Short name T390
Test name
Test status
Simulation time 256956490 ps
CPU time 21.41 seconds
Started Dec 31 01:32:06 PM PST 23
Finished Dec 31 01:32:28 PM PST 23
Peak memory 255056 kb
Host smart-341bce0c-2538-413d-9e92-15b5831cf31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24378
73132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2437873132
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2130580857
Short name T356
Test name
Test status
Simulation time 97174622970 ps
CPU time 2373.88 seconds
Started Dec 31 01:33:37 PM PST 23
Finished Dec 31 02:13:12 PM PST 23
Peak memory 289604 kb
Host smart-3e276c36-daac-4ab8-8535-c1e4a828475d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130580857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2130580857
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2489184143
Short name T103
Test name
Test status
Simulation time 51990878506 ps
CPU time 1163.88 seconds
Started Dec 31 01:33:03 PM PST 23
Finished Dec 31 01:52:28 PM PST 23
Peak memory 289040 kb
Host smart-d836a4a8-ff32-4c26-bc28-dd02396a3031
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489184143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2489184143
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.531095378
Short name T285
Test name
Test status
Simulation time 61846048987 ps
CPU time 202.25 seconds
Started Dec 31 01:32:58 PM PST 23
Finished Dec 31 01:36:21 PM PST 23
Peak memory 247128 kb
Host smart-392c7b0e-b0dd-4ef1-8292-77991a3a5196
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531095378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.531095378
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1632582103
Short name T711
Test name
Test status
Simulation time 951282961 ps
CPU time 37.69 seconds
Started Dec 31 01:31:28 PM PST 23
Finished Dec 31 01:32:07 PM PST 23
Peak memory 248628 kb
Host smart-ff512eae-d83b-4e9f-ae4e-a86fd78f6e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16325
82103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1632582103
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2567155447
Short name T636
Test name
Test status
Simulation time 246800567 ps
CPU time 15.99 seconds
Started Dec 31 01:31:29 PM PST 23
Finished Dec 31 01:31:46 PM PST 23
Peak memory 253996 kb
Host smart-ff478cf3-1207-4eb6-b399-1812ac1df3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671
55447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2567155447
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4274807821
Short name T97
Test name
Test status
Simulation time 502930021 ps
CPU time 24.23 seconds
Started Dec 31 01:33:04 PM PST 23
Finished Dec 31 01:33:29 PM PST 23
Peak memory 247824 kb
Host smart-ff696733-793a-4f7e-bde0-9de4468ef8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42748
07821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4274807821
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2359378233
Short name T486
Test name
Test status
Simulation time 3462335824 ps
CPU time 53.01 seconds
Started Dec 31 01:31:36 PM PST 23
Finished Dec 31 01:32:30 PM PST 23
Peak memory 248688 kb
Host smart-c72557c4-a29a-44b0-b6b2-1fe8a762ed02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23593
78233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2359378233
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2298413202
Short name T112
Test name
Test status
Simulation time 56733574140 ps
CPU time 2916.55 seconds
Started Dec 31 01:32:56 PM PST 23
Finished Dec 31 02:21:34 PM PST 23
Peak memory 288916 kb
Host smart-1442bf91-52a2-423c-a47f-a98070c070d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298413202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2298413202
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1933335439
Short name T200
Test name
Test status
Simulation time 46651904 ps
CPU time 2.27 seconds
Started Dec 31 01:32:47 PM PST 23
Finished Dec 31 01:32:50 PM PST 23
Peak memory 248816 kb
Host smart-052dd0fb-e7e0-4a7d-a051-9ef89ffa4b8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1933335439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1933335439
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2370031586
Short name T240
Test name
Test status
Simulation time 109804798436 ps
CPU time 1362.13 seconds
Started Dec 31 01:34:00 PM PST 23
Finished Dec 31 01:56:47 PM PST 23
Peak memory 273292 kb
Host smart-3eb0d65a-d9bf-4e9a-9ec5-68d5ae7b7630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370031586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2370031586
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2193949017
Short name T635
Test name
Test status
Simulation time 296249894 ps
CPU time 9.19 seconds
Started Dec 31 01:32:59 PM PST 23
Finished Dec 31 01:33:09 PM PST 23
Peak memory 240396 kb
Host smart-44f52fe0-67f8-4312-975e-ccd7a06d2ec9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193949017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2193949017
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3038845287
Short name T53
Test name
Test status
Simulation time 11883758408 ps
CPU time 102.18 seconds
Started Dec 31 01:32:05 PM PST 23
Finished Dec 31 01:33:49 PM PST 23
Peak memory 256828 kb
Host smart-b91e7bc1-d4a1-4884-947e-a1abccbcd6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30388
45287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3038845287
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.786658577
Short name T502
Test name
Test status
Simulation time 77809179 ps
CPU time 3.83 seconds
Started Dec 31 01:33:34 PM PST 23
Finished Dec 31 01:33:39 PM PST 23
Peak memory 240376 kb
Host smart-7f76d14d-33d9-4ec4-b4e2-8064eb707c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78665
8577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.786658577
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4025160168
Short name T342
Test name
Test status
Simulation time 16232122375 ps
CPU time 1269.91 seconds
Started Dec 31 01:33:58 PM PST 23
Finished Dec 31 01:55:11 PM PST 23
Peak memory 289176 kb
Host smart-10eeee86-8930-4e17-8b97-9998ae6a26cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025160168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4025160168
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.820185624
Short name T433
Test name
Test status
Simulation time 116956585083 ps
CPU time 1687.33 seconds
Started Dec 31 01:32:04 PM PST 23
Finished Dec 31 02:00:13 PM PST 23
Peak memory 272344 kb
Host smart-cec33e77-ff83-4c97-99c5-ae3b3ee93264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820185624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.820185624
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2154904379
Short name T234
Test name
Test status
Simulation time 469682973 ps
CPU time 22.72 seconds
Started Dec 31 01:33:44 PM PST 23
Finished Dec 31 01:34:08 PM PST 23
Peak memory 248560 kb
Host smart-7da7d776-896d-4984-8cef-08f6fa65fe44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
04379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2154904379
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3963564081
Short name T639
Test name
Test status
Simulation time 191920838 ps
CPU time 7.44 seconds
Started Dec 31 01:34:05 PM PST 23
Finished Dec 31 01:34:15 PM PST 23
Peak memory 248520 kb
Host smart-06015fc4-0199-4b68-b7d6-0f7547633364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39635
64081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3963564081
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2675512358
Short name T409
Test name
Test status
Simulation time 305915599 ps
CPU time 9.32 seconds
Started Dec 31 01:31:29 PM PST 23
Finished Dec 31 01:31:39 PM PST 23
Peak memory 247764 kb
Host smart-a7e37ce8-1066-42a6-97f6-3497e9d49503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26755
12358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2675512358
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3553304656
Short name T51
Test name
Test status
Simulation time 517460322 ps
CPU time 12.56 seconds
Started Dec 31 01:34:01 PM PST 23
Finished Dec 31 01:34:19 PM PST 23
Peak memory 256844 kb
Host smart-77ee7109-7603-41f7-9aa8-4f0ae778b255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35533
04656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3553304656
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3147301417
Short name T55
Test name
Test status
Simulation time 74165478825 ps
CPU time 1889.71 seconds
Started Dec 31 01:31:27 PM PST 23
Finished Dec 31 02:02:58 PM PST 23
Peak memory 306120 kb
Host smart-6c8d1e09-2fc6-4092-ae0f-b2525a9f555a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147301417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3147301417
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.415968747
Short name T481
Test name
Test status
Simulation time 463564303158 ps
CPU time 5034.25 seconds
Started Dec 31 01:32:21 PM PST 23
Finished Dec 31 02:56:22 PM PST 23
Peak memory 330656 kb
Host smart-039adff5-04e8-41b4-868c-6356c4f2b2fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415968747 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.415968747
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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