Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	119115	1			T4	123		T5	2508		T21	40
class_i[0x1]	60011	1			T5	26		T19	23		T23	3830
class_i[0x2]	79091	1			T5	28		T6	1		T23	992
class_i[0x3]	50176	1			T5	112		T6	6		T11	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	74692	1			T4	49		T5	756		T19	7
alert[0x1]	79548	1			T4	23		T5	674		T19	7
alert[0x2]	76004	1			T4	37		T5	616		T19	5
alert[0x3]	78149	1			T4	14		T5	628		T19	4

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

308110

1

T4

123

T5

2674

T19

23

esc_ping_fail

283

1

T9

2

T11

7

T12

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	74615	1			T4	49		T5	756		T19	7
esc_integrity_fail	alert[0x1]	79477	1			T4	23		T5	674		T19	7
esc_integrity_fail	alert[0x2]	75938	1			T4	37		T5	616		T19	5
esc_integrity_fail	alert[0x3]	78080	1			T4	14		T5	628		T19	4
esc_ping_fail	alert[0x0]	77	1			T9	1		T11	3		T12	3
esc_ping_fail	alert[0x1]	71	1			T9	1		T11	2		T12	2
esc_ping_fail	alert[0x2]	66	1			T11	1		T12	2		T263	2
esc_ping_fail	alert[0x3]	69	1			T11	1		T12	2		T263	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	119049	1			T4	123		T5	2508		T21	40
esc_integrity_fail	class_i[0x1]	59943	1			T5	26		T19	23		T23	3830
esc_integrity_fail	class_i[0x2]	79022	1			T5	28		T6	1		T23	992
esc_integrity_fail	class_i[0x3]	50096	1			T5	112		T6	6		T12	2
esc_ping_fail	class_i[0x0]	66	1			T9	2		T12	1		T263	1
esc_ping_fail	class_i[0x1]	68	1			T11	5		T263	4		T335	1
esc_ping_fail	class_i[0x2]	69	1			T12	6		T119	4		T343	6
esc_ping_fail	class_i[0x3]	80	1			T11	2		T12	2		T335	1