Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	187	1			T4	1		T5	2		T19	1
index[0x1]	172	1			T4	2		T60	2		T132	1
index[0x2]	222	1			T4	1		T5	2		T23	2
index[0x3]	180	1			T4	2		T5	2		T23	3

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	258	1			T4	2		T5	6		T6	1
lens_less_than_1000[1]	143	1			T4	2		T23	3		T248	1
lens_less_than_1000[2]	110	1			T132	2		T92	1		T279	2
lens_less_than_1000[3]	73	1			T57	1		T65	1		T93	1
lens_less_than_1000[4]	55	1			T63	1		T109	1		T98	1
lens_less_than_1000[5]	37	1			T4	1		T19	1		T23	2
lens_less_than_1000[6]	37	1			T4	1		T23	1		T57	1
lens_less_than_1000[7]	25	1			T42	1		T66	1		T102	1
lens_less_than_1000[8]	15	1			T66	1		T67	1		T75	1
lens_less_than_1000[9]	6	1			T55	2		T280	1		T281	1
len_2	2	1			T282	1		T111	1		-	-

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9] , len_2]	--	--	2
[index[0x3]]	[len_2]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	63	1			T4	1		T5	2		T6	1
index[0x0]	lens_less_than_1000[1]	38	1			T91	1		T283	1		T284	3
index[0x0]	lens_less_than_1000[2]	21	1			T92	1		T279	1		T75	1
index[0x0]	lens_less_than_1000[3]	23	1			T101	1		T285	2		T286	1
index[0x0]	lens_less_than_1000[4]	6	1			T63	1		T287	1		T75	1
index[0x0]	lens_less_than_1000[5]	12	1			T19	1		T248	1		T101	1
index[0x0]	lens_less_than_1000[6]	9	1			T23	1		T57	1		T98	1
index[0x0]	lens_less_than_1000[7]	7	1			T288	1		T289	1		T290	1
index[0x0]	lens_less_than_1000[8]	8	1			T75	1		T277	1		T291	1
index[0x1]	lens_less_than_1000[0]	61	1			T60	2		T249	1		T98	2
index[0x1]	lens_less_than_1000[1]	30	1			T4	1		T248	1		T65	1
index[0x1]	lens_less_than_1000[2]	29	1			T132	1		T82	1		T43	1
index[0x1]	lens_less_than_1000[3]	17	1			T261	1		T279	1		T102	1
index[0x1]	lens_less_than_1000[4]	12	1			T109	1		T92	1		T84	1
index[0x1]	lens_less_than_1000[5]	2	1			T280	1		T292	1		-	-
index[0x1]	lens_less_than_1000[6]	9	1			T4	1		T119	1		T293	1
index[0x1]	lens_less_than_1000[7]	7	1			T102	1		T294	1		T288	1
index[0x1]	lens_less_than_1000[8]	1	1			T67	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	3	1			T55	1		T280	1		T295	1
index[0x1]	len_2	1	1			T111	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	79	1			T5	2		T60	1		T25	4
index[0x2]	lens_less_than_1000[1]	32	1			T65	1		T296	1		T66	1
index[0x2]	lens_less_than_1000[2]	36	1			T132	1		T297	1		T276	1
index[0x2]	lens_less_than_1000[3]	24	1			T57	1		T65	1		T93	1
index[0x2]	lens_less_than_1000[4]	19	1			T92	1		T287	1		T298	1
index[0x2]	lens_less_than_1000[5]	16	1			T4	1		T23	2		T101	1
index[0x2]	lens_less_than_1000[6]	9	1			T92	1		T86	1		T38	1
index[0x2]	lens_less_than_1000[7]	4	1			T299	1		T300	1		T301	1
index[0x2]	lens_less_than_1000[8]	1	1			T66	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T302	1		-	-		-	-
index[0x2]	len_2	1	1			T282	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	55	1			T4	1		T5	2		T58	1
index[0x3]	lens_less_than_1000[1]	43	1			T4	1		T23	3		T98	1
index[0x3]	lens_less_than_1000[2]	24	1			T279	1		T235	1		T69	1
index[0x3]	lens_less_than_1000[3]	9	1			T303	2		T56	1		T129	1
index[0x3]	lens_less_than_1000[4]	18	1			T98	1		T104	1		T275	1
index[0x3]	lens_less_than_1000[5]	7	1			T123	2		T304	1		T305	1
index[0x3]	lens_less_than_1000[6]	10	1			T306	3		T75	1		T307	1
index[0x3]	lens_less_than_1000[7]	7	1			T42	1		T66	1		T290	1
index[0x3]	lens_less_than_1000[8]	5	1			T308	1		T309	1		T310	1
index[0x3]	lens_less_than_1000[9]	2	1			T55	1		T281	1		-	-