Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	66	1			T3	1		T5	1		T60	1
class_index[0x1]	69	1			T5	1		T60	1		T98	1
class_index[0x2]	56	1			T21	1		T58	1		T100	1
class_index[0x3]	63	1			T3	1		T19	1		T57	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	85	1			T3	1		T21	1		T58	1
intr_timeout_cnt[1]	64	1			T3	1		T5	1		T98	2
intr_timeout_cnt[2]	22	1			T57	1		T60	1		T143	1
intr_timeout_cnt[3]	13	1			T19	1		T60	1		T65	1
intr_timeout_cnt[4]	18	1			T5	1		T100	1		T67	1
intr_timeout_cnt[5]	10	1			T102	1		T131	1		T75	1
intr_timeout_cnt[6]	10	1			T25	1		T125	1		T311	1
intr_timeout_cnt[7]	13	1			T100	1		T43	1		T111	2
intr_timeout_cnt[8]	6	1			T100	1		T127	1		T77	1
intr_timeout_cnt[9]	13	1			T58	1		T66	1		T123	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	25	1			T18	1		T62	5		T120	1
class_index[0x0]	intr_timeout_cnt[1]	18	1			T3	1		T98	1		T104	1
class_index[0x0]	intr_timeout_cnt[2]	1	1			T310	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[3]	4	1			T60	1		T300	1		T312	1
class_index[0x0]	intr_timeout_cnt[4]	7	1			T5	1		T100	1		T67	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T77	1		T313	1		T314	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T25	1		T125	1		T315	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T111	1		T139	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T123	1		T316	1		T317	1
class_index[0x1]	intr_timeout_cnt[0]	21	1			T104	1		T106	3		T138	1
class_index[0x1]	intr_timeout_cnt[1]	24	1			T5	1		T98	1		T43	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T60	1		T318	1		T319	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T36	1		T320	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	7	1			T131	1		T139	1		T316	3
class_index[0x1]	intr_timeout_cnt[5]	3	1			T75	1		T321	1		T322	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T311	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T114	1		T323	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T100	1		T321	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T66	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T21	1		T58	1		T100	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T324	1		T321	1		T280	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T80	1		T315	1		T314	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T78	1		T36	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T36	1		T325	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T102	1		T131	1		T326	1
class_index[0x2]	intr_timeout_cnt[6]	3	1			T77	1		T322	1		T320	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T43	1		T111	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T77	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	4	1			T75	1		T77	1		T323	1
class_index[0x3]	intr_timeout_cnt[0]	19	1			T3	1		T142	1		T43	1
class_index[0x3]	intr_timeout_cnt[1]	8	1			T65	1		T92	1		T103	1
class_index[0x3]	intr_timeout_cnt[2]	10	1			T57	1		T143	1		T67	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T19	1		T65	1		T314	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T73	1		T139	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T327	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T295	1		T328	1		T329	1
class_index[0x3]	intr_timeout_cnt[7]	7	1			T100	1		T311	1		T280	1
class_index[0x3]	intr_timeout_cnt[8]	3	1			T127	1		T78	1		T330	1
class_index[0x3]	intr_timeout_cnt[9]	5	1			T58	1		T331	1		T77	1