Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	386191	1			T32	8		T34	1		T188	8
all_values[1]	386191	1			T32	8		T34	1		T188	8
all_values[2]	386191	1			T32	8		T34	1		T188	8
all_values[3]	386191	1			T32	8		T34	1		T188	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

769416

1

T32

16

T34

4

T188

20

auto[1]

775348

1

T32

16

T188

12

T189

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

926110

1

T32

18

T34

4

T188

23

auto[1]

618654

1

T32

14

T188

9

T189

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	110164	1			T32	1		T34	1		T188	2
all_values[0]	auto[0]	auto[1]	82465	1			T189	1		T376	3		T273	1
all_values[0]	auto[1]	auto[0]	111431	1			T32	3		T188	5		T189	5
all_values[0]	auto[1]	auto[1]	82131	1			T32	4		T188	1		T272	2
all_values[1]	auto[0]	auto[0]	117849	1			T32	5		T34	1		T188	2
all_values[1]	auto[0]	auto[1]	74716	1			T188	5		T272	2		T273	2
all_values[1]	auto[1]	auto[0]	118774	1			T32	2		T188	1		T189	1
all_values[1]	auto[1]	auto[1]	74852	1			T32	1		T189	1		T272	1
all_values[2]	auto[0]	auto[0]	117812	1			T32	3		T34	1		T188	4
all_values[2]	auto[0]	auto[1]	74574	1			T32	2		T189	2		T376	1
all_values[2]	auto[1]	auto[0]	119261	1			T32	2		T188	2		T189	3
all_values[2]	auto[1]	auto[1]	74544	1			T32	1		T188	2		T189	3
all_values[3]	auto[0]	auto[0]	114498	1			T32	1		T34	1		T188	6
all_values[3]	auto[0]	auto[1]	77338	1			T32	4		T188	1		T189	5
all_values[3]	auto[1]	auto[0]	116321	1			T32	1		T188	1		T376	1
all_values[3]	auto[1]	auto[1]	78034	1			T32	2		T189	1		T376	2