Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	386191	1			T32	8		T34	1		T188	8
all_pins[1]	386191	1			T32	8		T34	1		T188	8
all_pins[2]	386191	1			T32	8		T34	1		T188	8
all_pins[3]	386191	1			T32	8		T34	1		T188	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1235203	1			T32	24		T34	4		T188	29
values[0x1]	309561	1			T32	8		T188	3		T189	5
transitions[0x0=>0x1]	207556	1			T32	6		T188	3		T189	3
transitions[0x1=>0x0]	207799	1			T32	6		T188	3		T189	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	304060	1			T32	4		T34	1		T188	7
all_pins[0]	values[0x1]	82131	1			T32	4		T188	1		T272	2
all_pins[0]	transitions[0x0=>0x1]	81408	1			T32	3		T188	1		T272	1
all_pins[0]	transitions[0x1=>0x0]	77554	1			T32	1		T189	1		T376	2
all_pins[1]	values[0x0]	311339	1			T32	7		T34	1		T188	8
all_pins[1]	values[0x1]	74852	1			T32	1		T189	1		T272	1
all_pins[1]	transitions[0x0=>0x1]	40919	1			T32	1		T189	1		T377	3
all_pins[1]	transitions[0x1=>0x0]	48198	1			T32	4		T188	1		T272	1
all_pins[2]	values[0x0]	311647	1			T32	7		T34	1		T188	6
all_pins[2]	values[0x1]	74544	1			T32	1		T188	2		T189	3
all_pins[2]	transitions[0x0=>0x1]	41260	1			T188	2		T189	2		T376	1
all_pins[2]	transitions[0x1=>0x0]	41568	1			T272	1		T377	3		T378	1
all_pins[3]	values[0x0]	308157	1			T32	6		T34	1		T188	8
all_pins[3]	values[0x1]	78034	1			T32	2		T189	1		T376	2
all_pins[3]	transitions[0x0=>0x1]	43969	1			T32	2		T376	2		T272	1
all_pins[3]	transitions[0x1=>0x0]	40479	1			T32	1		T188	2		T189	2