Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T32	7		T188	7		T189	7
all_values[1]	284	1			T32	7		T188	7		T189	7
all_values[2]	284	1			T32	7		T188	7		T189	7
all_values[3]	284	1			T32	7		T188	7		T189	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

610

1

T32

16

T188

17

T189

20

auto[1]

526

1

T32

12

T188

11

T189

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

421

1

T32

10

T188

11

T189

10

auto[1]

715

1

T32

18

T188

17

T189

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T32

15

T188

17

T189

16

auto[1]

461

1

T32

13

T188

11

T189

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

48

1

T32

2

T188

2

T189

1

all_values[0]

auto[0]

auto[0]

auto[1]

28

1

T376

1

T273

1

T377

1

all_values[0]

auto[0]

auto[1]

auto[0]

49

1

T188

1

T189

3

T272

1

all_values[0]

auto[0]

auto[1]

auto[1]

40

1

T32

2

T273

1

T377

1

all_values[0]

auto[1]

auto[0]

auto[1]

67

1

T188

1

T189

2

T376

2

all_values[0]

auto[1]

auto[1]

auto[1]

52

1

T32

3

T188

3

T189

1

all_values[1]

auto[0]

auto[0]

auto[0]

75

1

T32

4

T188

1

T189

5

all_values[1]

auto[0]

auto[0]

auto[1]

26

1

T188

4

T189

1

T272

1

all_values[1]

auto[0]

auto[1]

auto[0]

51

1

T32

1

T188

1

T376

2

all_values[1]

auto[0]

auto[1]

auto[1]

30

1

T272

1

T377

1

T378

1

all_values[1]

auto[1]

auto[0]

auto[1]

54

1

T32

2

T189

1

T272

3

all_values[1]

auto[1]

auto[1]

auto[1]

48

1

T188

1

T377

2

T379

1

all_values[2]

auto[0]

auto[0]

auto[0]

62

1

T32

1

T188

2

T376

2

all_values[2]

auto[0]

auto[0]

auto[1]

26

1

T32

1

T189

1

T376

1

all_values[2]

auto[0]

auto[1]

auto[0]

44

1

T32

2

T188

1

T189

1

all_values[2]

auto[0]

auto[1]

auto[1]

35

1

T188

1

T189

1

T272

2

all_values[2]

auto[1]

auto[0]

auto[1]

69

1

T32

3

T188

1

T189

2

all_values[2]

auto[1]

auto[1]

auto[1]

48

1

T188

2

T189

2

T272

2

all_values[3]

auto[0]

auto[0]

auto[0]

61

1

T188

3

T272

2

T273

2

all_values[3]

auto[0]

auto[0]

auto[1]

26

1

T32

1

T188

1

T189

3

all_values[3]

auto[0]

auto[1]

auto[0]

31

1

T272

1

T273

1

T380

2

all_values[3]

auto[0]

auto[1]

auto[1]

43

1

T32

1

T376

2

T377

1

all_values[3]

auto[1]

auto[0]

auto[1]

68

1

T32

2

T188

2

T189

4

all_values[3]

auto[1]

auto[1]

auto[1]

55

1

T32

3

T188

1

T272

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal