Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	95352	1			T5	498		T6	1762		T23	410
accum_cnt_1000	254077	1			T4	413		T5	3045		T6	1717
accum_cnt_100	32778	1			T4	274		T5	272		T6	91
accum_cnt_50	58950	1			T1	28		T4	276		T5	266
accum_cnt_10	192261	1			T1	60		T2	4		T3	14
accum_cnt_0	458840	1			T1	8		T2	4		T3	18

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	285054	1			T1	24		T2	2		T3	8
class_index[0x1]	285053	1			T1	24		T2	2		T3	8
class_index[0x2]	285053	1			T1	24		T2	2		T3	8
class_index[0x3]	285052	1			T1	24		T2	2		T3	8

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26155	1			T5	498		T6	601		T60	210
class_index[0x0]	accum_cnt_1000	68238	1			T4	188		T5	1453		T6	684
class_index[0x0]	accum_cnt_100	8475	1			T4	43		T5	95		T6	34
class_index[0x0]	accum_cnt_50	16465	1			T1	12		T4	47		T5	113
class_index[0x0]	accum_cnt_10	59158	1			T1	11		T3	4		T4	9
class_index[0x0]	accum_cnt_0	90370	1			T1	1		T2	2		T3	4
class_index[0x1]	accum_cnt_2000	21932	1			T6	525		T88	104		T109	244
class_index[0x1]	accum_cnt_1000	63894	1			T5	398		T6	454		T60	504
class_index[0x1]	accum_cnt_100	8493	1			T4	134		T5	25		T6	28
class_index[0x1]	accum_cnt_50	15959	1			T1	8		T4	108		T5	61
class_index[0x1]	accum_cnt_10	55120	1			T1	11		T2	2		T3	4
class_index[0x1]	accum_cnt_0	108447	1			T1	5		T3	4		T7	25
class_index[0x2]	accum_cnt_2000	18238	1			T109	24		T251	435		T260	151
class_index[0x2]	accum_cnt_1000	53373	1			T4	175		T5	1194		T23	1011
class_index[0x2]	accum_cnt_100	8315	1			T4	65		T5	152		T23	82
class_index[0x2]	accum_cnt_50	13866	1			T1	8		T4	80		T5	92
class_index[0x2]	accum_cnt_10	44724	1			T1	14		T2	2		T3	3
class_index[0x2]	accum_cnt_0	136992	1			T1	2		T3	5		T7	25
class_index[0x3]	accum_cnt_2000	29027	1			T6	636		T23	410		T109	135
class_index[0x3]	accum_cnt_1000	68572	1			T4	50		T6	579		T23	671
class_index[0x3]	accum_cnt_100	7495	1			T4	32		T6	29		T23	41
class_index[0x3]	accum_cnt_50	12660	1			T4	41		T6	26		T23	47
class_index[0x3]	accum_cnt_10	33259	1			T1	24		T3	3		T4	6
class_index[0x3]	accum_cnt_0	123031	1			T2	2		T3	5		T7	25