Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4356	1			T12	1		T25	1		T88	1929
alert[0x1]	4464	1			T5	4		T9	1		T25	3
alert[0x2]	7336	1			T9	1		T12	1		T88	1466
alert[0x3]	6394	1			T4	16		T18	1		T25	243
alert[0x4]	7094	1			T11	1		T98	119		T93	37
alert[0x5]	9203	1			T21	3		T57	23		T58	3
alert[0x6]	5171	1			T11	1		T88	2916		T92	24
alert[0x7]	6479	1			T5	1		T23	1		T57	2
alert[0x8]	12302	1			T4	2		T23	9		T60	65
alert[0x9]	5971	1			T5	2		T12	1		T88	34
alert[0xa]	7089	1			T57	4		T11	1		T109	13
alert[0xb]	9804	1			T4	1		T5	1		T58	5
alert[0xc]	17615	1			T57	19		T109	6		T119	1
alert[0xd]	12832	1			T88	2117		T98	19		T91	2
alert[0xe]	9645	1			T88	1352		T109	253		T92	21
alert[0xf]	10092	1			T5	1		T57	7		T132	7
alert[0x10]	10065	1			T12	1		T88	119		T109	41
alert[0x11]	4135	1			T60	59		T109	91		T98	2
alert[0x12]	7536	1			T5	5		T23	3		T109	14
alert[0x13]	7768	1			T58	2		T88	36		T109	19
alert[0x14]	8984	1			T109	26		T261	549		T117	8
alert[0x15]	10710	1			T5	8		T57	3		T109	1
alert[0x16]	14711	1			T5	54		T18	1		T132	1
alert[0x17]	6545	1			T4	58		T21	1		T60	16
alert[0x18]	4137	1			T4	3		T11	1		T60	5
alert[0x19]	16237	1			T5	1		T132	1		T88	24
alert[0x1a]	5428	1			T4	9		T11	1		T18	2
alert[0x1b]	5764	1			T57	2		T88	14		T109	24
alert[0x1c]	3816	1			T57	1		T9	1		T11	1
alert[0x1d]	13506	1			T4	1		T5	10		T60	6
alert[0x1e]	10551	1			T60	4		T18	15		T109	115
alert[0x1f]	7209	1			T57	4		T58	3		T88	216
alert[0x20]	6534	1			T12	1		T88	34		T109	21
alert[0x21]	11767	1			T60	8		T12	1		T263	2
alert[0x22]	2802	1			T8	1		T263	1		T109	2
alert[0x23]	13439	1			T19	1		T88	142		T264	205
alert[0x24]	8326	1			T4	2		T19	2		T88	43
alert[0x25]	3782	1			T90	1		T92	40		T93	450
alert[0x26]	7681	1			T5	1		T57	12		T11	1
alert[0x27]	3193	1			T25	1		T98	44		T92	27
alert[0x28]	5100	1			T57	5		T25	27		T92	39
alert[0x29]	5819	1			T4	4		T21	18		T58	4
alert[0x2a]	4599	1			T4	1		T18	12		T12	1
alert[0x2b]	5783	1			T4	22		T11	1		T109	90
alert[0x2c]	6458	1			T18	1		T25	16		T88	508
alert[0x2d]	4052	1			T4	15		T5	27		T21	7
alert[0x2e]	7248	1			T12	1		T132	10		T63	1
alert[0x2f]	6665	1			T60	38		T12	2		T109	46
alert[0x30]	15748	1			T12	2		T109	19		T98	19
alert[0x31]	11738	1			T5	1		T21	2		T18	2
alert[0x32]	5514	1			T4	1		T9	1		T88	1157
alert[0x33]	6107	1			T4	1		T60	14		T12	2
alert[0x34]	6839	1			T11	1		T25	34		T109	90
alert[0x35]	4819	1			T5	3		T60	470		T12	1
alert[0x36]	6583	1			T60	84		T335	1		T120	250
alert[0x37]	15172	1			T4	3		T12	1		T88	17
alert[0x38]	3559	1			T57	1		T88	502		T109	29
alert[0x39]	7951	1			T23	3		T57	1		T11	1
alert[0x3a]	4772	1			T88	23		T93	99		T261	105
alert[0x3b]	6844	1			T263	1		T88	32		T93	162
alert[0x3c]	10065	1			T4	32		T11	1		T88	56
alert[0x3d]	6008	1			T109	12		T98	37		T92	125
alert[0x3e]	4140	1			T88	23		T109	186		T93	11
alert[0x3f]	8817	1			T18	3		T109	48		T90	15
alert[0x40]	16420	1			T21	3		T9	1		T18	7

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	141047	1			T4	141		T19	2		T11	4
class_i[0x1]	157605	1			T21	14		T57	89		T11	1
class_i[0x2]	126540	1			T4	30		T5	119		T19	1
class_i[0x3]	92101	1			T21	20		T23	16		T9	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

516619

1

T4

171

T5

119

T19

3

alert_ping_fail

674

1

T8

1

T9

8

T11

12

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4347	1			T25	1		T88	1929		T109	38
alert_integrity_fail	alert[0x1]	4455	1			T5	4		T25	3		T88	382
alert_integrity_fail	alert[0x2]	7321	1			T88	1466		T109	57		T42	12
alert_integrity_fail	alert[0x3]	6388	1			T4	16		T18	1		T25	243
alert_integrity_fail	alert[0x4]	7081	1			T98	119		T93	37		T235	38
alert_integrity_fail	alert[0x5]	9192	1			T21	3		T57	23		T58	3
alert_integrity_fail	alert[0x6]	5156	1			T88	2916		T92	24		T261	24
alert_integrity_fail	alert[0x7]	6469	1			T5	1		T23	1		T57	2
alert_integrity_fail	alert[0x8]	12285	1			T4	2		T23	9		T60	65
alert_integrity_fail	alert[0x9]	5961	1			T5	2		T88	34		T42	22
alert_integrity_fail	alert[0xa]	7078	1			T57	4		T109	13		T261	171
alert_integrity_fail	alert[0xb]	9791	1			T4	1		T5	1		T58	5
alert_integrity_fail	alert[0xc]	17610	1			T57	19		T109	6		T93	517
alert_integrity_fail	alert[0xd]	12826	1			T88	2117		T98	19		T91	2
alert_integrity_fail	alert[0xe]	9636	1			T88	1352		T109	253		T92	21
alert_integrity_fail	alert[0xf]	10082	1			T5	1		T57	7		T132	7
alert_integrity_fail	alert[0x10]	10057	1			T88	119		T109	41		T92	117
alert_integrity_fail	alert[0x11]	4131	1			T60	59		T109	91		T98	2
alert_integrity_fail	alert[0x12]	7529	1			T5	5		T23	3		T109	14
alert_integrity_fail	alert[0x13]	7757	1			T58	2		T88	36		T109	19
alert_integrity_fail	alert[0x14]	8971	1			T109	26		T261	549		T117	8
alert_integrity_fail	alert[0x15]	10698	1			T5	8		T57	3		T109	1
alert_integrity_fail	alert[0x16]	14695	1			T5	54		T18	1		T132	1
alert_integrity_fail	alert[0x17]	6532	1			T4	58		T21	1		T60	16
alert_integrity_fail	alert[0x18]	4126	1			T4	3		T60	5		T25	5
alert_integrity_fail	alert[0x19]	16230	1			T5	1		T132	1		T88	24
alert_integrity_fail	alert[0x1a]	5417	1			T4	9		T18	2		T109	26
alert_integrity_fail	alert[0x1b]	5757	1			T57	2		T88	14		T109	24
alert_integrity_fail	alert[0x1c]	3801	1			T57	1		T18	3		T109	154
alert_integrity_fail	alert[0x1d]	13489	1			T4	1		T5	10		T60	6
alert_integrity_fail	alert[0x1e]	10545	1			T60	4		T18	15		T109	115
alert_integrity_fail	alert[0x1f]	7190	1			T57	4		T58	3		T88	216
alert_integrity_fail	alert[0x20]	6524	1			T88	34		T109	21		T98	2
alert_integrity_fail	alert[0x21]	11754	1			T60	8		T98	12		T93	169
alert_integrity_fail	alert[0x22]	2796	1			T109	2		T92	51		T93	55
alert_integrity_fail	alert[0x23]	13428	1			T19	1		T88	142		T264	205
alert_integrity_fail	alert[0x24]	8310	1			T4	2		T19	2		T88	43
alert_integrity_fail	alert[0x25]	3775	1			T90	1		T92	40		T93	450
alert_integrity_fail	alert[0x26]	7670	1			T5	1		T57	12		T60	12
alert_integrity_fail	alert[0x27]	3187	1			T25	1		T98	44		T92	27
alert_integrity_fail	alert[0x28]	5093	1			T57	5		T25	27		T92	39
alert_integrity_fail	alert[0x29]	5801	1			T4	4		T21	18		T58	4
alert_integrity_fail	alert[0x2a]	4587	1			T4	1		T18	12		T88	1689
alert_integrity_fail	alert[0x2b]	5773	1			T4	22		T109	90		T92	1
alert_integrity_fail	alert[0x2c]	6450	1			T18	1		T25	16		T88	508
alert_integrity_fail	alert[0x2d]	4038	1			T4	15		T5	27		T21	7
alert_integrity_fail	alert[0x2e]	7237	1			T132	10		T88	47		T37	1
alert_integrity_fail	alert[0x2f]	6655	1			T60	38		T109	46		T93	323
alert_integrity_fail	alert[0x30]	15733	1			T109	19		T98	19		T90	3
alert_integrity_fail	alert[0x31]	11731	1			T5	1		T21	2		T18	2
alert_integrity_fail	alert[0x32]	5505	1			T4	1		T88	1157		T92	15
alert_integrity_fail	alert[0x33]	6096	1			T4	1		T60	14		T93	2034
alert_integrity_fail	alert[0x34]	6830	1			T25	34		T109	90		T93	45
alert_integrity_fail	alert[0x35]	4807	1			T5	3		T60	470		T88	44
alert_integrity_fail	alert[0x36]	6577	1			T60	84		T120	250		T111	2331
alert_integrity_fail	alert[0x37]	15160	1			T4	3		T88	17		T98	2
alert_integrity_fail	alert[0x38]	3552	1			T57	1		T88	502		T109	29
alert_integrity_fail	alert[0x39]	7937	1			T23	3		T57	1		T88	457
alert_integrity_fail	alert[0x3a]	4765	1			T88	23		T93	99		T261	105
alert_integrity_fail	alert[0x3b]	6836	1			T88	32		T93	162		T261	19
alert_integrity_fail	alert[0x3c]	10057	1			T4	32		T88	56		T98	6
alert_integrity_fail	alert[0x3d]	6000	1			T109	12		T98	37		T92	125
alert_integrity_fail	alert[0x3e]	4129	1			T88	23		T109	186		T93	11
alert_integrity_fail	alert[0x3f]	8813	1			T18	3		T109	48		T90	15
alert_integrity_fail	alert[0x40]	16410	1			T21	3		T18	7		T92	31
alert_ping_fail	alert[0x0]	9	1			T12	1		T336	2		T337	2
alert_ping_fail	alert[0x1]	9	1			T9	1		T338	1		T337	1
alert_ping_fail	alert[0x2]	15	1			T9	1		T12	1		T119	1
alert_ping_fail	alert[0x3]	6	1			T274	2		T337	1		T339	1
alert_ping_fail	alert[0x4]	13	1			T11	1		T274	1		T340	1
alert_ping_fail	alert[0x5]	11	1			T9	2		T12	1		T274	1
alert_ping_fail	alert[0x6]	15	1			T11	1		T335	1		T134	1
alert_ping_fail	alert[0x7]	10	1			T11	1		T263	1		T119	1
alert_ping_fail	alert[0x8]	17	1			T263	2		T245	2		T341	1
alert_ping_fail	alert[0x9]	10	1			T12	1		T87	1		T342	1
alert_ping_fail	alert[0xa]	11	1			T11	1		T274	1		T87	1
alert_ping_fail	alert[0xb]	13	1			T9	1		T343	1		T134	1
alert_ping_fail	alert[0xc]	5	1			T119	1		T340	1		T344	1
alert_ping_fail	alert[0xd]	6	1			T338	1		T345	1		T342	1
alert_ping_fail	alert[0xe]	9	1			T134	1		T346	1		T50	1
alert_ping_fail	alert[0xf]	10	1			T343	1		T336	1		T48	1
alert_ping_fail	alert[0x10]	8	1			T12	1		T340	2		T255	1
alert_ping_fail	alert[0x11]	4	1			T336	1		T340	1		T134	1
alert_ping_fail	alert[0x12]	7	1			T340	1		T347	1		T348	1
alert_ping_fail	alert[0x13]	11	1			T50	1		T349	1		T286	1
alert_ping_fail	alert[0x14]	13	1			T87	1		T340	1		T134	1
alert_ping_fail	alert[0x15]	12	1			T87	1		T343	1		T347	1
alert_ping_fail	alert[0x16]	16	1			T87	1		T240	1		T333	1
alert_ping_fail	alert[0x17]	13	1			T134	1		T50	1		T253	1
alert_ping_fail	alert[0x18]	11	1			T11	1		T274	1		T50	1
alert_ping_fail	alert[0x19]	7	1			T336	1		T337	1		T342	1
alert_ping_fail	alert[0x1a]	11	1			T11	1		T335	1		T293	1
alert_ping_fail	alert[0x1b]	7	1			T340	1		T337	3		T350	1
alert_ping_fail	alert[0x1c]	15	1			T9	1		T11	1		T293	1
alert_ping_fail	alert[0x1d]	17	1			T293	1		T87	1		T336	2
alert_ping_fail	alert[0x1e]	6	1			T87	1		T134	1		T48	1
alert_ping_fail	alert[0x1f]	19	1			T87	3		T340	2		T50	1
alert_ping_fail	alert[0x20]	10	1			T12	1		T50	1		T347	1
alert_ping_fail	alert[0x21]	13	1			T12	1		T263	2		T119	1
alert_ping_fail	alert[0x22]	6	1			T8	1		T263	1		T339	1
alert_ping_fail	alert[0x23]	11	1			T87	2		T48	1		T245	1
alert_ping_fail	alert[0x24]	16	1			T343	1		T340	1		T346	1
alert_ping_fail	alert[0x25]	7	1			T87	1		T50	1		T351	1
alert_ping_fail	alert[0x26]	11	1			T11	1		T12	1		T263	1
alert_ping_fail	alert[0x27]	6	1			T336	1		T50	2		T338	1
alert_ping_fail	alert[0x28]	7	1			T274	1		T340	1		T352	1
alert_ping_fail	alert[0x29]	18	1			T263	1		T274	1		T343	1
alert_ping_fail	alert[0x2a]	12	1			T12	1		T263	1		T119	1
alert_ping_fail	alert[0x2b]	10	1			T11	1		T119	2		T336	1
alert_ping_fail	alert[0x2c]	8	1			T346	1		T50	1		T337	1
alert_ping_fail	alert[0x2d]	14	1			T12	1		T87	1		T136	1
alert_ping_fail	alert[0x2e]	11	1			T12	1		T63	1		T274	1
alert_ping_fail	alert[0x2f]	10	1			T12	2		T240	1		T336	1
alert_ping_fail	alert[0x30]	15	1			T12	2		T87	1		T343	2
alert_ping_fail	alert[0x31]	7	1			T12	1		T338	2		T348	1
alert_ping_fail	alert[0x32]	9	1			T9	1		T274	2		T50	1
alert_ping_fail	alert[0x33]	11	1			T12	2		T87	1		T336	1
alert_ping_fail	alert[0x34]	9	1			T11	1		T335	1		T134	2
alert_ping_fail	alert[0x35]	12	1			T12	1		T263	1		T87	1
alert_ping_fail	alert[0x36]	6	1			T335	1		T343	1		T353	1
alert_ping_fail	alert[0x37]	12	1			T12	1		T274	1		T336	1
alert_ping_fail	alert[0x38]	7	1			T274	1		T350	1		T354	1
alert_ping_fail	alert[0x39]	14	1			T11	1		T12	1		T274	1
alert_ping_fail	alert[0x3a]	7	1			T343	1		T346	1		T355	1
alert_ping_fail	alert[0x3b]	8	1			T263	1		T87	1		T245	1
alert_ping_fail	alert[0x3c]	8	1			T11	1		T336	1		T346	2
alert_ping_fail	alert[0x3d]	8	1			T336	2		T356	1		T357	1
alert_ping_fail	alert[0x3e]	11	1			T346	1		T353	1		T348	2
alert_ping_fail	alert[0x3f]	4	1			T343	1		T134	1		T50	1
alert_ping_fail	alert[0x40]	10	1			T9	1		T119	1		T87	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	140939	1			T4	141		T19	2		T60	1324
alert_integrity_fail	class_i[0x1]	157416	1			T21	14		T57	89		T60	18
alert_integrity_fail	class_i[0x2]	126367	1			T4	30		T5	119		T19	1
alert_integrity_fail	class_i[0x3]	91897	1			T21	20		T23	16		T25	8
alert_ping_fail	class_i[0x0]	108	1			T11	4		T12	3		T263	3
alert_ping_fail	class_i[0x1]	189	1			T11	1		T12	3		T263	5
alert_ping_fail	class_i[0x2]	173	1			T8	1		T9	1		T11	3
alert_ping_fail	class_i[0x3]	204	1			T9	7		T11	4		T12	5