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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.68 100.00 100.00 100.00 99.38 99.64


Total test records in report: 850
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T781 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3195987056 Jan 03 01:29:14 PM PST 24 Jan 03 01:29:24 PM PST 24 9114523 ps
T175 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.319836773 Jan 03 01:29:22 PM PST 24 Jan 03 01:38:52 PM PST 24 7988178958 ps
T161 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2619307687 Jan 03 01:28:58 PM PST 24 Jan 03 01:34:37 PM PST 24 4435670920 ps
T782 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3576636789 Jan 03 01:30:03 PM PST 24 Jan 03 01:31:03 PM PST 24 329686459 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2092635304 Jan 03 01:30:17 PM PST 24 Jan 03 01:31:32 PM PST 24 1078669152 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.516628126 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:37 PM PST 24 89895112 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2596054741 Jan 03 01:29:03 PM PST 24 Jan 03 01:29:14 PM PST 24 105480847 ps
T786 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2296949700 Jan 03 01:29:46 PM PST 24 Jan 03 01:30:08 PM PST 24 67170675 ps
T787 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4154799527 Jan 03 01:30:03 PM PST 24 Jan 03 01:30:59 PM PST 24 52595954 ps
T788 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2174128546 Jan 03 01:30:02 PM PST 24 Jan 03 01:31:14 PM PST 24 1416346500 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2732950548 Jan 03 01:30:01 PM PST 24 Jan 03 01:30:54 PM PST 24 25073275 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2959576110 Jan 03 01:30:16 PM PST 24 Jan 03 01:31:28 PM PST 24 1436473818 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3807088309 Jan 03 01:29:19 PM PST 24 Jan 03 01:29:44 PM PST 24 191976760 ps
T792 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2199326505 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:38 PM PST 24 222290958 ps
T203 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2368342419 Jan 03 01:29:11 PM PST 24 Jan 03 01:29:41 PM PST 24 348383449 ps
T197 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2770317699 Jan 03 01:29:59 PM PST 24 Jan 03 01:31:36 PM PST 24 1245236608 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.239748674 Jan 03 01:29:52 PM PST 24 Jan 03 01:30:28 PM PST 24 8422155 ps
T193 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1658346804 Jan 03 01:29:25 PM PST 24 Jan 03 01:29:40 PM PST 24 184639291 ps
T794 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.703836507 Jan 03 01:29:23 PM PST 24 Jan 03 01:29:37 PM PST 24 22973510 ps
T795 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1333876225 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:21 PM PST 24 9612724 ps
T796 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2613346218 Jan 03 01:30:00 PM PST 24 Jan 03 01:30:55 PM PST 24 25085423 ps
T172 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3695532212 Jan 03 01:29:22 PM PST 24 Jan 03 01:37:23 PM PST 24 12692805747 ps
T176 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4048908 Jan 03 01:28:57 PM PST 24 Jan 03 01:31:51 PM PST 24 5876943482 ps
T797 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1298205190 Jan 03 01:29:15 PM PST 24 Jan 03 01:29:27 PM PST 24 46068553 ps
T798 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.875376151 Jan 03 01:29:23 PM PST 24 Jan 03 01:29:40 PM PST 24 115834398 ps
T799 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4217676934 Jan 03 01:29:51 PM PST 24 Jan 03 01:30:31 PM PST 24 1192619292 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4186054002 Jan 03 01:28:46 PM PST 24 Jan 03 01:29:03 PM PST 24 59541816 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2557718434 Jan 03 01:29:25 PM PST 24 Jan 03 01:29:43 PM PST 24 33993315 ps
T802 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2281241787 Jan 03 01:30:04 PM PST 24 Jan 03 01:30:57 PM PST 24 13610219 ps
T803 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1318407970 Jan 03 01:29:12 PM PST 24 Jan 03 01:29:22 PM PST 24 241304682 ps
T804 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2715099216 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:21 PM PST 24 10049515 ps
T805 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.873683435 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:28 PM PST 24 57710555 ps
T806 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3189466691 Jan 03 01:29:50 PM PST 24 Jan 03 01:30:17 PM PST 24 17651710 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.252990251 Jan 03 01:30:13 PM PST 24 Jan 03 01:31:15 PM PST 24 119597884 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1285741807 Jan 03 01:28:57 PM PST 24 Jan 03 01:29:05 PM PST 24 24938589 ps
T809 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.495475989 Jan 03 01:29:23 PM PST 24 Jan 03 01:29:49 PM PST 24 1026141886 ps
T156 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3040718881 Jan 03 01:29:21 PM PST 24 Jan 03 01:34:56 PM PST 24 36199930194 ps
T160 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4167142291 Jan 03 01:29:59 PM PST 24 Jan 03 01:50:22 PM PST 24 68843851107 ps
T810 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.993717193 Jan 03 01:29:52 PM PST 24 Jan 03 01:30:24 PM PST 24 9437859 ps
T811 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3526398186 Jan 03 01:29:51 PM PST 24 Jan 03 01:30:22 PM PST 24 24493794 ps
T812 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4105629717 Jan 03 01:30:14 PM PST 24 Jan 03 01:31:15 PM PST 24 185291063 ps
T813 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3850252333 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:21 PM PST 24 12885360 ps
T177 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2528572423 Jan 03 01:29:43 PM PST 24 Jan 03 01:32:08 PM PST 24 1645949882 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3846499584 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:57 PM PST 24 2812510179 ps
T815 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3481957482 Jan 03 01:29:03 PM PST 24 Jan 03 01:29:28 PM PST 24 340744516 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1511876076 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:49 PM PST 24 396203827 ps
T817 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1173514061 Jan 03 01:29:26 PM PST 24 Jan 03 01:29:46 PM PST 24 77332695 ps
T381 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.532432819 Jan 03 01:29:24 PM PST 24 Jan 03 01:37:34 PM PST 24 21384684828 ps
T818 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3109873466 Jan 03 01:29:49 PM PST 24 Jan 03 01:30:29 PM PST 24 212313053 ps
T199 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.212354429 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:38 PM PST 24 59547676 ps
T819 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1214681363 Jan 03 01:30:12 PM PST 24 Jan 03 01:31:08 PM PST 24 18977348 ps
T820 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2001614640 Jan 03 01:29:14 PM PST 24 Jan 03 01:29:23 PM PST 24 10003632 ps
T159 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2092543483 Jan 03 01:29:21 PM PST 24 Jan 03 01:39:18 PM PST 24 12547239888 ps
T821 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2090038320 Jan 03 01:29:21 PM PST 24 Jan 03 01:29:34 PM PST 24 8769796 ps
T822 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.74455265 Jan 03 01:29:50 PM PST 24 Jan 03 01:30:18 PM PST 24 44910908 ps
T162 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.115336898 Jan 03 01:30:03 PM PST 24 Jan 03 01:34:12 PM PST 24 3151599182 ps
T166 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2007045811 Jan 03 01:30:18 PM PST 24 Jan 03 01:52:01 PM PST 24 90334868219 ps
T198 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2277467073 Jan 03 01:30:05 PM PST 24 Jan 03 01:31:03 PM PST 24 41027395 ps
T823 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.633408426 Jan 03 01:29:58 PM PST 24 Jan 03 01:31:15 PM PST 24 169632728 ps
T173 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3363285145 Jan 03 01:29:55 PM PST 24 Jan 03 01:33:11 PM PST 24 1979130384 ps
T824 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2882804965 Jan 03 01:29:29 PM PST 24 Jan 03 01:29:52 PM PST 24 39877363 ps
T825 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2644430143 Jan 03 01:30:00 PM PST 24 Jan 03 01:31:13 PM PST 24 333112707 ps
T826 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4116914948 Jan 03 01:29:50 PM PST 24 Jan 03 01:30:19 PM PST 24 7878224 ps
T827 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.464474304 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:29 PM PST 24 555730002 ps
T828 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1833504756 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:25 PM PST 24 135873317 ps
T829 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1824838780 Jan 03 01:28:45 PM PST 24 Jan 03 01:28:54 PM PST 24 11868833 ps
T830 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3605957721 Jan 03 01:29:51 PM PST 24 Jan 03 01:30:24 PM PST 24 52065210 ps
T831 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.836410345 Jan 03 01:29:03 PM PST 24 Jan 03 01:29:10 PM PST 24 11546274 ps
T832 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2125383626 Jan 03 01:29:23 PM PST 24 Jan 03 01:29:40 PM PST 24 34943967 ps
T833 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2567225208 Jan 03 01:29:24 PM PST 24 Jan 03 01:30:23 PM PST 24 1445116784 ps
T834 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3292913309 Jan 03 01:28:54 PM PST 24 Jan 03 01:29:18 PM PST 24 182438425 ps
T167 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2128684256 Jan 03 01:29:15 PM PST 24 Jan 03 01:32:37 PM PST 24 2951580240 ps
T835 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.972563546 Jan 03 01:29:57 PM PST 24 Jan 03 01:30:54 PM PST 24 53740732 ps
T179 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4222595457 Jan 03 01:29:56 PM PST 24 Jan 03 01:32:46 PM PST 24 1979596320 ps
T196 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3120947311 Jan 03 01:28:55 PM PST 24 Jan 03 01:30:04 PM PST 24 3531460225 ps
T182 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3901407608 Jan 03 01:28:59 PM PST 24 Jan 03 01:32:51 PM PST 24 6429139809 ps
T836 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.454055364 Jan 03 01:29:11 PM PST 24 Jan 03 01:29:36 PM PST 24 670713786 ps
T837 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2947988004 Jan 03 01:29:31 PM PST 24 Jan 03 01:35:10 PM PST 24 17106186230 ps
T838 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2348032928 Jan 03 01:29:47 PM PST 24 Jan 03 01:30:05 PM PST 24 18806406 ps
T839 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.857165255 Jan 03 01:29:20 PM PST 24 Jan 03 01:29:33 PM PST 24 50317554 ps
T840 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.768552485 Jan 03 01:29:58 PM PST 24 Jan 03 01:31:00 PM PST 24 536878404 ps
T181 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3917901748 Jan 03 01:29:29 PM PST 24 Jan 03 01:32:18 PM PST 24 2501171129 ps
T163 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3515578750 Jan 03 01:29:51 PM PST 24 Jan 03 01:35:51 PM PST 24 2846498962 ps
T841 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4182716620 Jan 03 01:29:15 PM PST 24 Jan 03 01:29:43 PM PST 24 158743227 ps
T842 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.832091836 Jan 03 01:29:25 PM PST 24 Jan 03 01:29:38 PM PST 24 8510662 ps
T843 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2697710121 Jan 03 01:29:23 PM PST 24 Jan 03 01:29:36 PM PST 24 14524336 ps
T201 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2982617103 Jan 03 01:29:25 PM PST 24 Jan 03 01:29:59 PM PST 24 220600597 ps
T185 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1688596023 Jan 03 01:29:56 PM PST 24 Jan 03 01:42:39 PM PST 24 4609889634 ps
T844 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3674231195 Jan 03 01:29:25 PM PST 24 Jan 03 01:30:28 PM PST 24 2751451875 ps
T845 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1420893066 Jan 03 01:29:56 PM PST 24 Jan 03 01:30:53 PM PST 24 164713171 ps
T170 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2230946682 Jan 03 01:29:22 PM PST 24 Jan 03 01:31:16 PM PST 24 3388570318 ps
T174 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1576725631 Jan 03 01:30:07 PM PST 24 Jan 03 01:35:54 PM PST 24 4896966761 ps
T846 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2754661362 Jan 03 01:29:14 PM PST 24 Jan 03 01:29:44 PM PST 24 348906972 ps
T847 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2381969044 Jan 03 01:29:57 PM PST 24 Jan 03 01:30:52 PM PST 24 12230212 ps
T171 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2689518221 Jan 03 01:29:55 PM PST 24 Jan 03 01:34:18 PM PST 24 2167952342 ps
T183 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2626299792 Jan 03 01:30:03 PM PST 24 Jan 03 01:46:55 PM PST 24 48090265348 ps
T848 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2774426292 Jan 03 01:29:53 PM PST 24 Jan 03 01:30:34 PM PST 24 78846640 ps
T849 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1611307912 Jan 03 01:29:35 PM PST 24 Jan 03 01:30:29 PM PST 24 4303621964 ps
T202 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3599192555 Jan 03 01:29:24 PM PST 24 Jan 03 01:30:44 PM PST 24 1152109948 ps
T850 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4168847341 Jan 03 01:29:59 PM PST 24 Jan 03 01:31:04 PM PST 24 746490498 ps

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1786698614
Short name T16
Test name
Test status
Simulation time 31770409 ps
CPU time 2.96 seconds
Started Jan 03 01:29:36 PM PST 24
Finished Jan 03 01:29:56 PM PST 24
Peak memory 236392 kb
Host smart-f1f81659-6da4-4b00-b5a0-9f87d2c1adba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1786698614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1786698614
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2214640563
Short name T4
Test name
Test status
Simulation time 38151510257 ps
CPU time 1367.21 seconds
Started Jan 03 01:39:02 PM PST 24
Finished Jan 03 02:01:52 PM PST 24
Peak memory 285400 kb
Host smart-a0947bb9-d453-460f-98a2-d71699e8432f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214640563 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2214640563
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3603421066
Short name T26
Test name
Test status
Simulation time 640888646 ps
CPU time 26.01 seconds
Started Jan 03 01:28:44 PM PST 24
Finished Jan 03 01:29:18 PM PST 24
Peak memory 240360 kb
Host smart-4a1a9ded-bf1c-402a-b611-dbd7d4e26194
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3603421066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3603421066
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.247850463
Short name T30
Test name
Test status
Simulation time 19235936699 ps
CPU time 360.18 seconds
Started Jan 03 01:29:48 PM PST 24
Finished Jan 03 01:36:05 PM PST 24
Peak memory 272724 kb
Host smart-1803fadf-b64a-4dc1-990d-6ddfea960585
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=247850463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.247850463
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4014479151
Short name T17
Test name
Test status
Simulation time 145597668 ps
CPU time 9.3 seconds
Started Jan 03 01:36:07 PM PST 24
Finished Jan 03 01:36:29 PM PST 24
Peak memory 240320 kb
Host smart-8b6da879-b749-4498-b756-176f9653bef6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4014479151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4014479151
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.688447583
Short name T13
Test name
Test status
Simulation time 222344953 ps
CPU time 13.62 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:36:06 PM PST 24
Peak memory 277076 kb
Host smart-a128962a-807c-4d3f-b4b2-ff902349f055
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=688447583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.688447583
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.597791371
Short name T5
Test name
Test status
Simulation time 56716589677 ps
CPU time 4964.31 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 03:00:21 PM PST 24
Peak memory 350876 kb
Host smart-a347fd5d-fb11-4daa-9bbf-0e5c1f7fb213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597791371 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.597791371
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.624828845
Short name T333
Test name
Test status
Simulation time 205810276031 ps
CPU time 2720.77 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 02:22:51 PM PST 24
Peak memory 281388 kb
Host smart-3e2ed8dc-7df9-4800-bb5f-c6b70e4e0f3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624828845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.624828845
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1498838034
Short name T93
Test name
Test status
Simulation time 34632243844 ps
CPU time 2113.2 seconds
Started Jan 03 01:38:10 PM PST 24
Finished Jan 03 02:13:27 PM PST 24
Peak memory 289284 kb
Host smart-bfacdd95-cbdc-4a9a-945d-0f81805022cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498838034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1498838034
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1802333519
Short name T145
Test name
Test status
Simulation time 15469652010 ps
CPU time 1121.97 seconds
Started Jan 03 01:29:15 PM PST 24
Finished Jan 03 01:48:08 PM PST 24
Peak memory 270828 kb
Host smart-dc67feed-9148-4ce4-a88d-a266082322a5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802333519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1802333519
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1143349317
Short name T188
Test name
Test status
Simulation time 9888860 ps
CPU time 1.6 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:29:40 PM PST 24
Peak memory 235540 kb
Host smart-cbddd22f-4990-4501-838f-4ee6b3dfeae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1143349317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1143349317
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1680386221
Short name T164
Test name
Test status
Simulation time 5663336542 ps
CPU time 352.6 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:36:29 PM PST 24
Peak memory 265272 kb
Host smart-1a75289e-9b5f-417f-9ded-f24cd1a89ce2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1680386221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1680386221
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1104396304
Short name T109
Test name
Test status
Simulation time 17317485459 ps
CPU time 783.86 seconds
Started Jan 03 01:36:14 PM PST 24
Finished Jan 03 01:49:33 PM PST 24
Peak memory 272724 kb
Host smart-55ae9558-bcd7-47cc-9d72-7e1a02df7d52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104396304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1104396304
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4167142291
Short name T160
Test name
Test status
Simulation time 68843851107 ps
CPU time 1171.42 seconds
Started Jan 03 01:29:59 PM PST 24
Finished Jan 03 01:50:22 PM PST 24
Peak memory 265276 kb
Host smart-b653123f-7839-4ff4-b062-985a2b56e6cb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167142291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4167142291
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.396049122
Short name T12
Test name
Test status
Simulation time 17630019996 ps
CPU time 655.42 seconds
Started Jan 03 01:38:38 PM PST 24
Finished Jan 03 01:49:46 PM PST 24
Peak memory 247428 kb
Host smart-9b427ade-47f2-4ca1-9aef-840f97f51774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396049122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.396049122
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4099451719
Short name T334
Test name
Test status
Simulation time 108871382840 ps
CPU time 1442.17 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 02:00:26 PM PST 24
Peak memory 265040 kb
Host smart-fdf5e7b1-30c2-45da-9ee3-cd49cae61fc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099451719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4099451719
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1329110335
Short name T147
Test name
Test status
Simulation time 2015543544 ps
CPU time 202.35 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:32:59 PM PST 24
Peak memory 265244 kb
Host smart-52ed9ad0-d1c3-4a81-89f1-e87a757fa267
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1329110335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1329110335
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.863119301
Short name T60
Test name
Test status
Simulation time 27040456650 ps
CPU time 2372.69 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 02:17:12 PM PST 24
Peak memory 297964 kb
Host smart-f7ae3b95-be08-4d48-8f2f-72320fd08ced
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863119301 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.863119301
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2340300794
Short name T66
Test name
Test status
Simulation time 17339916140 ps
CPU time 2059.25 seconds
Started Jan 03 01:38:13 PM PST 24
Finished Jan 03 02:12:37 PM PST 24
Peak memory 306228 kb
Host smart-4c85ee95-cfbc-497d-a626-2b0120ef017f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340300794 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2340300794
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3176115948
Short name T352
Test name
Test status
Simulation time 152741472511 ps
CPU time 2804.11 seconds
Started Jan 03 01:35:41 PM PST 24
Finished Jan 03 02:22:29 PM PST 24
Peak memory 286556 kb
Host smart-e69e040f-6dd0-414f-a27c-a18ec04e3754
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176115948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3176115948
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3056040178
Short name T157
Test name
Test status
Simulation time 24359364864 ps
CPU time 948.53 seconds
Started Jan 03 01:28:44 PM PST 24
Finished Jan 03 01:44:40 PM PST 24
Peak memory 273092 kb
Host smart-2bbc5a21-c708-4b2d-8749-ee4a7b455a1c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056040178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3056040178
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2382257296
Short name T102
Test name
Test status
Simulation time 55634184078 ps
CPU time 3012.09 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 02:27:48 PM PST 24
Peak memory 289628 kb
Host smart-e5cbb08b-9b64-49fe-ae2b-c894b320c011
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382257296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2382257296
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2489433193
Short name T50
Test name
Test status
Simulation time 26147479955 ps
CPU time 547.26 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:47:46 PM PST 24
Peak memory 248576 kb
Host smart-ce91ab7b-7a18-43de-b7b6-a8990abea4b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489433193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2489433193
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3179913168
Short name T158
Test name
Test status
Simulation time 48235751070 ps
CPU time 1042.13 seconds
Started Jan 03 01:29:31 PM PST 24
Finished Jan 03 01:47:12 PM PST 24
Peak memory 265372 kb
Host smart-a45e26c5-65b4-45f7-965e-afd55b025efc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179913168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3179913168
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3824292768
Short name T192
Test name
Test status
Simulation time 674607679 ps
CPU time 41.41 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:31:08 PM PST 24
Peak memory 236716 kb
Host smart-1be8bf10-77fe-48bb-a3fc-ef988e4ef9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3824292768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3824292768
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2170600865
Short name T92
Test name
Test status
Simulation time 51435671674 ps
CPU time 2764.79 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 02:23:54 PM PST 24
Peak memory 288876 kb
Host smart-975e2b02-e38c-4493-b7bc-4429630f5ab9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170600865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2170600865
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.628491273
Short name T360
Test name
Test status
Simulation time 74450231545 ps
CPU time 2180.16 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 02:12:44 PM PST 24
Peak memory 286472 kb
Host smart-f1e7b036-dd99-4919-8b42-9c37f4697f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628491273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.628491273
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3990676837
Short name T111
Test name
Test status
Simulation time 49352196693 ps
CPU time 2689.53 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 02:20:40 PM PST 24
Peak memory 289176 kb
Host smart-5ef5d823-bf44-4633-a2cb-e7168c2cf903
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990676837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3990676837
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.678615369
Short name T75
Test name
Test status
Simulation time 96315038741 ps
CPU time 1971.18 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 02:10:21 PM PST 24
Peak memory 299188 kb
Host smart-26fb6462-9f9b-4aee-af44-5c14b5aaec3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678615369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.678615369
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3691787200
Short name T340
Test name
Test status
Simulation time 23873624770 ps
CPU time 497.56 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:46:03 PM PST 24
Peak memory 254816 kb
Host smart-e51320bd-bcd9-4295-9b6c-7f5541c1f99b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691787200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3691787200
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2859731860
Short name T155
Test name
Test status
Simulation time 1579041872 ps
CPU time 188.02 seconds
Started Jan 03 01:28:59 PM PST 24
Finished Jan 03 01:32:12 PM PST 24
Peak memory 265412 kb
Host smart-e0368cc6-ccd3-4ee6-9ca6-87ea25677b23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2859731860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2859731860
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3710298362
Short name T77
Test name
Test status
Simulation time 56967003391 ps
CPU time 3954.14 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 02:43:31 PM PST 24
Peak memory 321856 kb
Host smart-283c7b09-e39b-40f0-be31-984d59f1622d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710298362 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3710298362
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3729388850
Short name T146
Test name
Test status
Simulation time 9345531154 ps
CPU time 334 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:36:16 PM PST 24
Peak memory 268108 kb
Host smart-4eb5ee75-1063-4788-8010-76c9ac7fef86
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729388850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3729388850
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.501719988
Short name T98
Test name
Test status
Simulation time 707183197564 ps
CPU time 7158.74 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 03:36:59 PM PST 24
Peak memory 330436 kb
Host smart-6bd16ee7-60ce-4cf1-9f06-5859fd6f9cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501719988 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.501719988
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2796296528
Short name T354
Test name
Test status
Simulation time 177696419585 ps
CPU time 464.54 seconds
Started Jan 03 01:35:42 PM PST 24
Finished Jan 03 01:43:31 PM PST 24
Peak memory 248580 kb
Host smart-419cf222-8ee9-4c1b-a823-1aa2dc55e365
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796296528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2796296528
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.693990374
Short name T752
Test name
Test status
Simulation time 9618297 ps
CPU time 1.35 seconds
Started Jan 03 01:29:33 PM PST 24
Finished Jan 03 01:29:53 PM PST 24
Peak memory 236356 kb
Host smart-24cbc14e-bbae-4daf-8a59-d03584e61fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=693990374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.693990374
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2031912000
Short name T600
Test name
Test status
Simulation time 16127860945 ps
CPU time 518.72 seconds
Started Jan 03 01:37:31 PM PST 24
Finished Jan 03 01:46:20 PM PST 24
Peak memory 247480 kb
Host smart-996205a9-5539-419a-9848-6331317afd18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031912000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2031912000
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3688313958
Short name T295
Test name
Test status
Simulation time 49688919703 ps
CPU time 2861.91 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 02:25:28 PM PST 24
Peak memory 305948 kb
Host smart-3a8d1952-0bea-43ca-9a19-4de84436a0a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688313958 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3688313958
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4189014580
Short name T362
Test name
Test status
Simulation time 109934857280 ps
CPU time 1806.28 seconds
Started Jan 03 01:37:39 PM PST 24
Finished Jan 03 02:07:55 PM PST 24
Peak memory 282032 kb
Host smart-16ecb768-34c2-40f7-a226-a687988cae39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189014580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4189014580
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1985871548
Short name T36
Test name
Test status
Simulation time 65285151057 ps
CPU time 1168.25 seconds
Started Jan 03 01:37:10 PM PST 24
Finished Jan 03 01:56:57 PM PST 24
Peak memory 281620 kb
Host smart-9c90a24b-8371-4aea-a218-eb243e5c57a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985871548 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1985871548
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1601515234
Short name T148
Test name
Test status
Simulation time 6561832840 ps
CPU time 182.22 seconds
Started Jan 03 01:29:28 PM PST 24
Finished Jan 03 01:32:46 PM PST 24
Peak memory 270676 kb
Host smart-9ee77573-b00b-48a0-a918-1f11d66d4d15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1601515234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1601515234
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4222595457
Short name T179
Test name
Test status
Simulation time 1979596320 ps
CPU time 121.78 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:32:46 PM PST 24
Peak memory 256972 kb
Host smart-19f6fcf1-e964-47cd-bb6a-625ae1a46ca0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4222595457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4222595457
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2300443942
Short name T739
Test name
Test status
Simulation time 46293655475 ps
CPU time 2508.68 seconds
Started Jan 03 01:37:21 PM PST 24
Finished Jan 03 02:19:23 PM PST 24
Peak memory 283116 kb
Host smart-651f52a9-0f2e-459e-8ee8-85f9b92788da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300443942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2300443942
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2011712836
Short name T280
Test name
Test status
Simulation time 359908075548 ps
CPU time 2838.49 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 02:25:55 PM PST 24
Peak memory 298052 kb
Host smart-0da06961-89ea-43e5-8451-d1846286ae63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011712836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2011712836
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.115336898
Short name T162
Test name
Test status
Simulation time 3151599182 ps
CPU time 198.74 seconds
Started Jan 03 01:30:03 PM PST 24
Finished Jan 03 01:34:12 PM PST 24
Peak memory 266412 kb
Host smart-46581e19-2acf-4cad-b100-5de83e8d1a61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115336898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.115336898
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.593159382
Short name T45
Test name
Test status
Simulation time 206925004917 ps
CPU time 3232.74 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 02:30:17 PM PST 24
Peak memory 289328 kb
Host smart-c82f205d-45ff-4ea0-be1f-0f89543d8f6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593159382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.593159382
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3837951035
Short name T10
Test name
Test status
Simulation time 27837402023 ps
CPU time 1411.61 seconds
Started Jan 03 01:37:16 PM PST 24
Finished Jan 03 02:01:03 PM PST 24
Peak memory 265048 kb
Host smart-0ec4ece7-5f21-4294-a8be-d4bedb204fc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837951035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3837951035
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2321401714
Short name T87
Test name
Test status
Simulation time 25645861935 ps
CPU time 558.86 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 01:45:44 PM PST 24
Peak memory 248372 kb
Host smart-4f56acba-6a1e-4415-a343-174dfafaea78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321401714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2321401714
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.379122340
Short name T314
Test name
Test status
Simulation time 170957087511 ps
CPU time 4555.13 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 02:53:34 PM PST 24
Peak memory 338660 kb
Host smart-467a26fa-d5e3-4684-964a-258da3c0df81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379122340 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.379122340
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2626299792
Short name T183
Test name
Test status
Simulation time 48090265348 ps
CPU time 962.69 seconds
Started Jan 03 01:30:03 PM PST 24
Finished Jan 03 01:46:55 PM PST 24
Peak memory 265152 kb
Host smart-08e24e46-77f7-4791-b4e7-c16ac7c121fc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626299792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2626299792
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.844710817
Short name T223
Test name
Test status
Simulation time 55976082 ps
CPU time 4.29 seconds
Started Jan 03 01:36:04 PM PST 24
Finished Jan 03 01:36:18 PM PST 24
Peak memory 248784 kb
Host smart-0b22edb8-aff8-48b0-94df-1576c5d01069
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=844710817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.844710817
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.258196730
Short name T215
Test name
Test status
Simulation time 97813015 ps
CPU time 2.82 seconds
Started Jan 03 01:37:15 PM PST 24
Finished Jan 03 01:37:34 PM PST 24
Peak memory 248848 kb
Host smart-973d9b6c-51c7-4c6a-9cbf-153e12e274d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=258196730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.258196730
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2298070476
Short name T221
Test name
Test status
Simulation time 18635500 ps
CPU time 2.64 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:36:29 PM PST 24
Peak memory 248876 kb
Host smart-2cf9aab3-5e70-4771-85fb-86b96d8b4f35
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2298070476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2298070476
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3816388896
Short name T232
Test name
Test status
Simulation time 52906642 ps
CPU time 2.48 seconds
Started Jan 03 01:37:11 PM PST 24
Finished Jan 03 01:37:32 PM PST 24
Peak memory 248824 kb
Host smart-06a31ad7-4ebf-495b-a8d8-04d1a650e7ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3816388896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3816388896
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3661346870
Short name T62
Test name
Test status
Simulation time 13035034920 ps
CPU time 291.8 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 01:42:26 PM PST 24
Peak memory 256896 kb
Host smart-7e044911-2053-4795-9e95-ba06ebcf7ce1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661346870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3661346870
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3930642623
Short name T339
Test name
Test status
Simulation time 53670104753 ps
CPU time 537.14 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:44:47 PM PST 24
Peak memory 246536 kb
Host smart-90e55eaa-f842-4a0c-a329-ae0e41c6a8a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930642623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3930642623
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1980459885
Short name T369
Test name
Test status
Simulation time 127253707389 ps
CPU time 1976.82 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 02:10:27 PM PST 24
Peak memory 284848 kb
Host smart-2f4ea281-d5ef-4818-bde1-ff85c6db478b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980459885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1980459885
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1991383866
Short name T73
Test name
Test status
Simulation time 45255255099 ps
CPU time 925.44 seconds
Started Jan 03 01:36:58 PM PST 24
Finished Jan 03 01:52:45 PM PST 24
Peak memory 272348 kb
Host smart-5601bee8-4aab-4e31-ab31-a64c651513ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991383866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1991383866
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.717920161
Short name T301
Test name
Test status
Simulation time 10625584444 ps
CPU time 462.3 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:45:20 PM PST 24
Peak memory 247332 kb
Host smart-ecf5bbcd-5887-4683-8783-e2ff8fb27d9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717920161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.717920161
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1879025342
Short name T335
Test name
Test status
Simulation time 6373787119 ps
CPU time 127.26 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 01:39:49 PM PST 24
Peak memory 248648 kb
Host smart-50cbc536-a17f-4e21-9acd-f5cf9763b17e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879025342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1879025342
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.528241213
Short name T310
Test name
Test status
Simulation time 7383505141 ps
CPU time 428.17 seconds
Started Jan 03 01:37:30 PM PST 24
Finished Jan 03 01:44:49 PM PST 24
Peak memory 256876 kb
Host smart-fefdfb3d-70d4-4d61-82b8-eca5912068fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528241213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.528241213
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3059526683
Short name T144
Test name
Test status
Simulation time 7113717048 ps
CPU time 512.52 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:38:08 PM PST 24
Peak memory 265440 kb
Host smart-73bd78ef-9a71-429c-9281-361a7f040384
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059526683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3059526683
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2230946682
Short name T170
Test name
Test status
Simulation time 3388570318 ps
CPU time 101.92 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:31:16 PM PST 24
Peak memory 256712 kb
Host smart-23c064b3-46e3-4e37-bb3c-7dc85ca2dd5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2230946682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2230946682
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3917901748
Short name T181
Test name
Test status
Simulation time 2501171129 ps
CPU time 152.29 seconds
Started Jan 03 01:29:29 PM PST 24
Finished Jan 03 01:32:18 PM PST 24
Peak memory 266400 kb
Host smart-325ba872-2e30-414c-aee2-db5464c68720
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3917901748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3917901748
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2277467073
Short name T198
Test name
Test status
Simulation time 41027395 ps
CPU time 3.26 seconds
Started Jan 03 01:30:05 PM PST 24
Finished Jan 03 01:31:03 PM PST 24
Peak memory 236360 kb
Host smart-f770741b-1ddb-4704-b186-d7f9661fc255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2277467073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2277467073
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3040718881
Short name T156
Test name
Test status
Simulation time 36199930194 ps
CPU time 322.91 seconds
Started Jan 03 01:29:21 PM PST 24
Finished Jan 03 01:34:56 PM PST 24
Peak memory 265412 kb
Host smart-26b091c2-4818-413d-9cc7-fe01437faeb6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040718881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3040718881
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3614011182
Short name T749
Test name
Test status
Simulation time 14057449 ps
CPU time 1.28 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:26 PM PST 24
Peak memory 236476 kb
Host smart-9f21474f-8bde-4fa6-bc63-8b8b84c1e4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3614011182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3614011182
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1323337737
Short name T78
Test name
Test status
Simulation time 41866649127 ps
CPU time 606.46 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 01:47:37 PM PST 24
Peak memory 256804 kb
Host smart-d28fe2cd-d895-4f61-9c6b-dab108f20be0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323337737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1323337737
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1416235576
Short name T123
Test name
Test status
Simulation time 397995623014 ps
CPU time 5377.44 seconds
Started Jan 03 01:36:17 PM PST 24
Finished Jan 03 03:06:16 PM PST 24
Peak memory 322004 kb
Host smart-bfb8ef80-aa7c-41b5-93f2-60d0464c9c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416235576 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1416235576
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3671214745
Short name T315
Test name
Test status
Simulation time 774560412 ps
CPU time 55.12 seconds
Started Jan 03 01:36:17 PM PST 24
Finished Jan 03 01:37:35 PM PST 24
Peak memory 255184 kb
Host smart-d084074b-19da-4226-9d26-e576524dcd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36712
14745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3671214745
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1827900007
Short name T302
Test name
Test status
Simulation time 24578634540 ps
CPU time 1016.75 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:54:29 PM PST 24
Peak memory 281420 kb
Host smart-2113e13e-65a6-4e10-ac2d-e5a6efb041d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827900007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1827900007
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.336357873
Short name T288
Test name
Test status
Simulation time 1481469174 ps
CPU time 37.29 seconds
Started Jan 03 01:36:37 PM PST 24
Finished Jan 03 01:37:42 PM PST 24
Peak memory 254092 kb
Host smart-2e3accae-e4e3-4350-99d1-be8dd685ca41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
7873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.336357873
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3597483024
Short name T327
Test name
Test status
Simulation time 138507867723 ps
CPU time 4070.73 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 02:45:24 PM PST 24
Peak memory 315672 kb
Host smart-bb08a1b0-e40c-4bb7-bfd1-16ea3f563cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597483024 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3597483024
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.890691718
Short name T321
Test name
Test status
Simulation time 41632199180 ps
CPU time 2710.74 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 02:22:46 PM PST 24
Peak memory 304644 kb
Host smart-a4851601-fd96-495c-9f7e-c0e7e6340460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890691718 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.890691718
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3810349368
Short name T311
Test name
Test status
Simulation time 412349482 ps
CPU time 31.74 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:38:09 PM PST 24
Peak memory 255256 kb
Host smart-93df7001-d1b5-4eeb-a21f-a104388639ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38103
49368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3810349368
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2300075144
Short name T281
Test name
Test status
Simulation time 18401167423 ps
CPU time 1325.52 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 01:59:38 PM PST 24
Peak memory 288988 kb
Host smart-d1caf7d0-f4dd-4bc0-bcbc-9a7200e3469f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300075144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2300075144
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2180756605
Short name T67
Test name
Test status
Simulation time 17571113113 ps
CPU time 1171.37 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 01:57:06 PM PST 24
Peak memory 271040 kb
Host smart-37c8152c-83e6-428e-80e9-cdee2eafaf51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180756605 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2180756605
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1651752790
Short name T114
Test name
Test status
Simulation time 44849503099 ps
CPU time 2517.85 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 02:19:48 PM PST 24
Peak memory 288996 kb
Host smart-f3062949-f4d6-4660-9510-99ae38424b04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651752790 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1651752790
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2678849048
Short name T282
Test name
Test status
Simulation time 1228906314 ps
CPU time 66.96 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:37:00 PM PST 24
Peak memory 248596 kb
Host smart-4308f55f-48ec-4b0f-8d94-3b1b334ac879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26788
49048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2678849048
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2908519851
Short name T35
Test name
Test status
Simulation time 3263709578 ps
CPU time 48.25 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 01:38:29 PM PST 24
Peak memory 255736 kb
Host smart-4f48b8e4-8d00-496b-ab38-d42551c01de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
19851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2908519851
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.156300978
Short name T110
Test name
Test status
Simulation time 46689236626 ps
CPU time 2606.24 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 02:21:00 PM PST 24
Peak memory 288684 kb
Host smart-0f27fa9c-c61f-4fc3-beb0-62a0eede0405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156300978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.156300978
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.881403062
Short name T237
Test name
Test status
Simulation time 6482694804 ps
CPU time 143.57 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:39:59 PM PST 24
Peak memory 256284 kb
Host smart-e85f877b-c30e-4b03-9140-d003366cdb1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881403062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.881403062
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3599192555
Short name T202
Test name
Test status
Simulation time 1152109948 ps
CPU time 68.31 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:30:44 PM PST 24
Peak memory 236628 kb
Host smart-fb9dec65-a78e-45fa-abee-38640a479875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3599192555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3599192555
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3120947311
Short name T196
Test name
Test status
Simulation time 3531460225 ps
CPU time 64.75 seconds
Started Jan 03 01:28:55 PM PST 24
Finished Jan 03 01:30:04 PM PST 24
Peak memory 240440 kb
Host smart-beba8f11-e572-409e-8dd7-3cb1c83b77f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3120947311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3120947311
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.212354429
Short name T199
Test name
Test status
Simulation time 59547676 ps
CPU time 2.19 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 235592 kb
Host smart-3bc14676-a67d-4102-bc17-83c59ce92c92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=212354429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.212354429
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2770317699
Short name T197
Test name
Test status
Simulation time 1245236608 ps
CPU time 45.69 seconds
Started Jan 03 01:29:59 PM PST 24
Finished Jan 03 01:31:36 PM PST 24
Peak memory 239252 kb
Host smart-1e7b67d1-2416-4e7d-87ce-af3a677cc8f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2770317699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2770317699
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2007045811
Short name T166
Test name
Test status
Simulation time 90334868219 ps
CPU time 1244.19 seconds
Started Jan 03 01:30:18 PM PST 24
Finished Jan 03 01:52:01 PM PST 24
Peak memory 273476 kb
Host smart-a295165c-a9b9-4dfd-bfba-65f338d4112a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007045811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2007045811
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1658346804
Short name T193
Test name
Test status
Simulation time 184639291 ps
CPU time 2.05 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:40 PM PST 24
Peak memory 237020 kb
Host smart-4e17956e-b082-499a-abcf-71dfa2366fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1658346804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1658346804
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2869583960
Short name T186
Test name
Test status
Simulation time 22387196 ps
CPU time 2.63 seconds
Started Jan 03 01:29:00 PM PST 24
Finished Jan 03 01:29:09 PM PST 24
Peak memory 236800 kb
Host smart-fd6fd749-0af3-4777-9185-4001a4922a49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2869583960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2869583960
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3191847960
Short name T194
Test name
Test status
Simulation time 65431567 ps
CPU time 4.25 seconds
Started Jan 03 01:29:58 PM PST 24
Finished Jan 03 01:30:55 PM PST 24
Peak memory 236284 kb
Host smart-7caa36ca-f14c-489c-a976-a20605260f84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3191847960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3191847960
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.87529630
Short name T195
Test name
Test status
Simulation time 34847007 ps
CPU time 2.75 seconds
Started Jan 03 01:29:58 PM PST 24
Finished Jan 03 01:30:53 PM PST 24
Peak memory 236756 kb
Host smart-ae383e1d-f404-4ab1-a223-b60d12d3268d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=87529630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.87529630
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2982617103
Short name T201
Test name
Test status
Simulation time 220600597 ps
CPU time 21.6 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:59 PM PST 24
Peak memory 240324 kb
Host smart-d6f75b17-2c50-4ff3-92ac-44e1b5d0de3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2982617103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2982617103
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3109544897
Short name T184
Test name
Test status
Simulation time 1994412052 ps
CPU time 35.65 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:59 PM PST 24
Peak memory 239424 kb
Host smart-48699137-7e53-4d55-a528-6f5077af4481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3109544897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3109544897
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2368342419
Short name T203
Test name
Test status
Simulation time 348383449 ps
CPU time 28.44 seconds
Started Jan 03 01:29:11 PM PST 24
Finished Jan 03 01:29:41 PM PST 24
Peak memory 239504 kb
Host smart-05326bdb-772a-4465-af54-98fce74693a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2368342419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2368342419
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.823370454
Short name T207
Test name
Test status
Simulation time 15047628800 ps
CPU time 271.31 seconds
Started Jan 03 01:29:48 PM PST 24
Finished Jan 03 01:34:36 PM PST 24
Peak memory 240500 kb
Host smart-11d0e5c4-4597-4b89-bd5b-355de7cc9a57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=823370454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.823370454
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3821074818
Short name T743
Test name
Test status
Simulation time 71231689722 ps
CPU time 559.55 seconds
Started Jan 03 01:29:00 PM PST 24
Finished Jan 03 01:38:25 PM PST 24
Peak memory 236416 kb
Host smart-72d5b5b6-b1e3-4c22-84b7-c3ffebc3b1a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3821074818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3821074818
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.674976683
Short name T384
Test name
Test status
Simulation time 38866562 ps
CPU time 5.62 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:25 PM PST 24
Peak memory 240352 kb
Host smart-15ce57a1-3e14-453e-88fe-f3a174841a0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=674976683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.674976683
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1285741807
Short name T808
Test name
Test status
Simulation time 24938589 ps
CPU time 3.16 seconds
Started Jan 03 01:28:57 PM PST 24
Finished Jan 03 01:29:05 PM PST 24
Peak memory 238848 kb
Host smart-93c8f2a7-432d-41af-8a9d-bfd381c451e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285741807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1285741807
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2125383626
Short name T832
Test name
Test status
Simulation time 34943967 ps
CPU time 5.46 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:40 PM PST 24
Peak memory 236448 kb
Host smart-0f123eb2-4ab7-422c-9ec0-ae67e23070bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2125383626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2125383626
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1824838780
Short name T829
Test name
Test status
Simulation time 11868833 ps
CPU time 1.3 seconds
Started Jan 03 01:28:45 PM PST 24
Finished Jan 03 01:28:54 PM PST 24
Peak memory 236488 kb
Host smart-19ceebb2-a526-4a79-8daa-1bc6ebe884a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1824838780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1824838780
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2754661362
Short name T846
Test name
Test status
Simulation time 348906972 ps
CPU time 21.26 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:44 PM PST 24
Peak memory 243704 kb
Host smart-ab7846f8-e3b2-45e0-9d60-35b18438b4a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754661362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2754661362
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4048908
Short name T176
Test name
Test status
Simulation time 5876943482 ps
CPU time 168.83 seconds
Started Jan 03 01:28:57 PM PST 24
Finished Jan 03 01:31:51 PM PST 24
Peak memory 265372 kb
Host smart-007dce77-e201-454f-a6b6-aa2575b9dfcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4048908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.4048908
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4186054002
Short name T800
Test name
Test status
Simulation time 59541816 ps
CPU time 9.26 seconds
Started Jan 03 01:28:46 PM PST 24
Finished Jan 03 01:29:03 PM PST 24
Peak memory 248636 kb
Host smart-ee8d1fc1-945f-4190-b1a9-2998b0b60aff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4186054002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4186054002
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.564465876
Short name T773
Test name
Test status
Simulation time 8426057140 ps
CPU time 155.25 seconds
Started Jan 03 01:29:00 PM PST 24
Finished Jan 03 01:31:40 PM PST 24
Peak memory 236436 kb
Host smart-3b4a260a-3b50-4177-94ad-f727a0c38895
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=564465876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.564465876
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1147874653
Short name T332
Test name
Test status
Simulation time 16321872079 ps
CPU time 230.19 seconds
Started Jan 03 01:28:56 PM PST 24
Finished Jan 03 01:32:50 PM PST 24
Peak memory 236540 kb
Host smart-bb29573d-8669-4899-adde-010f99f51bea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1147874653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1147874653
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2862633657
Short name T777
Test name
Test status
Simulation time 161881846 ps
CPU time 4.79 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:26 PM PST 24
Peak memory 240320 kb
Host smart-e91c75a0-6b1b-430e-8b7e-59d96461d198
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2862633657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2862633657
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1326048459
Short name T29
Test name
Test status
Simulation time 57342679 ps
CPU time 6.74 seconds
Started Jan 03 01:28:56 PM PST 24
Finished Jan 03 01:29:07 PM PST 24
Peak memory 256824 kb
Host smart-a3fa37df-b9b2-4667-acef-54254ad430bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326048459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1326048459
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3627729538
Short name T762
Test name
Test status
Simulation time 129651915 ps
CPU time 9.59 seconds
Started Jan 03 01:29:11 PM PST 24
Finished Jan 03 01:29:24 PM PST 24
Peak memory 236448 kb
Host smart-cfd39185-1024-436b-8b0b-93ff3abaa2f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3627729538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3627729538
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3761671027
Short name T766
Test name
Test status
Simulation time 11880630 ps
CPU time 1.42 seconds
Started Jan 03 01:28:58 PM PST 24
Finished Jan 03 01:29:04 PM PST 24
Peak memory 236404 kb
Host smart-17969e9f-1b50-4c06-b587-3bfdac711342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3761671027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3761671027
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2567225208
Short name T833
Test name
Test status
Simulation time 1445116784 ps
CPU time 46.83 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:30:23 PM PST 24
Peak memory 244644 kb
Host smart-b9de79b3-adcd-4c3e-806e-ffb394d428b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2567225208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2567225208
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2619307687
Short name T161
Test name
Test status
Simulation time 4435670920 ps
CPU time 334.9 seconds
Started Jan 03 01:28:58 PM PST 24
Finished Jan 03 01:34:37 PM PST 24
Peak memory 265596 kb
Host smart-0b556711-dd87-4697-b28d-7febdb679447
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619307687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2619307687
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1603924746
Short name T191
Test name
Test status
Simulation time 57969650 ps
CPU time 4.96 seconds
Started Jan 03 01:28:56 PM PST 24
Finished Jan 03 01:29:06 PM PST 24
Peak memory 250676 kb
Host smart-89bb8ae0-b111-4d77-8527-4d3b9bb2644d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1603924746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1603924746
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1429057043
Short name T383
Test name
Test status
Simulation time 129793489 ps
CPU time 4.04 seconds
Started Jan 03 01:29:28 PM PST 24
Finished Jan 03 01:29:48 PM PST 24
Peak memory 240428 kb
Host smart-e5c875aa-3b19-46d3-9b58-cd2ab58999c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429057043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1429057043
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2557718434
Short name T801
Test name
Test status
Simulation time 33993315 ps
CPU time 5.28 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:43 PM PST 24
Peak memory 236464 kb
Host smart-13ac3382-ba57-414f-a28d-d75356fded09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2557718434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2557718434
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3325907715
Short name T779
Test name
Test status
Simulation time 44727458 ps
CPU time 1.42 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:29:41 PM PST 24
Peak memory 235604 kb
Host smart-6e0cc408-994c-4e73-ac79-4d95e73173f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3325907715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3325907715
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2284835612
Short name T764
Test name
Test status
Simulation time 4926383417 ps
CPU time 38.11 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:31:15 PM PST 24
Peak memory 248608 kb
Host smart-6d3520d1-cc99-42d6-b53e-68e0a6bd7c28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2284835612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2284835612
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1226759881
Short name T152
Test name
Test status
Simulation time 4211637493 ps
CPU time 158.07 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:32:12 PM PST 24
Peak memory 265460 kb
Host smart-12214948-5be4-4c8f-ac94-0f642e42922e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1226759881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1226759881
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1432594702
Short name T169
Test name
Test status
Simulation time 23868833435 ps
CPU time 280.12 seconds
Started Jan 03 01:29:03 PM PST 24
Finished Jan 03 01:33:48 PM PST 24
Peak memory 265556 kb
Host smart-16ef6217-b453-4478-bd65-ea5bfc8ce9bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432594702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1432594702
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4217676934
Short name T799
Test name
Test status
Simulation time 1192619292 ps
CPU time 12 seconds
Started Jan 03 01:29:51 PM PST 24
Finished Jan 03 01:30:31 PM PST 24
Peak memory 253508 kb
Host smart-a848c437-8f6e-468f-80d7-332d2d3bcad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4217676934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4217676934
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2882804965
Short name T824
Test name
Test status
Simulation time 39877363 ps
CPU time 7.29 seconds
Started Jan 03 01:29:29 PM PST 24
Finished Jan 03 01:29:52 PM PST 24
Peak memory 256776 kb
Host smart-86de650e-0e71-4c30-b8b6-89d0b34b1ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882804965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2882804965
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1420893066
Short name T845
Test name
Test status
Simulation time 164713171 ps
CPU time 9.52 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:30:53 PM PST 24
Peak memory 236336 kb
Host smart-d29309fb-4125-415a-9402-4bef77334295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1420893066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1420893066
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.432430740
Short name T380
Test name
Test status
Simulation time 12809345 ps
CPU time 1.28 seconds
Started Jan 03 01:29:53 PM PST 24
Finished Jan 03 01:30:33 PM PST 24
Peak memory 236464 kb
Host smart-0d37e5f2-6c46-428b-b973-20cd5d81c3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=432430740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.432430740
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3846499584
Short name T814
Test name
Test status
Simulation time 2812510179 ps
CPU time 23.14 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:57 PM PST 24
Peak memory 244736 kb
Host smart-5b27e702-cc5e-47b5-8867-9b851db3969c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3846499584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3846499584
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2352393626
Short name T776
Test name
Test status
Simulation time 73217770 ps
CPU time 9.13 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:36 PM PST 24
Peak memory 252004 kb
Host smart-d1681c10-60f1-45a8-afc7-b26b49358d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352393626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2352393626
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4154799527
Short name T787
Test name
Test status
Simulation time 52595954 ps
CPU time 5.39 seconds
Started Jan 03 01:30:03 PM PST 24
Finished Jan 03 01:30:59 PM PST 24
Peak memory 256884 kb
Host smart-29a74174-276c-4d8c-a033-350b46165dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154799527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4154799527
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2744531498
Short name T206
Test name
Test status
Simulation time 75599453 ps
CPU time 5.48 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:56 PM PST 24
Peak memory 236444 kb
Host smart-a951ce99-0ce5-4877-8d67-d65f4f21d187
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2744531498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2744531498
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1511876076
Short name T816
Test name
Test status
Simulation time 396203827 ps
CPU time 12.36 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:49 PM PST 24
Peak memory 244660 kb
Host smart-753c8291-4806-48ad-8b2f-bdacf870845f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1511876076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1511876076
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.619065862
Short name T751
Test name
Test status
Simulation time 271083393 ps
CPU time 8.18 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:31:01 PM PST 24
Peak memory 248584 kb
Host smart-f94e2eca-645e-4cff-ab6d-12964fb17990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=619065862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.619065862
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.637080406
Short name T778
Test name
Test status
Simulation time 21942122 ps
CPU time 4.39 seconds
Started Jan 03 01:30:07 PM PST 24
Finished Jan 03 01:31:04 PM PST 24
Peak memory 256916 kb
Host smart-589df680-ea21-4592-a4d4-8822ef7c0a13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637080406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.637080406
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3174634821
Short name T386
Test name
Test status
Simulation time 309344738 ps
CPU time 7.44 seconds
Started Jan 03 01:30:04 PM PST 24
Finished Jan 03 01:31:03 PM PST 24
Peak memory 240404 kb
Host smart-b01ead81-0d92-43b2-85fe-c931e27cfde1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3174634821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3174634821
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2212162383
Short name T774
Test name
Test status
Simulation time 12011525 ps
CPU time 1.51 seconds
Started Jan 03 01:30:10 PM PST 24
Finished Jan 03 01:31:05 PM PST 24
Peak memory 235512 kb
Host smart-3d51d94a-320f-41dc-94e3-9c0e2224de1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2212162383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2212162383
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4168847341
Short name T850
Test name
Test status
Simulation time 746490498 ps
CPU time 13.17 seconds
Started Jan 03 01:29:59 PM PST 24
Finished Jan 03 01:31:04 PM PST 24
Peak memory 244472 kb
Host smart-b980c63b-c539-4aef-bcd2-1f69b3e593d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4168847341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4168847341
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2174128546
Short name T788
Test name
Test status
Simulation time 1416346500 ps
CPU time 21.74 seconds
Started Jan 03 01:30:02 PM PST 24
Finished Jan 03 01:31:14 PM PST 24
Peak memory 248336 kb
Host smart-f1182a33-b33b-411e-8784-eb699acde1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2174128546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2174128546
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.623375072
Short name T746
Test name
Test status
Simulation time 271180175 ps
CPU time 7.06 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:44 PM PST 24
Peak memory 243332 kb
Host smart-2ec9e252-a316-4a0b-88a4-5ba43ed86bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623375072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.623375072
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1023895198
Short name T744
Test name
Test status
Simulation time 52869184 ps
CPU time 4.39 seconds
Started Jan 03 01:30:05 PM PST 24
Finished Jan 03 01:31:04 PM PST 24
Peak memory 235476 kb
Host smart-2d140632-0048-482b-b5e5-238dbec42133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1023895198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1023895198
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.154859413
Short name T273
Test name
Test status
Simulation time 17562820 ps
CPU time 1.37 seconds
Started Jan 03 01:30:14 PM PST 24
Finished Jan 03 01:31:11 PM PST 24
Peak memory 236496 kb
Host smart-dd3f209d-9870-40a1-af7a-56585ec28783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=154859413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.154859413
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.454055364
Short name T836
Test name
Test status
Simulation time 670713786 ps
CPU time 23.01 seconds
Started Jan 03 01:29:11 PM PST 24
Finished Jan 03 01:29:36 PM PST 24
Peak memory 244696 kb
Host smart-bf79384e-38b8-4794-a8c1-dd0de5d2f2ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=454055364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.454055364
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1576725631
Short name T174
Test name
Test status
Simulation time 4896966761 ps
CPU time 294.19 seconds
Started Jan 03 01:30:07 PM PST 24
Finished Jan 03 01:35:54 PM PST 24
Peak memory 265368 kb
Host smart-45d23891-04ae-4ff3-9e4f-73e70ea296cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1576725631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1576725631
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2959576110
Short name T790
Test name
Test status
Simulation time 1436473818 ps
CPU time 15.25 seconds
Started Jan 03 01:30:16 PM PST 24
Finished Jan 03 01:31:28 PM PST 24
Peak memory 248672 kb
Host smart-05ad039a-c4be-449c-b036-d4c3927b8810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2959576110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2959576110
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1318407970
Short name T803
Test name
Test status
Simulation time 241304682 ps
CPU time 6.25 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:22 PM PST 24
Peak memory 250500 kb
Host smart-9449f076-cc3a-4f1f-abb5-5b12f40ea5b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318407970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1318407970
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3166900083
Short name T210
Test name
Test status
Simulation time 368309233 ps
CPU time 8.04 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:46 PM PST 24
Peak memory 235468 kb
Host smart-c1b02ad5-5014-43f3-869d-2ce42869b217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3166900083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3166900083
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2697710121
Short name T843
Test name
Test status
Simulation time 14524336 ps
CPU time 1.23 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:36 PM PST 24
Peak memory 235580 kb
Host smart-0ee7bf18-53a1-4b25-81a4-06532fddd268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2697710121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2697710121
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3941517460
Short name T209
Test name
Test status
Simulation time 1062140252 ps
CPU time 37.42 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:56 PM PST 24
Peak memory 244628 kb
Host smart-772645ee-65ea-4f59-9f33-7fe9aeb24e4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3941517460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3941517460
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2034845011
Short name T31
Test name
Test status
Simulation time 1506360369 ps
CPU time 85.89 seconds
Started Jan 03 01:29:48 PM PST 24
Finished Jan 03 01:31:31 PM PST 24
Peak memory 265268 kb
Host smart-5e695d44-26cb-4da5-af24-48f701e73c14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2034845011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2034845011
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2092635304
Short name T783
Test name
Test status
Simulation time 1078669152 ps
CPU time 16.44 seconds
Started Jan 03 01:30:17 PM PST 24
Finished Jan 03 01:31:32 PM PST 24
Peak memory 247976 kb
Host smart-ab643151-f5b2-47d8-af71-d69b9bc11ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2092635304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2092635304
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.775870008
Short name T775
Test name
Test status
Simulation time 85181860 ps
CPU time 6.75 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:40 PM PST 24
Peak memory 251112 kb
Host smart-187066ea-9a29-46ad-a475-6d39d1ad3f53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775870008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.775870008
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2199326505
Short name T792
Test name
Test status
Simulation time 222290958 ps
CPU time 4.82 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:38 PM PST 24
Peak memory 235600 kb
Host smart-01d810f1-9150-45e6-8b77-ab26e6b7c0cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2199326505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2199326505
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3223205518
Short name T378
Test name
Test status
Simulation time 6330585 ps
CPU time 1.38 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 236480 kb
Host smart-0db68fed-e9c7-4d31-9a32-be5fbc370cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3223205518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3223205518
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3406953147
Short name T771
Test name
Test status
Simulation time 1439049110 ps
CPU time 17.56 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:56 PM PST 24
Peak memory 243788 kb
Host smart-c9f62f65-570d-417a-ba54-6b0ef4b163ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3406953147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3406953147
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2092543483
Short name T159
Test name
Test status
Simulation time 12547239888 ps
CPU time 584.7 seconds
Started Jan 03 01:29:21 PM PST 24
Finished Jan 03 01:39:18 PM PST 24
Peak memory 265336 kb
Host smart-a828cd0e-d6d4-4e64-bb59-0749f909241e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092543483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2092543483
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.495475989
Short name T809
Test name
Test status
Simulation time 1026141886 ps
CPU time 14.43 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:49 PM PST 24
Peak memory 248664 kb
Host smart-20c444d0-367c-41e5-9cd3-fe79e611c808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=495475989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.495475989
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2774426292
Short name T848
Test name
Test status
Simulation time 78846640 ps
CPU time 3.55 seconds
Started Jan 03 01:29:53 PM PST 24
Finished Jan 03 01:30:34 PM PST 24
Peak memory 240276 kb
Host smart-eb563490-d1a6-4089-b109-246d01767c63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774426292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2774426292
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2865986012
Short name T150
Test name
Test status
Simulation time 37599038 ps
CPU time 5.43 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:30:43 PM PST 24
Peak memory 240384 kb
Host smart-18a92eff-16ef-4988-b9f7-68b06af2d8b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2865986012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2865986012
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2281241787
Short name T802
Test name
Test status
Simulation time 13610219 ps
CPU time 1.43 seconds
Started Jan 03 01:30:04 PM PST 24
Finished Jan 03 01:30:57 PM PST 24
Peak memory 235536 kb
Host smart-4c35ef8e-fe5c-4e05-a724-a2891d9afc11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281241787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2281241787
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2644430143
Short name T825
Test name
Test status
Simulation time 333112707 ps
CPU time 22.14 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:31:13 PM PST 24
Peak memory 240328 kb
Host smart-a4c35c81-4615-4d51-a08a-f89072d5cbab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2644430143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2644430143
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3515578750
Short name T163
Test name
Test status
Simulation time 2846498962 ps
CPU time 331.59 seconds
Started Jan 03 01:29:51 PM PST 24
Finished Jan 03 01:35:51 PM PST 24
Peak memory 267772 kb
Host smart-540d70b6-20e9-4a7b-9ea3-64c059ff143d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515578750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3515578750
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3109873466
Short name T818
Test name
Test status
Simulation time 212313053 ps
CPU time 16.44 seconds
Started Jan 03 01:29:49 PM PST 24
Finished Jan 03 01:30:29 PM PST 24
Peak memory 248756 kb
Host smart-a4a2b856-e173-47c7-a170-9f98637488c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3109873466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3109873466
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.479209185
Short name T28
Test name
Test status
Simulation time 62930797 ps
CPU time 2.3 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:27 PM PST 24
Peak memory 236480 kb
Host smart-d5105975-b960-44a3-982b-2676258b2bba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=479209185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.479209185
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.516628126
Short name T784
Test name
Test status
Simulation time 89895112 ps
CPU time 3.71 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:37 PM PST 24
Peak memory 237560 kb
Host smart-a1c0ad53-6fb4-46c2-ba80-a2b28162e680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516628126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.516628126
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1070111332
Short name T742
Test name
Test status
Simulation time 73390859 ps
CPU time 3.17 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:54 PM PST 24
Peak memory 235612 kb
Host smart-4894c4be-dd3a-47f1-b7e5-03da4f5f8b0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1070111332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1070111332
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2381969044
Short name T847
Test name
Test status
Simulation time 12230212 ps
CPU time 1.58 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:52 PM PST 24
Peak memory 234592 kb
Host smart-aef48cd5-e958-4983-90fe-354d9ca0b146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2381969044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2381969044
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1662989228
Short name T178
Test name
Test status
Simulation time 210615675 ps
CPU time 21.65 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:30:58 PM PST 24
Peak memory 248584 kb
Host smart-a53061cd-47a5-40b5-b8d9-2652ef4959f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1662989228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1662989228
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2689518221
Short name T171
Test name
Test status
Simulation time 2167952342 ps
CPU time 220.19 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:34:18 PM PST 24
Peak memory 265348 kb
Host smart-f4f235fb-31a6-4967-9f6e-93446540d8d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2689518221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2689518221
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1688596023
Short name T185
Test name
Test status
Simulation time 4609889634 ps
CPU time 711.41 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:42:39 PM PST 24
Peak memory 265344 kb
Host smart-29185582-c347-4340-91f9-9e18a42204fd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688596023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1688596023
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.768552485
Short name T840
Test name
Test status
Simulation time 536878404 ps
CPU time 9.54 seconds
Started Jan 03 01:29:58 PM PST 24
Finished Jan 03 01:31:00 PM PST 24
Peak memory 253736 kb
Host smart-2302dd11-e2cb-4272-bb81-d3324b554eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=768552485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.768552485
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.252990251
Short name T807
Test name
Test status
Simulation time 119597884 ps
CPU time 6.39 seconds
Started Jan 03 01:30:13 PM PST 24
Finished Jan 03 01:31:15 PM PST 24
Peak memory 253300 kb
Host smart-5d5a470f-1629-4109-bef6-911219c1c0c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252990251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.252990251
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4105629717
Short name T812
Test name
Test status
Simulation time 185291063 ps
CPU time 4.77 seconds
Started Jan 03 01:30:14 PM PST 24
Finished Jan 03 01:31:15 PM PST 24
Peak memory 236484 kb
Host smart-0dd1c9dd-ecdd-40ff-86a4-11c02f36ddc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4105629717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4105629717
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2732950548
Short name T789
Test name
Test status
Simulation time 25073275 ps
CPU time 1.69 seconds
Started Jan 03 01:30:01 PM PST 24
Finished Jan 03 01:30:54 PM PST 24
Peak memory 236480 kb
Host smart-cb8c7a91-aff1-44e7-9dce-1a19bd645aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2732950548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2732950548
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2671223908
Short name T154
Test name
Test status
Simulation time 1024596329 ps
CPU time 35.71 seconds
Started Jan 03 01:30:07 PM PST 24
Finished Jan 03 01:31:36 PM PST 24
Peak memory 244664 kb
Host smart-790757f9-2f65-4049-9a4a-08a98722aa5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2671223908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2671223908
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.826122197
Short name T165
Test name
Test status
Simulation time 8236870806 ps
CPU time 329.7 seconds
Started Jan 03 01:30:03 PM PST 24
Finished Jan 03 01:36:22 PM PST 24
Peak memory 266240 kb
Host smart-872ca0ba-8ff5-4650-930f-f672fb3afad4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=826122197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.826122197
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3576636789
Short name T782
Test name
Test status
Simulation time 329686459 ps
CPU time 9.07 seconds
Started Jan 03 01:30:03 PM PST 24
Finished Jan 03 01:31:03 PM PST 24
Peak memory 253632 kb
Host smart-af4ea05a-966c-49b5-9e0c-8ae8b8346ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3576636789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3576636789
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2883086858
Short name T748
Test name
Test status
Simulation time 8211064860 ps
CPU time 151.81 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:31:53 PM PST 24
Peak memory 236544 kb
Host smart-618546ee-32ab-40fc-a51c-92b1e7532d22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2883086858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2883086858
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2869610387
Short name T205
Test name
Test status
Simulation time 15252856351 ps
CPU time 269.05 seconds
Started Jan 03 01:28:59 PM PST 24
Finished Jan 03 01:33:34 PM PST 24
Peak memory 236428 kb
Host smart-a4af6577-f276-48fc-80c3-7ea15ea0979e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2869610387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2869610387
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2596054741
Short name T785
Test name
Test status
Simulation time 105480847 ps
CPU time 5.52 seconds
Started Jan 03 01:29:03 PM PST 24
Finished Jan 03 01:29:14 PM PST 24
Peak memory 240388 kb
Host smart-7a747b78-fa5d-45b7-9583-6f5c6dce62c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2596054741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2596054741
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2296949700
Short name T786
Test name
Test status
Simulation time 67170675 ps
CPU time 6.99 seconds
Started Jan 03 01:29:46 PM PST 24
Finished Jan 03 01:30:08 PM PST 24
Peak memory 244180 kb
Host smart-c0fca459-5c98-4854-94b1-bbab07ce435d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296949700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2296949700
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1885036686
Short name T213
Test name
Test status
Simulation time 451421676 ps
CPU time 8 seconds
Started Jan 03 01:29:09 PM PST 24
Finished Jan 03 01:29:20 PM PST 24
Peak memory 236476 kb
Host smart-cda13ccd-8e35-46b4-863a-9a0e40d5357e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1885036686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1885036686
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4245624369
Short name T750
Test name
Test status
Simulation time 24857497 ps
CPU time 1.25 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:17 PM PST 24
Peak memory 235608 kb
Host smart-1faf969e-3bd1-459d-a883-35de1877dcec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4245624369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4245624369
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3292913309
Short name T834
Test name
Test status
Simulation time 182438425 ps
CPU time 19.43 seconds
Started Jan 03 01:28:54 PM PST 24
Finished Jan 03 01:29:18 PM PST 24
Peak memory 243708 kb
Host smart-721c49d6-4d55-4e96-9591-1d669b859375
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3292913309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3292913309
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3564666163
Short name T149
Test name
Test status
Simulation time 4857425355 ps
CPU time 295.86 seconds
Started Jan 03 01:28:54 PM PST 24
Finished Jan 03 01:33:55 PM PST 24
Peak memory 265300 kb
Host smart-ba14c5ca-fb72-4c3b-a51b-1e8705aaee6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3564666163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3564666163
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.873683435
Short name T805
Test name
Test status
Simulation time 57710555 ps
CPU time 7.71 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:28 PM PST 24
Peak memory 247828 kb
Host smart-34ecca70-2a9d-4e6a-9324-c6c133c700e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=873683435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.873683435
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.534692280
Short name T379
Test name
Test status
Simulation time 9860281 ps
CPU time 1.26 seconds
Started Jan 03 01:30:06 PM PST 24
Finished Jan 03 01:31:01 PM PST 24
Peak memory 236488 kb
Host smart-db226940-5705-4bc3-8108-35ca9cc23610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=534692280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.534692280
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1214681363
Short name T819
Test name
Test status
Simulation time 18977348 ps
CPU time 1.3 seconds
Started Jan 03 01:30:12 PM PST 24
Finished Jan 03 01:31:08 PM PST 24
Peak memory 236480 kb
Host smart-c4e69b98-580a-44e1-9709-fa24f038fe1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1214681363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1214681363
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2715099216
Short name T804
Test name
Test status
Simulation time 10049515 ps
CPU time 1.4 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:21 PM PST 24
Peak memory 235552 kb
Host smart-97c19562-3596-4247-9955-38b4feff4c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2715099216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2715099216
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1333876225
Short name T795
Test name
Test status
Simulation time 9612724 ps
CPU time 1.59 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:21 PM PST 24
Peak memory 235568 kb
Host smart-d263ad43-f216-4827-9e8b-427fc1ab91ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1333876225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1333876225
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1786244972
Short name T377
Test name
Test status
Simulation time 18967881 ps
CPU time 1.2 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:17 PM PST 24
Peak memory 236552 kb
Host smart-af966d4d-843f-4f31-a18f-1cdb0dff1e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1786244972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1786244972
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1800929797
Short name T747
Test name
Test status
Simulation time 11116338 ps
CPU time 1.25 seconds
Started Jan 03 01:29:10 PM PST 24
Finished Jan 03 01:29:14 PM PST 24
Peak memory 234604 kb
Host smart-45d0f6c4-e9fc-490f-835a-206b65cf75b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1800929797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1800929797
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1232630989
Short name T780
Test name
Test status
Simulation time 18230340 ps
CPU time 1.26 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:17 PM PST 24
Peak memory 236432 kb
Host smart-94899f03-c277-488c-81a6-619f326bb3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1232630989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1232630989
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.857165255
Short name T839
Test name
Test status
Simulation time 50317554 ps
CPU time 1.27 seconds
Started Jan 03 01:29:20 PM PST 24
Finished Jan 03 01:29:33 PM PST 24
Peak memory 236484 kb
Host smart-e88a6910-20f2-4fe9-b9c0-c8e88466ac80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=857165255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.857165255
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1755932146
Short name T761
Test name
Test status
Simulation time 8713031 ps
CPU time 1.54 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:29:41 PM PST 24
Peak memory 236452 kb
Host smart-ae55cea5-3a85-436c-a1df-dd194fd4cf74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1755932146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1755932146
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2090038320
Short name T821
Test name
Test status
Simulation time 8769796 ps
CPU time 1.59 seconds
Started Jan 03 01:29:21 PM PST 24
Finished Jan 03 01:29:34 PM PST 24
Peak memory 236480 kb
Host smart-f3ea2e67-9dec-40a9-a175-106f33e4e042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2090038320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2090038320
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2947988004
Short name T837
Test name
Test status
Simulation time 17106186230 ps
CPU time 321.15 seconds
Started Jan 03 01:29:31 PM PST 24
Finished Jan 03 01:35:10 PM PST 24
Peak memory 238872 kb
Host smart-fa538878-81e9-4187-8f9b-a47cf147dfa0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2947988004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2947988004
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3595818835
Short name T270
Test name
Test status
Simulation time 8815661229 ps
CPU time 463.6 seconds
Started Jan 03 01:29:50 PM PST 24
Finished Jan 03 01:37:59 PM PST 24
Peak memory 236496 kb
Host smart-fd508f10-add8-455f-8ee7-7a481d985f8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3595818835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3595818835
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1375017986
Short name T271
Test name
Test status
Simulation time 243621529 ps
CPU time 6.32 seconds
Started Jan 03 01:29:47 PM PST 24
Finished Jan 03 01:30:10 PM PST 24
Peak memory 240316 kb
Host smart-b62d4c39-63fd-42f9-850c-f7e1eec434ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1375017986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1375017986
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.346288923
Short name T33
Test name
Test status
Simulation time 136312327 ps
CPU time 6.55 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:29 PM PST 24
Peak memory 251816 kb
Host smart-be6e2fea-321f-4d92-b2a0-ff453395eb1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346288923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.346288923
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3605957721
Short name T830
Test name
Test status
Simulation time 52065210 ps
CPU time 4.4 seconds
Started Jan 03 01:29:51 PM PST 24
Finished Jan 03 01:30:24 PM PST 24
Peak memory 236484 kb
Host smart-b4232d90-31a9-4be9-8290-0b8cb48e3149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3605957721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3605957721
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1355576898
Short name T765
Test name
Test status
Simulation time 7101168 ps
CPU time 1.25 seconds
Started Jan 03 01:29:50 PM PST 24
Finished Jan 03 01:30:18 PM PST 24
Peak memory 236520 kb
Host smart-464049e1-449d-4489-baa3-d7620a97395b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1355576898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1355576898
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1611307912
Short name T849
Test name
Test status
Simulation time 4303621964 ps
CPU time 35.85 seconds
Started Jan 03 01:29:35 PM PST 24
Finished Jan 03 01:30:29 PM PST 24
Peak memory 248616 kb
Host smart-212e8501-bc68-47fe-a20d-a3380c4c8dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1611307912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1611307912
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.532432819
Short name T381
Test name
Test status
Simulation time 21384684828 ps
CPU time 477.36 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:37:34 PM PST 24
Peak memory 265484 kb
Host smart-e47698fb-77d0-402b-97eb-51492710048a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532432819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.532432819
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3807088309
Short name T791
Test name
Test status
Simulation time 191976760 ps
CPU time 13.18 seconds
Started Jan 03 01:29:19 PM PST 24
Finished Jan 03 01:29:44 PM PST 24
Peak memory 252816 kb
Host smart-10b2ddb3-d010-482a-af8a-4f51c601ab68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3807088309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3807088309
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.836680136
Short name T278
Test name
Test status
Simulation time 2595591191 ps
CPU time 85.52 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:31:01 PM PST 24
Peak memory 245216 kb
Host smart-c82b26e3-6e8e-424c-b36c-14894de727af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=836680136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.836680136
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2348032928
Short name T838
Test name
Test status
Simulation time 18806406 ps
CPU time 1.29 seconds
Started Jan 03 01:29:47 PM PST 24
Finished Jan 03 01:30:05 PM PST 24
Peak memory 234600 kb
Host smart-35cd1b47-495f-4655-8681-d5c3dd1543d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2348032928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2348032928
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1516577261
Short name T272
Test name
Test status
Simulation time 24654053 ps
CPU time 1.55 seconds
Started Jan 03 01:29:47 PM PST 24
Finished Jan 03 01:30:05 PM PST 24
Peak memory 236524 kb
Host smart-5510a7a4-2022-4812-98dd-92ba653e1ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1516577261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1516577261
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2001614640
Short name T820
Test name
Test status
Simulation time 10003632 ps
CPU time 1.25 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:23 PM PST 24
Peak memory 235484 kb
Host smart-3b163a65-08b8-4376-a186-7e47e57bc7c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2001614640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2001614640
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1257476401
Short name T770
Test name
Test status
Simulation time 9865611 ps
CPU time 1.49 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:39 PM PST 24
Peak memory 234636 kb
Host smart-4187d6c7-a019-46c7-9b56-1aa0f0bb6160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1257476401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1257476401
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2980201155
Short name T753
Test name
Test status
Simulation time 10514777 ps
CPU time 1.26 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:36 PM PST 24
Peak memory 236432 kb
Host smart-690ab447-1952-41d0-8f14-d421317874c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2980201155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2980201155
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1210858339
Short name T755
Test name
Test status
Simulation time 15018792 ps
CPU time 1.51 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:29:40 PM PST 24
Peak memory 235676 kb
Host smart-a793fb6c-0217-4312-b9a9-c115ef729b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1210858339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1210858339
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.703836507
Short name T794
Test name
Test status
Simulation time 22973510 ps
CPU time 1.33 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:37 PM PST 24
Peak memory 235716 kb
Host smart-3d3df9f9-e6f5-42b5-a57b-e00e059ded5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=703836507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.703836507
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2774327981
Short name T189
Test name
Test status
Simulation time 8174435 ps
CPU time 1.35 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:30:43 PM PST 24
Peak memory 235672 kb
Host smart-a618fca3-e04e-4e8c-affc-ecf578745e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2774327981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2774327981
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3066380372
Short name T768
Test name
Test status
Simulation time 20422404 ps
CPU time 1.39 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:29:40 PM PST 24
Peak memory 236376 kb
Host smart-31adfa0d-d395-48d2-a7a2-fde08c657917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3066380372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3066380372
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2366049628
Short name T754
Test name
Test status
Simulation time 1755466937 ps
CPU time 115.96 seconds
Started Jan 03 01:29:54 PM PST 24
Finished Jan 03 01:32:29 PM PST 24
Peak memory 236428 kb
Host smart-fd8a855d-dc21-448f-a9c3-df461d27859c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2366049628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2366049628
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4258719588
Short name T767
Test name
Test status
Simulation time 17129890142 ps
CPU time 253.45 seconds
Started Jan 03 01:29:33 PM PST 24
Finished Jan 03 01:34:05 PM PST 24
Peak memory 240484 kb
Host smart-70432ac0-3ff2-4465-9912-73a6be4341a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4258719588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4258719588
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2808422205
Short name T211
Test name
Test status
Simulation time 133508098 ps
CPU time 5.63 seconds
Started Jan 03 01:29:34 PM PST 24
Finished Jan 03 01:29:58 PM PST 24
Peak memory 240408 kb
Host smart-6366e6d9-1496-4edf-ab3c-7d17463f2b58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2808422205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2808422205
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2613346218
Short name T796
Test name
Test status
Simulation time 25085423 ps
CPU time 4.15 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:30:55 PM PST 24
Peak memory 240944 kb
Host smart-9fd85667-45d6-4fd9-87e8-a3e9be7f7955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613346218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2613346218
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1132353250
Short name T180
Test name
Test status
Simulation time 228651291 ps
CPU time 5.25 seconds
Started Jan 03 01:29:56 PM PST 24
Finished Jan 03 01:30:52 PM PST 24
Peak memory 235464 kb
Host smart-3e149551-976c-42d8-9128-96d940e51f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1132353250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1132353250
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.239748674
Short name T793
Test name
Test status
Simulation time 8422155 ps
CPU time 1.53 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:28 PM PST 24
Peak memory 235608 kb
Host smart-2cb5f094-0904-48e3-8dc8-2c8a63b7b640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=239748674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.239748674
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.633408426
Short name T823
Test name
Test status
Simulation time 169632728 ps
CPU time 24.75 seconds
Started Jan 03 01:29:58 PM PST 24
Finished Jan 03 01:31:15 PM PST 24
Peak memory 248532 kb
Host smart-b1d94cf3-0c64-4b36-9f9a-506728b00be8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=633408426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.633408426
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2650344800
Short name T187
Test name
Test status
Simulation time 1045144632 ps
CPU time 18.35 seconds
Started Jan 03 01:29:35 PM PST 24
Finished Jan 03 01:30:11 PM PST 24
Peak memory 248096 kb
Host smart-75ee8518-081c-4c98-ae87-43b85a8b2cec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2650344800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2650344800
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4116914948
Short name T826
Test name
Test status
Simulation time 7878224 ps
CPU time 1.46 seconds
Started Jan 03 01:29:50 PM PST 24
Finished Jan 03 01:30:19 PM PST 24
Peak memory 236460 kb
Host smart-8e1a218e-1c18-477c-afeb-c0edbc5a4541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4116914948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4116914948
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.4117452554
Short name T756
Test name
Test status
Simulation time 7478438 ps
CPU time 1.36 seconds
Started Jan 03 01:29:31 PM PST 24
Finished Jan 03 01:29:51 PM PST 24
Peak memory 236476 kb
Host smart-b57c4e69-7a8d-4ed7-90b9-9e17f847f2d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4117452554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4117452554
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3189466691
Short name T806
Test name
Test status
Simulation time 17651710 ps
CPU time 1.25 seconds
Started Jan 03 01:29:50 PM PST 24
Finished Jan 03 01:30:17 PM PST 24
Peak memory 236524 kb
Host smart-d8ad66e9-0e3b-4594-ae74-aa33f17f77c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3189466691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3189466691
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.832091836
Short name T842
Test name
Test status
Simulation time 8510662 ps
CPU time 1.31 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:29:38 PM PST 24
Peak memory 235692 kb
Host smart-c548001a-e94f-44eb-b29b-abbfd3eb7248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=832091836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.832091836
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3526398186
Short name T811
Test name
Test status
Simulation time 24493794 ps
CPU time 1.41 seconds
Started Jan 03 01:29:51 PM PST 24
Finished Jan 03 01:30:22 PM PST 24
Peak memory 235548 kb
Host smart-bf9b6ab2-6052-4067-a822-0f019dc9ba98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3526398186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3526398186
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.993717193
Short name T810
Test name
Test status
Simulation time 9437859 ps
CPU time 1.54 seconds
Started Jan 03 01:29:52 PM PST 24
Finished Jan 03 01:30:24 PM PST 24
Peak memory 235552 kb
Host smart-de8e4d3e-32e3-4cde-b82c-bd78fec35b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=993717193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.993717193
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4276787196
Short name T772
Test name
Test status
Simulation time 7565323 ps
CPU time 1.42 seconds
Started Jan 03 01:29:50 PM PST 24
Finished Jan 03 01:30:18 PM PST 24
Peak memory 235592 kb
Host smart-f94e3dfd-89a9-462f-b84b-c93d3aaf1e3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4276787196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4276787196
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.160833300
Short name T376
Test name
Test status
Simulation time 10878781 ps
CPU time 1.59 seconds
Started Jan 03 01:29:00 PM PST 24
Finished Jan 03 01:29:07 PM PST 24
Peak memory 236540 kb
Host smart-401705de-6a50-4924-97a5-566f9995392f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=160833300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.160833300
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1298205190
Short name T797
Test name
Test status
Simulation time 46068553 ps
CPU time 1.41 seconds
Started Jan 03 01:29:15 PM PST 24
Finished Jan 03 01:29:27 PM PST 24
Peak memory 235512 kb
Host smart-a4d0bd2a-ab1c-4e09-8326-ee678cd89e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1298205190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1298205190
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1833504756
Short name T828
Test name
Test status
Simulation time 135873317 ps
CPU time 7.28 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:25 PM PST 24
Peak memory 252028 kb
Host smart-d33fda87-54a7-4644-9d32-fa512d13b903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833504756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1833504756
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.875376151
Short name T798
Test name
Test status
Simulation time 115834398 ps
CPU time 4.81 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:40 PM PST 24
Peak memory 239388 kb
Host smart-8ba0a2ee-8075-4636-8642-db1aeae1b5ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=875376151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.875376151
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1656127592
Short name T32
Test name
Test status
Simulation time 9293365 ps
CPU time 1.47 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:17 PM PST 24
Peak memory 235712 kb
Host smart-a1a20609-0c15-4ade-9dcf-58f942712662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1656127592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1656127592
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3641018190
Short name T760
Test name
Test status
Simulation time 712208855 ps
CPU time 23.25 seconds
Started Jan 03 01:28:55 PM PST 24
Finished Jan 03 01:29:23 PM PST 24
Peak memory 244572 kb
Host smart-d9a7c5be-f07b-402f-83fa-c421d24cd584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3641018190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3641018190
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3363285145
Short name T173
Test name
Test status
Simulation time 1979130384 ps
CPU time 153.52 seconds
Started Jan 03 01:29:55 PM PST 24
Finished Jan 03 01:33:11 PM PST 24
Peak memory 257132 kb
Host smart-b4473a81-9e33-4dff-adb6-0753948c3fee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3363285145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3363285145
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1582692378
Short name T151
Test name
Test status
Simulation time 19204094820 ps
CPU time 320.29 seconds
Started Jan 03 01:30:01 PM PST 24
Finished Jan 03 01:36:13 PM PST 24
Peak memory 265320 kb
Host smart-243e6e67-5ffa-4ddb-82a8-dce9f8815612
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582692378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1582692378
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.972563546
Short name T835
Test name
Test status
Simulation time 53740732 ps
CPU time 4.51 seconds
Started Jan 03 01:29:57 PM PST 24
Finished Jan 03 01:30:54 PM PST 24
Peak memory 248684 kb
Host smart-158eebb1-e701-4ec0-a16a-ffeea81fc7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=972563546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.972563546
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1254167982
Short name T769
Test name
Test status
Simulation time 62305455 ps
CPU time 2.11 seconds
Started Jan 03 01:30:00 PM PST 24
Finished Jan 03 01:30:53 PM PST 24
Peak memory 237368 kb
Host smart-a44da19a-81a5-4022-93b5-2d1fd985c3ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1254167982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1254167982
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1173514061
Short name T817
Test name
Test status
Simulation time 77332695 ps
CPU time 7.3 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:29:46 PM PST 24
Peak memory 243000 kb
Host smart-f72c226a-73cb-4285-92c6-9a90527ccf3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173514061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1173514061
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1481842283
Short name T758
Test name
Test status
Simulation time 23668837 ps
CPU time 3.7 seconds
Started Jan 03 01:29:23 PM PST 24
Finished Jan 03 01:29:39 PM PST 24
Peak memory 236520 kb
Host smart-e638cce0-e7b3-45f1-9a58-06e2531fd4c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1481842283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1481842283
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3195987056
Short name T781
Test name
Test status
Simulation time 9114523 ps
CPU time 1.51 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:24 PM PST 24
Peak memory 235520 kb
Host smart-1e4550b2-eeee-441c-9823-ed931d74cd4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3195987056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3195987056
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.353169424
Short name T208
Test name
Test status
Simulation time 2105247662 ps
CPU time 38.84 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:30:16 PM PST 24
Peak memory 248568 kb
Host smart-53f5f5f3-0506-4016-a15e-2c5e134c0912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=353169424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.353169424
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3901407608
Short name T182
Test name
Test status
Simulation time 6429139809 ps
CPU time 227.25 seconds
Started Jan 03 01:28:59 PM PST 24
Finished Jan 03 01:32:51 PM PST 24
Peak memory 265388 kb
Host smart-6d3b0a28-921d-447f-be7c-ef7fd21c5aab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3901407608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3901407608
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3420156283
Short name T153
Test name
Test status
Simulation time 5448782892 ps
CPU time 663.85 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:40:38 PM PST 24
Peak memory 265396 kb
Host smart-8cc742c4-e10a-4086-a44d-c8465ac061da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420156283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3420156283
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.464474304
Short name T827
Test name
Test status
Simulation time 555730002 ps
CPU time 9.58 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:29 PM PST 24
Peak memory 248384 kb
Host smart-ddc1bbd4-fd6f-4878-b0cd-7ec86802f3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=464474304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.464474304
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1558782348
Short name T385
Test name
Test status
Simulation time 56676633 ps
CPU time 6.48 seconds
Started Jan 03 01:29:12 PM PST 24
Finished Jan 03 01:29:22 PM PST 24
Peak memory 248680 kb
Host smart-d9ed493a-a62b-460b-a8a0-ed15b3ad7447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558782348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1558782348
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2611069526
Short name T27
Test name
Test status
Simulation time 41617458 ps
CPU time 5.15 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:29:44 PM PST 24
Peak memory 235448 kb
Host smart-216a96a8-a159-4809-82b0-27e28f935b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2611069526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2611069526
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.699656332
Short name T759
Test name
Test status
Simulation time 15381571 ps
CPU time 1.5 seconds
Started Jan 03 01:29:46 PM PST 24
Finished Jan 03 01:30:03 PM PST 24
Peak memory 236520 kb
Host smart-c3892255-d413-4b40-b317-9e8056a0e302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=699656332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.699656332
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3481957482
Short name T815
Test name
Test status
Simulation time 340744516 ps
CPU time 18.95 seconds
Started Jan 03 01:29:03 PM PST 24
Finished Jan 03 01:29:28 PM PST 24
Peak memory 243620 kb
Host smart-84b55bd4-9a85-49cb-8a34-c8ba14dd2882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3481957482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3481957482
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2759956152
Short name T168
Test name
Test status
Simulation time 15793095763 ps
CPU time 566.91 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:39:05 PM PST 24
Peak memory 273060 kb
Host smart-09efac6a-15da-4971-9d97-e22967574727
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759956152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2759956152
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2748734310
Short name T757
Test name
Test status
Simulation time 54802038 ps
CPU time 6.71 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:28 PM PST 24
Peak memory 248568 kb
Host smart-4e793383-330b-42ea-86b3-d5a01cc540ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2748734310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2748734310
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2545826619
Short name T204
Test name
Test status
Simulation time 100642363 ps
CPU time 5.69 seconds
Started Jan 03 01:29:24 PM PST 24
Finished Jan 03 01:29:42 PM PST 24
Peak memory 242852 kb
Host smart-2af6d1bd-a3d6-4fa1-aef2-43ed68151487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545826619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2545826619
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.610713985
Short name T745
Test name
Test status
Simulation time 64614306 ps
CPU time 5.64 seconds
Started Jan 03 01:29:01 PM PST 24
Finished Jan 03 01:29:12 PM PST 24
Peak memory 238628 kb
Host smart-92013360-02ea-4d65-984d-ce88f698d9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=610713985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.610713985
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.836410345
Short name T831
Test name
Test status
Simulation time 11546274 ps
CPU time 1.29 seconds
Started Jan 03 01:29:03 PM PST 24
Finished Jan 03 01:29:10 PM PST 24
Peak memory 236488 kb
Host smart-e413726a-dc6d-464b-aacb-2a17965ec591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=836410345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.836410345
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1789755927
Short name T763
Test name
Test status
Simulation time 1119113839 ps
CPU time 21.78 seconds
Started Jan 03 01:29:26 PM PST 24
Finished Jan 03 01:30:01 PM PST 24
Peak memory 244504 kb
Host smart-a9d5beb3-5836-4522-acb7-be3b137aca68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1789755927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1789755927
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2128684256
Short name T167
Test name
Test status
Simulation time 2951580240 ps
CPU time 192.5 seconds
Started Jan 03 01:29:15 PM PST 24
Finished Jan 03 01:32:37 PM PST 24
Peak memory 257092 kb
Host smart-9f8e0090-cc48-461f-93e1-671f55231464
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2128684256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2128684256
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.319836773
Short name T175
Test name
Test status
Simulation time 7988178958 ps
CPU time 558.01 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:38:52 PM PST 24
Peak memory 265288 kb
Host smart-bd3c0da3-21a6-4187-b901-ab82cdbc000d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319836773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.319836773
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2019519822
Short name T190
Test name
Test status
Simulation time 89419228 ps
CPU time 12.63 seconds
Started Jan 03 01:29:04 PM PST 24
Finished Jan 03 01:29:21 PM PST 24
Peak memory 248300 kb
Host smart-408685c9-eb5b-41bd-86a9-2af3f923aab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2019519822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2019519822
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4229292922
Short name T200
Test name
Test status
Simulation time 56352193 ps
CPU time 2.64 seconds
Started Jan 03 01:29:49 PM PST 24
Finished Jan 03 01:30:14 PM PST 24
Peak memory 235504 kb
Host smart-bab45493-1f94-4d08-82a3-109825d6ceb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4229292922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4229292922
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.74455265
Short name T822
Test name
Test status
Simulation time 44910908 ps
CPU time 3.03 seconds
Started Jan 03 01:29:50 PM PST 24
Finished Jan 03 01:30:18 PM PST 24
Peak memory 238000 kb
Host smart-ec7497d7-13ec-4bcb-80f0-c7f4ef10ad4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74455265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.alert_handler_csr_mem_rw_with_rand_reset.74455265
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1969705395
Short name T382
Test name
Test status
Simulation time 92959369 ps
CPU time 8.31 seconds
Started Jan 03 01:29:14 PM PST 24
Finished Jan 03 01:29:30 PM PST 24
Peak memory 236440 kb
Host smart-64383198-eac4-45b4-8a72-49f8ae1e3fee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1969705395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1969705395
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3850252333
Short name T813
Test name
Test status
Simulation time 12885360 ps
CPU time 1.21 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:21 PM PST 24
Peak memory 236484 kb
Host smart-1777f130-574a-46bd-ae87-8c0c0bb68109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3850252333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3850252333
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3674231195
Short name T844
Test name
Test status
Simulation time 2751451875 ps
CPU time 50.55 seconds
Started Jan 03 01:29:25 PM PST 24
Finished Jan 03 01:30:28 PM PST 24
Peak memory 244668 kb
Host smart-20ae5fb7-76d6-429c-bc0d-5557130842d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3674231195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3674231195
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2528572423
Short name T177
Test name
Test status
Simulation time 1645949882 ps
CPU time 131.82 seconds
Started Jan 03 01:29:43 PM PST 24
Finished Jan 03 01:32:08 PM PST 24
Peak memory 256492 kb
Host smart-31029872-7d8a-4101-a953-8001dfce7987
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2528572423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2528572423
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3695532212
Short name T172
Test name
Test status
Simulation time 12692805747 ps
CPU time 469.22 seconds
Started Jan 03 01:29:22 PM PST 24
Finished Jan 03 01:37:23 PM PST 24
Peak memory 265420 kb
Host smart-2d5f423d-b0f0-4fe1-b000-b7c8f6f3a5aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695532212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3695532212
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3802496652
Short name T34
Test name
Test status
Simulation time 87511993 ps
CPU time 7.18 seconds
Started Jan 03 01:29:13 PM PST 24
Finished Jan 03 01:29:25 PM PST 24
Peak memory 240564 kb
Host smart-e1cf4577-3bc4-4867-9b28-46c5373bd056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3802496652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3802496652
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4182716620
Short name T841
Test name
Test status
Simulation time 158743227 ps
CPU time 18.62 seconds
Started Jan 03 01:29:15 PM PST 24
Finished Jan 03 01:29:43 PM PST 24
Peak memory 239252 kb
Host smart-dfb2c964-53e8-44d2-83a3-a619656a8bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4182716620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4182716620
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.798069480
Short name T484
Test name
Test status
Simulation time 63443024682 ps
CPU time 1008.86 seconds
Started Jan 03 01:36:06 PM PST 24
Finished Jan 03 01:53:06 PM PST 24
Peak memory 273324 kb
Host smart-d3c16c83-0c53-4447-9caf-420933185197
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798069480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.798069480
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1702237835
Short name T700
Test name
Test status
Simulation time 1136142946 ps
CPU time 26.59 seconds
Started Jan 03 01:36:09 PM PST 24
Finished Jan 03 01:36:50 PM PST 24
Peak memory 240404 kb
Host smart-fec9627f-8730-4b9d-9257-2e9e5d924c92
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1702237835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1702237835
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2259606746
Short name T304
Test name
Test status
Simulation time 12457680957 ps
CPU time 180.44 seconds
Started Jan 03 01:35:28 PM PST 24
Finished Jan 03 01:38:37 PM PST 24
Peak memory 256788 kb
Host smart-69f878ff-c047-4860-973b-b170a3f1b878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22596
06746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2259606746
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4153650415
Short name T640
Test name
Test status
Simulation time 2009008206 ps
CPU time 36.36 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:36:26 PM PST 24
Peak memory 255388 kb
Host smart-fdfe0b82-4efe-45dd-ab46-9c2cf25383ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41536
50415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4153650415
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.986923281
Short name T631
Test name
Test status
Simulation time 36682720130 ps
CPU time 1982.45 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 02:08:53 PM PST 24
Peak memory 272472 kb
Host smart-21ac01fd-a549-4a80-86f2-bfb1ea4c3c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986923281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.986923281
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.971822706
Short name T542
Test name
Test status
Simulation time 121438926228 ps
CPU time 1510.93 seconds
Started Jan 03 01:35:29 PM PST 24
Finished Jan 03 02:00:48 PM PST 24
Peak memory 289416 kb
Host smart-5c4e95d5-7e4a-402a-bffc-2eed4e024dfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971822706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.971822706
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3923672674
Short name T48
Test name
Test status
Simulation time 5431211643 ps
CPU time 209.96 seconds
Started Jan 03 01:35:29 PM PST 24
Finished Jan 03 01:39:08 PM PST 24
Peak memory 247520 kb
Host smart-7ed76f47-fa7f-487d-8492-897169743bba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923672674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3923672674
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2784949032
Short name T44
Test name
Test status
Simulation time 314112034 ps
CPU time 28.65 seconds
Started Jan 03 01:35:26 PM PST 24
Finished Jan 03 01:36:03 PM PST 24
Peak memory 255308 kb
Host smart-88e2d3e5-a349-4525-9084-67218b3acdff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
49032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2784949032
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.353735496
Short name T398
Test name
Test status
Simulation time 3078465901 ps
CPU time 41.91 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 01:37:05 PM PST 24
Peak memory 255196 kb
Host smart-b328bd27-c17c-4e4d-941e-dd8a611a5404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35373
5496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.353735496
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4235008999
Short name T47
Test name
Test status
Simulation time 2015200697 ps
CPU time 25.12 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 01:36:49 PM PST 24
Peak memory 269508 kb
Host smart-3462aef0-81cb-45c4-9f71-7b114d06f815
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4235008999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4235008999
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4249935075
Short name T326
Test name
Test status
Simulation time 3543445764 ps
CPU time 51.97 seconds
Started Jan 03 01:35:27 PM PST 24
Finished Jan 03 01:36:28 PM PST 24
Peak memory 255048 kb
Host smart-91274660-ffb5-413d-a440-289fa99b35c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42499
35075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4249935075
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1751319796
Short name T409
Test name
Test status
Simulation time 977373866 ps
CPU time 27.3 seconds
Started Jan 03 01:36:09 PM PST 24
Finished Jan 03 01:36:51 PM PST 24
Peak memory 256828 kb
Host smart-58e2826a-3f3c-4263-817f-fdd90c68485b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17513
19796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1751319796
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2798853643
Short name T80
Test name
Test status
Simulation time 22242618785 ps
CPU time 1681.17 seconds
Started Jan 03 01:35:41 PM PST 24
Finished Jan 03 02:03:44 PM PST 24
Peak memory 288888 kb
Host smart-ac85f256-5fe3-494f-88be-dd5dd5f2de48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798853643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2798853643
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1093924849
Short name T612
Test name
Test status
Simulation time 459471684462 ps
CPU time 3979.33 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 02:42:11 PM PST 24
Peak memory 338216 kb
Host smart-ccd6ba02-edcd-4cc0-a7dd-ea3bf10416da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093924849 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1093924849
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2585744699
Short name T225
Test name
Test status
Simulation time 110956078 ps
CPU time 3.04 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:35:53 PM PST 24
Peak memory 248892 kb
Host smart-862f7440-0fb9-4fad-ac23-645af8391085
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2585744699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2585744699
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1123507534
Short name T599
Test name
Test status
Simulation time 76146057950 ps
CPU time 1570.65 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 02:02:34 PM PST 24
Peak memory 288656 kb
Host smart-52160916-aec5-4b16-9deb-8c613d6a4407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123507534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1123507534
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.561072724
Short name T483
Test name
Test status
Simulation time 7873099495 ps
CPU time 133.28 seconds
Started Jan 03 01:35:46 PM PST 24
Finished Jan 03 01:38:07 PM PST 24
Peak memory 250464 kb
Host smart-3195339d-2370-4fd5-a5f1-0ea1d6d76dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56107
2724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.561072724
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4052028910
Short name T545
Test name
Test status
Simulation time 545368596 ps
CPU time 12.55 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:36:36 PM PST 24
Peak memory 253276 kb
Host smart-ae4ef1ab-3c67-45e9-a398-6a8b8736e41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
28910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4052028910
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1753522730
Short name T294
Test name
Test status
Simulation time 663202273137 ps
CPU time 3184.52 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 02:28:55 PM PST 24
Peak memory 288904 kb
Host smart-1c75560f-bbef-4e09-96e8-029f497a0253
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753522730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1753522730
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1243127593
Short name T524
Test name
Test status
Simulation time 94987854 ps
CPU time 4.12 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:35:57 PM PST 24
Peak memory 240340 kb
Host smart-d189de6a-f9f2-460f-ac29-53f4ca8f8991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12431
27593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1243127593
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3471611746
Short name T417
Test name
Test status
Simulation time 5326285434 ps
CPU time 43.43 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 01:37:07 PM PST 24
Peak memory 248232 kb
Host smart-da9b6831-7bde-4ec1-88c0-5d87315e8a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34716
11746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3471611746
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.751310229
Short name T15
Test name
Test status
Simulation time 1004349154 ps
CPU time 14.19 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:36:07 PM PST 24
Peak memory 269408 kb
Host smart-938f70b5-3591-47a9-9794-fb0c8cd66d7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=751310229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.751310229
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2140180340
Short name T132
Test name
Test status
Simulation time 543937625 ps
CPU time 14.55 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:36:07 PM PST 24
Peak memory 248608 kb
Host smart-56bda91e-ac4c-4a28-9626-ad6eb9b606d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21401
80340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2140180340
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3580964309
Short name T457
Test name
Test status
Simulation time 1830435431 ps
CPU time 27.95 seconds
Started Jan 03 01:36:09 PM PST 24
Finished Jan 03 01:36:51 PM PST 24
Peak memory 248668 kb
Host smart-d00665fd-d8c7-47d5-903a-1ead9fbc346c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
64309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3580964309
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3180979707
Short name T324
Test name
Test status
Simulation time 8709320854 ps
CPU time 492.79 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:44:03 PM PST 24
Peak memory 256776 kb
Host smart-a7f3282d-adad-41c8-94b2-b7bcd6d53e23
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180979707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3180979707
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2345232013
Short name T728
Test name
Test status
Simulation time 33675881530 ps
CPU time 2153.64 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 02:11:44 PM PST 24
Peak memory 286800 kb
Host smart-52af5fad-4f12-4483-8943-802f6023e29f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345232013 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2345232013
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.238080994
Short name T712
Test name
Test status
Simulation time 46075094263 ps
CPU time 2586.59 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 02:20:09 PM PST 24
Peak memory 289576 kb
Host smart-30f8b490-fa66-4247-85f8-76f4b4f2632b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238080994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.238080994
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3769894031
Short name T497
Test name
Test status
Simulation time 155864309 ps
CPU time 9.38 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:37:44 PM PST 24
Peak memory 240440 kb
Host smart-6f20109e-49d0-46ae-9376-58d49960c6b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3769894031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3769894031
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3069917286
Short name T471
Test name
Test status
Simulation time 1158691621 ps
CPU time 97.7 seconds
Started Jan 03 01:37:07 PM PST 24
Finished Jan 03 01:39:04 PM PST 24
Peak memory 249440 kb
Host smart-b008655e-8c9c-41d2-bf96-1807d0fb52bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30699
17286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3069917286
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.865883849
Short name T666
Test name
Test status
Simulation time 86877353 ps
CPU time 7.98 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:37:39 PM PST 24
Peak memory 251500 kb
Host smart-a7f73450-0235-4833-bb71-7d5b6e1fa519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86588
3849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.865883849
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2679879018
Short name T621
Test name
Test status
Simulation time 87004997443 ps
CPU time 1314.59 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:59:25 PM PST 24
Peak memory 265088 kb
Host smart-34298a75-102a-4072-ae7e-db78646be2bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679879018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2679879018
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1040101800
Short name T478
Test name
Test status
Simulation time 71956491320 ps
CPU time 1247.65 seconds
Started Jan 03 01:36:55 PM PST 24
Finished Jan 03 01:58:05 PM PST 24
Peak memory 273244 kb
Host smart-75bd8e6f-5b1f-4826-b5e2-ec3cfeb2cc05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040101800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1040101800
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1004165898
Short name T348
Test name
Test status
Simulation time 48609578664 ps
CPU time 479.03 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:45:29 PM PST 24
Peak memory 247516 kb
Host smart-6f7d20aa-8bf5-4d23-9f02-e9b96c6554a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004165898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1004165898
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.118057757
Short name T674
Test name
Test status
Simulation time 52121445 ps
CPU time 5.4 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:37:42 PM PST 24
Peak memory 240452 kb
Host smart-a090810a-0f9b-49a2-b90f-79f969f3e651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
7757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.118057757
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3498889236
Short name T670
Test name
Test status
Simulation time 421277135 ps
CPU time 34.36 seconds
Started Jan 03 01:36:52 PM PST 24
Finished Jan 03 01:37:50 PM PST 24
Peak memory 247036 kb
Host smart-80708f9c-8085-4be9-9830-cfad81114d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34988
89236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3498889236
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1546825993
Short name T142
Test name
Test status
Simulation time 270345510 ps
CPU time 16.14 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 01:37:17 PM PST 24
Peak memory 247128 kb
Host smart-3b36f8fc-0147-4368-8e3f-975867958226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15468
25993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1546825993
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2396986263
Short name T695
Test name
Test status
Simulation time 79500989 ps
CPU time 6.64 seconds
Started Jan 03 01:36:18 PM PST 24
Finished Jan 03 01:36:50 PM PST 24
Peak memory 240616 kb
Host smart-ac77f324-3285-4e8d-ac6b-102c4d562a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
86263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2396986263
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2261422441
Short name T320
Test name
Test status
Simulation time 247940578094 ps
CPU time 8408.63 seconds
Started Jan 03 01:37:16 PM PST 24
Finished Jan 03 03:57:41 PM PST 24
Peak memory 321976 kb
Host smart-11d359e0-745c-480b-9895-c95a73cc2120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261422441 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2261422441
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2428882887
Short name T711
Test name
Test status
Simulation time 73772603946 ps
CPU time 1425.31 seconds
Started Jan 03 01:37:15 PM PST 24
Finished Jan 03 02:01:17 PM PST 24
Peak memory 289428 kb
Host smart-db5232f2-3b0c-4638-91c7-d03b7aba7f55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428882887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2428882887
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2698147298
Short name T462
Test name
Test status
Simulation time 665671524 ps
CPU time 10.75 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:37:47 PM PST 24
Peak memory 240488 kb
Host smart-7ee4900d-d0ee-41da-8cca-39ce22444000
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2698147298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2698147298
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3826834855
Short name T20
Test name
Test status
Simulation time 752752523 ps
CPU time 17.44 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:37:49 PM PST 24
Peak memory 255216 kb
Host smart-1b933374-bb18-4561-89b1-1df0a43edfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38268
34855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3826834855
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1066361956
Short name T574
Test name
Test status
Simulation time 405973792 ps
CPU time 27.73 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 01:38:02 PM PST 24
Peak memory 254932 kb
Host smart-b3b639c3-57a3-43ce-af84-ed41cc883346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10663
61956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1066361956
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3759891250
Short name T53
Test name
Test status
Simulation time 18850205825 ps
CPU time 966.13 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:53:42 PM PST 24
Peak memory 272812 kb
Host smart-dff5d7b4-6dbe-460c-84b2-953ab0f4425b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759891250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3759891250
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3972752042
Short name T347
Test name
Test status
Simulation time 4023924294 ps
CPU time 163.81 seconds
Started Jan 03 01:37:16 PM PST 24
Finished Jan 03 01:40:15 PM PST 24
Peak memory 247504 kb
Host smart-5090c55e-6811-4a50-93d1-5bd64ad7944e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972752042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3972752042
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4232501684
Short name T443
Test name
Test status
Simulation time 478653850 ps
CPU time 27.56 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:38:00 PM PST 24
Peak memory 255152 kb
Host smart-a98b5654-043e-49e2-b8fa-a17bdf44e6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42325
01684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4232501684
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3033178089
Short name T551
Test name
Test status
Simulation time 1352551276 ps
CPU time 30.65 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:38:04 PM PST 24
Peak memory 254740 kb
Host smart-80de6616-ed55-4666-8fce-77dbc0722c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30331
78089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3033178089
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3604114585
Short name T313
Test name
Test status
Simulation time 2153203005 ps
CPU time 36.72 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:38:12 PM PST 24
Peak memory 254988 kb
Host smart-46874e80-0427-42be-86d3-98183c64bb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36041
14585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3604114585
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1684666768
Short name T623
Test name
Test status
Simulation time 335867483 ps
CPU time 36.71 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:38:10 PM PST 24
Peak memory 248620 kb
Host smart-7c2b03e5-dd1c-4d40-ae31-ea311ab74322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16846
66768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1684666768
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2771479653
Short name T235
Test name
Test status
Simulation time 120765253403 ps
CPU time 1709.68 seconds
Started Jan 03 01:35:46 PM PST 24
Finished Jan 03 02:04:24 PM PST 24
Peak memory 286416 kb
Host smart-3b817b39-fad5-4a77-97ae-ecdba86b10a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771479653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2771479653
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3545584592
Short name T128
Test name
Test status
Simulation time 41825148670 ps
CPU time 4266.66 seconds
Started Jan 03 01:36:14 PM PST 24
Finished Jan 03 02:47:36 PM PST 24
Peak memory 354600 kb
Host smart-dcd3ef6c-4c28-4f60-b428-53d09c711841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545584592 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3545584592
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.496351158
Short name T216
Test name
Test status
Simulation time 82418162 ps
CPU time 3.61 seconds
Started Jan 03 01:36:16 PM PST 24
Finished Jan 03 01:36:39 PM PST 24
Peak memory 248888 kb
Host smart-6067cd88-7454-49e9-b077-85848c11e4b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=496351158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.496351158
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2026009377
Short name T115
Test name
Test status
Simulation time 111565512030 ps
CPU time 1757.78 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 02:05:44 PM PST 24
Peak memory 272528 kb
Host smart-afe5b4a5-d4d7-4f5f-a3ad-3d3e52f3eaad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026009377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2026009377
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1949881647
Short name T571
Test name
Test status
Simulation time 1960019819 ps
CPU time 32.35 seconds
Started Jan 03 01:36:17 PM PST 24
Finished Jan 03 01:37:14 PM PST 24
Peak memory 240316 kb
Host smart-5baac6fb-ef0c-4172-8620-f5a54748b6e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1949881647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1949881647
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3631971568
Short name T585
Test name
Test status
Simulation time 5395923920 ps
CPU time 86.55 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 01:37:53 PM PST 24
Peak memory 255948 kb
Host smart-f3061b6d-8dc1-4808-b2ef-bb9ce02db82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
71568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3631971568
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4074541194
Short name T579
Test name
Test status
Simulation time 988372416 ps
CPU time 51.71 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 01:37:15 PM PST 24
Peak memory 254796 kb
Host smart-a5af0bc6-10b2-460e-a872-3d5c02af0429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40745
41194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4074541194
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3477509727
Short name T366
Test name
Test status
Simulation time 35576439537 ps
CPU time 726.38 seconds
Started Jan 03 01:36:17 PM PST 24
Finished Jan 03 01:48:48 PM PST 24
Peak memory 265132 kb
Host smart-7762c18e-27eb-4c21-92ad-fd5bc1f84e33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477509727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3477509727
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.697032376
Short name T607
Test name
Test status
Simulation time 51288985264 ps
CPU time 2267.82 seconds
Started Jan 03 01:36:16 PM PST 24
Finished Jan 03 02:14:24 PM PST 24
Peak memory 282664 kb
Host smart-1d5a36c6-943d-41bd-a4a7-70c97fcb6f8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697032376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.697032376
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1805409427
Short name T519
Test name
Test status
Simulation time 1457650957 ps
CPU time 49.8 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:37:13 PM PST 24
Peak memory 248496 kb
Host smart-d5e59b61-23ee-4896-8684-cf975d22232e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18054
09427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1805409427
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1732007421
Short name T646
Test name
Test status
Simulation time 4210632104 ps
CPU time 45.08 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:37:09 PM PST 24
Peak memory 255120 kb
Host smart-2421bc81-6bec-49ab-bd0e-302ede4bb6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17320
07421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1732007421
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1956958643
Short name T127
Test name
Test status
Simulation time 482802923 ps
CPU time 31.77 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:36:55 PM PST 24
Peak memory 254708 kb
Host smart-119e2da3-2004-4adb-8861-ff67cf10a923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19569
58643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1956958643
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3135955627
Short name T259
Test name
Test status
Simulation time 182514703 ps
CPU time 15.48 seconds
Started Jan 03 01:35:47 PM PST 24
Finished Jan 03 01:36:10 PM PST 24
Peak memory 248612 kb
Host smart-9d894a78-5d73-4658-aec7-5eca46cc145e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31359
55627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3135955627
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1354633808
Short name T529
Test name
Test status
Simulation time 130080906329 ps
CPU time 2025.73 seconds
Started Jan 03 01:36:19 PM PST 24
Finished Jan 03 02:10:31 PM PST 24
Peak memory 284228 kb
Host smart-b34b7aaf-f1ee-4537-991b-aae781da5dcd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354633808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1354633808
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4076294942
Short name T231
Test name
Test status
Simulation time 27312114 ps
CPU time 2.26 seconds
Started Jan 03 01:37:09 PM PST 24
Finished Jan 03 01:37:30 PM PST 24
Peak memory 248836 kb
Host smart-4917876e-d90d-4fcc-a8cb-1b98f5df5056
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4076294942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4076294942
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3428518402
Short name T256
Test name
Test status
Simulation time 357143689 ps
CPU time 6.6 seconds
Started Jan 03 01:37:08 PM PST 24
Finished Jan 03 01:37:34 PM PST 24
Peak memory 240356 kb
Host smart-2133f636-622b-45c6-9c6b-bd4d3b9eacb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3428518402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3428518402
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.684953527
Short name T391
Test name
Test status
Simulation time 1883550206 ps
CPU time 32.66 seconds
Started Jan 03 01:36:36 PM PST 24
Finished Jan 03 01:37:37 PM PST 24
Peak memory 255396 kb
Host smart-578ddd60-0b17-4507-82c1-715b05a96681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68495
3527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.684953527
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3890978024
Short name T247
Test name
Test status
Simulation time 1017300610 ps
CPU time 56.1 seconds
Started Jan 03 01:36:52 PM PST 24
Finished Jan 03 01:38:12 PM PST 24
Peak memory 255020 kb
Host smart-e6e0e5ab-9561-47fe-b4fb-2b08f833a6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38909
78024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3890978024
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.10328917
Short name T367
Test name
Test status
Simulation time 14220580460 ps
CPU time 1173.68 seconds
Started Jan 03 01:36:54 PM PST 24
Finished Jan 03 01:56:51 PM PST 24
Peak memory 281820 kb
Host smart-7be8ec19-eedf-43ce-93eb-eb94304516f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10328917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.10328917
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3982753048
Short name T83
Test name
Test status
Simulation time 38996081514 ps
CPU time 2125.85 seconds
Started Jan 03 01:36:19 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 283712 kb
Host smart-e5f47f0b-bde1-4024-8c7d-38ee25878264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982753048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3982753048
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1540128050
Short name T697
Test name
Test status
Simulation time 70249121897 ps
CPU time 172.02 seconds
Started Jan 03 01:36:18 PM PST 24
Finished Jan 03 01:39:35 PM PST 24
Peak memory 247416 kb
Host smart-f68364b4-8401-479a-9c00-53218fa5859e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540128050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1540128050
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1575271149
Short name T433
Test name
Test status
Simulation time 1078575086 ps
CPU time 17.06 seconds
Started Jan 03 01:36:22 PM PST 24
Finished Jan 03 01:37:04 PM PST 24
Peak memory 248648 kb
Host smart-1152bc9e-34a5-4c56-a698-2de2db370ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
71149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1575271149
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1179669386
Short name T404
Test name
Test status
Simulation time 1013815639 ps
CPU time 18.98 seconds
Started Jan 03 01:36:32 PM PST 24
Finished Jan 03 01:37:19 PM PST 24
Peak memory 254564 kb
Host smart-b46ba3c4-ff19-4de8-a8dd-7eac9ccd61f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11796
69386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1179669386
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.64214981
Short name T407
Test name
Test status
Simulation time 1628610740 ps
CPU time 30.01 seconds
Started Jan 03 01:36:15 PM PST 24
Finished Jan 03 01:37:00 PM PST 24
Peak memory 255184 kb
Host smart-effe1346-1895-423a-a635-98ad72778b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64214
981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.64214981
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2714514257
Short name T509
Test name
Test status
Simulation time 123460205046 ps
CPU time 2010.86 seconds
Started Jan 03 01:37:09 PM PST 24
Finished Jan 03 02:10:59 PM PST 24
Peak memory 281524 kb
Host smart-d3e5ea6c-8bb4-4459-bdf7-651770d88ded
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714514257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2714514257
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2383049720
Short name T688
Test name
Test status
Simulation time 244966293498 ps
CPU time 4155.19 seconds
Started Jan 03 01:36:33 PM PST 24
Finished Jan 03 02:46:17 PM PST 24
Peak memory 299160 kb
Host smart-c5cca608-22d4-4d18-8867-a35252475cc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383049720 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2383049720
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1195194877
Short name T230
Test name
Test status
Simulation time 61292430 ps
CPU time 3.28 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 01:37:05 PM PST 24
Peak memory 248836 kb
Host smart-0673fde1-53db-4ea3-8e79-4c9d5aebc50b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1195194877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1195194877
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2657836288
Short name T718
Test name
Test status
Simulation time 70264727916 ps
CPU time 1112.41 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 01:56:03 PM PST 24
Peak memory 289180 kb
Host smart-68880c8a-9975-42fa-b646-2a77c94b92d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657836288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2657836288
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3578321112
Short name T252
Test name
Test status
Simulation time 172843043 ps
CPU time 9.91 seconds
Started Jan 03 01:37:11 PM PST 24
Finished Jan 03 01:37:39 PM PST 24
Peak memory 240436 kb
Host smart-33cd3ffe-87e1-4d05-b0e0-a784f80bbe02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3578321112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3578321112
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.576954905
Short name T442
Test name
Test status
Simulation time 7819018887 ps
CPU time 165.52 seconds
Started Jan 03 01:36:57 PM PST 24
Finished Jan 03 01:40:03 PM PST 24
Peak memory 256824 kb
Host smart-c3e1649d-d639-431d-bc55-9f1beb583b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57695
4905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.576954905
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.245621787
Short name T566
Test name
Test status
Simulation time 368178749 ps
CPU time 7.84 seconds
Started Jan 03 01:36:36 PM PST 24
Finished Jan 03 01:37:12 PM PST 24
Peak memory 252576 kb
Host smart-09424187-9055-4c02-95a1-f12d8c7500bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
1787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.245621787
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.228330975
Short name T244
Test name
Test status
Simulation time 134168743303 ps
CPU time 2273.18 seconds
Started Jan 03 01:36:36 PM PST 24
Finished Jan 03 02:14:58 PM PST 24
Peak memory 289052 kb
Host smart-5fc037d8-81ee-4051-84a2-473a06902b2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228330975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.228330975
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.850806019
Short name T263
Test name
Test status
Simulation time 5924080020 ps
CPU time 260.2 seconds
Started Jan 03 01:36:57 PM PST 24
Finished Jan 03 01:41:40 PM PST 24
Peak memory 247244 kb
Host smart-2d11a44d-6deb-4151-b604-d5fc95f3a9ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850806019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.850806019
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3097251675
Short name T632
Test name
Test status
Simulation time 580166068 ps
CPU time 31.91 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 01:38:09 PM PST 24
Peak memory 248508 kb
Host smart-279fd674-b8cd-4dac-9892-59feee071ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30972
51675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3097251675
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1501618307
Short name T138
Test name
Test status
Simulation time 4632571434 ps
CPU time 52.53 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 01:38:28 PM PST 24
Peak memory 255380 kb
Host smart-f1300618-b10b-464a-bc3d-14fbba38483a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
18307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1501618307
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1873725719
Short name T54
Test name
Test status
Simulation time 354237330 ps
CPU time 35.17 seconds
Started Jan 03 01:37:15 PM PST 24
Finished Jan 03 01:38:06 PM PST 24
Peak memory 248664 kb
Host smart-147a07ab-be58-4c81-9660-12e782b5a058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18737
25719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1873725719
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2605695094
Short name T23
Test name
Test status
Simulation time 16778136729 ps
CPU time 1577.31 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 02:03:47 PM PST 24
Peak memory 289336 kb
Host smart-000855aa-8e57-4e00-9120-709e9aacfd7c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605695094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2605695094
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3763208822
Short name T117
Test name
Test status
Simulation time 26672830210 ps
CPU time 1800.68 seconds
Started Jan 03 01:37:10 PM PST 24
Finished Jan 03 02:07:29 PM PST 24
Peak memory 283388 kb
Host smart-fdb77336-2e2f-4ae6-8d18-2838901d0446
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763208822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3763208822
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2627247862
Short name T268
Test name
Test status
Simulation time 1006957650 ps
CPU time 24.36 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:37:55 PM PST 24
Peak memory 240388 kb
Host smart-02efe7d7-3aee-4d10-8ed6-00e4167dc65b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2627247862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2627247862
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2706998620
Short name T283
Test name
Test status
Simulation time 39398769430 ps
CPU time 130.56 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 01:39:13 PM PST 24
Peak memory 248764 kb
Host smart-4d0cee78-78e4-4af2-97d0-913f02231a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
98620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2706998620
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1053854414
Short name T3
Test name
Test status
Simulation time 565693431 ps
CPU time 16.87 seconds
Started Jan 03 01:36:32 PM PST 24
Finished Jan 03 01:37:17 PM PST 24
Peak memory 253660 kb
Host smart-fb7b96a3-dbd6-4a8e-8334-5c5ed2d6b914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10538
54414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1053854414
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3957523298
Short name T364
Test name
Test status
Simulation time 21231428684 ps
CPU time 1411.96 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 02:01:03 PM PST 24
Peak memory 288820 kb
Host smart-be163e30-02b5-429a-a269-f65f858869a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957523298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3957523298
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2900582631
Short name T584
Test name
Test status
Simulation time 33078114938 ps
CPU time 1945.75 seconds
Started Jan 03 01:36:38 PM PST 24
Finished Jan 03 02:09:33 PM PST 24
Peak memory 282096 kb
Host smart-ccfffa5b-25f2-43e7-8944-243e8bff5b2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900582631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2900582631
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2501862573
Short name T615
Test name
Test status
Simulation time 25161460537 ps
CPU time 168.41 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:40:18 PM PST 24
Peak memory 247536 kb
Host smart-96e1e6fc-7686-4b25-bb5c-2035e320352d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501862573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2501862573
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2521463463
Short name T681
Test name
Test status
Simulation time 203692830 ps
CPU time 13.21 seconds
Started Jan 03 01:36:35 PM PST 24
Finished Jan 03 01:37:16 PM PST 24
Peak memory 252156 kb
Host smart-4634d20a-095f-47fc-ab2a-889c8677a8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25214
63463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2521463463
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3775744934
Short name T722
Test name
Test status
Simulation time 430640283 ps
CPU time 31.8 seconds
Started Jan 03 01:36:35 PM PST 24
Finished Jan 03 01:37:35 PM PST 24
Peak memory 255388 kb
Host smart-581a8825-f7ed-4f57-b3cf-b3715153992a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37757
44934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3775744934
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.798043149
Short name T633
Test name
Test status
Simulation time 348215688 ps
CPU time 24.49 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:37:54 PM PST 24
Peak memory 255596 kb
Host smart-91d09ca9-e2db-41a5-ab19-e9f08349aae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79804
3149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.798043149
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2221348256
Short name T405
Test name
Test status
Simulation time 1690701124 ps
CPU time 29.69 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:38:00 PM PST 24
Peak memory 248624 kb
Host smart-4c031fbf-7500-4dd2-810d-fbc5ed07ece3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22213
48256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2221348256
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2198540149
Short name T717
Test name
Test status
Simulation time 211609665016 ps
CPU time 5353.47 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 03:06:16 PM PST 24
Peak memory 322156 kb
Host smart-94356da5-123c-4955-8f66-eb2bd7a07397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198540149 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2198540149
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3088866565
Short name T219
Test name
Test status
Simulation time 31370842 ps
CPU time 2.56 seconds
Started Jan 03 01:37:11 PM PST 24
Finished Jan 03 01:37:32 PM PST 24
Peak memory 248800 kb
Host smart-bec844a2-07b0-4243-bd1b-18542fd37bbd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3088866565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3088866565
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1735372360
Short name T257
Test name
Test status
Simulation time 303108148650 ps
CPU time 2340.97 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 02:16:31 PM PST 24
Peak memory 289204 kb
Host smart-ad122950-5c0a-4648-9ee5-5462721eca76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735372360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1735372360
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3228672217
Short name T424
Test name
Test status
Simulation time 432954030 ps
CPU time 20.5 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 01:37:23 PM PST 24
Peak memory 240364 kb
Host smart-128a21a0-f6d4-4f76-9d98-ca7cf1f1f903
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3228672217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3228672217
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.818729746
Short name T85
Test name
Test status
Simulation time 155297847 ps
CPU time 15.42 seconds
Started Jan 03 01:37:10 PM PST 24
Finished Jan 03 01:37:44 PM PST 24
Peak memory 255360 kb
Host smart-9f03df94-ade8-43eb-8d4c-b971a48f625c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81872
9746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.818729746
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.550708631
Short name T97
Test name
Test status
Simulation time 367530181 ps
CPU time 20.83 seconds
Started Jan 03 01:37:11 PM PST 24
Finished Jan 03 01:37:50 PM PST 24
Peak memory 253544 kb
Host smart-0609059b-2b91-4f5f-9eda-a8b2b51809f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55070
8631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.550708631
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3469796830
Short name T663
Test name
Test status
Simulation time 129869198592 ps
CPU time 2001.7 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 02:10:52 PM PST 24
Peak memory 283768 kb
Host smart-9b9b7b3a-cf9e-4cf1-8639-4b866a5d1f15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469796830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3469796830
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3732018594
Short name T343
Test name
Test status
Simulation time 11544447716 ps
CPU time 405.02 seconds
Started Jan 03 01:36:36 PM PST 24
Finished Jan 03 01:43:49 PM PST 24
Peak memory 247572 kb
Host smart-9be7c34b-9660-4fda-b29e-c7011d72a162
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732018594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3732018594
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.753842477
Short name T630
Test name
Test status
Simulation time 700453008 ps
CPU time 19.56 seconds
Started Jan 03 01:36:31 PM PST 24
Finished Jan 03 01:37:19 PM PST 24
Peak memory 253976 kb
Host smart-e1fc57fd-393d-4f57-82ed-e80dc10a2c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75384
2477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.753842477
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3943517463
Short name T725
Test name
Test status
Simulation time 584257013 ps
CPU time 16.9 seconds
Started Jan 03 01:37:11 PM PST 24
Finished Jan 03 01:37:47 PM PST 24
Peak memory 250888 kb
Host smart-0e3004f1-6499-4402-8af0-c73bbac12f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39435
17463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3943517463
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2425726869
Short name T719
Test name
Test status
Simulation time 1378093766 ps
CPU time 49.16 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:38:19 PM PST 24
Peak memory 246968 kb
Host smart-b45ac6c2-3dbf-4415-ab55-c02d0a628c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24257
26869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2425726869
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3239737316
Short name T449
Test name
Test status
Simulation time 6564023236 ps
CPU time 25.57 seconds
Started Jan 03 01:37:11 PM PST 24
Finished Jan 03 01:37:55 PM PST 24
Peak memory 255184 kb
Host smart-5f7f15dd-3b55-43e7-bc94-7fc7537da461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32397
37316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3239737316
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2042888472
Short name T617
Test name
Test status
Simulation time 14713021098 ps
CPU time 1411.45 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 02:01:02 PM PST 24
Peak memory 288636 kb
Host smart-07a394a6-e266-4e35-8447-5dd27c80b8c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042888472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2042888472
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3036905227
Short name T724
Test name
Test status
Simulation time 75339815148 ps
CPU time 2549.11 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 02:19:31 PM PST 24
Peak memory 289784 kb
Host smart-3f7cd10b-c06a-4eda-830c-aa0e25f04e19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036905227 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3036905227
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3680621640
Short name T226
Test name
Test status
Simulation time 18362407 ps
CPU time 2.53 seconds
Started Jan 03 01:36:54 PM PST 24
Finished Jan 03 01:37:20 PM PST 24
Peak memory 248816 kb
Host smart-1ede7910-1ca2-41ef-8560-5018f5eaa437
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3680621640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3680621640
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1857260854
Short name T635
Test name
Test status
Simulation time 35969367255 ps
CPU time 1140.6 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:56:31 PM PST 24
Peak memory 265020 kb
Host smart-d6e0330b-a1d6-40ed-9af8-2111417db3d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857260854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1857260854
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1670718689
Short name T505
Test name
Test status
Simulation time 2580585255 ps
CPU time 52.71 seconds
Started Jan 03 01:36:55 PM PST 24
Finished Jan 03 01:38:10 PM PST 24
Peak memory 240516 kb
Host smart-7b8c1af6-bb3e-4a20-a1f6-04776ac0dcb2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1670718689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1670718689
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1302149534
Short name T463
Test name
Test status
Simulation time 1194106534 ps
CPU time 17.97 seconds
Started Jan 03 01:36:34 PM PST 24
Finished Jan 03 01:37:20 PM PST 24
Peak memory 248376 kb
Host smart-61c8dd84-601b-4aaf-b33d-49c52887983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021
49534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1302149534
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2771550103
Short name T429
Test name
Test status
Simulation time 95600925 ps
CPU time 4.52 seconds
Started Jan 03 01:36:38 PM PST 24
Finished Jan 03 01:37:11 PM PST 24
Peak memory 250260 kb
Host smart-38cd1aa0-d170-42fd-8e80-e3cf9281e4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
50103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2771550103
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3595062267
Short name T613
Test name
Test status
Simulation time 89846668580 ps
CPU time 1545.68 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 02:03:16 PM PST 24
Peak memory 270128 kb
Host smart-74d308c5-5610-492d-831e-26feb0729b1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595062267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3595062267
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.211023916
Short name T134
Test name
Test status
Simulation time 59879586811 ps
CPU time 458.67 seconds
Started Jan 03 01:36:37 PM PST 24
Finished Jan 03 01:44:44 PM PST 24
Peak memory 247476 kb
Host smart-1b542ca9-dae4-45b3-85d8-56b8e399e97d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211023916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.211023916
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1169709409
Short name T690
Test name
Test status
Simulation time 3188590916 ps
CPU time 47.97 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:38:19 PM PST 24
Peak memory 248704 kb
Host smart-7903bdb6-9c52-4094-aaaa-3c143a60a2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11697
09409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1169709409
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3079030326
Short name T620
Test name
Test status
Simulation time 272860551 ps
CPU time 26.47 seconds
Started Jan 03 01:36:36 PM PST 24
Finished Jan 03 01:37:31 PM PST 24
Peak memory 246988 kb
Host smart-8c7a717c-1237-4798-8b0d-c64f7d0fcdfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30790
30326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3079030326
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3680564402
Short name T648
Test name
Test status
Simulation time 779283212 ps
CPU time 44.33 seconds
Started Jan 03 01:36:37 PM PST 24
Finished Jan 03 01:37:49 PM PST 24
Peak memory 255528 kb
Host smart-1766c9ce-75c3-45cb-83ae-339ebc3d78db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36805
64402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3680564402
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.25614014
Short name T431
Test name
Test status
Simulation time 481863448 ps
CPU time 21.46 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:37:54 PM PST 24
Peak memory 248664 kb
Host smart-7c1ecb9e-e8b7-45c9-b38b-8c859afeca6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25614
014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.25614014
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2754353448
Short name T652
Test name
Test status
Simulation time 29456062098 ps
CPU time 1708.22 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 02:05:59 PM PST 24
Peak memory 282856 kb
Host smart-ceaffa76-4eea-47e9-93bf-5ad17bbd4044
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754353448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2754353448
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1528537151
Short name T220
Test name
Test status
Simulation time 151834938 ps
CPU time 3.68 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:37:40 PM PST 24
Peak memory 248840 kb
Host smart-ee64d325-3d99-4f67-b5c6-61a3d95886d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1528537151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1528537151
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3908564860
Short name T120
Test name
Test status
Simulation time 177191327884 ps
CPU time 2385.27 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 02:17:20 PM PST 24
Peak memory 289588 kb
Host smart-00e47738-ae7c-4e6f-83d4-f429b80cf85f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908564860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3908564860
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2297487917
Short name T501
Test name
Test status
Simulation time 6105453971 ps
CPU time 48.23 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:38:19 PM PST 24
Peak memory 248632 kb
Host smart-32e00e7e-fd8c-401c-a550-a218ef361356
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2297487917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2297487917
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.398496406
Short name T598
Test name
Test status
Simulation time 1491042864 ps
CPU time 123.35 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:39:36 PM PST 24
Peak memory 256764 kb
Host smart-195ab758-ffcc-49a6-b7e9-54b4e00f457b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39849
6406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.398496406
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2100429211
Short name T99
Test name
Test status
Simulation time 502694164 ps
CPU time 19.99 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:37:51 PM PST 24
Peak memory 254288 kb
Host smart-c7ded677-09c5-4461-90f2-57d0ea946609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
29211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2100429211
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2256566431
Short name T698
Test name
Test status
Simulation time 44217407225 ps
CPU time 1439.72 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 02:01:31 PM PST 24
Peak memory 280380 kb
Host smart-b024fc03-8fff-4280-9d5c-0b09f54faaca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256566431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2256566431
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1346907402
Short name T292
Test name
Test status
Simulation time 77074058461 ps
CPU time 1261.88 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:58:34 PM PST 24
Peak memory 289056 kb
Host smart-a6037b09-98e5-4d91-bba5-6c7d95a04dbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346907402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1346907402
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3337285297
Short name T355
Test name
Test status
Simulation time 108305215671 ps
CPU time 255.84 seconds
Started Jan 03 01:37:15 PM PST 24
Finished Jan 03 01:41:47 PM PST 24
Peak memory 247432 kb
Host smart-1160ad8a-8d3f-4a1c-9330-34666fa20410
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337285297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3337285297
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3282024258
Short name T499
Test name
Test status
Simulation time 18260512306 ps
CPU time 52.83 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 01:38:23 PM PST 24
Peak memory 248700 kb
Host smart-0d827c7d-07dd-4631-931a-1be6f182ebf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
24258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3282024258
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4182906352
Short name T518
Test name
Test status
Simulation time 631234351 ps
CPU time 37.52 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:38:09 PM PST 24
Peak memory 255220 kb
Host smart-04d9ce1b-d8f4-4c6c-99b5-25303a773f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41829
06352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4182906352
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3414611618
Short name T19
Test name
Test status
Simulation time 493247386 ps
CPU time 28.63 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 01:37:59 PM PST 24
Peak memory 247256 kb
Host smart-b9b1258c-aaa3-4d6f-a82f-65a6b3df9be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34146
11618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3414611618
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1017651156
Short name T456
Test name
Test status
Simulation time 1371460507 ps
CPU time 38.44 seconds
Started Jan 03 01:37:12 PM PST 24
Finished Jan 03 01:38:08 PM PST 24
Peak memory 248636 kb
Host smart-aa61d7c3-28fb-46d1-9349-bb117ba2a06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10176
51156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1017651156
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1916109751
Short name T233
Test name
Test status
Simulation time 125191261 ps
CPU time 3.28 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:37:40 PM PST 24
Peak memory 248896 kb
Host smart-6803a4e3-ba06-4c95-a37b-328b554f9e5c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1916109751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1916109751
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.4195738838
Short name T678
Test name
Test status
Simulation time 43783568310 ps
CPU time 1149.45 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:56:45 PM PST 24
Peak memory 289080 kb
Host smart-7f9e37c9-6d7a-446a-a379-31d7a6899514
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195738838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4195738838
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.4274297624
Short name T527
Test name
Test status
Simulation time 1407811381 ps
CPU time 10.34 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 01:37:43 PM PST 24
Peak memory 240392 kb
Host smart-fef5d66e-cb8f-4d9d-8c01-f1a4222c9292
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4274297624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4274297624
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2738805543
Short name T84
Test name
Test status
Simulation time 3919236685 ps
CPU time 75.3 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:38:52 PM PST 24
Peak memory 256376 kb
Host smart-65740029-d218-4c57-9747-3a8319057db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27388
05543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2738805543
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.874723090
Short name T399
Test name
Test status
Simulation time 450043795 ps
CPU time 26.83 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:38:02 PM PST 24
Peak memory 248228 kb
Host smart-3620ae19-3291-4ba3-97de-1c4269443702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87472
3090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.874723090
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1900681473
Short name T358
Test name
Test status
Simulation time 18508686665 ps
CPU time 1062.74 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:55:20 PM PST 24
Peak memory 264856 kb
Host smart-1f3f994d-ede8-4eab-90e5-07b82f171f18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900681473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1900681473
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1967942115
Short name T89
Test name
Test status
Simulation time 92763167216 ps
CPU time 518.87 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:46:16 PM PST 24
Peak memory 271224 kb
Host smart-1caada2f-619e-41a1-af80-00e2c180aab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967942115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1967942115
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3784793666
Short name T564
Test name
Test status
Simulation time 255696629 ps
CPU time 19.71 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:37:55 PM PST 24
Peak memory 248640 kb
Host smart-20baf2b0-9ea6-4497-a674-7b600cda4545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37847
93666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3784793666
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1659273277
Short name T693
Test name
Test status
Simulation time 309748815 ps
CPU time 34.56 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:38:10 PM PST 24
Peak memory 255444 kb
Host smart-4b2b81da-8577-4686-94d1-4d764b034d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16592
73277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1659273277
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.426570837
Short name T609
Test name
Test status
Simulation time 751908618 ps
CPU time 33.6 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:38:06 PM PST 24
Peak memory 248692 kb
Host smart-32dddab9-566c-4f7c-8773-3bf0ce8cf733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42657
0837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.426570837
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1213509392
Short name T517
Test name
Test status
Simulation time 71831049022 ps
CPU time 4425.39 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 02:51:24 PM PST 24
Peak memory 306288 kb
Host smart-b4bbecce-11cf-4e81-b733-6ffec4cb57c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213509392 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1213509392
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2970803569
Short name T222
Test name
Test status
Simulation time 33142027 ps
CPU time 3.55 seconds
Started Jan 03 01:35:48 PM PST 24
Finished Jan 03 01:36:00 PM PST 24
Peak memory 248820 kb
Host smart-91524e05-b4c6-4104-8ce4-a77b52907e68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2970803569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2970803569
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3058824185
Short name T435
Test name
Test status
Simulation time 24788084829 ps
CPU time 1493.88 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 02:00:45 PM PST 24
Peak memory 265124 kb
Host smart-a7013d73-1b4e-448e-b27e-c6eda38b81e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058824185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3058824185
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3751109052
Short name T250
Test name
Test status
Simulation time 657737484 ps
CPU time 10.67 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 01:36:34 PM PST 24
Peak memory 240416 kb
Host smart-ea7d509e-0d17-49cd-bf12-cb0b48693a8b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3751109052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3751109052
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2496677662
Short name T729
Test name
Test status
Simulation time 1322008386 ps
CPU time 130.36 seconds
Started Jan 03 01:36:07 PM PST 24
Finished Jan 03 01:38:30 PM PST 24
Peak memory 255872 kb
Host smart-9ce90612-40a6-4351-aeec-a73ead4ec006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24966
77662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2496677662
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4217285140
Short name T502
Test name
Test status
Simulation time 1038691782 ps
CPU time 45.84 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:36:38 PM PST 24
Peak memory 254888 kb
Host smart-f3d734b8-37f3-42a0-ab65-ca15dc8b162e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42172
85140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4217285140
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1765330876
Short name T359
Test name
Test status
Simulation time 94241760715 ps
CPU time 1449.18 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 02:00:01 PM PST 24
Peak memory 265080 kb
Host smart-a4f3d5a2-dfef-4286-b8e1-1cb6649efe45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765330876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1765330876
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3270239827
Short name T82
Test name
Test status
Simulation time 97061985340 ps
CPU time 1494.02 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 02:00:47 PM PST 24
Peak memory 265092 kb
Host smart-080af3be-e041-4141-8855-47dfd155f050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270239827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3270239827
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2284748803
Short name T581
Test name
Test status
Simulation time 132715033 ps
CPU time 14.41 seconds
Started Jan 03 01:35:42 PM PST 24
Finished Jan 03 01:36:02 PM PST 24
Peak memory 256820 kb
Host smart-e85d5769-965c-400a-b0e7-04dd69482a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22847
48803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2284748803
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.880089752
Short name T568
Test name
Test status
Simulation time 358053139 ps
CPU time 23.81 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 01:36:15 PM PST 24
Peak memory 254596 kb
Host smart-54cd4e6a-1737-4d88-8076-20ec701109f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88008
9752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.880089752
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3100206414
Short name T91
Test name
Test status
Simulation time 93746278 ps
CPU time 10.88 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:36:04 PM PST 24
Peak memory 248508 kb
Host smart-df20b8df-9176-4698-b8f1-ba71e46739d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31002
06414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3100206414
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.802476186
Short name T504
Test name
Test status
Simulation time 1600571386 ps
CPU time 24.14 seconds
Started Jan 03 01:35:49 PM PST 24
Finished Jan 03 01:36:21 PM PST 24
Peak memory 248592 kb
Host smart-7480635c-0a29-431b-86ae-e17de367c0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80247
6186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.802476186
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3514408714
Short name T330
Test name
Test status
Simulation time 10462499671 ps
CPU time 111.58 seconds
Started Jan 03 01:36:05 PM PST 24
Finished Jan 03 01:38:06 PM PST 24
Peak memory 256436 kb
Host smart-0752b1fa-0933-4b16-860a-1519be9c4630
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514408714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3514408714
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3845954341
Short name T627
Test name
Test status
Simulation time 25292487912 ps
CPU time 1529.75 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 02:01:23 PM PST 24
Peak memory 284908 kb
Host smart-69a1f37f-7dff-435b-abc1-23351bb8a53f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845954341 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3845954341
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2715333878
Short name T594
Test name
Test status
Simulation time 16579761450 ps
CPU time 709.34 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 01:49:28 PM PST 24
Peak memory 265140 kb
Host smart-995491ff-e07b-4f13-95c4-ee3db5c052ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715333878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2715333878
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3623508772
Short name T618
Test name
Test status
Simulation time 3742857211 ps
CPU time 234.51 seconds
Started Jan 03 01:37:21 PM PST 24
Finished Jan 03 01:41:29 PM PST 24
Peak memory 256712 kb
Host smart-07f193e0-1905-404b-b7d1-4311cca571a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235
08772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3623508772
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3572955011
Short name T400
Test name
Test status
Simulation time 1520805345 ps
CPU time 8.05 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:37:46 PM PST 24
Peak memory 250492 kb
Host smart-cc94ea73-d47e-41da-9969-ea43439652b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
55011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3572955011
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2122868883
Short name T299
Test name
Test status
Simulation time 37898339196 ps
CPU time 1452.11 seconds
Started Jan 03 01:37:31 PM PST 24
Finished Jan 03 02:01:54 PM PST 24
Peak memory 281320 kb
Host smart-a95dac25-a6ab-4671-a36d-f2ef5a53800e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122868883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2122868883
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3590887421
Short name T251
Test name
Test status
Simulation time 67394268899 ps
CPU time 1267.84 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:58:44 PM PST 24
Peak memory 285500 kb
Host smart-6180497f-759c-401a-82cf-e8b0f12cf8db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590887421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3590887421
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.672049718
Short name T622
Test name
Test status
Simulation time 235086680 ps
CPU time 19.07 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:37:57 PM PST 24
Peak memory 248520 kb
Host smart-45f20dc0-e92b-4706-912a-eeaacb25223f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67204
9718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.672049718
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1676152427
Short name T592
Test name
Test status
Simulation time 882102609 ps
CPU time 51.1 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:38:27 PM PST 24
Peak memory 254856 kb
Host smart-8f003c9b-a721-40cd-9add-4ec96239751c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
52427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1676152427
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.21667721
Short name T312
Test name
Test status
Simulation time 188392213 ps
CPU time 17.52 seconds
Started Jan 03 01:37:31 PM PST 24
Finished Jan 03 01:37:59 PM PST 24
Peak memory 248560 kb
Host smart-d6a84c49-a5e9-43fc-9b04-64d77c7961b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21667
721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.21667721
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3097290820
Short name T234
Test name
Test status
Simulation time 49904995 ps
CPU time 2.67 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 01:37:43 PM PST 24
Peak memory 240400 kb
Host smart-815443ba-a5e9-4566-aab2-0f58121653e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30972
90820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3097290820
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2680376695
Short name T18
Test name
Test status
Simulation time 66519750783 ps
CPU time 1780.99 seconds
Started Jan 03 01:37:53 PM PST 24
Finished Jan 03 02:07:37 PM PST 24
Peak memory 287504 kb
Host smart-9746e92f-db9a-4ca8-9a3d-e66f3b63c562
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680376695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2680376695
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2575469350
Short name T544
Test name
Test status
Simulation time 459042567266 ps
CPU time 6452.35 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 03:25:15 PM PST 24
Peak memory 314288 kb
Host smart-2c8d0ffb-952b-43f0-b53f-6889990dee76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575469350 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2575469350
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2061188666
Short name T140
Test name
Test status
Simulation time 57688721196 ps
CPU time 1328.93 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:59:49 PM PST 24
Peak memory 289388 kb
Host smart-952fd3f5-1869-4296-a0db-37fbf09e4d76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061188666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2061188666
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4065365363
Short name T389
Test name
Test status
Simulation time 3685339200 ps
CPU time 58.48 seconds
Started Jan 03 01:37:30 PM PST 24
Finished Jan 03 01:38:40 PM PST 24
Peak memory 248548 kb
Host smart-555472c8-d3b1-4b5b-9291-16a5740e4f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
65363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4065365363
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2539460742
Short name T716
Test name
Test status
Simulation time 251230141 ps
CPU time 23.13 seconds
Started Jan 03 01:37:50 PM PST 24
Finished Jan 03 01:38:17 PM PST 24
Peak memory 254100 kb
Host smart-fc3811d7-5416-4673-a92d-572e96b5045b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25394
60742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2539460742
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3258124191
Short name T647
Test name
Test status
Simulation time 51118394485 ps
CPU time 1432.21 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 02:01:42 PM PST 24
Peak memory 288860 kb
Host smart-1031a775-f629-4fdc-914e-8005c2753f17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258124191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3258124191
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1637568903
Short name T265
Test name
Test status
Simulation time 58025593370 ps
CPU time 1202.9 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 01:57:36 PM PST 24
Peak memory 273216 kb
Host smart-0a9bbccd-eb4d-4d2c-bfbf-91037c5a3951
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637568903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1637568903
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3383786259
Short name T689
Test name
Test status
Simulation time 24986653830 ps
CPU time 253.99 seconds
Started Jan 03 01:37:41 PM PST 24
Finished Jan 03 01:42:04 PM PST 24
Peak memory 247556 kb
Host smart-4d7375c0-fb27-48e7-8765-7ddcd0d3aa62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383786259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3383786259
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2595796741
Short name T714
Test name
Test status
Simulation time 1374219613 ps
CPU time 21.25 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:37:58 PM PST 24
Peak memory 248632 kb
Host smart-8e566d20-cd07-4a32-9fdc-a2637e2eb2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25957
96741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2595796741
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3300065653
Short name T303
Test name
Test status
Simulation time 889259671 ps
CPU time 40 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 01:38:29 PM PST 24
Peak memory 246960 kb
Host smart-1a8f0a2d-299f-4844-907e-9801bb3b0104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000
65653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3300065653
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2274332184
Short name T125
Test name
Test status
Simulation time 3955854537 ps
CPU time 35.88 seconds
Started Jan 03 01:37:34 PM PST 24
Finished Jan 03 01:38:20 PM PST 24
Peak memory 256236 kb
Host smart-07dddd5a-7864-4333-9d9c-a92dc357e520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22743
32184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2274332184
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2991468489
Short name T610
Test name
Test status
Simulation time 1863886143 ps
CPU time 37.1 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 01:38:25 PM PST 24
Peak memory 248556 kb
Host smart-2bdd3a8d-46df-4b5b-8387-b9c575a7b21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29914
68489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2991468489
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1931247512
Short name T316
Test name
Test status
Simulation time 587028434283 ps
CPU time 2757.49 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 02:23:33 PM PST 24
Peak memory 281520 kb
Host smart-5789cccf-0dd6-4524-8d92-5038a261d45c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931247512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1931247512
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4231403134
Short name T556
Test name
Test status
Simulation time 62345383948 ps
CPU time 3426.85 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 02:34:42 PM PST 24
Peak memory 337884 kb
Host smart-4f43b407-aa86-4715-aeca-b9d97865b269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231403134 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4231403134
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.341181299
Short name T625
Test name
Test status
Simulation time 54392883345 ps
CPU time 2442.83 seconds
Started Jan 03 01:37:16 PM PST 24
Finished Jan 03 02:18:14 PM PST 24
Peak memory 289032 kb
Host smart-f39b01a3-4447-4f1e-8f43-50b7374269ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341181299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.341181299
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2450518666
Short name T572
Test name
Test status
Simulation time 4203500539 ps
CPU time 234.06 seconds
Started Jan 03 01:37:16 PM PST 24
Finished Jan 03 01:41:26 PM PST 24
Peak memory 256228 kb
Host smart-7605e915-d248-47f5-a391-dfd5d56a4b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24505
18666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2450518666
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1014330190
Short name T506
Test name
Test status
Simulation time 212897718 ps
CPU time 6.2 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:37:37 PM PST 24
Peak memory 251716 kb
Host smart-89c96728-dcd2-43da-aaff-5ed51b69543f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10143
30190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1014330190
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3383263666
Short name T611
Test name
Test status
Simulation time 223641271837 ps
CPU time 3236.85 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 02:31:29 PM PST 24
Peak memory 289352 kb
Host smart-b4e1304a-bb89-4569-b9cb-0e978f42e0b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383263666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3383263666
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1794088334
Short name T654
Test name
Test status
Simulation time 103971467238 ps
CPU time 1523.19 seconds
Started Jan 03 01:37:21 PM PST 24
Finished Jan 03 02:02:57 PM PST 24
Peak memory 273100 kb
Host smart-f305127d-025d-4de4-8bab-1ee8e6584338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794088334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1794088334
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1279279876
Short name T338
Test name
Test status
Simulation time 11752084307 ps
CPU time 464.84 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:45:16 PM PST 24
Peak memory 247380 kb
Host smart-11396de7-2e6a-485d-8767-e8e20965d6db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279279876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1279279876
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1476037226
Short name T81
Test name
Test status
Simulation time 939771310 ps
CPU time 16.8 seconds
Started Jan 03 01:37:35 PM PST 24
Finished Jan 03 01:38:01 PM PST 24
Peak memory 248696 kb
Host smart-ffb72842-0bf2-4a31-a60c-486b5465fdaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14760
37226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1476037226
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1275471856
Short name T436
Test name
Test status
Simulation time 1026317306 ps
CPU time 56.07 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:38:28 PM PST 24
Peak memory 255568 kb
Host smart-dac0d31a-b416-4f3b-bf99-10f1884bcfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12754
71856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1275471856
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.117370826
Short name T723
Test name
Test status
Simulation time 4768378215 ps
CPU time 48.39 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:38:19 PM PST 24
Peak memory 255616 kb
Host smart-ea6aa57e-d5ee-4a35-b37d-9fb822d3360b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11737
0826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.117370826
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2137606514
Short name T447
Test name
Test status
Simulation time 338780875 ps
CPU time 22.34 seconds
Started Jan 03 01:37:49 PM PST 24
Finished Jan 03 01:38:16 PM PST 24
Peak memory 248568 kb
Host smart-7543ab96-bb2c-416c-9f41-cd60572ae98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
06514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2137606514
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2173644171
Short name T493
Test name
Test status
Simulation time 89238707868 ps
CPU time 5486.2 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 03:08:59 PM PST 24
Peak memory 321936 kb
Host smart-fca42637-bb7b-4011-bd50-1cd93de54577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173644171 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2173644171
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1969335148
Short name T465
Test name
Test status
Simulation time 13614768717 ps
CPU time 680.73 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 01:48:54 PM PST 24
Peak memory 265072 kb
Host smart-92c6c44d-db7f-447a-83e7-41b4d4844f0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969335148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1969335148
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.4068313070
Short name T650
Test name
Test status
Simulation time 46343748800 ps
CPU time 269.31 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:42:07 PM PST 24
Peak memory 256912 kb
Host smart-018a0c42-314b-487d-a2ab-040df08a0b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40683
13070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4068313070
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1216201022
Short name T526
Test name
Test status
Simulation time 3162211935 ps
CPU time 51.12 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:38:24 PM PST 24
Peak memory 254928 kb
Host smart-e1a53a83-3af2-4cf1-9ef8-03f8841ff283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12162
01022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1216201022
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.257865843
Short name T373
Test name
Test status
Simulation time 43689784517 ps
CPU time 2487.57 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 02:19:05 PM PST 24
Peak memory 289272 kb
Host smart-de5814e1-54a6-41a8-a409-b96a46c00e20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257865843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.257865843
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1326908980
Short name T133
Test name
Test status
Simulation time 106046250417 ps
CPU time 2907.32 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 02:26:05 PM PST 24
Peak memory 288936 kb
Host smart-60368c0c-00ca-47ac-9552-a8e332c3c2bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326908980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1326908980
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1649912964
Short name T694
Test name
Test status
Simulation time 21726721935 ps
CPU time 244.5 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:41:43 PM PST 24
Peak memory 247588 kb
Host smart-65037638-7ab3-445f-9059-5f69507a284c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649912964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1649912964
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2624653001
Short name T290
Test name
Test status
Simulation time 2735971528 ps
CPU time 43.53 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:38:16 PM PST 24
Peak memory 256844 kb
Host smart-efbefe39-d328-4e58-8176-f2fe99ff9c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
53001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2624653001
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.235436823
Short name T279
Test name
Test status
Simulation time 1465435115 ps
CPU time 37.81 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:38:13 PM PST 24
Peak memory 247592 kb
Host smart-d2e48bba-bebd-42e6-a703-ad26ae1627c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23543
6823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.235436823
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2089118886
Short name T669
Test name
Test status
Simulation time 30824239 ps
CPU time 4.58 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:37:41 PM PST 24
Peak memory 239428 kb
Host smart-76394ac5-3c51-428a-9d0c-711dda16b9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20891
18886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2089118886
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1152909332
Short name T736
Test name
Test status
Simulation time 166918761 ps
CPU time 16.53 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:37:49 PM PST 24
Peak memory 248604 kb
Host smart-6389dd3d-2913-4021-af1b-3e5e267713b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11529
09332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1152909332
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2883183066
Short name T143
Test name
Test status
Simulation time 1191851423 ps
CPU time 50.04 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:38:26 PM PST 24
Peak memory 248692 kb
Host smart-12314d07-2fb5-437f-93a8-b35c61f830d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883183066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2883183066
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1001252709
Short name T419
Test name
Test status
Simulation time 67939992724 ps
CPU time 1428.81 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 02:01:24 PM PST 24
Peak memory 289468 kb
Host smart-fc1cbd45-7086-4682-8969-83dc7de09e12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001252709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1001252709
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.440169136
Short name T602
Test name
Test status
Simulation time 3718183158 ps
CPU time 68.56 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 01:38:49 PM PST 24
Peak memory 256248 kb
Host smart-b4dbcf06-0452-4ac7-aa10-c36c44fe519d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44016
9136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.440169136
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3532628497
Short name T664
Test name
Test status
Simulation time 1407820517 ps
CPU time 49.89 seconds
Started Jan 03 01:37:28 PM PST 24
Finished Jan 03 01:38:30 PM PST 24
Peak memory 255124 kb
Host smart-e6adde37-97ab-4921-8d2a-e13b1d575ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35326
28497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3532628497
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4070132627
Short name T370
Test name
Test status
Simulation time 53744836700 ps
CPU time 1695.87 seconds
Started Jan 03 01:37:31 PM PST 24
Finished Jan 03 02:05:58 PM PST 24
Peak memory 265060 kb
Host smart-c72bdbd5-2186-43c3-b003-5b07034ef0e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070132627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4070132627
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3516059480
Short name T665
Test name
Test status
Simulation time 10225756680 ps
CPU time 804.79 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 01:51:13 PM PST 24
Peak memory 272572 kb
Host smart-cf42f667-dbdb-40e9-ae4c-499d13fc0a55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516059480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3516059480
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.545735855
Short name T735
Test name
Test status
Simulation time 6383368614 ps
CPU time 252.91 seconds
Started Jan 03 01:37:30 PM PST 24
Finished Jan 03 01:41:54 PM PST 24
Peak memory 247500 kb
Host smart-b8479c04-fd50-4471-9100-88b72b07a339
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545735855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.545735855
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2262026514
Short name T643
Test name
Test status
Simulation time 608570805 ps
CPU time 34 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:38:09 PM PST 24
Peak memory 255316 kb
Host smart-325671a7-be8b-4567-acac-2ce7a962bb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
26514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2262026514
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3243172810
Short name T721
Test name
Test status
Simulation time 1527806464 ps
CPU time 44.44 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 01:38:18 PM PST 24
Peak memory 248588 kb
Host smart-080e5c9b-9bec-4711-bf10-d5979d578e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32431
72810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3243172810
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1420107001
Short name T512
Test name
Test status
Simulation time 168798309 ps
CPU time 6.33 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 01:37:45 PM PST 24
Peak memory 253232 kb
Host smart-b12e3603-f5fc-43cb-927f-04ec06269d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14201
07001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1420107001
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2624042442
Short name T570
Test name
Test status
Simulation time 6133502438 ps
CPU time 26.37 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 01:38:05 PM PST 24
Peak memory 248768 kb
Host smart-4e75b49f-2557-4133-86f2-616dd79f6458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26240
42442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2624042442
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1949966431
Short name T494
Test name
Test status
Simulation time 814543832 ps
CPU time 50.98 seconds
Started Jan 03 01:37:31 PM PST 24
Finished Jan 03 01:38:33 PM PST 24
Peak memory 255440 kb
Host smart-bcc929ad-ec1a-4eaf-aece-191583d4ba2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949966431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1949966431
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2794131030
Short name T738
Test name
Test status
Simulation time 34527401308 ps
CPU time 994.01 seconds
Started Jan 03 01:37:30 PM PST 24
Finished Jan 03 01:54:15 PM PST 24
Peak memory 272652 kb
Host smart-72250d97-78bb-4ac0-aac5-26f270f9f5a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794131030 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2794131030
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.194271003
Short name T573
Test name
Test status
Simulation time 207053760969 ps
CPU time 844.31 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 01:51:47 PM PST 24
Peak memory 272364 kb
Host smart-676eca5c-9302-44b6-acf5-666f6b7c2079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194271003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.194271003
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2851861884
Short name T461
Test name
Test status
Simulation time 4436461560 ps
CPU time 100.34 seconds
Started Jan 03 01:37:44 PM PST 24
Finished Jan 03 01:39:32 PM PST 24
Peak memory 256804 kb
Host smart-961b28e1-8f3e-4db8-8079-c668e3ff4200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28518
61884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2851861884
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3383790813
Short name T520
Test name
Test status
Simulation time 174780533 ps
CPU time 13.45 seconds
Started Jan 03 01:37:45 PM PST 24
Finished Jan 03 01:38:06 PM PST 24
Peak memory 248664 kb
Host smart-650df407-9bd1-479a-a28e-9d2f8ba42528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33837
90813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3383790813
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1678534207
Short name T365
Test name
Test status
Simulation time 48988558774 ps
CPU time 2811.49 seconds
Started Jan 03 01:37:34 PM PST 24
Finished Jan 03 02:24:35 PM PST 24
Peak memory 289596 kb
Host smart-be16e0bf-2445-4e36-84e6-6a5cfbc5194d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678534207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1678534207
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1100804668
Short name T444
Test name
Test status
Simulation time 44789341931 ps
CPU time 1019.31 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 01:54:43 PM PST 24
Peak memory 264736 kb
Host smart-9920b1b3-b1dd-4278-a26f-c3aa9fff8c22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100804668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1100804668
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3256198718
Short name T353
Test name
Test status
Simulation time 28646057198 ps
CPU time 307.85 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 01:42:57 PM PST 24
Peak memory 246412 kb
Host smart-1ea8d22b-7bc1-4af7-99f5-f308b15f2606
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256198718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3256198718
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1237969742
Short name T426
Test name
Test status
Simulation time 15859479060 ps
CPU time 53.21 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:38:29 PM PST 24
Peak memory 248592 kb
Host smart-64a91225-3658-4e3b-b935-b26d3590e2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12379
69742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1237969742
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.18877890
Short name T124
Test name
Test status
Simulation time 395152560 ps
CPU time 22.66 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:38:10 PM PST 24
Peak memory 253900 kb
Host smart-56af825f-9d43-4b1f-9313-857cae81c5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18877
890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.18877890
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.881463103
Short name T658
Test name
Test status
Simulation time 308247645 ps
CPU time 35.39 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 01:38:19 PM PST 24
Peak memory 256036 kb
Host smart-8d42a874-1926-40eb-aded-64bc5f955d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88146
3103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.881463103
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.530023896
Short name T388
Test name
Test status
Simulation time 56247228 ps
CPU time 4.8 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 01:37:52 PM PST 24
Peak memory 240292 kb
Host smart-16ab59b2-d9e2-480c-855b-448eeb67703d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53002
3896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.530023896
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3449809092
Short name T74
Test name
Test status
Simulation time 170946001126 ps
CPU time 2459.53 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 02:18:43 PM PST 24
Peak memory 289040 kb
Host smart-cd31670b-fdfd-4295-a219-1026dfbd279d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449809092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3449809092
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2652991380
Short name T108
Test name
Test status
Simulation time 167957214976 ps
CPU time 2448.85 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 02:18:20 PM PST 24
Peak memory 289376 kb
Host smart-5e4b16bc-a769-4e63-95d6-d095fde9f122
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652991380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2652991380
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2184698002
Short name T515
Test name
Test status
Simulation time 1380321992 ps
CPU time 99.34 seconds
Started Jan 03 01:37:16 PM PST 24
Finished Jan 03 01:39:11 PM PST 24
Peak memory 249596 kb
Host smart-21fdc2fb-ead7-4de2-ad8a-7c4d3d220c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
98002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2184698002
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3853681920
Short name T254
Test name
Test status
Simulation time 323722110 ps
CPU time 11.14 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 01:37:44 PM PST 24
Peak memory 253220 kb
Host smart-c017b4cd-6556-4d76-afaf-37e0926feedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
81920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3853681920
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3956973307
Short name T86
Test name
Test status
Simulation time 33847760816 ps
CPU time 1828.41 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 02:08:02 PM PST 24
Peak memory 281428 kb
Host smart-a73c8ebc-4a11-4254-a214-80e60f7360c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956973307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3956973307
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.959174284
Short name T344
Test name
Test status
Simulation time 64494759415 ps
CPU time 487.63 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:45:43 PM PST 24
Peak memory 247540 kb
Host smart-8a859fc1-cb33-4a0c-93d5-c3d7040f112b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959174284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.959174284
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2166213029
Short name T72
Test name
Test status
Simulation time 364809051 ps
CPU time 23.19 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:38:00 PM PST 24
Peak memory 248512 kb
Host smart-06354fe5-6a06-4db8-867f-5d1538225218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
13029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2166213029
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2806481302
Short name T713
Test name
Test status
Simulation time 1910276683 ps
CPU time 32.75 seconds
Started Jan 03 01:37:15 PM PST 24
Finished Jan 03 01:38:04 PM PST 24
Peak memory 254556 kb
Host smart-758a1a7c-ead9-46ba-a16d-1ac3adf24377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
81302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2806481302
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.506733976
Short name T248
Test name
Test status
Simulation time 310915032 ps
CPU time 11.16 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 01:37:44 PM PST 24
Peak memory 247756 kb
Host smart-b03cb8fc-b6ff-4706-b910-977e54ade1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50673
3976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.506733976
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3150749180
Short name T239
Test name
Test status
Simulation time 2653935946 ps
CPU time 43.25 seconds
Started Jan 03 01:37:34 PM PST 24
Finished Jan 03 01:38:27 PM PST 24
Peak memory 248748 kb
Host smart-af23d017-fa93-4bd2-84d1-12812c89f0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
49180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3150749180
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2148922087
Short name T402
Test name
Test status
Simulation time 29114181577 ps
CPU time 1424.89 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 02:01:20 PM PST 24
Peak memory 288036 kb
Host smart-b77bace4-912d-444e-ba4f-fcff6f6fdd04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148922087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2148922087
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3793562882
Short name T507
Test name
Test status
Simulation time 7339102928 ps
CPU time 198.36 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:40:51 PM PST 24
Peak memory 256220 kb
Host smart-589e8c00-1337-4d48-b17f-baccfa1d5e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37935
62882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3793562882
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1567812877
Short name T428
Test name
Test status
Simulation time 391037314 ps
CPU time 23.24 seconds
Started Jan 03 01:37:15 PM PST 24
Finished Jan 03 01:37:54 PM PST 24
Peak memory 254996 kb
Host smart-f813b5bf-bcd3-4172-9e36-c6e1b09d6091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678
12877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1567812877
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2796029349
Short name T737
Test name
Test status
Simulation time 21884524897 ps
CPU time 1555.61 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 02:03:28 PM PST 24
Peak memory 289352 kb
Host smart-85d59885-e0b3-4e42-ae5f-83c31ae2c7b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796029349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2796029349
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.523212673
Short name T740
Test name
Test status
Simulation time 138378094328 ps
CPU time 2364.78 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 02:16:58 PM PST 24
Peak memory 287684 kb
Host smart-d80d1e13-9193-4b27-a854-25bcd18a0e3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523212673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.523212673
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.329567155
Short name T624
Test name
Test status
Simulation time 19735192982 ps
CPU time 423.71 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 01:44:36 PM PST 24
Peak memory 247596 kb
Host smart-f5aea893-6ac8-4cae-a9f7-e35c9f5cd9ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329567155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.329567155
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3440623710
Short name T682
Test name
Test status
Simulation time 2643605636 ps
CPU time 43.03 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:38:15 PM PST 24
Peak memory 248680 kb
Host smart-3678e74a-99e7-4396-8e5c-8e8261bece42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34406
23710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3440623710
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1997991387
Short name T575
Test name
Test status
Simulation time 35758546 ps
CPU time 3.69 seconds
Started Jan 03 01:37:21 PM PST 24
Finished Jan 03 01:37:38 PM PST 24
Peak memory 238696 kb
Host smart-d49fa2fb-8b8c-4ce3-b70c-968793f1344c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19979
91387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1997991387
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1769716254
Short name T651
Test name
Test status
Simulation time 306593931 ps
CPU time 9.17 seconds
Started Jan 03 01:37:22 PM PST 24
Finished Jan 03 01:37:44 PM PST 24
Peak memory 253812 kb
Host smart-31289acc-9100-4859-b964-3d16068465a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17697
16254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1769716254
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.723958653
Short name T285
Test name
Test status
Simulation time 377080533 ps
CPU time 30.6 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 01:38:03 PM PST 24
Peak memory 248660 kb
Host smart-b26143a9-7bb7-44b9-933e-fe44ad41a407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72395
8653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.723958653
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.744168931
Short name T677
Test name
Test status
Simulation time 110417364534 ps
CPU time 2596.94 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 02:20:54 PM PST 24
Peak memory 289204 kb
Host smart-cb6dbb4d-0d8b-4eda-a6ca-91d7789e70fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744168931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.744168931
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.212995378
Short name T549
Test name
Test status
Simulation time 1828982277 ps
CPU time 78.56 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:38:54 PM PST 24
Peak memory 255884 kb
Host smart-6fb4d438-0244-4a60-8ad6-e8d6b6cd764b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21299
5378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.212995378
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3664239148
Short name T439
Test name
Test status
Simulation time 171826603 ps
CPU time 17.3 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 01:37:54 PM PST 24
Peak memory 255028 kb
Host smart-1d9b661d-4d70-47fa-9d66-2bf7dfc48245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36642
39148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3664239148
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2727241144
Short name T267
Test name
Test status
Simulation time 104751466135 ps
CPU time 1291.51 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 01:59:10 PM PST 24
Peak memory 272880 kb
Host smart-4655f26a-8292-4a8f-95ca-03633b0d3230
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727241144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2727241144
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1569258325
Short name T403
Test name
Test status
Simulation time 163022815794 ps
CPU time 2439.73 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 02:18:15 PM PST 24
Peak memory 285164 kb
Host smart-b6d364f8-9777-4356-b80f-0a9b08bb184c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569258325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1569258325
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3957305744
Short name T605
Test name
Test status
Simulation time 5161394249 ps
CPU time 77.56 seconds
Started Jan 03 01:37:15 PM PST 24
Finished Jan 03 01:38:49 PM PST 24
Peak memory 255728 kb
Host smart-88e41602-133e-4138-92a1-a145d6fce143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
05744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3957305744
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2754725282
Short name T40
Test name
Test status
Simulation time 65893329 ps
CPU time 9.05 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:37:41 PM PST 24
Peak memory 253408 kb
Host smart-31e4466e-0cb8-4151-82f3-252de0c3b762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27547
25282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2754725282
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1211539752
Short name T432
Test name
Test status
Simulation time 238116159 ps
CPU time 16.16 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 01:37:49 PM PST 24
Peak memory 254492 kb
Host smart-c40fc260-915c-47ef-ac76-186b30f78715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
39752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1211539752
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2563504487
Short name T438
Test name
Test status
Simulation time 968106529 ps
CPU time 20.38 seconds
Started Jan 03 01:37:19 PM PST 24
Finished Jan 03 01:37:53 PM PST 24
Peak memory 256864 kb
Host smart-8b5b3e2d-e217-4ece-a0fa-e07da3c9d152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635
04487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2563504487
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2810336929
Short name T139
Test name
Test status
Simulation time 323627782396 ps
CPU time 4607.35 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 02:54:25 PM PST 24
Peak memory 305132 kb
Host smart-f11b52ca-6e0b-42c5-a1ed-ccfb64e2c793
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810336929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2810336929
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3974093304
Short name T38
Test name
Test status
Simulation time 40097944711 ps
CPU time 2124.27 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 02:13:05 PM PST 24
Peak memory 272716 kb
Host smart-3769fbfa-90d9-47be-9983-81b194844278
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974093304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3974093304
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.177451359
Short name T699
Test name
Test status
Simulation time 2196759583 ps
CPU time 109.38 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 01:39:28 PM PST 24
Peak memory 256244 kb
Host smart-c18b7bab-cd55-4be9-9958-8456de64320b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
1359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.177451359
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2735146645
Short name T558
Test name
Test status
Simulation time 1512144033 ps
CPU time 35.49 seconds
Started Jan 03 01:37:28 PM PST 24
Finished Jan 03 01:38:15 PM PST 24
Peak memory 255248 kb
Host smart-0701f335-ffb1-4c23-88c9-a5cebc5a413d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27351
46645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2735146645
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4157983304
Short name T136
Test name
Test status
Simulation time 42179050120 ps
CPU time 1199.43 seconds
Started Jan 03 01:37:50 PM PST 24
Finished Jan 03 01:57:54 PM PST 24
Peak memory 272492 kb
Host smart-bcf62f32-7d06-4d8e-8199-52d6cd6bc859
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157983304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4157983304
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1519302374
Short name T410
Test name
Test status
Simulation time 51362185933 ps
CPU time 617.27 seconds
Started Jan 03 01:37:23 PM PST 24
Finished Jan 03 01:47:52 PM PST 24
Peak memory 272868 kb
Host smart-a770e71d-543b-4d4f-84ae-96641ea318b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519302374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1519302374
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.44888062
Short name T589
Test name
Test status
Simulation time 29687395799 ps
CPU time 444.62 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 01:45:05 PM PST 24
Peak memory 246484 kb
Host smart-3074cdb7-0232-49fa-b853-702624bf4a1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44888062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.44888062
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4081585900
Short name T459
Test name
Test status
Simulation time 471275993 ps
CPU time 38.14 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 01:38:17 PM PST 24
Peak memory 248672 kb
Host smart-360394ed-071b-43c9-be81-4e988a241214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40815
85900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4081585900
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2185453184
Short name T708
Test name
Test status
Simulation time 942030525 ps
CPU time 52.9 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:38:31 PM PST 24
Peak memory 255088 kb
Host smart-31ec4956-6809-483a-807e-29a862007600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854
53184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2185453184
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3487678210
Short name T460
Test name
Test status
Simulation time 157274187 ps
CPU time 4.65 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:37:43 PM PST 24
Peak memory 240448 kb
Host smart-63fe41b0-8539-417a-a405-46c23d1332e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34876
78210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3487678210
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.382835157
Short name T387
Test name
Test status
Simulation time 395667600 ps
CPU time 34.5 seconds
Started Jan 03 01:37:28 PM PST 24
Finished Jan 03 01:38:14 PM PST 24
Peak memory 256776 kb
Host smart-e5cf91e7-cca9-4e18-bfc6-4ae2693fada7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38283
5157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.382835157
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.356292889
Short name T228
Test name
Test status
Simulation time 135653026 ps
CPU time 3.23 seconds
Started Jan 03 01:36:03 PM PST 24
Finished Jan 03 01:36:16 PM PST 24
Peak memory 248812 kb
Host smart-324dfd63-869a-435a-803e-80947d3850e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=356292889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.356292889
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.958750459
Short name T454
Test name
Test status
Simulation time 50531568462 ps
CPU time 2918.77 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 02:25:03 PM PST 24
Peak memory 289172 kb
Host smart-56fc612e-ebfc-480b-8858-0415cae9984c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958750459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.958750459
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3127270354
Short name T533
Test name
Test status
Simulation time 636602632 ps
CPU time 11.29 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:36:35 PM PST 24
Peak memory 240464 kb
Host smart-b9eb0103-dee6-43ce-a50f-f0eb431837a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3127270354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3127270354
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.4087617945
Short name T655
Test name
Test status
Simulation time 1671053220 ps
CPU time 50.12 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 01:36:41 PM PST 24
Peak memory 248120 kb
Host smart-4216935a-10cd-4397-acd5-224d7a780c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40876
17945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.4087617945
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1044055374
Short name T683
Test name
Test status
Simulation time 509193829 ps
CPU time 10.11 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 01:36:02 PM PST 24
Peak memory 252384 kb
Host smart-176e9bf0-18df-4a41-a3df-e76e079baac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10440
55374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1044055374
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2033909855
Short name T535
Test name
Test status
Simulation time 7863020530 ps
CPU time 703.47 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:47:33 PM PST 24
Peak memory 267072 kb
Host smart-e9ad25ca-b5bb-44c4-9535-51a578592794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033909855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2033909855
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1011637068
Short name T486
Test name
Test status
Simulation time 29583549601 ps
CPU time 173.15 seconds
Started Jan 03 01:35:41 PM PST 24
Finished Jan 03 01:38:36 PM PST 24
Peak memory 247556 kb
Host smart-4a78132a-943d-4ebe-9a46-5f5846abaed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011637068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1011637068
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1029244528
Short name T68
Test name
Test status
Simulation time 1031280889 ps
CPU time 46.37 seconds
Started Jan 03 01:35:42 PM PST 24
Finished Jan 03 01:36:34 PM PST 24
Peak memory 248624 kb
Host smart-df6e0d04-c2f3-48b4-834f-022151438ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10292
44528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1029244528
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.410240203
Short name T241
Test name
Test status
Simulation time 76677960 ps
CPU time 7.43 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:35:56 PM PST 24
Peak memory 248124 kb
Host smart-ec9ba38c-366e-4442-bba4-c0567f742de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41024
0203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.410240203
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.766682383
Short name T46
Test name
Test status
Simulation time 430150815 ps
CPU time 13.19 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 01:36:37 PM PST 24
Peak memory 278208 kb
Host smart-f08db335-9e22-45db-8f78-a4002cc7c5be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=766682383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.766682383
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.532483438
Short name T577
Test name
Test status
Simulation time 292113457 ps
CPU time 30.82 seconds
Started Jan 03 01:36:10 PM PST 24
Finished Jan 03 01:36:54 PM PST 24
Peak memory 248604 kb
Host smart-7e6f426c-6a20-452c-978e-d68c0a7f2856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53248
3438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.532483438
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.492424423
Short name T411
Test name
Test status
Simulation time 589142946 ps
CPU time 27.93 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 01:36:19 PM PST 24
Peak memory 248600 kb
Host smart-a1f8fe4f-fbf9-4b0b-a7ff-626fafd41442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49242
4423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.492424423
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3713215146
Short name T704
Test name
Test status
Simulation time 37949696053 ps
CPU time 1151.86 seconds
Started Jan 03 01:36:08 PM PST 24
Finished Jan 03 01:55:35 PM PST 24
Peak memory 272600 kb
Host smart-fd4fe85c-6116-403e-905b-0f2236b03702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713215146 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3713215146
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2677494127
Short name T37
Test name
Test status
Simulation time 22731599560 ps
CPU time 1223.01 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 01:58:13 PM PST 24
Peak memory 272632 kb
Host smart-dfb2c1a6-452e-43e3-99c9-b4b5650dac36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677494127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2677494127
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2766145775
Short name T291
Test name
Test status
Simulation time 2258360497 ps
CPU time 126.27 seconds
Started Jan 03 01:37:31 PM PST 24
Finished Jan 03 01:39:48 PM PST 24
Peak memory 256084 kb
Host smart-e01263c6-9263-4045-9781-0b8a198fbe60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27661
45775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2766145775
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1307315803
Short name T22
Test name
Test status
Simulation time 288222850 ps
CPU time 4.28 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:37:40 PM PST 24
Peak memory 238728 kb
Host smart-a0bd1093-3dfc-4d09-b49d-489116029d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13073
15803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1307315803
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.4030330390
Short name T262
Test name
Test status
Simulation time 32666837974 ps
CPU time 1603.51 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 02:04:20 PM PST 24
Peak memory 272640 kb
Host smart-bfda85db-bd89-49f7-bc0c-aa27b44738b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030330390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4030330390
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.825176575
Short name T397
Test name
Test status
Simulation time 29920544138 ps
CPU time 864.96 seconds
Started Jan 03 01:37:34 PM PST 24
Finished Jan 03 01:52:09 PM PST 24
Peak memory 264716 kb
Host smart-26a5462d-da72-4ce5-a3c9-335f54fb8be7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825176575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.825176575
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1247763783
Short name T657
Test name
Test status
Simulation time 12653089652 ps
CPU time 483.64 seconds
Started Jan 03 01:37:46 PM PST 24
Finished Jan 03 01:45:56 PM PST 24
Peak memory 247508 kb
Host smart-3fb6e280-aa3a-4460-8416-730abe2b7ca9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247763783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1247763783
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2502450826
Short name T715
Test name
Test status
Simulation time 922514392 ps
CPU time 28.61 seconds
Started Jan 03 01:39:11 PM PST 24
Finished Jan 03 01:39:41 PM PST 24
Peak memory 255412 kb
Host smart-79966d38-18fd-4a43-9caa-c63fcc7ec66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25024
50826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2502450826
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2682946640
Short name T61
Test name
Test status
Simulation time 1572114148 ps
CPU time 34.59 seconds
Started Jan 03 01:37:30 PM PST 24
Finished Jan 03 01:38:16 PM PST 24
Peak memory 247768 kb
Host smart-24681f3b-d83c-442c-a144-3883221faa8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26829
46640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2682946640
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.691231910
Short name T414
Test name
Test status
Simulation time 1084106179 ps
CPU time 23.16 seconds
Started Jan 03 01:37:47 PM PST 24
Finished Jan 03 01:38:16 PM PST 24
Peak memory 254004 kb
Host smart-5047915a-29c8-48e8-8e7c-46991ca25b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69123
1910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.691231910
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3983223118
Short name T656
Test name
Test status
Simulation time 156200384 ps
CPU time 11.82 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 01:37:54 PM PST 24
Peak memory 248784 kb
Host smart-4eb065ef-482f-4226-974d-24922d26f067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39832
23118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3983223118
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.589309664
Short name T308
Test name
Test status
Simulation time 12966061062 ps
CPU time 238.75 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 01:41:42 PM PST 24
Peak memory 256888 kb
Host smart-21d5f22f-9eef-4400-97dd-a31e3917bdea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589309664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.589309664
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1934203219
Short name T516
Test name
Test status
Simulation time 140073835581 ps
CPU time 3391.4 seconds
Started Jan 03 01:37:30 PM PST 24
Finished Jan 03 02:34:12 PM PST 24
Peak memory 322220 kb
Host smart-d70f95e1-940c-44f2-b0c3-2ce82ab09b9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934203219 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1934203219
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.606710511
Short name T616
Test name
Test status
Simulation time 167763634298 ps
CPU time 2043.65 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 273132 kb
Host smart-00dc75a2-b5d1-4ec6-bd62-ab78e1394325
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606710511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.606710511
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2174336473
Short name T555
Test name
Test status
Simulation time 1351407118 ps
CPU time 36.94 seconds
Started Jan 03 01:37:35 PM PST 24
Finished Jan 03 01:38:21 PM PST 24
Peak memory 255484 kb
Host smart-b324593b-65f7-40fe-99de-a53088a51f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21743
36473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2174336473
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.892010396
Short name T236
Test name
Test status
Simulation time 3181396875 ps
CPU time 47.93 seconds
Started Jan 03 01:37:24 PM PST 24
Finished Jan 03 01:38:23 PM PST 24
Peak memory 254760 kb
Host smart-171d9af3-e401-42c2-a4e4-cdedccdcefaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89201
0396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.892010396
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.550758124
Short name T492
Test name
Test status
Simulation time 14494073332 ps
CPU time 984.06 seconds
Started Jan 03 01:37:20 PM PST 24
Finished Jan 03 01:53:57 PM PST 24
Peak memory 272548 kb
Host smart-16e24969-edb8-4024-bd2a-6f01b57d0a07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550758124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.550758124
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1284157262
Short name T11
Test name
Test status
Simulation time 28206146377 ps
CPU time 302.84 seconds
Started Jan 03 01:37:35 PM PST 24
Finished Jan 03 01:42:47 PM PST 24
Peak memory 247316 kb
Host smart-f496e283-40af-4e7e-8260-c80a9f4bac33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284157262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1284157262
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2384299400
Short name T287
Test name
Test status
Simulation time 253063048 ps
CPU time 9.53 seconds
Started Jan 03 01:37:26 PM PST 24
Finished Jan 03 01:37:47 PM PST 24
Peak memory 248784 kb
Host smart-ee24899b-adb2-4c86-9903-e4c022143a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842
99400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2384299400
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2037777769
Short name T412
Test name
Test status
Simulation time 6033049493 ps
CPU time 37.24 seconds
Started Jan 03 01:37:35 PM PST 24
Finished Jan 03 01:38:21 PM PST 24
Peak memory 254516 kb
Host smart-e80c5244-21b8-4329-a9ab-1c7aaa6f7eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20377
77769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2037777769
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1922570710
Short name T415
Test name
Test status
Simulation time 509259603 ps
CPU time 32.41 seconds
Started Jan 03 01:37:35 PM PST 24
Finished Jan 03 01:38:16 PM PST 24
Peak memory 255400 kb
Host smart-81d4de71-b81a-429f-940d-65a5980fd92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19225
70710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1922570710
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1963512287
Short name T448
Test name
Test status
Simulation time 758422684 ps
CPU time 23.14 seconds
Started Jan 03 01:37:34 PM PST 24
Finished Jan 03 01:38:07 PM PST 24
Peak memory 248564 kb
Host smart-394198bd-820f-4d7e-9e15-43ffb8c37b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19635
12287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1963512287
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.981901184
Short name T653
Test name
Test status
Simulation time 585130960 ps
CPU time 26.2 seconds
Started Jan 03 01:37:18 PM PST 24
Finished Jan 03 01:37:59 PM PST 24
Peak memory 248732 kb
Host smart-b95264c3-29fb-4684-920f-036ad5eefdfe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981901184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.981901184
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.280026632
Short name T317
Test name
Test status
Simulation time 61793843601 ps
CPU time 3887.85 seconds
Started Jan 03 01:37:39 PM PST 24
Finished Jan 03 02:42:37 PM PST 24
Peak memory 304844 kb
Host smart-2121ffe7-cd17-4ae5-80ab-f66f6e31bf75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280026632 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.280026632
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4199111784
Short name T496
Test name
Test status
Simulation time 145665411188 ps
CPU time 2346.62 seconds
Started Jan 03 01:37:45 PM PST 24
Finished Jan 03 02:16:59 PM PST 24
Peak memory 288252 kb
Host smart-45c86f88-f358-4aaa-870b-7815b8101f1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199111784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4199111784
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1348400274
Short name T413
Test name
Test status
Simulation time 1700882415 ps
CPU time 53.78 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:38:39 PM PST 24
Peak memory 256204 kb
Host smart-28f0347d-021f-4f3f-8062-807926137ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13484
00274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1348400274
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3891767199
Short name T418
Test name
Test status
Simulation time 4128821963 ps
CPU time 55.33 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:38:41 PM PST 24
Peak memory 248320 kb
Host smart-742b9b84-653c-41a7-8383-4072dc6aea4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38917
67199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3891767199
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1025594194
Short name T372
Test name
Test status
Simulation time 12893810398 ps
CPU time 868.38 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:52:15 PM PST 24
Peak memory 272792 kb
Host smart-533f47ab-e35e-49fc-a5b5-53c801ffa19d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025594194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1025594194
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1153708520
Short name T284
Test name
Test status
Simulation time 16221344639 ps
CPU time 884.24 seconds
Started Jan 03 01:37:52 PM PST 24
Finished Jan 03 01:52:40 PM PST 24
Peak memory 282004 kb
Host smart-bf052ea3-14cb-4255-952d-867bd78c67cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153708520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1153708520
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.371316269
Short name T495
Test name
Test status
Simulation time 152483929 ps
CPU time 10.05 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:37:56 PM PST 24
Peak memory 240624 kb
Host smart-4ff0174b-bb23-4d80-8155-0e0fe88175e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37131
6269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.371316269
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1539010816
Short name T485
Test name
Test status
Simulation time 1919587765 ps
CPU time 60.3 seconds
Started Jan 03 01:37:51 PM PST 24
Finished Jan 03 01:38:55 PM PST 24
Peak memory 254948 kb
Host smart-2d89fa23-a667-4a1b-9827-f2915131cac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15390
10816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1539010816
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.914185428
Short name T318
Test name
Test status
Simulation time 1536546453 ps
CPU time 46.8 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:38:33 PM PST 24
Peak memory 255328 kb
Host smart-c2dedd71-e211-4fca-8cbf-bc81744ab1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91418
5428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.914185428
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.621758672
Short name T511
Test name
Test status
Simulation time 145304837 ps
CPU time 9.91 seconds
Started Jan 03 01:37:50 PM PST 24
Finished Jan 03 01:38:04 PM PST 24
Peak memory 248784 kb
Host smart-87f7818c-9f6d-4b8c-8447-f8e8b7bb5d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62175
8672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.621758672
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3813482872
Short name T101
Test name
Test status
Simulation time 32637457922 ps
CPU time 2085.25 seconds
Started Jan 03 01:37:25 PM PST 24
Finished Jan 03 02:12:22 PM PST 24
Peak memory 288712 kb
Host smart-a0e62224-4997-4361-b80c-6ea84d408f77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813482872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3813482872
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.4192908420
Short name T329
Test name
Test status
Simulation time 59496762120 ps
CPU time 5386.21 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 03:07:31 PM PST 24
Peak memory 353772 kb
Host smart-8d49d46a-2bdf-4a01-ba9d-1de1a60569d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192908420 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.4192908420
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.330465759
Short name T70
Test name
Test status
Simulation time 64178784394 ps
CPU time 1855.15 seconds
Started Jan 03 01:37:52 PM PST 24
Finished Jan 03 02:08:50 PM PST 24
Peak memory 272752 kb
Host smart-09f828b5-fca4-4055-a482-ed7a45f55903
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330465759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.330465759
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2459615217
Short name T552
Test name
Test status
Simulation time 457898748 ps
CPU time 35.8 seconds
Started Jan 03 01:37:35 PM PST 24
Finished Jan 03 01:38:20 PM PST 24
Peak memory 255744 kb
Host smart-09d233a1-6c67-46c2-b352-bbee8c626c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24596
15217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2459615217
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1399011314
Short name T258
Test name
Test status
Simulation time 474713169 ps
CPU time 30.06 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:38:15 PM PST 24
Peak memory 254304 kb
Host smart-cef703c8-295d-495a-85ee-cbf344c40284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
11314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1399011314
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1969195909
Short name T242
Test name
Test status
Simulation time 40407061405 ps
CPU time 1910.92 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 02:09:36 PM PST 24
Peak memory 273116 kb
Host smart-11040294-1563-48ff-959b-6f77dc5bf974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969195909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1969195909
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3589241912
Short name T309
Test name
Test status
Simulation time 319537902118 ps
CPU time 1597.18 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 02:04:25 PM PST 24
Peak memory 272852 kb
Host smart-e778593d-9889-409d-b544-820e7b04a9d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589241912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3589241912
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4267797659
Short name T357
Test name
Test status
Simulation time 110598052414 ps
CPU time 641.29 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:48:28 PM PST 24
Peak memory 255440 kb
Host smart-88ce1a80-49e1-4a5d-9731-e3afc40f9ed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267797659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4267797659
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4172050440
Short name T541
Test name
Test status
Simulation time 111008993 ps
CPU time 12.8 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:37:59 PM PST 24
Peak memory 248608 kb
Host smart-84161a5c-04ac-4ac3-9a2a-69e4b152666e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
50440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4172050440
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.475906407
Short name T121
Test name
Test status
Simulation time 4481587262 ps
CPU time 50.02 seconds
Started Jan 03 01:37:46 PM PST 24
Finished Jan 03 01:38:42 PM PST 24
Peak memory 254900 kb
Host smart-dc5c1407-5b28-4d9f-a1bb-c9c53a57f834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47590
6407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.475906407
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2398541094
Short name T422
Test name
Test status
Simulation time 1555995735 ps
CPU time 54.98 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:38:41 PM PST 24
Peak memory 248676 kb
Host smart-472f08f8-a655-4e84-b60b-452b2dabe9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23985
41094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2398541094
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2574429256
Short name T491
Test name
Test status
Simulation time 4898757841 ps
CPU time 72.6 seconds
Started Jan 03 01:37:51 PM PST 24
Finished Jan 03 01:39:07 PM PST 24
Peak memory 248728 kb
Host smart-d9969207-2d33-4b3c-ad01-a29c712f78ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25744
29256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2574429256
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3626024920
Short name T112
Test name
Test status
Simulation time 23479654421 ps
CPU time 999.98 seconds
Started Jan 03 01:37:37 PM PST 24
Finished Jan 03 01:54:26 PM PST 24
Peak memory 273240 kb
Host smart-3ebf95bf-7e98-4b14-8fe2-836d2f521d41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626024920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3626024920
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2487505484
Short name T261
Test name
Test status
Simulation time 181851849138 ps
CPU time 2563.07 seconds
Started Jan 03 01:37:47 PM PST 24
Finished Jan 03 02:20:36 PM PST 24
Peak memory 284920 kb
Host smart-d43d8533-ab85-4886-818d-64e8132886af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487505484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2487505484
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2933424607
Short name T534
Test name
Test status
Simulation time 17262524842 ps
CPU time 141.57 seconds
Started Jan 03 01:37:47 PM PST 24
Finished Jan 03 01:40:14 PM PST 24
Peak memory 256844 kb
Host smart-986771f3-e5b0-4880-b04c-ec7ac3931d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29334
24607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2933424607
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.893974791
Short name T562
Test name
Test status
Simulation time 630043006 ps
CPU time 31.42 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 01:38:19 PM PST 24
Peak memory 255296 kb
Host smart-b2498ba6-da86-432a-948f-946887eb67dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89397
4791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.893974791
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.412745227
Short name T55
Test name
Test status
Simulation time 18878541370 ps
CPU time 720.25 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 01:49:48 PM PST 24
Peak memory 265096 kb
Host smart-8a594fe7-0f30-4f77-8dd2-ff3ecfdf99ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412745227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.412745227
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1890662001
Short name T480
Test name
Test status
Simulation time 47004879949 ps
CPU time 1344.32 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 02:00:05 PM PST 24
Peak memory 289548 kb
Host smart-434fd60c-3a66-4521-a80b-83e3bcf3bad9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890662001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1890662001
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1659287562
Short name T676
Test name
Test status
Simulation time 9163692058 ps
CPU time 188.82 seconds
Started Jan 03 01:37:39 PM PST 24
Finished Jan 03 01:40:57 PM PST 24
Peak memory 246284 kb
Host smart-65494ff8-7c1d-4d09-af79-8dc78728a527
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659287562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1659287562
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.241484879
Short name T427
Test name
Test status
Simulation time 116853220 ps
CPU time 11.78 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 01:37:59 PM PST 24
Peak memory 248572 kb
Host smart-a04f452f-408f-4652-8a11-53e2abcd7eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24148
4879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.241484879
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1901475498
Short name T548
Test name
Test status
Simulation time 2183901253 ps
CPU time 61.27 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:38:46 PM PST 24
Peak memory 255076 kb
Host smart-3c3bc4cb-169b-4677-9074-707cc7e9af99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19014
75498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1901475498
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1365395075
Short name T563
Test name
Test status
Simulation time 3547316381 ps
CPU time 43.83 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 01:38:24 PM PST 24
Peak memory 248560 kb
Host smart-58fe6aa3-9cac-4d53-803d-ef6d259e7581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
95075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1365395075
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2879134282
Short name T525
Test name
Test status
Simulation time 114428697 ps
CPU time 12.77 seconds
Started Jan 03 01:37:38 PM PST 24
Finished Jan 03 01:38:01 PM PST 24
Peak memory 254996 kb
Host smart-775aaf81-b268-4bb1-a182-9aa594fae0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28791
34282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2879134282
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.578164874
Short name T451
Test name
Test status
Simulation time 269244271392 ps
CPU time 3849.89 seconds
Started Jan 03 01:37:45 PM PST 24
Finished Jan 03 02:42:03 PM PST 24
Peak memory 299920 kb
Host smart-d925d5f4-123b-47ec-978e-1b2529bf6c13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578164874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.578164874
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2006394596
Short name T490
Test name
Test status
Simulation time 68403603059 ps
CPU time 5414.58 seconds
Started Jan 03 01:37:52 PM PST 24
Finished Jan 03 03:08:11 PM PST 24
Peak memory 355352 kb
Host smart-23eb18a8-ab47-4492-b5ff-6f3f58117ffa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006394596 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2006394596
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.288463510
Short name T553
Test name
Test status
Simulation time 29155235222 ps
CPU time 1556.82 seconds
Started Jan 03 01:37:46 PM PST 24
Finished Jan 03 02:03:49 PM PST 24
Peak memory 273176 kb
Host smart-f5383314-2716-4669-805c-f6982d6bef6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288463510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.288463510
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.429420423
Short name T559
Test name
Test status
Simulation time 865197404 ps
CPU time 51.73 seconds
Started Jan 03 01:37:55 PM PST 24
Finished Jan 03 01:38:49 PM PST 24
Peak memory 255808 kb
Host smart-d5181664-71b3-4f30-a080-9523228cdf24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42942
0423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.429420423
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.110947200
Short name T550
Test name
Test status
Simulation time 2701047008 ps
CPU time 41.8 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 01:38:31 PM PST 24
Peak memory 255148 kb
Host smart-1cecdec5-9d23-49b3-a857-9f585b07af71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11094
7200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.110947200
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3295050899
Short name T671
Test name
Test status
Simulation time 21453452899 ps
CPU time 953.65 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 01:53:36 PM PST 24
Peak memory 269416 kb
Host smart-2f9464c4-4552-42c4-b0da-d7f398f8ae3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295050899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3295050899
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2925311963
Short name T350
Test name
Test status
Simulation time 4691709400 ps
CPU time 173.7 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:40:39 PM PST 24
Peak memory 253008 kb
Host smart-f6d681c1-3bb6-4594-827e-65fbb27efe9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925311963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2925311963
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.726480565
Short name T636
Test name
Test status
Simulation time 1286550364 ps
CPU time 66.37 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 01:38:55 PM PST 24
Peak memory 248572 kb
Host smart-28f05b9f-ad13-4f9e-863a-6b8dfd0c68d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72648
0565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.726480565
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.68797923
Short name T394
Test name
Test status
Simulation time 637814681 ps
CPU time 18.33 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 01:38:08 PM PST 24
Peak memory 246456 kb
Host smart-1e962802-1588-4b26-b21d-fd462fc92381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68797
923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.68797923
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2994536454
Short name T58
Test name
Test status
Simulation time 936130509 ps
CPU time 29.95 seconds
Started Jan 03 01:37:51 PM PST 24
Finished Jan 03 01:38:24 PM PST 24
Peak memory 247072 kb
Host smart-1921ccae-6930-41f6-b0ce-4e9cbe46880d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
36454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2994536454
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2507401321
Short name T576
Test name
Test status
Simulation time 2835534326 ps
CPU time 52.47 seconds
Started Jan 03 01:37:39 PM PST 24
Finished Jan 03 01:38:41 PM PST 24
Peak memory 256880 kb
Host smart-ff69d137-0fa3-4c49-9d04-e57df44d1d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074
01321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2507401321
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1654035755
Short name T43
Test name
Test status
Simulation time 59383588547 ps
CPU time 778.52 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 01:50:41 PM PST 24
Peak memory 273192 kb
Host smart-d94c19c8-d3b0-46a5-a841-b30370c0b108
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654035755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1654035755
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1169784054
Short name T306
Test name
Test status
Simulation time 300088960865 ps
CPU time 5566.97 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 03:10:28 PM PST 24
Peak memory 335140 kb
Host smart-cc07ac63-847f-407e-98bc-ece493ab90db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169784054 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1169784054
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1238584845
Short name T730
Test name
Test status
Simulation time 94876603144 ps
CPU time 2504.79 seconds
Started Jan 03 01:37:47 PM PST 24
Finished Jan 03 02:19:38 PM PST 24
Peak memory 287908 kb
Host smart-7cbda4c0-3465-47ae-b6a1-db2ed699f7d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238584845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1238584845
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1320779549
Short name T468
Test name
Test status
Simulation time 2384472499 ps
CPU time 127.83 seconds
Started Jan 03 01:37:52 PM PST 24
Finished Jan 03 01:40:03 PM PST 24
Peak memory 256040 kb
Host smart-aaffe90d-45ef-4e49-a809-31634ea88947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
79549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1320779549
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2520147685
Short name T644
Test name
Test status
Simulation time 610943526 ps
CPU time 15.98 seconds
Started Jan 03 01:37:40 PM PST 24
Finished Jan 03 01:38:06 PM PST 24
Peak memory 254304 kb
Host smart-bd87ef37-aa55-415b-9b16-d199f9f96723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
47685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2520147685
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3256298508
Short name T240
Test name
Test status
Simulation time 43415422851 ps
CPU time 994.93 seconds
Started Jan 03 01:37:42 PM PST 24
Finished Jan 03 01:54:26 PM PST 24
Peak memory 272608 kb
Host smart-0ecb1a32-fc5b-4a53-b813-e0f4a8204d60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256298508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3256298508
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1342447666
Short name T249
Test name
Test status
Simulation time 43662680275 ps
CPU time 801.11 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 01:51:04 PM PST 24
Peak memory 269184 kb
Host smart-f70339f8-f616-4c87-8597-aba759f3837b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342447666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1342447666
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3853829354
Short name T345
Test name
Test status
Simulation time 7985444651 ps
CPU time 321.01 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 01:43:04 PM PST 24
Peak memory 248660 kb
Host smart-a73014dc-60f2-4606-9e85-64ba22367880
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853829354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3853829354
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1829560213
Short name T692
Test name
Test status
Simulation time 815048435 ps
CPU time 48.7 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:38:34 PM PST 24
Peak memory 255420 kb
Host smart-44894fb6-cdf6-4faa-ae04-e8e4f40eef6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18295
60213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1829560213
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2766752463
Short name T466
Test name
Test status
Simulation time 808140245 ps
CPU time 48.13 seconds
Started Jan 03 01:37:46 PM PST 24
Finished Jan 03 01:38:40 PM PST 24
Peak memory 254840 kb
Host smart-c76d318e-4b65-45b2-963e-241ff86d7d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27667
52463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2766752463
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.654942076
Short name T583
Test name
Test status
Simulation time 512949353 ps
CPU time 29.95 seconds
Started Jan 03 01:37:31 PM PST 24
Finished Jan 03 01:38:11 PM PST 24
Peak memory 254360 kb
Host smart-91d67112-4080-4346-9abd-91b21688bf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65494
2076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.654942076
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4120907031
Short name T476
Test name
Test status
Simulation time 6590525582 ps
CPU time 33.86 seconds
Started Jan 03 01:37:30 PM PST 24
Finished Jan 03 01:38:14 PM PST 24
Peak memory 248776 kb
Host smart-d5b322e9-37eb-4946-827a-f220ccdb44a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41209
07031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4120907031
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.407415770
Short name T603
Test name
Test status
Simulation time 34399240668 ps
CPU time 910.58 seconds
Started Jan 03 01:37:50 PM PST 24
Finished Jan 03 01:53:05 PM PST 24
Peak memory 273196 kb
Host smart-ddaf1320-5460-41a6-a66a-19ca67707576
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407415770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.407415770
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3824080762
Short name T420
Test name
Test status
Simulation time 13863180102 ps
CPU time 162.35 seconds
Started Jan 03 01:37:52 PM PST 24
Finished Jan 03 01:40:37 PM PST 24
Peak memory 256200 kb
Host smart-f86c2ad4-894e-464b-ab3b-a89e5b771a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38240
80762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3824080762
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1291352554
Short name T489
Test name
Test status
Simulation time 1130509272 ps
CPU time 21.76 seconds
Started Jan 03 01:37:50 PM PST 24
Finished Jan 03 01:38:16 PM PST 24
Peak memory 254720 kb
Host smart-021d555c-a23e-404a-b3a4-bb11ab01ff36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12913
52554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1291352554
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.796554542
Short name T741
Test name
Test status
Simulation time 42054307172 ps
CPU time 835.31 seconds
Started Jan 03 01:37:50 PM PST 24
Finished Jan 03 01:51:49 PM PST 24
Peak memory 272284 kb
Host smart-940b80c6-d92f-4059-8760-66ac29b78385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796554542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.796554542
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1804853627
Short name T528
Test name
Test status
Simulation time 136448461889 ps
CPU time 1980.92 seconds
Started Jan 03 01:37:44 PM PST 24
Finished Jan 03 02:10:53 PM PST 24
Peak memory 289412 kb
Host smart-d88cd404-dc74-4e49-8b89-13e3fc89c232
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804853627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1804853627
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2493964144
Short name T255
Test name
Test status
Simulation time 2022393578 ps
CPU time 80.81 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 01:39:03 PM PST 24
Peak memory 246512 kb
Host smart-003f2af0-17d3-481d-9dec-f333d9cb1033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493964144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2493964144
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.466966605
Short name T7
Test name
Test status
Simulation time 693060584 ps
CPU time 45.41 seconds
Started Jan 03 01:37:47 PM PST 24
Finished Jan 03 01:38:38 PM PST 24
Peak memory 248620 kb
Host smart-7adf6104-13aa-4df3-b5fd-fe1955ec17f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46696
6605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.466966605
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.211596565
Short name T582
Test name
Test status
Simulation time 955343592 ps
CPU time 54.25 seconds
Started Jan 03 01:37:52 PM PST 24
Finished Jan 03 01:38:50 PM PST 24
Peak memory 255204 kb
Host smart-ef49f294-aade-474f-8f49-e071edf9a27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21159
6565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.211596565
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1835243428
Short name T137
Test name
Test status
Simulation time 453838046 ps
CPU time 30.35 seconds
Started Jan 03 01:37:48 PM PST 24
Finished Jan 03 01:38:23 PM PST 24
Peak memory 254912 kb
Host smart-365b966d-757b-49e7-b43d-43b7e23b2190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352
43428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1835243428
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3284115638
Short name T408
Test name
Test status
Simulation time 8646535261 ps
CPU time 44.87 seconds
Started Jan 03 01:37:36 PM PST 24
Finished Jan 03 01:38:30 PM PST 24
Peak memory 248676 kb
Host smart-4b896341-a6b0-4c47-9747-f0129488b764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32841
15638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3284115638
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1337235570
Short name T467
Test name
Test status
Simulation time 14804462854 ps
CPU time 1721.41 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 02:06:24 PM PST 24
Peak memory 301224 kb
Host smart-b38089f4-8e40-4fa9-ac39-15c8c17a6afb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337235570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1337235570
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3148295189
Short name T65
Test name
Test status
Simulation time 13807191481 ps
CPU time 799.4 seconds
Started Jan 03 01:37:47 PM PST 24
Finished Jan 03 01:51:12 PM PST 24
Peak memory 269060 kb
Host smart-192ce0d9-9a2d-4e53-b5fb-bce126d39f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148295189 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3148295189
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.4268475547
Short name T481
Test name
Test status
Simulation time 47033840011 ps
CPU time 2523.27 seconds
Started Jan 03 01:37:51 PM PST 24
Finished Jan 03 02:19:58 PM PST 24
Peak memory 288756 kb
Host smart-fbeb3f6d-2549-4d29-82d1-01de30964353
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268475547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.4268475547
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1437027648
Short name T637
Test name
Test status
Simulation time 1583991993 ps
CPU time 130.98 seconds
Started Jan 03 01:37:39 PM PST 24
Finished Jan 03 01:39:59 PM PST 24
Peak memory 255780 kb
Host smart-5ec7a5bb-4388-4936-9d71-1ad82ec42875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14370
27648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1437027648
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.758016837
Short name T543
Test name
Test status
Simulation time 51945164 ps
CPU time 2.62 seconds
Started Jan 03 01:37:47 PM PST 24
Finished Jan 03 01:37:55 PM PST 24
Peak memory 238744 kb
Host smart-a2d443d0-c892-4e22-9f14-444068309104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75801
6837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.758016837
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.698529538
Short name T531
Test name
Test status
Simulation time 140879064662 ps
CPU time 1904.96 seconds
Started Jan 03 01:37:39 PM PST 24
Finished Jan 03 02:09:33 PM PST 24
Peak memory 272640 kb
Host smart-a436ed15-257c-4c77-8ec4-7f39fdfd5ed7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698529538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.698529538
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2710925606
Short name T401
Test name
Test status
Simulation time 47521462763 ps
CPU time 1147.43 seconds
Started Jan 03 01:37:45 PM PST 24
Finished Jan 03 01:57:00 PM PST 24
Peak memory 287508 kb
Host smart-efd3a632-60dc-4ab7-830d-b836dc7c9654
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710925606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2710925606
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3851106821
Short name T614
Test name
Test status
Simulation time 17489631113 ps
CPU time 349.95 seconds
Started Jan 03 01:37:46 PM PST 24
Finished Jan 03 01:43:42 PM PST 24
Peak memory 247236 kb
Host smart-8952243f-b645-4b18-9f6e-e56fd467d218
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851106821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3851106821
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3307502450
Short name T441
Test name
Test status
Simulation time 246579080 ps
CPU time 16.21 seconds
Started Jan 03 01:37:32 PM PST 24
Finished Jan 03 01:37:58 PM PST 24
Peak memory 255396 kb
Host smart-1d0f120e-aef2-44b0-8007-aaf524dbf9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33075
02450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3307502450
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3638152893
Short name T141
Test name
Test status
Simulation time 184327114 ps
CPU time 21.01 seconds
Started Jan 03 01:37:29 PM PST 24
Finished Jan 03 01:38:01 PM PST 24
Peak memory 254484 kb
Host smart-dc29cf61-e140-4c49-a2cd-57e53ce3b2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36381
52893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3638152893
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1147693792
Short name T39
Test name
Test status
Simulation time 331798473 ps
CPU time 35.59 seconds
Started Jan 03 01:37:33 PM PST 24
Finished Jan 03 01:38:18 PM PST 24
Peak memory 248660 kb
Host smart-79e12cb7-ceaa-47e5-bd37-899c1b8d2cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11476
93792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1147693792
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2298568603
Short name T731
Test name
Test status
Simulation time 7429995388 ps
CPU time 183.58 seconds
Started Jan 03 01:37:27 PM PST 24
Finished Jan 03 01:40:42 PM PST 24
Peak memory 256824 kb
Host smart-127ebb5f-024e-4e68-939a-92834f9dd57a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298568603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2298568603
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3631464997
Short name T634
Test name
Test status
Simulation time 46192226003 ps
CPU time 2891.58 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 02:26:28 PM PST 24
Peak memory 289728 kb
Host smart-9870bdaf-af1a-4154-9c7a-1f17297d7c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631464997 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3631464997
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1792323216
Short name T521
Test name
Test status
Simulation time 199933280979 ps
CPU time 1323.77 seconds
Started Jan 03 01:38:07 PM PST 24
Finished Jan 03 02:00:13 PM PST 24
Peak memory 283140 kb
Host smart-9f4e09c6-e39c-40a4-8ec2-d3c975bb8bca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792323216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1792323216
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3120778170
Short name T706
Test name
Test status
Simulation time 14284894925 ps
CPU time 46.38 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 01:39:30 PM PST 24
Peak memory 255760 kb
Host smart-82b19ac5-e692-4610-83c2-ea66fefcd0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
78170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3120778170
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3890572425
Short name T578
Test name
Test status
Simulation time 238825384 ps
CPU time 20.38 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 01:38:36 PM PST 24
Peak memory 254272 kb
Host smart-1895eaf2-66df-48e5-8510-16f0a7a56790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38905
72425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3890572425
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4263458320
Short name T668
Test name
Test status
Simulation time 21693078666 ps
CPU time 1623.64 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 02:05:21 PM PST 24
Peak memory 289072 kb
Host smart-382e8fbe-aab2-443a-bc2b-43e2175da05f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263458320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4263458320
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4285007970
Short name T601
Test name
Test status
Simulation time 115728577486 ps
CPU time 1715.19 seconds
Started Jan 03 01:38:17 PM PST 24
Finished Jan 03 02:06:56 PM PST 24
Peak memory 272056 kb
Host smart-189f10a0-84a5-42bc-affa-85dfba4204af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285007970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4285007970
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.32981408
Short name T274
Test name
Test status
Simulation time 42969338273 ps
CPU time 424.85 seconds
Started Jan 03 01:38:09 PM PST 24
Finished Jan 03 01:45:17 PM PST 24
Peak memory 247588 kb
Host smart-7ba40d8e-b45a-4ae6-b251-87763cc141fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32981408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.32981408
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1528573379
Short name T24
Test name
Test status
Simulation time 529273110 ps
CPU time 14.57 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 01:38:31 PM PST 24
Peak memory 248668 kb
Host smart-8827f2af-a3dd-448b-b99b-7eb79e9f4cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15285
73379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1528573379
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2207348720
Short name T464
Test name
Test status
Simulation time 156108816 ps
CPU time 3.92 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:38:41 PM PST 24
Peak memory 238436 kb
Host smart-f678eb0b-a7c6-4aaa-a95f-e005d397c40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22073
48720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2207348720
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1819574934
Short name T331
Test name
Test status
Simulation time 123069190 ps
CPU time 5.26 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 01:38:20 PM PST 24
Peak memory 239512 kb
Host smart-27e5fb37-dcc9-4ee2-96dc-7c271095e9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
74934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1819574934
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1481969943
Short name T641
Test name
Test status
Simulation time 640097116 ps
CPU time 21.64 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 01:38:38 PM PST 24
Peak memory 248620 kb
Host smart-0dfe3460-123b-4012-9f27-1f49467c1d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
69943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1481969943
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2697840036
Short name T540
Test name
Test status
Simulation time 59393177261 ps
CPU time 3281.8 seconds
Started Jan 03 01:38:10 PM PST 24
Finished Jan 03 02:32:55 PM PST 24
Peak memory 288804 kb
Host smart-0836a49d-1b4f-44c3-a9c0-3f5da2f2c689
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697840036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2697840036
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1962897347
Short name T488
Test name
Test status
Simulation time 17234419322 ps
CPU time 1842.23 seconds
Started Jan 03 01:38:13 PM PST 24
Finished Jan 03 02:09:00 PM PST 24
Peak memory 297804 kb
Host smart-94b297b7-d92e-4720-af4c-3470cf1f2fca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962897347 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1962897347
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2404972156
Short name T217
Test name
Test status
Simulation time 20468531 ps
CPU time 2.05 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:36:29 PM PST 24
Peak memory 248892 kb
Host smart-b678c0b3-53a2-44a5-bd12-b0c93fe041c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2404972156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2404972156
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3305411787
Short name T452
Test name
Test status
Simulation time 84458033037 ps
CPU time 1346.56 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:58:20 PM PST 24
Peak memory 272068 kb
Host smart-b21a5346-e966-4bc8-aab5-28323a67c431
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305411787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3305411787
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2137222179
Short name T596
Test name
Test status
Simulation time 2492772079 ps
CPU time 20.91 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 01:36:47 PM PST 24
Peak memory 240488 kb
Host smart-e9c25800-6721-47f6-b92c-6e4bf55271b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2137222179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2137222179
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1751136488
Short name T434
Test name
Test status
Simulation time 30987269961 ps
CPU time 158.99 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 01:38:30 PM PST 24
Peak memory 255964 kb
Host smart-68791e35-9e28-4621-b355-6c414feccd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17511
36488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1751136488
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1485371586
Short name T590
Test name
Test status
Simulation time 1731456994 ps
CPU time 29.1 seconds
Started Jan 03 01:35:50 PM PST 24
Finished Jan 03 01:36:28 PM PST 24
Peak memory 255296 kb
Host smart-e5ad8cfb-64c0-42c9-bec7-541017d3907e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
71586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1485371586
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1006960203
Short name T245
Test name
Test status
Simulation time 6744078138 ps
CPU time 236.8 seconds
Started Jan 03 01:35:50 PM PST 24
Finished Jan 03 01:39:57 PM PST 24
Peak memory 247472 kb
Host smart-de95959e-2cda-45c4-ba9c-691204bcda97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006960203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1006960203
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1387393783
Short name T423
Test name
Test status
Simulation time 276328025 ps
CPU time 10.54 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:36:00 PM PST 24
Peak memory 253548 kb
Host smart-43c47402-feb4-410e-a531-fb1609112975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13873
93783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1387393783
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3604742645
Short name T430
Test name
Test status
Simulation time 771098147 ps
CPU time 52.66 seconds
Started Jan 03 01:36:06 PM PST 24
Finished Jan 03 01:37:09 PM PST 24
Peak memory 254848 kb
Host smart-877f9a5e-da30-4e3b-8759-e73023f74e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36047
42645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3604742645
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1349712336
Short name T14
Test name
Test status
Simulation time 2683478500 ps
CPU time 67.51 seconds
Started Jan 03 01:35:49 PM PST 24
Finished Jan 03 01:37:06 PM PST 24
Peak memory 273436 kb
Host smart-8d92d740-4f70-40a0-9fcd-d6454e65b9fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1349712336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1349712336
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.452967962
Short name T687
Test name
Test status
Simulation time 443442340 ps
CPU time 22.83 seconds
Started Jan 03 01:35:46 PM PST 24
Finished Jan 03 01:36:17 PM PST 24
Peak memory 254540 kb
Host smart-a18f633a-20af-46d3-a486-8f463aae5997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45296
7962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.452967962
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.334001054
Short name T276
Test name
Test status
Simulation time 27824949868 ps
CPU time 1686.72 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 02:04:30 PM PST 24
Peak memory 289232 kb
Host smart-e21441fe-c8ee-4e32-a2e7-2f047a4135ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334001054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.334001054
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1752207652
Short name T130
Test name
Test status
Simulation time 102797530072 ps
CPU time 5850.29 seconds
Started Jan 03 01:35:50 PM PST 24
Finished Jan 03 03:13:30 PM PST 24
Peak memory 322044 kb
Host smart-657d87e2-32d1-4b87-ab03-b988252cdd21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752207652 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1752207652
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3773203105
Short name T557
Test name
Test status
Simulation time 36840488113 ps
CPU time 772.62 seconds
Started Jan 03 01:38:09 PM PST 24
Finished Jan 03 01:51:05 PM PST 24
Peak memory 266000 kb
Host smart-a1173ed8-c428-41d4-80a9-76277d55ec09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773203105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3773203105
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2117018747
Short name T487
Test name
Test status
Simulation time 3875752733 ps
CPU time 69.96 seconds
Started Jan 03 01:38:10 PM PST 24
Finished Jan 03 01:39:23 PM PST 24
Peak memory 256352 kb
Host smart-0047ee6a-be54-4a28-98d6-7aeb0c99ba3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21170
18747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2117018747
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1254959788
Short name T94
Test name
Test status
Simulation time 6941676114 ps
CPU time 66.42 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 01:39:23 PM PST 24
Peak memory 248216 kb
Host smart-71f6d58c-79d1-4512-a394-452c297f5962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12549
59788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1254959788
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1938491325
Short name T587
Test name
Test status
Simulation time 171401233734 ps
CPU time 2199.3 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 02:15:17 PM PST 24
Peak memory 285044 kb
Host smart-1d60bfd8-c874-412c-a95f-1477be56a591
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938491325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1938491325
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.654717646
Short name T477
Test name
Test status
Simulation time 128714099303 ps
CPU time 1739.1 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 02:07:15 PM PST 24
Peak memory 271988 kb
Host smart-e2377bd0-ca1f-4d8f-9cb0-4d7edb50952b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654717646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.654717646
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3469055401
Short name T470
Test name
Test status
Simulation time 837949231 ps
CPU time 20.97 seconds
Started Jan 03 01:38:08 PM PST 24
Finished Jan 03 01:38:32 PM PST 24
Peak memory 248600 kb
Host smart-ab7e7678-9316-4569-ab51-6ea83f4c55e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
55401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3469055401
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.914983932
Short name T64
Test name
Test status
Simulation time 777109792 ps
CPU time 28.08 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 01:38:45 PM PST 24
Peak memory 247944 kb
Host smart-b6273479-2f17-4605-ad0d-43342162d77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91498
3932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.914983932
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.927358424
Short name T57
Test name
Test status
Simulation time 807890760 ps
CPU time 46.47 seconds
Started Jan 03 01:38:10 PM PST 24
Finished Jan 03 01:39:00 PM PST 24
Peak memory 246832 kb
Host smart-e7364268-dfd6-494d-9dc9-5653000dd4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92735
8424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.927358424
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4247917745
Short name T675
Test name
Test status
Simulation time 455738744 ps
CPU time 25.87 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 01:38:41 PM PST 24
Peak memory 248660 kb
Host smart-de6b1968-210e-439f-8e5d-00036c2005a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42479
17745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4247917745
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4114745564
Short name T322
Test name
Test status
Simulation time 63668755807 ps
CPU time 1696.41 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 02:07:03 PM PST 24
Peak memory 299892 kb
Host smart-51609bb0-d368-481c-b879-92e9c262531a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114745564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4114745564
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2721819524
Short name T482
Test name
Test status
Simulation time 78572788638 ps
CPU time 3750.91 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 02:40:49 PM PST 24
Peak memory 337004 kb
Host smart-37e9528b-9e55-425d-b575-30fe4d9571ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721819524 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2721819524
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3106770174
Short name T597
Test name
Test status
Simulation time 157704015443 ps
CPU time 2025.37 seconds
Started Jan 03 01:38:15 PM PST 24
Finished Jan 03 02:12:05 PM PST 24
Peak memory 289520 kb
Host smart-844a3b33-d44c-4901-b444-88829d4ce9c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106770174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3106770174
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.675880503
Short name T52
Test name
Test status
Simulation time 10572161668 ps
CPU time 179.73 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:41:37 PM PST 24
Peak memory 256844 kb
Host smart-e79f8e2a-6daa-4521-bd6d-9d1c24dde4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67588
0503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.675880503
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.4247297262
Short name T453
Test name
Test status
Simulation time 977433005 ps
CPU time 54.25 seconds
Started Jan 03 01:38:38 PM PST 24
Finished Jan 03 01:39:43 PM PST 24
Peak memory 254976 kb
Host smart-1fe5ef6d-0a63-4403-9e7b-26c15611cdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42472
97262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.4247297262
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3853690303
Short name T363
Test name
Test status
Simulation time 8345338816 ps
CPU time 849.18 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:52:46 PM PST 24
Peak memory 272508 kb
Host smart-f4619389-a9b7-40ba-960f-decc3b9d680e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853690303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3853690303
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3271292183
Short name T673
Test name
Test status
Simulation time 195584940823 ps
CPU time 2376.87 seconds
Started Jan 03 01:38:38 PM PST 24
Finished Jan 03 02:18:28 PM PST 24
Peak memory 282304 kb
Host smart-c839ed0d-6b67-4eb5-8f0c-21bf91471cbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271292183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3271292183
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1873780806
Short name T56
Test name
Test status
Simulation time 426101395 ps
CPU time 17.39 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:38:55 PM PST 24
Peak memory 248552 kb
Host smart-36f4a222-7387-45cd-98b4-d0e479506da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18737
80806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1873780806
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1456580188
Short name T554
Test name
Test status
Simulation time 1626860075 ps
CPU time 38.17 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 01:39:14 PM PST 24
Peak memory 256004 kb
Host smart-6cd2b779-050d-4752-8251-57642ec347ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14565
80188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1456580188
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.126753636
Short name T604
Test name
Test status
Simulation time 93688755 ps
CPU time 11.01 seconds
Started Jan 03 01:38:13 PM PST 24
Finished Jan 03 01:38:29 PM PST 24
Peak memory 254396 kb
Host smart-e48aaedf-ee7d-4ded-8eeb-93aaf9218b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12675
3636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.126753636
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3008393996
Short name T705
Test name
Test status
Simulation time 629515911 ps
CPU time 33.97 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 01:39:17 PM PST 24
Peak memory 248724 kb
Host smart-760c9291-f397-4519-a622-89d488f209f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30083
93996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3008393996
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2683606471
Short name T300
Test name
Test status
Simulation time 56063607765 ps
CPU time 3043.58 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 02:29:23 PM PST 24
Peak memory 289368 kb
Host smart-6c34f9d0-b4ef-4c13-b64c-663bc575b5c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683606471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2683606471
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3365970993
Short name T328
Test name
Test status
Simulation time 214336975138 ps
CPU time 5549.13 seconds
Started Jan 03 01:39:02 PM PST 24
Finished Jan 03 03:11:33 PM PST 24
Peak memory 338120 kb
Host smart-a1f68ee1-30d0-4fa0-9eb3-bece6ef5c413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365970993 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3365970993
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3407431792
Short name T289
Test name
Test status
Simulation time 85411792870 ps
CPU time 1312.22 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 02:00:41 PM PST 24
Peak memory 281472 kb
Host smart-bdef0e39-4361-4009-bd65-5a458b8367c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407431792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3407431792
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1621209811
Short name T685
Test name
Test status
Simulation time 1038613303 ps
CPU time 97.32 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 01:40:17 PM PST 24
Peak memory 256772 kb
Host smart-fae34c6b-2326-40a3-8744-fb4f633f5c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16212
09811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1621209811
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1147046634
Short name T307
Test name
Test status
Simulation time 1116544734 ps
CPU time 33.99 seconds
Started Jan 03 01:39:04 PM PST 24
Finished Jan 03 01:39:40 PM PST 24
Peak memory 254136 kb
Host smart-216f6b71-c428-46e7-8872-3024d55fea39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11470
46634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1147046634
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1844695116
Short name T374
Test name
Test status
Simulation time 116055391745 ps
CPU time 1498.46 seconds
Started Jan 03 01:39:02 PM PST 24
Finished Jan 03 02:04:02 PM PST 24
Peak memory 272960 kb
Host smart-3ffbbe2b-1815-4da8-b503-5bdbfeec3e4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844695116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1844695116
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.695662527
Short name T532
Test name
Test status
Simulation time 17951944901 ps
CPU time 1225.22 seconds
Started Jan 03 01:38:39 PM PST 24
Finished Jan 03 01:59:16 PM PST 24
Peak memory 273288 kb
Host smart-2b9cfa31-2f6a-46bf-b26f-df14f7ff96f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695662527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.695662527
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1378518161
Short name T336
Test name
Test status
Simulation time 31061834827 ps
CPU time 546.79 seconds
Started Jan 03 01:39:02 PM PST 24
Finished Jan 03 01:48:11 PM PST 24
Peak memory 247280 kb
Host smart-ba080619-9367-4ffe-a25c-20285148b004
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378518161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1378518161
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1315711349
Short name T660
Test name
Test status
Simulation time 5035553134 ps
CPU time 57.69 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 01:39:40 PM PST 24
Peak memory 256332 kb
Host smart-928547a4-f92f-42e9-8bbc-22c81ed007ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13157
11349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1315711349
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1258158053
Short name T538
Test name
Test status
Simulation time 861911096 ps
CPU time 55.26 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 01:39:42 PM PST 24
Peak memory 255004 kb
Host smart-fb281715-9792-4ca3-90af-6df47c7ba9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
58053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1258158053
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1560222090
Short name T475
Test name
Test status
Simulation time 179718419 ps
CPU time 21.31 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 01:39:04 PM PST 24
Peak memory 247808 kb
Host smart-a6ed6741-b40f-43b6-8811-29bd3c2bbd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15602
22090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1560222090
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2843562086
Short name T473
Test name
Test status
Simulation time 248078671 ps
CPU time 13.82 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:38:53 PM PST 24
Peak memory 248528 kb
Host smart-55ca7bb6-fcf7-470a-8ad5-5a1d1bb191ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
62086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2843562086
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.941863873
Short name T591
Test name
Test status
Simulation time 264580188307 ps
CPU time 3275.34 seconds
Started Jan 03 01:39:00 PM PST 24
Finished Jan 03 02:33:37 PM PST 24
Peak memory 289420 kb
Host smart-18e36134-9560-456b-ac09-8a4a178ef5c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941863873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.941863873
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.300734226
Short name T76
Test name
Test status
Simulation time 7537728025 ps
CPU time 774.29 seconds
Started Jan 03 01:39:09 PM PST 24
Finished Jan 03 01:52:04 PM PST 24
Peak memory 266160 kb
Host smart-8b908c7f-5809-427e-9356-7430affc3520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300734226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.300734226
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.286791776
Short name T437
Test name
Test status
Simulation time 3619307112 ps
CPU time 110.73 seconds
Started Jan 03 01:39:31 PM PST 24
Finished Jan 03 01:41:30 PM PST 24
Peak memory 256024 kb
Host smart-ec7a4fb8-b656-4675-b989-efa03f64b874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28679
1776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.286791776
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3491969898
Short name T547
Test name
Test status
Simulation time 775595184 ps
CPU time 28.05 seconds
Started Jan 03 01:38:54 PM PST 24
Finished Jan 03 01:39:26 PM PST 24
Peak memory 254824 kb
Host smart-65c701f6-13e7-4214-9693-8e4583a162ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34919
69898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3491969898
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.199295190
Short name T368
Test name
Test status
Simulation time 11229712024 ps
CPU time 1106.32 seconds
Started Jan 03 01:39:03 PM PST 24
Finished Jan 03 01:57:32 PM PST 24
Peak memory 273120 kb
Host smart-5f550823-573a-40f1-9f53-315d168453d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199295190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.199295190
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1631369689
Short name T116
Test name
Test status
Simulation time 18844904527 ps
CPU time 1086.19 seconds
Started Jan 03 01:39:27 PM PST 24
Finished Jan 03 01:57:41 PM PST 24
Peak memory 265052 kb
Host smart-9813545b-32bd-46a9-afb6-6e8b42b5966e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631369689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1631369689
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.507426038
Short name T293
Test name
Test status
Simulation time 1338991880 ps
CPU time 59.81 seconds
Started Jan 03 01:39:14 PM PST 24
Finished Jan 03 01:40:15 PM PST 24
Peak memory 248628 kb
Host smart-9e4c5fae-8c2c-4861-8c75-be2ce0d90728
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507426038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.507426038
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2009150754
Short name T71
Test name
Test status
Simulation time 5223021179 ps
CPU time 31.89 seconds
Started Jan 03 01:38:39 PM PST 24
Finished Jan 03 01:39:24 PM PST 24
Peak memory 248724 kb
Host smart-720519da-9ad5-46c1-aa39-5362f7945b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20091
50754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2009150754
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2482324103
Short name T479
Test name
Test status
Simulation time 73076132 ps
CPU time 5.66 seconds
Started Jan 03 01:38:56 PM PST 24
Finished Jan 03 01:39:04 PM PST 24
Peak memory 238660 kb
Host smart-43561221-a16c-48a6-8743-c843ee3a260e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24823
24103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2482324103
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2636542662
Short name T100
Test name
Test status
Simulation time 1379028447 ps
CPU time 47.61 seconds
Started Jan 03 01:38:56 PM PST 24
Finished Jan 03 01:39:46 PM PST 24
Peak memory 248536 kb
Host smart-a9a33cee-8484-4693-8aa8-e5c2069362b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26365
42662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2636542662
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4036482844
Short name T96
Test name
Test status
Simulation time 659502230 ps
CPU time 26.49 seconds
Started Jan 03 01:38:38 PM PST 24
Finished Jan 03 01:39:15 PM PST 24
Peak memory 248728 kb
Host smart-ecf9b30d-c4c5-497e-89f8-8fade1cd7582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
82844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4036482844
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.470109016
Short name T323
Test name
Test status
Simulation time 75115840607 ps
CPU time 2123.39 seconds
Started Jan 03 01:39:36 PM PST 24
Finished Jan 03 02:15:08 PM PST 24
Peak memory 282428 kb
Host smart-85f9a4b2-7421-4d2c-ad54-a4088ba7a37f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470109016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.470109016
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.121150687
Short name T25
Test name
Test status
Simulation time 73784610801 ps
CPU time 1142.95 seconds
Started Jan 03 01:39:13 PM PST 24
Finished Jan 03 01:58:17 PM PST 24
Peak memory 273296 kb
Host smart-91844c0f-e891-494c-871e-0720386bf24c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121150687 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.121150687
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1404987074
Short name T510
Test name
Test status
Simulation time 7621180102 ps
CPU time 205.45 seconds
Started Jan 03 01:38:08 PM PST 24
Finished Jan 03 01:41:36 PM PST 24
Peak memory 256196 kb
Host smart-a69fe6d5-d9e8-4574-aa8e-463d6b3adad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
87074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1404987074
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3608878428
Short name T1
Test name
Test status
Simulation time 372167890 ps
CPU time 19.97 seconds
Started Jan 03 01:38:10 PM PST 24
Finished Jan 03 01:38:33 PM PST 24
Peak memory 255080 kb
Host smart-5651c7a3-15fd-4a43-9809-66774f3423ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36088
78428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3608878428
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3245851246
Short name T628
Test name
Test status
Simulation time 161947449828 ps
CPU time 2661.88 seconds
Started Jan 03 01:38:09 PM PST 24
Finished Jan 03 02:22:34 PM PST 24
Peak memory 288820 kb
Host smart-2540d085-2dee-449b-be0b-758a86cd572d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245851246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3245851246
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2928152845
Short name T710
Test name
Test status
Simulation time 28248560030 ps
CPU time 676.6 seconds
Started Jan 03 01:38:09 PM PST 24
Finished Jan 03 01:49:29 PM PST 24
Peak memory 272052 kb
Host smart-9290b872-2bea-4622-84a9-3abcd6cf64ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928152845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2928152845
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.218540148
Short name T9
Test name
Test status
Simulation time 5043011085 ps
CPU time 200.37 seconds
Started Jan 03 01:38:12 PM PST 24
Finished Jan 03 01:41:37 PM PST 24
Peak memory 248564 kb
Host smart-db197ffb-a927-4047-80b8-17ca8e1f5dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218540148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.218540148
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.255205970
Short name T390
Test name
Test status
Simulation time 1072824010 ps
CPU time 64.9 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 01:39:19 PM PST 24
Peak memory 248636 kb
Host smart-29892c76-01d3-46f6-87b0-055544f6c88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
5970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.255205970
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2731689580
Short name T720
Test name
Test status
Simulation time 129994285 ps
CPU time 13.49 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 01:38:50 PM PST 24
Peak memory 248588 kb
Host smart-f3a760ad-9b84-4c1d-9d74-0130cf466dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27316
89580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2731689580
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.333689314
Short name T131
Test name
Test status
Simulation time 732361573 ps
CPU time 20.91 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:38:59 PM PST 24
Peak memory 256724 kb
Host smart-d6d3bc28-9567-4c2c-9558-26b68eb2f421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33368
9314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.333689314
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1609632921
Short name T458
Test name
Test status
Simulation time 608172214 ps
CPU time 17.09 seconds
Started Jan 03 01:38:08 PM PST 24
Finished Jan 03 01:38:28 PM PST 24
Peak memory 248704 kb
Host smart-5b834d04-f909-48f8-a19b-6be972e7cca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16096
32921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1609632921
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1851339680
Short name T129
Test name
Test status
Simulation time 22346974937 ps
CPU time 503.84 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 01:47:12 PM PST 24
Peak memory 265100 kb
Host smart-749babb9-ff90-460e-8f0b-18bb9543c1ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851339680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1851339680
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.910237572
Short name T113
Test name
Test status
Simulation time 59599423191 ps
CPU time 3690.16 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 02:40:09 PM PST 24
Peak memory 314540 kb
Host smart-846d20a2-4db4-473e-902d-4766bfd40c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910237572 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.910237572
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3789650191
Short name T88
Test name
Test status
Simulation time 12920936850 ps
CPU time 1117.3 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:57:16 PM PST 24
Peak memory 288492 kb
Host smart-5212cb70-7b42-4c48-bcf2-5a82759d4a8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789650191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3789650191
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.654181866
Short name T530
Test name
Test status
Simulation time 4664984647 ps
CPU time 247.66 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:42:46 PM PST 24
Peak memory 256816 kb
Host smart-f9d31285-7d6a-40ea-9225-86c733bc1ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65418
1866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.654181866
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3546072743
Short name T105
Test name
Test status
Simulation time 1033161841 ps
CPU time 61.69 seconds
Started Jan 03 01:38:39 PM PST 24
Finished Jan 03 01:39:53 PM PST 24
Peak memory 254976 kb
Host smart-ca6c336e-d967-46b6-baa1-6625bfc04695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35460
72743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3546072743
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4245473381
Short name T349
Test name
Test status
Simulation time 74838609778 ps
CPU time 1335.97 seconds
Started Jan 03 01:38:39 PM PST 24
Finished Jan 03 02:01:08 PM PST 24
Peak memory 272744 kb
Host smart-2a3d8bf0-4b88-4158-b113-11d86ed73657
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245473381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4245473381
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3133664257
Short name T672
Test name
Test status
Simulation time 10594511929 ps
CPU time 1117.18 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:57:15 PM PST 24
Peak memory 288820 kb
Host smart-917de51f-2fb7-4e4e-9218-8e061c1509c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133664257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3133664257
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2081612474
Short name T253
Test name
Test status
Simulation time 53958581211 ps
CPU time 232.03 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 01:42:31 PM PST 24
Peak memory 247532 kb
Host smart-d6b4b1bd-000c-48b3-bda9-18c9031116e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081612474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2081612474
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2093381996
Short name T662
Test name
Test status
Simulation time 1564182368 ps
CPU time 46.5 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 01:39:23 PM PST 24
Peak memory 254996 kb
Host smart-3036be49-3803-4f89-b6e8-508cae2a6a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20933
81996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2093381996
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.494456275
Short name T396
Test name
Test status
Simulation time 558413936 ps
CPU time 16.48 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:38:54 PM PST 24
Peak memory 254300 kb
Host smart-e5799b45-ac35-4e46-8fce-b89662a7e5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49445
6275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.494456275
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2477549901
Short name T595
Test name
Test status
Simulation time 1937627024 ps
CPU time 31.72 seconds
Started Jan 03 01:38:32 PM PST 24
Finished Jan 03 01:39:06 PM PST 24
Peak memory 255332 kb
Host smart-7424fbf0-5b81-430c-b2cd-2c7b83ab009f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24775
49901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2477549901
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2490995828
Short name T296
Test name
Test status
Simulation time 495276059 ps
CPU time 29.6 seconds
Started Jan 03 01:38:40 PM PST 24
Finished Jan 03 01:39:22 PM PST 24
Peak memory 256868 kb
Host smart-41af38fe-165a-4f61-b763-6470bb3f8b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909
95828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2490995828
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2021738114
Short name T539
Test name
Test status
Simulation time 67752539855 ps
CPU time 1903.16 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 02:10:29 PM PST 24
Peak memory 286052 kb
Host smart-dd1813de-2bb2-4950-b329-2ea1fc079af8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021738114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2021738114
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.68903789
Short name T684
Test name
Test status
Simulation time 14895100203 ps
CPU time 992.94 seconds
Started Jan 03 01:38:40 PM PST 24
Finished Jan 03 01:55:25 PM PST 24
Peak memory 273408 kb
Host smart-5c88d738-5251-433b-9153-c38f3bc3f7b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68903789 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.68903789
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2672584099
Short name T469
Test name
Test status
Simulation time 48449899693 ps
CPU time 2687.75 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 02:23:03 PM PST 24
Peak memory 289392 kb
Host smart-718a60af-5088-4f99-aa95-ecf37c8c3305
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672584099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2672584099
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1313909372
Short name T513
Test name
Test status
Simulation time 2814029552 ps
CPU time 180 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 01:41:16 PM PST 24
Peak memory 256292 kb
Host smart-0eb8abaf-494a-4408-8363-9189fb760a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13139
09372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1313909372
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2685435815
Short name T392
Test name
Test status
Simulation time 650035692 ps
CPU time 19.14 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:38:57 PM PST 24
Peak memory 254264 kb
Host smart-f86916ac-f3f3-4ffb-aa80-26787788e015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26854
35815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2685435815
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1593633316
Short name T286
Test name
Test status
Simulation time 47789219387 ps
CPU time 2467.12 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 02:19:44 PM PST 24
Peak memory 289560 kb
Host smart-51229da5-9be3-4b51-b8d4-50a5647c0c92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593633316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1593633316
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3049791586
Short name T608
Test name
Test status
Simulation time 27085646887 ps
CPU time 653.55 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 01:49:30 PM PST 24
Peak memory 265140 kb
Host smart-87e485d6-1fc3-4dda-ad66-053d36f0fe6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049791586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3049791586
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4152167854
Short name T734
Test name
Test status
Simulation time 2544740107 ps
CPU time 96.1 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 01:39:52 PM PST 24
Peak memory 247528 kb
Host smart-c4d5f7ff-08a5-4071-84c5-27cb68817562
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152167854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4152167854
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3290562475
Short name T546
Test name
Test status
Simulation time 2751189234 ps
CPU time 33.54 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 01:39:22 PM PST 24
Peak memory 254484 kb
Host smart-e68915fc-0764-4017-bf6f-43476220deb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32905
62475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3290562475
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3976068900
Short name T246
Test name
Test status
Simulation time 156453339 ps
CPU time 5.96 seconds
Started Jan 03 01:39:04 PM PST 24
Finished Jan 03 01:39:12 PM PST 24
Peak memory 238688 kb
Host smart-757fc0c0-432c-4cf1-b7ab-2f230055fca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39760
68900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3976068900
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2507608491
Short name T474
Test name
Test status
Simulation time 141030345 ps
CPU time 9.7 seconds
Started Jan 03 01:38:10 PM PST 24
Finished Jan 03 01:38:23 PM PST 24
Peak memory 246836 kb
Host smart-97e0e120-3828-4c13-876f-496920c01d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25076
08491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2507608491
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.520213744
Short name T606
Test name
Test status
Simulation time 51610618 ps
CPU time 6.56 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:38:45 PM PST 24
Peak memory 248592 kb
Host smart-c34db3f4-0019-4dcd-90cb-50ccec200267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52021
3744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.520213744
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2048083134
Short name T733
Test name
Test status
Simulation time 24822862887 ps
CPU time 1608.58 seconds
Started Jan 03 01:38:32 PM PST 24
Finished Jan 03 02:05:22 PM PST 24
Peak memory 283316 kb
Host smart-297a4107-ce07-4c34-8b21-55c37d484393
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048083134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2048083134
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.4172262731
Short name T266
Test name
Test status
Simulation time 11157322870 ps
CPU time 920.04 seconds
Started Jan 03 01:38:13 PM PST 24
Finished Jan 03 01:53:38 PM PST 24
Peak memory 272716 kb
Host smart-da5f560d-93e7-440e-89dd-7d3237b55d60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172262731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.4172262731
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.862310840
Short name T659
Test name
Test status
Simulation time 304178902 ps
CPU time 26.34 seconds
Started Jan 03 01:38:13 PM PST 24
Finished Jan 03 01:38:44 PM PST 24
Peak memory 255224 kb
Host smart-8e797b86-30d9-4228-8ec9-5d1a731bc184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86231
0840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.862310840
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.181548867
Short name T472
Test name
Test status
Simulation time 324163321 ps
CPU time 27.81 seconds
Started Jan 03 01:38:15 PM PST 24
Finished Jan 03 01:38:47 PM PST 24
Peak memory 255092 kb
Host smart-e1f23a45-6ce7-4c0a-92cd-f1754fd1147f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18154
8867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.181548867
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3893880746
Short name T361
Test name
Test status
Simulation time 164151165472 ps
CPU time 2161.3 seconds
Started Jan 03 01:38:15 PM PST 24
Finished Jan 03 02:14:20 PM PST 24
Peak memory 281080 kb
Host smart-696047af-b574-4994-9ef9-077498a04624
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893880746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3893880746
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.825040153
Short name T565
Test name
Test status
Simulation time 79648179468 ps
CPU time 904.24 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:53:42 PM PST 24
Peak memory 272880 kb
Host smart-9afb7627-22e7-408b-bec5-1cdc9bf94461
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825040153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.825040153
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2548165285
Short name T686
Test name
Test status
Simulation time 4180265520 ps
CPU time 165.79 seconds
Started Jan 03 01:38:41 PM PST 24
Finished Jan 03 01:41:38 PM PST 24
Peak memory 248624 kb
Host smart-f23a6b9f-6aec-4a81-932e-92fb3d3b76c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548165285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2548165285
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2315366456
Short name T702
Test name
Test status
Simulation time 171878195 ps
CPU time 17.48 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 01:38:54 PM PST 24
Peak memory 248608 kb
Host smart-b85e1b94-5445-4414-9a89-25ba94c76ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23153
66456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2315366456
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2839860621
Short name T500
Test name
Test status
Simulation time 503426666 ps
CPU time 13.87 seconds
Started Jan 03 01:38:11 PM PST 24
Finished Jan 03 01:38:30 PM PST 24
Peak memory 246856 kb
Host smart-cc52b40f-bf38-469a-a3cd-417d2e466c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28398
60621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2839860621
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3964680803
Short name T561
Test name
Test status
Simulation time 663578116 ps
CPU time 18.49 seconds
Started Jan 03 01:38:33 PM PST 24
Finished Jan 03 01:38:54 PM PST 24
Peak memory 255276 kb
Host smart-2b299a72-433c-4dea-bd6e-2125ba6ebda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39646
80803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3964680803
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1591448535
Short name T393
Test name
Test status
Simulation time 1562269701 ps
CPU time 52.77 seconds
Started Jan 03 01:38:13 PM PST 24
Finished Jan 03 01:39:10 PM PST 24
Peak memory 255380 kb
Host smart-a8c858c1-b684-4883-8581-4a50bdff4816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
48535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1591448535
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1559227946
Short name T667
Test name
Test status
Simulation time 84569326607 ps
CPU time 5358.29 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 03:08:07 PM PST 24
Peak memory 317352 kb
Host smart-7bf9349d-65e5-43d5-b2ca-a0f120cb0e44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559227946 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1559227946
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2807757302
Short name T523
Test name
Test status
Simulation time 13605387709 ps
CPU time 1080.69 seconds
Started Jan 03 01:38:36 PM PST 24
Finished Jan 03 01:56:45 PM PST 24
Peak memory 288780 kb
Host smart-1e622089-03a3-4613-be2d-7624d49d3569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807757302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2807757302
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2256968807
Short name T503
Test name
Test status
Simulation time 6386273486 ps
CPU time 182.8 seconds
Started Jan 03 01:38:37 PM PST 24
Finished Jan 03 01:41:51 PM PST 24
Peak memory 256872 kb
Host smart-19d223bd-3f48-4b99-8548-04d92650648f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
68807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2256968807
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.353994860
Short name T107
Test name
Test status
Simulation time 512313027 ps
CPU time 25.02 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:39:03 PM PST 24
Peak memory 248588 kb
Host smart-85015443-fbe1-445d-8862-53c6215c2eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35399
4860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.353994860
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3620467579
Short name T8
Test name
Test status
Simulation time 16823519941 ps
CPU time 1372.08 seconds
Started Jan 03 01:39:03 PM PST 24
Finished Jan 03 02:01:58 PM PST 24
Peak memory 288516 kb
Host smart-1ba5711b-72ed-4a14-95ac-26c729e7cfca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620467579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3620467579
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2105811253
Short name T537
Test name
Test status
Simulation time 8545514118 ps
CPU time 641.37 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:49:20 PM PST 24
Peak memory 264868 kb
Host smart-fa4e2ee6-f7af-45e3-b1a5-e884e9c4891b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105811253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2105811253
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3427179744
Short name T119
Test name
Test status
Simulation time 5036457302 ps
CPU time 201.92 seconds
Started Jan 03 01:39:02 PM PST 24
Finished Jan 03 01:42:25 PM PST 24
Peak memory 246536 kb
Host smart-802ad2fa-bfbc-4f61-808f-ac52ca0ea282
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427179744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3427179744
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.103481621
Short name T680
Test name
Test status
Simulation time 628308660 ps
CPU time 36.72 seconds
Started Jan 03 01:38:34 PM PST 24
Finished Jan 03 01:39:14 PM PST 24
Peak memory 248644 kb
Host smart-4f4a650a-5dc5-446b-80c2-190b274effc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10348
1621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.103481621
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4106042573
Short name T106
Test name
Test status
Simulation time 617044331 ps
CPU time 32.55 seconds
Started Jan 03 01:38:38 PM PST 24
Finished Jan 03 01:39:24 PM PST 24
Peak memory 247128 kb
Host smart-82eaf584-3d48-4962-9144-3da2d1d5b168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41060
42573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4106042573
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2424310181
Short name T90
Test name
Test status
Simulation time 617693930 ps
CPU time 38.4 seconds
Started Jan 03 01:38:35 PM PST 24
Finished Jan 03 01:39:17 PM PST 24
Peak memory 255336 kb
Host smart-c31a9eb9-27d9-4e2e-ab25-463d2f37df10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
10181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2424310181
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2842573011
Short name T421
Test name
Test status
Simulation time 1395180968 ps
CPU time 22.53 seconds
Started Jan 03 01:38:38 PM PST 24
Finished Jan 03 01:39:12 PM PST 24
Peak memory 248676 kb
Host smart-f3dd1e84-4602-4e48-9dc3-ba9b29f6b399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
73011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2842573011
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1205668315
Short name T626
Test name
Test status
Simulation time 8510980755 ps
CPU time 908.79 seconds
Started Jan 03 01:39:02 PM PST 24
Finished Jan 03 01:54:13 PM PST 24
Peak memory 289508 kb
Host smart-82e97eb5-32c2-4b78-a731-2d875120af86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205668315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1205668315
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1834456176
Short name T51
Test name
Test status
Simulation time 93437644539 ps
CPU time 2570.46 seconds
Started Jan 03 01:39:02 PM PST 24
Finished Jan 03 02:21:55 PM PST 24
Peak memory 306084 kb
Host smart-f8b9828e-ee84-4354-a6c1-6a9fc2e1ea49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834456176 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1834456176
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1412121806
Short name T6
Test name
Test status
Simulation time 211159738723 ps
CPU time 1057.89 seconds
Started Jan 03 01:39:14 PM PST 24
Finished Jan 03 01:56:53 PM PST 24
Peak memory 286820 kb
Host smart-8a425f48-ea88-46d2-a7d5-a7560efcaa19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412121806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1412121806
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1920906706
Short name T406
Test name
Test status
Simulation time 1730449233 ps
CPU time 71.47 seconds
Started Jan 03 01:39:03 PM PST 24
Finished Jan 03 01:40:17 PM PST 24
Peak memory 255888 kb
Host smart-af624d95-c9fb-4cf1-b8f8-f53c7a96a189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19209
06706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1920906706
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1072739721
Short name T49
Test name
Test status
Simulation time 265671455 ps
CPU time 21.75 seconds
Started Jan 03 01:38:38 PM PST 24
Finished Jan 03 01:39:10 PM PST 24
Peak memory 248532 kb
Host smart-606c1df7-6343-4ca3-93de-9292f26ef4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10727
39721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1072739721
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.411404823
Short name T375
Test name
Test status
Simulation time 35745052338 ps
CPU time 1219.18 seconds
Started Jan 03 01:39:28 PM PST 24
Finished Jan 03 01:59:54 PM PST 24
Peak memory 273264 kb
Host smart-9045e7dc-67ea-4394-a25f-70cdf5cb725a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411404823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.411404823
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1365964318
Short name T260
Test name
Test status
Simulation time 60528083141 ps
CPU time 1078.85 seconds
Started Jan 03 01:39:31 PM PST 24
Finished Jan 03 01:57:38 PM PST 24
Peak memory 272360 kb
Host smart-be74893c-0019-4258-bac5-27b6cc19d692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365964318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1365964318
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2576420049
Short name T629
Test name
Test status
Simulation time 41015534688 ps
CPU time 411.22 seconds
Started Jan 03 01:39:14 PM PST 24
Finished Jan 03 01:46:06 PM PST 24
Peak memory 247496 kb
Host smart-56cefc9a-4686-4752-b227-59f38dba6963
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576420049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2576420049
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3036505861
Short name T638
Test name
Test status
Simulation time 1246864352 ps
CPU time 64.83 seconds
Started Jan 03 01:38:54 PM PST 24
Finished Jan 03 01:40:03 PM PST 24
Peak memory 248660 kb
Host smart-af187157-d7a5-4589-bc3a-36bd3cd770c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30365
05861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3036505861
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2844769993
Short name T59
Test name
Test status
Simulation time 1194857069 ps
CPU time 12.35 seconds
Started Jan 03 01:38:40 PM PST 24
Finished Jan 03 01:39:04 PM PST 24
Peak memory 252952 kb
Host smart-8d9da327-a9ea-42cd-8e16-5bb86b501cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28447
69993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2844769993
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.368637270
Short name T298
Test name
Test status
Simulation time 232795675 ps
CPU time 7.84 seconds
Started Jan 03 01:39:04 PM PST 24
Finished Jan 03 01:39:14 PM PST 24
Peak memory 248696 kb
Host smart-31b4bd8f-4cec-4c00-8acf-8bcba35a7341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36863
7270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.368637270
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3108895502
Short name T703
Test name
Test status
Simulation time 3548796107 ps
CPU time 59.21 seconds
Started Jan 03 01:39:03 PM PST 24
Finished Jan 03 01:40:04 PM PST 24
Peak memory 256384 kb
Host smart-d005133e-5807-4d07-835a-5e99579758ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31088
95502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3108895502
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3974720309
Short name T104
Test name
Test status
Simulation time 113342552046 ps
CPU time 3321.91 seconds
Started Jan 03 01:39:13 PM PST 24
Finished Jan 03 02:34:37 PM PST 24
Peak memory 304624 kb
Host smart-edefde29-a198-4653-9923-0308c863f275
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974720309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3974720309
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3853159026
Short name T649
Test name
Test status
Simulation time 276306197537 ps
CPU time 1650.85 seconds
Started Jan 03 01:39:28 PM PST 24
Finished Jan 03 02:07:08 PM PST 24
Peak memory 289800 kb
Host smart-7cce61f1-f7d8-4c14-a559-c411e49168d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853159026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3853159026
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1138584706
Short name T214
Test name
Test status
Simulation time 16709111 ps
CPU time 2.67 seconds
Started Jan 03 01:36:18 PM PST 24
Finished Jan 03 01:36:46 PM PST 24
Peak memory 248876 kb
Host smart-a1a3ee90-a3f3-4a69-afd1-7d3b2cd809e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1138584706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1138584706
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3611543244
Short name T264
Test name
Test status
Simulation time 26162516516 ps
CPU time 1583.01 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 02:02:49 PM PST 24
Peak memory 273048 kb
Host smart-2e4ec381-9282-49a7-94f3-9edd8841c3f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611543244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3611543244
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3621502782
Short name T416
Test name
Test status
Simulation time 1753233380 ps
CPU time 16.56 seconds
Started Jan 03 01:36:52 PM PST 24
Finished Jan 03 01:37:32 PM PST 24
Peak memory 248512 kb
Host smart-f0146e91-7faa-4717-808b-b439ae2e2e73
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3621502782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3621502782
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.658348088
Short name T709
Test name
Test status
Simulation time 25621455864 ps
CPU time 227.58 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 01:40:13 PM PST 24
Peak memory 256208 kb
Host smart-f79fcdc8-0c25-48f9-ac8c-086ae2228035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65834
8088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.658348088
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1613132702
Short name T103
Test name
Test status
Simulation time 937382974 ps
CPU time 30.48 seconds
Started Jan 03 01:36:14 PM PST 24
Finished Jan 03 01:37:00 PM PST 24
Peak memory 248328 kb
Host smart-3195dd0d-bbba-421e-94de-b732e6db5f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
32702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1613132702
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2562522156
Short name T63
Test name
Test status
Simulation time 35132513534 ps
CPU time 1531.54 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 02:01:57 PM PST 24
Peak memory 281384 kb
Host smart-f1614b64-18fd-4aac-a42d-05e73aa396db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562522156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2562522156
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.138780941
Short name T118
Test name
Test status
Simulation time 122178665797 ps
CPU time 1748.1 seconds
Started Jan 03 01:36:32 PM PST 24
Finished Jan 03 02:06:08 PM PST 24
Peak memory 272660 kb
Host smart-0d83a07b-6e8a-45d8-b893-14146f28989b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138780941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.138780941
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.63197408
Short name T351
Test name
Test status
Simulation time 5574805743 ps
CPU time 233.3 seconds
Started Jan 03 01:36:16 PM PST 24
Finished Jan 03 01:40:30 PM PST 24
Peak memory 248604 kb
Host smart-9127141d-ba75-45ee-b827-0da9bbb1d5e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63197408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.63197408
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3139455806
Short name T238
Test name
Test status
Simulation time 558450051 ps
CPU time 16.92 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 01:36:41 PM PST 24
Peak memory 254220 kb
Host smart-1f55df76-b1b8-404a-a4dd-0c78762d0bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31394
55806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3139455806
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1883903779
Short name T2
Test name
Test status
Simulation time 64344294 ps
CPU time 5.38 seconds
Started Jan 03 01:36:14 PM PST 24
Finished Jan 03 01:36:32 PM PST 24
Peak memory 238708 kb
Host smart-d82368b7-bdd9-47c4-a109-f794cb4358a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
03779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1883903779
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.821447536
Short name T508
Test name
Test status
Simulation time 188672880 ps
CPU time 20.41 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:36:44 PM PST 24
Peak memory 248524 kb
Host smart-e22a0165-16d8-4d90-80c8-25541186f3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82144
7536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.821447536
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.331138903
Short name T41
Test name
Test status
Simulation time 358512351 ps
CPU time 18.78 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 01:36:45 PM PST 24
Peak memory 248696 kb
Host smart-1ea4d319-5e71-4a99-8f96-b97d2957f0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33113
8903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.331138903
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2365507263
Short name T679
Test name
Test status
Simulation time 49708112561 ps
CPU time 2644.84 seconds
Started Jan 03 01:36:52 PM PST 24
Finished Jan 03 02:21:21 PM PST 24
Peak memory 281472 kb
Host smart-ff0a5550-4ad4-4251-b194-c44b16689069
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365507263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2365507263
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4203878463
Short name T619
Test name
Test status
Simulation time 60217366031 ps
CPU time 3094.57 seconds
Started Jan 03 01:36:19 PM PST 24
Finished Jan 03 02:28:19 PM PST 24
Peak memory 322040 kb
Host smart-eab72fb7-f08e-4fdf-a290-8ddaa1fa16f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203878463 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4203878463
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1476220231
Short name T218
Test name
Test status
Simulation time 21917012 ps
CPU time 2.8 seconds
Started Jan 03 01:35:46 PM PST 24
Finished Jan 03 01:35:57 PM PST 24
Peak memory 248864 kb
Host smart-51c15d54-bbf6-4e05-9412-ee412a0a5918
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1476220231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1476220231
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2541349284
Short name T661
Test name
Test status
Simulation time 239508232149 ps
CPU time 1337.21 seconds
Started Jan 03 01:36:16 PM PST 24
Finished Jan 03 01:58:53 PM PST 24
Peak memory 273036 kb
Host smart-3ee1f618-c0c4-4257-a7cc-689dc654fbe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541349284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2541349284
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1760722045
Short name T593
Test name
Test status
Simulation time 6631459409 ps
CPU time 73.38 seconds
Started Jan 03 01:37:11 PM PST 24
Finished Jan 03 01:38:43 PM PST 24
Peak memory 248664 kb
Host smart-d66052c6-078c-4276-b7db-375fbfa3fb91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1760722045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1760722045
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2282391228
Short name T707
Test name
Test status
Simulation time 5678124875 ps
CPU time 320.18 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 01:42:51 PM PST 24
Peak memory 256196 kb
Host smart-6e52350a-aa38-4cc8-afee-d5db066a385a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22823
91228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2282391228
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3822748758
Short name T732
Test name
Test status
Simulation time 1537239203 ps
CPU time 59.29 seconds
Started Jan 03 01:36:51 PM PST 24
Finished Jan 03 01:38:14 PM PST 24
Peak memory 248696 kb
Host smart-30f1e691-ded4-4592-8641-711b83829ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
48758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3822748758
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1743131805
Short name T341
Test name
Test status
Simulation time 45957378844 ps
CPU time 924.04 seconds
Started Jan 03 01:37:16 PM PST 24
Finished Jan 03 01:52:56 PM PST 24
Peak memory 272716 kb
Host smart-33717bcd-1f51-47d1-83ae-bd6b5337bb2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743131805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1743131805
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1584714410
Short name T645
Test name
Test status
Simulation time 24763234464 ps
CPU time 1284.59 seconds
Started Jan 03 01:37:14 PM PST 24
Finished Jan 03 01:58:55 PM PST 24
Peak memory 286380 kb
Host smart-7cb473f4-3b58-4f9d-9477-f280fee71312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584714410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1584714410
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1266850920
Short name T346
Test name
Test status
Simulation time 12291790073 ps
CPU time 492.24 seconds
Started Jan 03 01:36:31 PM PST 24
Finished Jan 03 01:45:11 PM PST 24
Peak memory 247572 kb
Host smart-0073da3f-f29d-4028-96f6-15e99cd5e18e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266850920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1266850920
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3799213821
Short name T69
Test name
Test status
Simulation time 1508343661 ps
CPU time 26.58 seconds
Started Jan 03 01:36:54 PM PST 24
Finished Jan 03 01:37:44 PM PST 24
Peak memory 248656 kb
Host smart-92b45eca-88f0-4e61-bf78-29bbc5bc44b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37992
13821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3799213821
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3718722523
Short name T122
Test name
Test status
Simulation time 205389534 ps
CPU time 8.69 seconds
Started Jan 03 01:36:20 PM PST 24
Finished Jan 03 01:36:55 PM PST 24
Peak memory 239912 kb
Host smart-b7ba9d2f-d589-457e-9125-932c3b3e80f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37187
22523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3718722523
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2933938763
Short name T639
Test name
Test status
Simulation time 194249949 ps
CPU time 18.03 seconds
Started Jan 03 01:37:08 PM PST 24
Finished Jan 03 01:37:45 PM PST 24
Peak memory 255220 kb
Host smart-ec775d3a-8d16-4599-bc10-efb4dfbc91e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
38763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2933938763
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1810578142
Short name T455
Test name
Test status
Simulation time 248165828 ps
CPU time 23.03 seconds
Started Jan 03 01:37:08 PM PST 24
Finished Jan 03 01:37:50 PM PST 24
Peak memory 248676 kb
Host smart-7388d761-9580-40f6-be68-446f67b0e4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18105
78142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1810578142
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1451362218
Short name T305
Test name
Test status
Simulation time 46763744266 ps
CPU time 1045.58 seconds
Started Jan 03 01:37:13 PM PST 24
Finished Jan 03 01:54:56 PM PST 24
Peak memory 282496 kb
Host smart-0c28c80e-5e82-45a6-8470-3c4767fd2599
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451362218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1451362218
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.4083117670
Short name T277
Test name
Test status
Simulation time 76611841902 ps
CPU time 1946.39 seconds
Started Jan 03 01:36:55 PM PST 24
Finished Jan 03 02:09:44 PM PST 24
Peak memory 306084 kb
Host smart-15ab62ba-05cf-40c8-a9b0-7b14f4c54f7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083117670 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.4083117670
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3952859753
Short name T227
Test name
Test status
Simulation time 46094680 ps
CPU time 4.28 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 01:36:28 PM PST 24
Peak memory 248904 kb
Host smart-77c91d41-8ba2-4912-8ec3-2580ce9732d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3952859753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3952859753
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.808568523
Short name T42
Test name
Test status
Simulation time 20809020242 ps
CPU time 1002.96 seconds
Started Jan 03 01:36:07 PM PST 24
Finished Jan 03 01:53:01 PM PST 24
Peak memory 289056 kb
Host smart-6f1b8cb9-af87-46a7-91ee-8e6e93264618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808568523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.808568523
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1507546869
Short name T243
Test name
Test status
Simulation time 810706849 ps
CPU time 35.78 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 01:37:02 PM PST 24
Peak memory 240496 kb
Host smart-3dadbd37-c789-4463-9e97-c016f34e394b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1507546869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1507546869
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.740328907
Short name T297
Test name
Test status
Simulation time 4143837396 ps
CPU time 85.29 seconds
Started Jan 03 01:36:03 PM PST 24
Finished Jan 03 01:37:33 PM PST 24
Peak memory 248396 kb
Host smart-5401266f-dec4-4f76-8c1d-73cb6d13369f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74032
8907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.740328907
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.230662621
Short name T522
Test name
Test status
Simulation time 331706283 ps
CPU time 27.37 seconds
Started Jan 03 01:35:44 PM PST 24
Finished Jan 03 01:36:18 PM PST 24
Peak memory 254632 kb
Host smart-e96d02fc-3418-459d-ba88-d2bc0a1f58a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23066
2621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.230662621
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4032215170
Short name T269
Test name
Test status
Simulation time 15339429195 ps
CPU time 824.82 seconds
Started Jan 03 01:35:45 PM PST 24
Finished Jan 03 01:49:38 PM PST 24
Peak memory 272596 kb
Host smart-430bc99f-dccb-4479-8468-916521231fe0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032215170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4032215170
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.668132362
Short name T445
Test name
Test status
Simulation time 57731138517 ps
CPU time 1264.05 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:57:28 PM PST 24
Peak memory 272280 kb
Host smart-9f576d37-36a5-4f89-9eca-a992b74e2edd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668132362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.668132362
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3424176481
Short name T337
Test name
Test status
Simulation time 17971426391 ps
CPU time 391.76 seconds
Started Jan 03 01:36:11 PM PST 24
Finished Jan 03 01:42:55 PM PST 24
Peak memory 247300 kb
Host smart-de0ed22a-4e4e-4b9d-871b-4edc149713d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424176481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3424176481
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3487657879
Short name T395
Test name
Test status
Simulation time 208287422 ps
CPU time 7.13 seconds
Started Jan 03 01:35:43 PM PST 24
Finished Jan 03 01:35:57 PM PST 24
Peak memory 248568 kb
Host smart-89a88327-13f5-4549-bad2-125e836e3035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34876
57879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3487657879
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2536577441
Short name T212
Test name
Test status
Simulation time 28585563 ps
CPU time 2.96 seconds
Started Jan 03 01:37:17 PM PST 24
Finished Jan 03 01:37:35 PM PST 24
Peak memory 238664 kb
Host smart-68da1ec6-6cb2-4501-8d7f-ba03a66d3cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25365
77441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2536577441
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3896505895
Short name T79
Test name
Test status
Simulation time 2877097809 ps
CPU time 41.71 seconds
Started Jan 03 01:36:09 PM PST 24
Finished Jan 03 01:37:05 PM PST 24
Peak memory 255656 kb
Host smart-eaf7f05a-0503-4864-b9b6-fe1ffa3a6433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38965
05895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3896505895
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3468989875
Short name T425
Test name
Test status
Simulation time 2379357007 ps
CPU time 36.05 seconds
Started Jan 03 01:35:46 PM PST 24
Finished Jan 03 01:36:29 PM PST 24
Peak memory 248644 kb
Host smart-968c0360-bb65-4a4a-828e-8fc49248a22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34689
89875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3468989875
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3909182982
Short name T275
Test name
Test status
Simulation time 25041465570 ps
CPU time 1711.37 seconds
Started Jan 03 01:35:49 PM PST 24
Finished Jan 03 02:04:29 PM PST 24
Peak memory 305532 kb
Host smart-ff8feee3-808b-4e28-a16b-aedd7e6ad428
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909182982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3909182982
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1283916197
Short name T642
Test name
Test status
Simulation time 70417893902 ps
CPU time 2821.3 seconds
Started Jan 03 01:35:49 PM PST 24
Finished Jan 03 02:22:59 PM PST 24
Peak memory 314060 kb
Host smart-ef06d1d8-b3e5-455b-bbf9-0a4f30b9930b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283916197 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1283916197
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3538262624
Short name T224
Test name
Test status
Simulation time 44959597 ps
CPU time 3.79 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:36:27 PM PST 24
Peak memory 248876 kb
Host smart-7b45b4c2-4f1a-43cd-8167-bf83c2e2e11a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3538262624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3538262624
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1036240810
Short name T727
Test name
Test status
Simulation time 34742633846 ps
CPU time 848.86 seconds
Started Jan 03 01:36:08 PM PST 24
Finished Jan 03 01:50:32 PM PST 24
Peak memory 283428 kb
Host smart-ccc717c7-1557-414d-9a3a-3211ca05a07c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036240810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1036240810
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1485770127
Short name T536
Test name
Test status
Simulation time 222005260 ps
CPU time 11.63 seconds
Started Jan 03 01:36:18 PM PST 24
Finished Jan 03 01:36:54 PM PST 24
Peak memory 240452 kb
Host smart-b437e417-8910-46cd-a305-f5f0116042d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1485770127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1485770127
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.517246037
Short name T450
Test name
Test status
Simulation time 6524972437 ps
CPU time 212.05 seconds
Started Jan 03 01:35:48 PM PST 24
Finished Jan 03 01:39:29 PM PST 24
Peak memory 256808 kb
Host smart-bfc718f3-222b-424b-86a7-09b65c6898f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51724
6037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.517246037
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.342680938
Short name T440
Test name
Test status
Simulation time 791034714 ps
CPU time 14.49 seconds
Started Jan 03 01:35:50 PM PST 24
Finished Jan 03 01:36:13 PM PST 24
Peak memory 253588 kb
Host smart-530e78ee-6c5b-41dd-af5e-cd128c4b5283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34268
0938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.342680938
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1582216837
Short name T371
Test name
Test status
Simulation time 61193585694 ps
CPU time 1481.46 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 02:01:08 PM PST 24
Peak memory 288168 kb
Host smart-d5a724a0-4600-4de1-8fe9-749102ddc7c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582216837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1582216837
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2160400491
Short name T580
Test name
Test status
Simulation time 45366777752 ps
CPU time 919.17 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 01:51:45 PM PST 24
Peak memory 273316 kb
Host smart-f300a188-3299-4b5b-8a8a-ac500131d69b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160400491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2160400491
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.928511052
Short name T356
Test name
Test status
Simulation time 15659178805 ps
CPU time 162.43 seconds
Started Jan 03 01:36:14 PM PST 24
Finished Jan 03 01:39:11 PM PST 24
Peak memory 247440 kb
Host smart-19a82541-1aa3-431c-813b-327ca6aa7d29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928511052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.928511052
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3762300254
Short name T498
Test name
Test status
Simulation time 137330191 ps
CPU time 5.79 seconds
Started Jan 03 01:35:50 PM PST 24
Finished Jan 03 01:36:05 PM PST 24
Peak memory 248648 kb
Host smart-0668c47d-b6a4-4db6-aed9-f159be39b9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37623
00254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3762300254
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1658918192
Short name T701
Test name
Test status
Simulation time 247220033 ps
CPU time 26.77 seconds
Started Jan 03 01:35:50 PM PST 24
Finished Jan 03 01:36:26 PM PST 24
Peak memory 247040 kb
Host smart-a9c7b956-cb94-4988-9609-79677a9cf85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16589
18192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1658918192
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.263582493
Short name T446
Test name
Test status
Simulation time 1002561628 ps
CPU time 29.21 seconds
Started Jan 03 01:36:13 PM PST 24
Finished Jan 03 01:36:55 PM PST 24
Peak memory 247804 kb
Host smart-a331ecb5-1acd-4f1d-81b5-eef9ac5cfbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26358
2493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.263582493
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.4169434701
Short name T588
Test name
Test status
Simulation time 506695135 ps
CPU time 9.81 seconds
Started Jan 03 01:35:48 PM PST 24
Finished Jan 03 01:36:06 PM PST 24
Peak memory 256700 kb
Host smart-4c199ac4-8f74-451f-8b71-9472c7985346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41694
34701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.4169434701
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1056278928
Short name T21
Test name
Test status
Simulation time 2896649416 ps
CPU time 164.33 seconds
Started Jan 03 01:36:12 PM PST 24
Finished Jan 03 01:39:10 PM PST 24
Peak memory 256824 kb
Host smart-5a59d203-1bf5-4a4f-8058-386aa324cda8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056278928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1056278928
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.150451398
Short name T319
Test name
Test status
Simulation time 30907287611 ps
CPU time 3305.2 seconds
Started Jan 03 01:35:47 PM PST 24
Finished Jan 03 02:31:01 PM PST 24
Peak memory 322016 kb
Host smart-d6527b4b-eda7-4a33-ac26-5c87f76f4c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150451398 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.150451398
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.343130605
Short name T229
Test name
Test status
Simulation time 37385010 ps
CPU time 2.17 seconds
Started Jan 03 01:36:14 PM PST 24
Finished Jan 03 01:36:29 PM PST 24
Peak memory 248856 kb
Host smart-ffb495ae-8eec-465c-8c21-ec810c96ef68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=343130605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.343130605
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.729191639
Short name T126
Test name
Test status
Simulation time 38431622535 ps
CPU time 2280.94 seconds
Started Jan 03 01:36:15 PM PST 24
Finished Jan 03 02:14:34 PM PST 24
Peak memory 289332 kb
Host smart-25e940b1-0a6b-4adb-84e1-4cddfea52992
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729191639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.729191639
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3277581398
Short name T567
Test name
Test status
Simulation time 1016314297 ps
CPU time 41.55 seconds
Started Jan 03 01:36:33 PM PST 24
Finished Jan 03 01:37:43 PM PST 24
Peak memory 240388 kb
Host smart-f61e5258-6b22-471b-977d-57aac1ea94ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3277581398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3277581398
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1481447319
Short name T691
Test name
Test status
Simulation time 8885515037 ps
CPU time 121.92 seconds
Started Jan 03 01:36:14 PM PST 24
Finished Jan 03 01:38:29 PM PST 24
Peak memory 248224 kb
Host smart-08810f2b-777e-4fe6-852d-4c990ae4bbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
47319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1481447319
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4104993143
Short name T95
Test name
Test status
Simulation time 756177160 ps
CPU time 45.64 seconds
Started Jan 03 01:36:16 PM PST 24
Finished Jan 03 01:37:22 PM PST 24
Peak memory 255036 kb
Host smart-20f3505a-56b7-48c9-8c32-a55a65013618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41049
93143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4104993143
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3819133363
Short name T696
Test name
Test status
Simulation time 149958961153 ps
CPU time 2253.41 seconds
Started Jan 03 01:36:16 PM PST 24
Finished Jan 03 02:14:10 PM PST 24
Peak memory 288752 kb
Host smart-b03ad5fc-b598-4c39-9b99-3b272cd23aa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819133363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3819133363
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3601207157
Short name T514
Test name
Test status
Simulation time 106806089966 ps
CPU time 1841.55 seconds
Started Jan 03 01:36:53 PM PST 24
Finished Jan 03 02:07:59 PM PST 24
Peak memory 289056 kb
Host smart-7cef242b-9e08-42e6-9f05-d17fb05ec168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601207157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3601207157
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4113213051
Short name T342
Test name
Test status
Simulation time 10157745897 ps
CPU time 408.32 seconds
Started Jan 03 01:36:17 PM PST 24
Finished Jan 03 01:43:26 PM PST 24
Peak memory 247560 kb
Host smart-642d4431-01aa-40b8-964f-1f249b96bf29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113213051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4113213051
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3647408887
Short name T560
Test name
Test status
Simulation time 216976218 ps
CPU time 18.22 seconds
Started Jan 03 01:36:19 PM PST 24
Finished Jan 03 01:37:03 PM PST 24
Peak memory 255040 kb
Host smart-07e418fd-6a7b-40f9-af54-1c8808648f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36474
08887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3647408887
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1827616547
Short name T135
Test name
Test status
Simulation time 2433514574 ps
CPU time 14.33 seconds
Started Jan 03 01:36:16 PM PST 24
Finished Jan 03 01:36:51 PM PST 24
Peak memory 248384 kb
Host smart-78d58cf4-c758-449e-9008-f7ff59199ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18276
16547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1827616547
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2913203753
Short name T569
Test name
Test status
Simulation time 2877427556 ps
CPU time 18.73 seconds
Started Jan 03 01:36:53 PM PST 24
Finished Jan 03 01:37:35 PM PST 24
Peak memory 246900 kb
Host smart-e55aebba-8278-4035-a42e-9c24a2fbaca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29132
03753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2913203753
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2525343310
Short name T586
Test name
Test status
Simulation time 1125110558 ps
CPU time 19.95 seconds
Started Jan 03 01:36:15 PM PST 24
Finished Jan 03 01:36:55 PM PST 24
Peak memory 248644 kb
Host smart-d5c86dff-11fd-4c90-bba2-99ab36dad1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25253
43310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2525343310
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.78552061
Short name T325
Test name
Test status
Simulation time 30234678188 ps
CPU time 1409.77 seconds
Started Jan 03 01:36:55 PM PST 24
Finished Jan 03 02:00:47 PM PST 24
Peak memory 289204 kb
Host smart-87508f62-8a43-423c-bb05-6af8b9fbd306
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78552061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handl
er_stress_all.78552061
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2953055837
Short name T726
Test name
Test status
Simulation time 189836112930 ps
CPU time 3057.32 seconds
Started Jan 03 01:36:51 PM PST 24
Finished Jan 03 02:28:12 PM PST 24
Peak memory 306152 kb
Host smart-1a7e87c3-f03b-4e0d-a5a3-f8f44743c472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953055837 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2953055837
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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