Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	116308	1			T6	33		T7	29		T15	4
class_i[0x1]	93998	1			T6	8		T7	234		T15	4242
class_i[0x2]	65864	1			T6	390		T7	611		T16	2
class_i[0x3]	81465	1			T6	7		T18	6		T5	2460

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	86983	1			T6	77		T18	1		T5	639
alert[0x1]	89568	1			T6	27		T5	616		T7	210
alert[0x2]	88227	1			T6	11		T18	5		T5	589
alert[0x3]	92857	1			T6	323		T5	616		T7	249

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

357337

1

T6

438

T18

6

T5

2460

esc_ping_fail

298

1

T8

7

T9

8

T10

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	86895	1			T6	77		T18	1		T5	639
esc_integrity_fail	alert[0x1]	89493	1			T6	27		T5	616		T7	210
esc_integrity_fail	alert[0x2]	88162	1			T6	11		T18	5		T5	589
esc_integrity_fail	alert[0x3]	92787	1			T6	323		T5	616		T7	249
esc_ping_fail	alert[0x0]	88	1			T8	3		T9	2		T75	3
esc_ping_fail	alert[0x1]	75	1			T8	1		T9	2		T10	3
esc_ping_fail	alert[0x2]	65	1			T8	2		T9	2		T10	1
esc_ping_fail	alert[0x3]	70	1			T8	1		T9	2		T10	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	116243	1			T6	33		T7	29		T15	4
esc_integrity_fail	class_i[0x1]	93896	1			T6	8		T7	234		T15	4242
esc_integrity_fail	class_i[0x2]	65789	1			T6	390		T7	611		T16	2
esc_integrity_fail	class_i[0x3]	81409	1			T6	7		T18	6		T5	2460
esc_ping_fail	class_i[0x0]	65	1			T8	6		T307	3		T301	1
esc_ping_fail	class_i[0x1]	102	1			T8	1		T9	8		T10	1
esc_ping_fail	class_i[0x2]	75	1			T10	5		T44	1		T113	1
esc_ping_fail	class_i[0x3]	56	1			T216	1		T298	10		T304	1