Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	203	1			T4	1		T18	1		T7	8
index[0x1]	192	1			T18	1		T7	2		T15	1
index[0x2]	166	1			T6	1		T18	1		T5	1
index[0x3]	213	1			T4	1		T18	1		T7	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	241	1			T4	1		T7	3		T15	4
lens_less_than_1000[1]	134	1			T6	1		T5	1		T7	3
lens_less_than_1000[2]	109	1			T4	1		T18	2		T7	1
lens_less_than_1000[3]	93	1			T7	1		T20	1		T52	2
lens_less_than_1000[4]	79	1			T7	4		T20	1		T36	3
lens_less_than_1000[5]	34	1			T18	1		T20	1		T37	1
lens_less_than_1000[6]	40	1			T18	1		T15	1		T82	1
lens_less_than_1000[7]	22	1			T7	1		T20	1		T85	1
lens_less_than_1000[8]	9	1			T87	1		T272	1		T273	1
lens_less_than_1000[9]	2	1			T274	1		T275	1		-	-
len_2	11	1			T66	2		T189	1		T242	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x1] , index[0x2]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	67	1			T7	2		T15	1		T20	1
index[0x0]	lens_less_than_1000[1]	30	1			T7	1		T54	2		T57	1
index[0x0]	lens_less_than_1000[2]	26	1			T4	1		T18	1		T54	1
index[0x0]	lens_less_than_1000[3]	23	1			T36	1		T276	1		T63	1
index[0x0]	lens_less_than_1000[4]	27	1			T7	4		T20	1		T36	1
index[0x0]	lens_less_than_1000[5]	10	1			T20	1		T277	1		T102	1
index[0x0]	lens_less_than_1000[6]	9	1			T187	1		T278	1		T113	1
index[0x0]	lens_less_than_1000[7]	5	1			T7	1		T20	1		T279	1
index[0x0]	lens_less_than_1000[9]	1	1			T274	1		-	-		-	-
index[0x0]	len_2	5	1			T66	1		T242	2		T280	2
index[0x1]	lens_less_than_1000[0]	58	1			T7	1		T15	1		T54	1
index[0x1]	lens_less_than_1000[1]	36	1			T7	1		T54	2		T33	2
index[0x1]	lens_less_than_1000[2]	23	1			T18	1		T20	2		T65	1
index[0x1]	lens_less_than_1000[3]	17	1			T20	1		T52	1		T74	1
index[0x1]	lens_less_than_1000[4]	20	1			T31	1		T71	1		T281	1
index[0x1]	lens_less_than_1000[5]	9	1			T37	1		T62	1		T87	1
index[0x1]	lens_less_than_1000[6]	15	1			T85	1		T42	1		T269	1
index[0x1]	lens_less_than_1000[7]	9	1			T85	1		T113	1		T66	1
index[0x1]	lens_less_than_1000[8]	4	1			T87	1		T272	1		T273	1
index[0x1]	len_2	1	1			T189	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	53	1			T76	1		T62	1		T35	1
index[0x2]	lens_less_than_1000[1]	35	1			T6	1		T5	1		T236	1
index[0x2]	lens_less_than_1000[2]	28	1			T7	1		T51	1		T60	1
index[0x2]	lens_less_than_1000[3]	26	1			T7	1		T52	1		T53	1
index[0x2]	lens_less_than_1000[4]	10	1			T36	1		T60	1		T282	1
index[0x2]	lens_less_than_1000[5]	4	1			T85	1		T283	1		T284	1
index[0x2]	lens_less_than_1000[6]	4	1			T18	1		T15	1		T63	1
index[0x2]	lens_less_than_1000[7]	3	1			T285	1		T257	1		T286	1
index[0x2]	lens_less_than_1000[8]	2	1			T287	1		T255	1		-	-
index[0x2]	len_2	1	1			T288	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	63	1			T4	1		T15	2		T16	1
index[0x3]	lens_less_than_1000[1]	33	1			T7	1		T15	3		T35	1
index[0x3]	lens_less_than_1000[2]	32	1			T20	1		T60	2		T61	1
index[0x3]	lens_less_than_1000[3]	27	1			T60	1		T85	3		T111	2
index[0x3]	lens_less_than_1000[4]	22	1			T36	1		T60	1		T38	1
index[0x3]	lens_less_than_1000[5]	11	1			T18	1		T289	1		T32	1
index[0x3]	lens_less_than_1000[6]	12	1			T82	1		T92	1		T106	2
index[0x3]	lens_less_than_1000[7]	5	1			T272	1		T290	1		T291	1
index[0x3]	lens_less_than_1000[8]	3	1			T291	1		T261	1		T292	1
index[0x3]	lens_less_than_1000[9]	1	1			T275	1		-	-		-	-
index[0x3]	len_2	4	1			T66	1		T248	1		T280	2