Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	67	1			T7	1		T20	2		T82	1
class_index[0x1]	74	1			T15	1		T36	2		T79	2
class_index[0x2]	68	1			T20	4		T33	1		T60	1
class_index[0x3]	78	1			T18	1		T56	1		T50	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	106	1			T18	1		T20	4		T33	1
intr_timeout_cnt[1]	53	1			T15	1		T60	2		T83	2
intr_timeout_cnt[2]	40	1			T7	1		T56	1		T50	2
intr_timeout_cnt[3]	22	1			T79	2		T85	1		T46	1
intr_timeout_cnt[4]	17	1			T36	1		T62	2		T32	1
intr_timeout_cnt[5]	8	1			T85	1		T239	1		T240	1
intr_timeout_cnt[6]	20	1			T20	2		T85	1		T86	1
intr_timeout_cnt[7]	8	1			T241	1		T68	1		T240	1
intr_timeout_cnt[8]	6	1			T32	1		T242	1		T243	1
intr_timeout_cnt[9]	7	1			T20	1		T71	1		T87	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T20	1		T82	1		T79	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T83	1		T62	1		T32	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T7	1		T71	1		T244	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T46	1		T245	1		T246	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T247	1		T248	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T249	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	6	1			T87	1		T32	1		T230	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T250	1		T251	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T20	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	29	1			T36	1		T79	1		T63	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T15	1		T60	1		T252	2
class_index[0x1]	intr_timeout_cnt[2]	8	1			T35	1		T245	1		T253	2
class_index[0x1]	intr_timeout_cnt[3]	11	1			T79	1		T85	1		T254	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T36	1		T255	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T86	1		T256	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T240	1		T257	2		T258	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T242	1		T243	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	3	1			T239	1		T240	1		T259	1
class_index[0x2]	intr_timeout_cnt[0]	24	1			T20	2		T33	1		T85	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T60	1		T63	1		T260	1
class_index[0x2]	intr_timeout_cnt[2]	8	1			T247	1		T243	1		T191	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T86	1		T241	1		T246	1
class_index[0x2]	intr_timeout_cnt[4]	7	1			T191	1		T261	1		T262	1
class_index[0x2]	intr_timeout_cnt[5]	7	1			T85	1		T239	1		T240	1
class_index[0x2]	intr_timeout_cnt[6]	3	1			T20	2		T68	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T68	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T32	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T87	1		T263	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	26	1			T18	1		T20	1		T264	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T83	1		T265	2		T266	1
class_index[0x3]	intr_timeout_cnt[2]	17	1			T56	1		T50	2		T36	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T79	1		T267	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	6	1			T62	2		T32	1		T250	1
class_index[0x3]	intr_timeout_cnt[6]	9	1			T85	1		T268	1		T269	1
class_index[0x3]	intr_timeout_cnt[7]	3	1			T241	1		T270	1		T271	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T250	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T71	1		-	-		-	-