Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	397331	1			T23	1		T26	1		T27	4
all_values[1]	397331	1			T23	1		T26	1		T27	4
all_values[2]	397331	1			T23	1		T26	1		T27	4
all_values[3]	397331	1			T23	1		T26	1		T27	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

791528

1

T23

4

T26

4

T27

12

auto[1]

797796

1

T27

4

T159

16

T160

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

944550

1

T23

4

T26

4

T27

15

auto[1]

644774

1

T27

1

T159

9

T160

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	113172	1			T23	1		T26	1		T114	1
all_values[0]	auto[0]	auto[1]	84571	1			T27	1		T159	1		T185	2
all_values[0]	auto[1]	auto[0]	114626	1			T27	3		T159	5		T160	1
all_values[0]	auto[1]	auto[1]	84962	1			T159	1		T185	2		T186	5
all_values[1]	auto[0]	auto[0]	119303	1			T23	1		T26	1		T27	3
all_values[1]	auto[0]	auto[1]	78648	1			T185	2		T340	3		T341	1
all_values[1]	auto[1]	auto[0]	120438	1			T27	1		T159	1		T160	3
all_values[1]	auto[1]	auto[1]	78942	1			T159	3		T160	1		T185	1
all_values[2]	auto[0]	auto[0]	118615	1			T23	1		T26	1		T27	4
all_values[2]	auto[0]	auto[1]	79425	1			T185	3		T186	3		T340	1
all_values[2]	auto[1]	auto[0]	120012	1			T159	1		T186	1		T340	1
all_values[2]	auto[1]	auto[1]	79279	1			T159	2		T185	1		T186	1
all_values[3]	auto[0]	auto[0]	118393	1			T23	1		T26	1		T27	4
all_values[3]	auto[0]	auto[1]	79401	1			T159	1		T185	2		T186	2
all_values[3]	auto[1]	auto[0]	119991	1			T159	2		T160	1		T185	3
all_values[3]	auto[1]	auto[1]	79546	1			T159	1		T186	1		T340	1