Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	397331	1			T23	1		T26	1		T27	4
all_pins[1]	397331	1			T23	1		T26	1		T27	4
all_pins[2]	397331	1			T23	1		T26	1		T27	4
all_pins[3]	397331	1			T23	1		T26	1		T27	4

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1266595	1			T23	4		T26	4		T27	16
values[0x1]	322729	1			T159	7		T160	1		T185	4
transitions[0x0=>0x1]	214828	1			T159	4		T160	1		T185	2
transitions[0x1=>0x0]	215107	1			T159	4		T160	1		T185	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	312369	1			T23	1		T26	1		T27	4
all_pins[0]	values[0x1]	84962	1			T159	1		T185	2		T186	5
all_pins[0]	transitions[0x0=>0x1]	84166	1			T185	2		T186	3		T340	1
all_pins[0]	transitions[0x1=>0x0]	79029	1			T341	1		T342	2		T238	3
all_pins[1]	values[0x0]	318389	1			T23	1		T26	1		T27	4
all_pins[1]	values[0x1]	78942	1			T159	3		T160	1		T185	1
all_pins[1]	transitions[0x0=>0x1]	43089	1			T159	3		T160	1		T186	1
all_pins[1]	transitions[0x1=>0x0]	49109	1			T159	1		T185	1		T186	5
all_pins[2]	values[0x0]	318052	1			T23	1		T26	1		T27	4
all_pins[2]	values[0x1]	79279	1			T159	2		T185	1		T186	1
all_pins[2]	transitions[0x0=>0x1]	43631	1			T159	1		T186	1		T340	3
all_pins[2]	transitions[0x1=>0x0]	43294	1			T159	2		T160	1		T186	1
all_pins[3]	values[0x0]	317785	1			T23	1		T26	1		T27	4
all_pins[3]	values[0x1]	79546	1			T159	1		T186	1		T340	1
all_pins[3]	transitions[0x0=>0x1]	43942	1			T340	1		T341	1		T342	3
all_pins[3]	transitions[0x1=>0x0]	43675	1			T159	1		T185	1		T340	3