Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T27	4		T159	7		T160	4
all_values[1]	287	1			T27	4		T159	7		T160	4
all_values[2]	287	1			T27	4		T159	7		T160	4
all_values[3]	287	1			T27	4		T159	7		T160	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T27

13

T159

15

T160

9

auto[1]

507

1

T27

3

T159

13

T160

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

458

1

T27

11

T159

16

T160

9

auto[1]

690

1

T27

5

T159

12

T160

7

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

672

1

T27

11

T159

20

T160

9

auto[1]

476

1

T27

5

T159

8

T160

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T27

1

T159

1

T160

1

all_values[0]

auto[0]

auto[0]

auto[1]

20

1

T185

1

T340

1

T341

2

all_values[0]

auto[0]

auto[1]

auto[0]

59

1

T27

1

T159

3

T160

2

all_values[0]

auto[0]

auto[1]

auto[1]

35

1

T159

1

T185

1

T186

4

all_values[0]

auto[1]

auto[0]

auto[1]

63

1

T159

2

T160

1

T185

1

all_values[0]

auto[1]

auto[1]

auto[1]

51

1

T27

2

T185

1

T186

1

all_values[1]

auto[0]

auto[0]

auto[0]

60

1

T27

3

T159

3

T185

2

all_values[1]

auto[0]

auto[0]

auto[1]

33

1

T185

1

T340

1

T341

1

all_values[1]

auto[0]

auto[1]

auto[0]

48

1

T159

1

T160

1

T185

1

all_values[1]

auto[0]

auto[1]

auto[1]

23

1

T159

1

T342

1

T343

1

all_values[1]

auto[1]

auto[0]

auto[1]

68

1

T27

1

T159

1

T160

1

all_values[1]

auto[1]

auto[1]

auto[1]

55

1

T159

1

T160

2

T185

1

all_values[2]

auto[0]

auto[0]

auto[0]

74

1

T27

3

T159

3

T160

2

all_values[2]

auto[0]

auto[0]

auto[1]

35

1

T185

1

T186

1

T340

1

all_values[2]

auto[0]

auto[1]

auto[0]

38

1

T159

1

T341

2

T238

2

all_values[2]

auto[0]

auto[1]

auto[1]

22

1

T159

1

T340

1

T344

1

all_values[2]

auto[1]

auto[0]

auto[1]

65

1

T27

1

T160

2

T185

3

all_values[2]

auto[1]

auto[1]

auto[1]

53

1

T159

2

T186

1

T340

1

all_values[3]

auto[0]

auto[0]

auto[0]

60

1

T27

3

T159

2

T160

1

all_values[3]

auto[0]

auto[0]

auto[1]

33

1

T159

1

T185

1

T186

1

all_values[3]

auto[0]

auto[1]

auto[0]

60

1

T159

2

T160

2

T185

2

all_values[3]

auto[0]

auto[1]

auto[1]

13

1

T340

1

T341

1

T238

1

all_values[3]

auto[1]

auto[0]

auto[1]

71

1

T27

1

T159

2

T160

1

all_values[3]

auto[1]

auto[1]

auto[1]

50

1

T186

1

T340

2

T341

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal