Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	96826	1			T4	515		T18	496		T5	141
accum_cnt_1000	260696	1			T3	845		T4	1778		T18	1436
accum_cnt_100	31243	1			T3	57		T4	202		T18	80
accum_cnt_50	71561	1			T2	14		T3	44		T6	1
accum_cnt_10	211764	1			T1	4		T2	2		T3	1911
accum_cnt_0	454661	1			T1	16		T2	48		T3	967

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	293709	1			T1	5		T2	16		T3	956
class_index[0x1]	293708	1			T1	5		T2	16		T3	956
class_index[0x2]	293708	1			T1	5		T2	16		T3	956
class_index[0x3]	293707	1			T1	5		T2	16		T3	956

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23631	1			T15	531		T20	399		T52	123
class_index[0x0]	accum_cnt_1000	74646	1			T3	845		T7	65		T15	747
class_index[0x0]	accum_cnt_100	8769	1			T3	57		T7	52		T15	44
class_index[0x0]	accum_cnt_50	21350	1			T2	14		T3	44		T4	1337
class_index[0x0]	accum_cnt_10	56083	1			T2	2		T3	6		T6	19
class_index[0x0]	accum_cnt_0	96913	1			T1	5		T3	4		T4	1
class_index[0x1]	accum_cnt_2000	25043	1			T18	261		T15	283		T16	504
class_index[0x1]	accum_cnt_1000	61139	1			T18	695		T7	113		T15	1369
class_index[0x1]	accum_cnt_100	7333	1			T18	34		T7	53		T15	102
class_index[0x1]	accum_cnt_50	15397	1			T18	60		T7	55		T15	75
class_index[0x1]	accum_cnt_10	51267	1			T3	956		T6	19		T18	16
class_index[0x1]	accum_cnt_0	121389	1			T1	5		T2	16		T4	1355
class_index[0x2]	accum_cnt_2000	23048	1			T5	141		T7	63		T15	886
class_index[0x2]	accum_cnt_1000	60209	1			T4	1015		T5	519		T7	794
class_index[0x2]	accum_cnt_100	7363	1			T4	166		T18	2		T5	31
class_index[0x2]	accum_cnt_50	16481	1			T4	124		T18	23		T5	24
class_index[0x2]	accum_cnt_10	52260	1			T1	4		T3	949		T6	19
class_index[0x2]	accum_cnt_0	124528	1			T1	1		T2	16		T3	7
class_index[0x3]	accum_cnt_2000	25104	1			T4	515		T18	235		T15	412
class_index[0x3]	accum_cnt_1000	64702	1			T4	763		T18	741		T7	137
class_index[0x3]	accum_cnt_100	7778	1			T4	36		T18	44		T7	109
class_index[0x3]	accum_cnt_50	18333	1			T6	1		T4	28		T18	24
class_index[0x3]	accum_cnt_10	52154	1			T6	14		T4	8		T18	34
class_index[0x3]	accum_cnt_0	111831	1			T1	5		T2	16		T3	956