Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7178	1			T76	8		T79	236		T60	988
alert[0x1]	3022	1			T75	1		T187	109		T87	30
alert[0x2]	10362	1			T20	13		T33	20		T36	936
alert[0x3]	7478	1			T8	1		T9	1		T20	9
alert[0x4]	6716	1			T15	948		T33	1059		T75	1
alert[0x5]	3922	1			T7	6		T10	1		T76	50
alert[0x6]	7627	1			T8	1		T10	2		T52	5
alert[0x7]	5025	1			T9	1		T50	21		T20	1
alert[0x8]	5985	1			T15	141		T20	11		T36	8
alert[0x9]	7149	1			T236	9		T71	11		T85	3
alert[0xa]	11725	1			T15	534		T76	6730		T236	1
alert[0xb]	3744	1			T15	35		T33	126		T75	2
alert[0xc]	3990	1			T50	3		T36	1		T75	1
alert[0xd]	6733	1			T19	215		T10	1		T36	48
alert[0xe]	6438	1			T10	1		T36	1		T76	28
alert[0xf]	10550	1			T7	50		T8	1		T19	77
alert[0x10]	6664	1			T50	21		T36	7		T76	955
alert[0x11]	16300	1			T7	22		T15	11364		T10	1
alert[0x12]	7922	1			T18	2		T15	35		T16	3
alert[0x13]	5011	1			T7	139		T15	118		T8	1
alert[0x14]	8494	1			T7	9		T33	48		T76	3
alert[0x15]	4942	1			T8	2		T33	86		T36	2
alert[0x16]	5440	1			T15	255		T8	1		T236	29
alert[0x17]	5646	1			T7	4		T8	1		T37	1
alert[0x18]	8645	1			T7	4		T15	395		T8	1
alert[0x19]	5622	1			T7	4		T10	1		T79	69
alert[0x1a]	4814	1			T16	17		T75	2		T236	54
alert[0x1b]	6414	1			T15	14		T9	2		T10	2
alert[0x1c]	6450	1			T18	1		T7	785		T8	1
alert[0x1d]	8569	1			T7	11		T15	1		T33	10
alert[0x1e]	12398	1			T7	2		T15	615		T33	355
alert[0x1f]	3418	1			T7	2		T10	1		T33	24
alert[0x20]	7409	1			T7	24		T33	25		T75	1
alert[0x21]	2886	1			T3	1		T7	8		T15	342
alert[0x22]	16455	1			T7	9		T9	1		T33	1
alert[0x23]	11271	1			T15	188		T8	1		T194	1
alert[0x24]	7269	1			T15	374		T9	1		T33	19
alert[0x25]	6934	1			T6	4		T8	2		T9	1
alert[0x26]	15835	1			T7	6		T15	107		T50	1
alert[0x27]	9667	1			T15	79		T16	1		T33	108
alert[0x28]	4999	1			T15	11		T16	15		T10	1
alert[0x29]	5875	1			T8	3		T33	4		T36	226
alert[0x2a]	7988	1			T3	1		T15	1628		T20	12
alert[0x2b]	5456	1			T9	1		T20	1		T10	1
alert[0x2c]	13184	1			T4	2		T7	22		T33	57
alert[0x2d]	5992	1			T18	5		T76	1636		T37	1
alert[0x2e]	11260	1			T7	4		T15	131		T9	1
alert[0x2f]	4665	1			T76	118		T89	2		T236	27
alert[0x30]	9196	1			T7	209		T9	1		T33	19
alert[0x31]	8474	1			T36	7		T75	1		T194	1
alert[0x32]	14810	1			T33	9		T36	7		T76	1046
alert[0x33]	8237	1			T7	51		T15	1254		T16	3
alert[0x34]	8851	1			T15	17		T76	51		T236	213
alert[0x35]	4215	1			T15	6		T76	125		T37	1
alert[0x36]	11179	1			T15	264		T9	1		T10	1
alert[0x37]	7867	1			T15	69		T9	1		T33	80
alert[0x38]	7085	1			T7	540		T15	7		T8	1
alert[0x39]	6141	1			T15	80		T8	1		T10	1
alert[0x3a]	8003	1			T8	1		T33	20		T36	9
alert[0x3b]	4018	1			T7	19		T9	1		T20	7
alert[0x3c]	8364	1			T7	2		T15	51		T16	5
alert[0x3d]	14368	1			T8	1		T20	13		T36	6
alert[0x3e]	15640	1			T18	38		T7	1		T15	36
alert[0x3f]	9869	1			T15	190		T76	9		T187	1
alert[0x40]	4511	1			T7	89		T15	100		T36	24

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	117588	1			T7	10		T15	12		T8	1
class_i[0x1]	113854	1			T7	463		T15	8825		T9	1
class_i[0x2]	153743	1			T3	2		T7	21		T8	19
class_i[0x3]	127181	1			T6	4		T4	2		T18	46

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

511674

1

T6

4

T18

46

T7

2022

alert_ping_fail

692

1

T3

2

T4

2

T8

20

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7168	1			T76	8		T79	236		T60	988
alert_integrity_fail	alert[0x1]	3012	1			T187	109		T87	30		T111	239
alert_integrity_fail	alert[0x2]	10349	1			T20	13		T33	20		T36	936
alert_integrity_fail	alert[0x3]	7463	1			T20	9		T33	43		T236	35
alert_integrity_fail	alert[0x4]	6705	1			T15	948		T33	1059		T236	524
alert_integrity_fail	alert[0x5]	3905	1			T7	6		T76	50		T82	87
alert_integrity_fail	alert[0x6]	7611	1			T52	5		T33	33		T76	2325
alert_integrity_fail	alert[0x7]	5018	1			T50	21		T20	1		T60	20
alert_integrity_fail	alert[0x8]	5971	1			T15	141		T20	11		T36	8
alert_integrity_fail	alert[0x9]	7139	1			T236	9		T71	11		T85	3
alert_integrity_fail	alert[0xa]	11717	1			T15	534		T76	6730		T236	1
alert_integrity_fail	alert[0xb]	3731	1			T15	35		T33	126		T76	161
alert_integrity_fail	alert[0xc]	3985	1			T50	3		T36	1		T76	35
alert_integrity_fail	alert[0xd]	6720	1			T19	215		T36	48		T276	6
alert_integrity_fail	alert[0xe]	6422	1			T36	1		T76	28		T236	36
alert_integrity_fail	alert[0xf]	10540	1			T7	50		T19	77		T33	1192
alert_integrity_fail	alert[0x10]	6654	1			T50	21		T36	7		T76	955
alert_integrity_fail	alert[0x11]	16284	1			T7	22		T15	11364		T36	99
alert_integrity_fail	alert[0x12]	7912	1			T18	2		T15	35		T16	3
alert_integrity_fail	alert[0x13]	4998	1			T7	139		T15	118		T236	6
alert_integrity_fail	alert[0x14]	8478	1			T7	9		T33	48		T76	3
alert_integrity_fail	alert[0x15]	4923	1			T33	86		T36	2		T76	14
alert_integrity_fail	alert[0x16]	5429	1			T15	255		T236	29		T79	16
alert_integrity_fail	alert[0x17]	5636	1			T7	4		T187	1		T236	24
alert_integrity_fail	alert[0x18]	8635	1			T7	4		T15	395		T33	122
alert_integrity_fail	alert[0x19]	5617	1			T7	4		T79	69		T60	429
alert_integrity_fail	alert[0x1a]	4807	1			T16	17		T236	54		T60	255
alert_integrity_fail	alert[0x1b]	6400	1			T15	14		T33	75		T79	277
alert_integrity_fail	alert[0x1c]	6438	1			T18	1		T7	785		T52	1
alert_integrity_fail	alert[0x1d]	8566	1			T7	11		T15	1		T33	10
alert_integrity_fail	alert[0x1e]	12385	1			T7	2		T15	615		T33	355
alert_integrity_fail	alert[0x1f]	3413	1			T7	2		T33	24		T36	1
alert_integrity_fail	alert[0x20]	7395	1			T7	24		T33	25		T82	15
alert_integrity_fail	alert[0x21]	2874	1			T7	8		T15	342		T76	27
alert_integrity_fail	alert[0x22]	16440	1			T7	9		T33	1		T76	17
alert_integrity_fail	alert[0x23]	11263	1			T15	188		T236	463		T60	156
alert_integrity_fail	alert[0x24]	7258	1			T15	374		T33	19		T76	68
alert_integrity_fail	alert[0x25]	6925	1			T6	4		T33	4		T60	178
alert_integrity_fail	alert[0x26]	15821	1			T7	6		T15	107		T50	1
alert_integrity_fail	alert[0x27]	9660	1			T15	79		T16	1		T33	108
alert_integrity_fail	alert[0x28]	4992	1			T15	11		T16	15		T33	143
alert_integrity_fail	alert[0x29]	5864	1			T33	4		T36	226		T76	2
alert_integrity_fail	alert[0x2a]	7973	1			T15	1628		T20	12		T36	21
alert_integrity_fail	alert[0x2b]	5445	1			T20	1		T76	1389		T187	7
alert_integrity_fail	alert[0x2c]	13176	1			T7	22		T33	57		T236	5141
alert_integrity_fail	alert[0x2d]	5983	1			T18	5		T76	1636		T60	299
alert_integrity_fail	alert[0x2e]	11245	1			T7	4		T15	131		T36	4
alert_integrity_fail	alert[0x2f]	4653	1			T76	118		T236	27		T79	125
alert_integrity_fail	alert[0x30]	9182	1			T7	209		T33	19		T76	28
alert_integrity_fail	alert[0x31]	8465	1			T36	7		T236	53		T60	558
alert_integrity_fail	alert[0x32]	14800	1			T33	9		T36	7		T76	1046
alert_integrity_fail	alert[0x33]	8232	1			T7	51		T15	1254		T16	3
alert_integrity_fail	alert[0x34]	8844	1			T15	17		T76	51		T236	213
alert_integrity_fail	alert[0x35]	4206	1			T15	6		T76	125		T60	48
alert_integrity_fail	alert[0x36]	11175	1			T15	264		T33	105		T76	47
alert_integrity_fail	alert[0x37]	7857	1			T15	69		T33	80		T36	1
alert_integrity_fail	alert[0x38]	7071	1			T7	540		T15	7		T33	994
alert_integrity_fail	alert[0x39]	6132	1			T15	80		T33	157		T36	6
alert_integrity_fail	alert[0x3a]	7995	1			T33	20		T36	9		T76	143
alert_integrity_fail	alert[0x3b]	4010	1			T7	19		T20	7		T60	13
alert_integrity_fail	alert[0x3c]	8353	1			T7	2		T15	51		T16	5
alert_integrity_fail	alert[0x3d]	14358	1			T20	13		T36	6		T76	711
alert_integrity_fail	alert[0x3e]	15629	1			T18	38		T7	1		T15	36
alert_integrity_fail	alert[0x3f]	9862	1			T15	190		T76	9		T187	1
alert_integrity_fail	alert[0x40]	4505	1			T7	89		T15	100		T36	24
alert_ping_fail	alert[0x0]	10	1			T298	2		T299	1		T300	1
alert_ping_fail	alert[0x1]	10	1			T75	1		T298	1		T301	1
alert_ping_fail	alert[0x2]	13	1			T194	1		T216	1		T298	1
alert_ping_fail	alert[0x3]	15	1			T8	1		T9	1		T216	1
alert_ping_fail	alert[0x4]	11	1			T75	1		T298	1		T302	1
alert_ping_fail	alert[0x5]	17	1			T10	1		T289	1		T303	1
alert_ping_fail	alert[0x6]	16	1			T8	1		T10	2		T289	1
alert_ping_fail	alert[0x7]	7	1			T9	1		T37	1		T216	1
alert_ping_fail	alert[0x8]	14	1			T37	1		T216	1		T304	1
alert_ping_fail	alert[0x9]	10	1			T289	1		T300	1		T305	1
alert_ping_fail	alert[0xa]	8	1			T306	1		T307	1		T308	1
alert_ping_fail	alert[0xb]	13	1			T75	2		T194	1		T37	1
alert_ping_fail	alert[0xc]	5	1			T75	1		T194	1		T216	1
alert_ping_fail	alert[0xd]	13	1			T10	1		T75	1		T37	1
alert_ping_fail	alert[0xe]	16	1			T10	1		T306	1		T309	2
alert_ping_fail	alert[0xf]	10	1			T8	1		T75	1		T194	1
alert_ping_fail	alert[0x10]	10	1			T216	1		T307	2		T310	1
alert_ping_fail	alert[0x11]	16	1			T10	1		T194	1		T289	1
alert_ping_fail	alert[0x12]	10	1			T10	1		T44	1		T298	1
alert_ping_fail	alert[0x13]	13	1			T8	1		T9	1		T306	1
alert_ping_fail	alert[0x14]	16	1			T289	1		T216	1		T296	1
alert_ping_fail	alert[0x15]	19	1			T8	2		T37	1		T293	1
alert_ping_fail	alert[0x16]	11	1			T8	1		T294	2		T308	1
alert_ping_fail	alert[0x17]	10	1			T8	1		T37	1		T306	1
alert_ping_fail	alert[0x18]	10	1			T8	1		T75	1		T300	1
alert_ping_fail	alert[0x19]	5	1			T10	1		T311	1		T273	1
alert_ping_fail	alert[0x1a]	7	1			T75	2		T309	1		T273	1
alert_ping_fail	alert[0x1b]	14	1			T9	2		T10	2		T298	1
alert_ping_fail	alert[0x1c]	12	1			T8	1		T75	1		T37	2
alert_ping_fail	alert[0x1d]	3	1			T311	1		T312	1		T313	1
alert_ping_fail	alert[0x1e]	13	1			T75	3		T311	2		T305	1
alert_ping_fail	alert[0x1f]	5	1			T10	1		T293	1		T314	1
alert_ping_fail	alert[0x20]	14	1			T75	1		T306	1		T289	1
alert_ping_fail	alert[0x21]	12	1			T3	1		T75	1		T37	1
alert_ping_fail	alert[0x22]	15	1			T9	1		T44	1		T298	1
alert_ping_fail	alert[0x23]	8	1			T8	1		T194	1		T301	2
alert_ping_fail	alert[0x24]	11	1			T9	1		T75	1		T298	2
alert_ping_fail	alert[0x25]	9	1			T8	2		T9	1		T44	1
alert_ping_fail	alert[0x26]	14	1			T10	2		T216	1		T307	1
alert_ping_fail	alert[0x27]	7	1			T75	1		T37	1		T315	1
alert_ping_fail	alert[0x28]	7	1			T10	1		T44	1		T311	1
alert_ping_fail	alert[0x29]	11	1			T8	3		T37	1		T300	1
alert_ping_fail	alert[0x2a]	15	1			T3	1		T194	2		T216	2
alert_ping_fail	alert[0x2b]	11	1			T9	1		T10	1		T295	1
alert_ping_fail	alert[0x2c]	8	1			T4	2		T308	1		T314	1
alert_ping_fail	alert[0x2d]	9	1			T37	1		T302	1		T313	2
alert_ping_fail	alert[0x2e]	15	1			T9	1		T315	1		T316	2
alert_ping_fail	alert[0x2f]	12	1			T89	2		T44	1		T307	2
alert_ping_fail	alert[0x30]	14	1			T9	1		T37	1		T295	1
alert_ping_fail	alert[0x31]	9	1			T75	1		T194	1		T37	1
alert_ping_fail	alert[0x32]	10	1			T306	1		T310	1		T317	1
alert_ping_fail	alert[0x33]	5	1			T75	1		T309	1		T318	1
alert_ping_fail	alert[0x34]	7	1			T306	1		T311	1		T299	1
alert_ping_fail	alert[0x35]	9	1			T37	1		T298	1		T302	3
alert_ping_fail	alert[0x36]	4	1			T9	1		T10	1		T319	1
alert_ping_fail	alert[0x37]	10	1			T9	1		T307	1		T308	1
alert_ping_fail	alert[0x38]	14	1			T8	1		T10	2		T75	1
alert_ping_fail	alert[0x39]	9	1			T8	1		T10	1		T37	1
alert_ping_fail	alert[0x3a]	8	1			T8	1		T194	1		T304	1
alert_ping_fail	alert[0x3b]	8	1			T9	1		T37	1		T298	2
alert_ping_fail	alert[0x3c]	11	1			T75	1		T289	1		T307	1
alert_ping_fail	alert[0x3d]	10	1			T8	1		T194	1		T37	1
alert_ping_fail	alert[0x3e]	11	1			T9	1		T75	1		T194	1
alert_ping_fail	alert[0x3f]	7	1			T289	1		T298	1		T273	1
alert_ping_fail	alert[0x40]	6	1			T37	1		T216	1		T30	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	117365	1			T7	10		T15	12		T19	2
alert_integrity_fail	class_i[0x1]	113670	1			T7	463		T15	8825		T19	1
alert_integrity_fail	class_i[0x2]	153571	1			T7	21		T16	44		T20	4
alert_integrity_fail	class_i[0x3]	127068	1			T6	4		T18	46		T7	1528
alert_ping_fail	class_i[0x0]	223	1			T8	1		T9	1		T75	3
alert_ping_fail	class_i[0x1]	184	1			T9	1		T10	19		T194	2
alert_ping_fail	class_i[0x2]	172	1			T3	2		T8	19		T9	13
alert_ping_fail	class_i[0x3]	113	1			T4	2		T75	20		T194	1