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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.67 99.97 100.00 100.00 99.38 99.56


Total test records in report: 850
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T778 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2833312469 Jan 21 03:06:16 PM PST 24 Jan 21 03:06:40 PM PST 24 164783811 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1685384173 Jan 21 03:06:16 PM PST 24 Jan 21 03:06:21 PM PST 24 36456736 ps
T139 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3071038349 Jan 21 03:06:41 PM PST 24 Jan 21 03:17:55 PM PST 24 42575515693 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3012950522 Jan 21 03:18:50 PM PST 24 Jan 21 03:19:01 PM PST 24 125098106 ps
T174 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1652237155 Jan 21 03:06:18 PM PST 24 Jan 21 03:07:05 PM PST 24 4229122560 ps
T781 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1763451429 Jan 21 03:06:05 PM PST 24 Jan 21 03:06:10 PM PST 24 73719783 ps
T782 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2399321641 Jan 21 03:06:39 PM PST 24 Jan 21 03:07:01 PM PST 24 178131968 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4139424835 Jan 21 03:06:49 PM PST 24 Jan 21 03:07:00 PM PST 24 124822787 ps
T784 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1928514842 Jan 21 03:07:22 PM PST 24 Jan 21 03:07:28 PM PST 24 8167179 ps
T785 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3043358404 Jan 21 03:07:25 PM PST 24 Jan 21 03:07:28 PM PST 24 13668347 ps
T786 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.594655174 Jan 21 03:07:12 PM PST 24 Jan 21 03:07:24 PM PST 24 20586965 ps
T787 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2231841065 Jan 21 03:06:25 PM PST 24 Jan 21 03:06:38 PM PST 24 622255941 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2477686859 Jan 21 03:05:39 PM PST 24 Jan 21 03:06:47 PM PST 24 578096694 ps
T789 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3459606555 Jan 21 03:06:33 PM PST 24 Jan 21 03:06:36 PM PST 24 28645530 ps
T790 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3053051405 Jan 21 03:05:45 PM PST 24 Jan 21 03:08:20 PM PST 24 24916414992 ps
T123 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.17899961 Jan 21 03:06:39 PM PST 24 Jan 21 03:09:19 PM PST 24 2280566685 ps
T178 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2836698555 Jan 21 03:06:18 PM PST 24 Jan 21 03:07:05 PM PST 24 1201657600 ps
T791 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.430638492 Jan 21 03:06:21 PM PST 24 Jan 21 03:06:29 PM PST 24 26410790 ps
T792 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1451084457 Jan 21 03:07:34 PM PST 24 Jan 21 03:07:36 PM PST 24 6450742 ps
T129 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1508434634 Jan 21 03:07:13 PM PST 24 Jan 21 03:18:46 PM PST 24 5029608767 ps
T793 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.975956495 Jan 21 03:06:58 PM PST 24 Jan 21 03:07:01 PM PST 24 8746748 ps
T794 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3268374082 Jan 21 03:07:24 PM PST 24 Jan 21 03:07:28 PM PST 24 11766236 ps
T180 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.330420545 Jan 21 03:05:51 PM PST 24 Jan 21 03:06:28 PM PST 24 1875905852 ps
T140 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1657371760 Jan 21 03:06:24 PM PST 24 Jan 21 03:12:16 PM PST 24 19245979457 ps
T795 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1742637311 Jan 21 03:07:21 PM PST 24 Jan 21 03:07:25 PM PST 24 25446638 ps
T796 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2075088194 Jan 21 03:07:26 PM PST 24 Jan 21 03:07:28 PM PST 24 20442134 ps
T797 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4267798142 Jan 21 03:05:47 PM PST 24 Jan 21 03:05:52 PM PST 24 173907530 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2904040971 Jan 21 03:06:25 PM PST 24 Jan 21 03:06:34 PM PST 24 825934685 ps
T799 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1819742826 Jan 21 03:06:15 PM PST 24 Jan 21 03:06:54 PM PST 24 1211190019 ps
T800 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1612966495 Jan 21 03:06:50 PM PST 24 Jan 21 03:07:27 PM PST 24 511539741 ps
T801 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2763993409 Jan 21 03:06:34 PM PST 24 Jan 21 03:06:41 PM PST 24 151402424 ps
T802 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3435660072 Jan 21 03:06:09 PM PST 24 Jan 21 03:06:19 PM PST 24 96591342 ps
T173 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3158920308 Jan 21 03:07:12 PM PST 24 Jan 21 03:07:41 PM PST 24 296304107 ps
T803 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1885773846 Jan 21 03:06:23 PM PST 24 Jan 21 03:06:26 PM PST 24 18650437 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4036203858 Jan 21 03:06:29 PM PST 24 Jan 21 03:06:35 PM PST 24 20888249 ps
T143 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4003629799 Jan 21 03:06:04 PM PST 24 Jan 21 03:08:25 PM PST 24 3914526744 ps
T805 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3640681763 Jan 21 03:06:57 PM PST 24 Jan 21 03:07:05 PM PST 24 42724261 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3576550786 Jan 21 03:05:55 PM PST 24 Jan 21 03:06:01 PM PST 24 30882189 ps
T170 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2857410046 Jan 21 03:06:16 PM PST 24 Jan 21 03:06:53 PM PST 24 1136847846 ps
T807 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.371712860 Jan 21 03:07:13 PM PST 24 Jan 21 03:07:25 PM PST 24 34905432 ps
T808 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2875354502 Jan 21 03:07:15 PM PST 24 Jan 21 03:07:52 PM PST 24 180826024 ps
T150 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.629860690 Jan 21 03:06:23 PM PST 24 Jan 21 03:08:58 PM PST 24 2064630238 ps
T809 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1210435200 Jan 21 03:07:23 PM PST 24 Jan 21 03:07:28 PM PST 24 21288897 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1829467449 Jan 21 03:05:56 PM PST 24 Jan 21 03:06:02 PM PST 24 76722336 ps
T811 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.779777111 Jan 21 03:06:16 PM PST 24 Jan 21 03:06:25 PM PST 24 266934451 ps
T179 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3498324641 Jan 21 03:06:16 PM PST 24 Jan 21 03:06:54 PM PST 24 955364253 ps
T812 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.451332573 Jan 21 03:07:29 PM PST 24 Jan 21 03:07:31 PM PST 24 17565918 ps
T813 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3728949372 Jan 21 03:06:02 PM PST 24 Jan 21 03:06:19 PM PST 24 3401034158 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2491837151 Jan 21 03:05:45 PM PST 24 Jan 21 03:05:49 PM PST 24 18869679 ps
T815 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2362435277 Jan 21 03:05:42 PM PST 24 Jan 21 03:05:52 PM PST 24 142500842 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.313194655 Jan 21 03:06:14 PM PST 24 Jan 21 03:06:18 PM PST 24 55751725 ps
T817 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3050079199 Jan 21 03:05:41 PM PST 24 Jan 21 03:05:47 PM PST 24 266174414 ps
T818 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3359655035 Jan 21 03:06:44 PM PST 24 Jan 21 03:06:49 PM PST 24 152569246 ps
T819 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.434199153 Jan 21 03:06:16 PM PST 24 Jan 21 03:06:26 PM PST 24 1174534514 ps
T820 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2501240592 Jan 21 03:07:46 PM PST 24 Jan 21 03:07:49 PM PST 24 16624317 ps
T821 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4120138551 Jan 21 03:06:30 PM PST 24 Jan 21 03:06:35 PM PST 24 76503031 ps
T822 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3068634063 Jan 21 03:05:54 PM PST 24 Jan 21 03:08:12 PM PST 24 1063345333 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1081926513 Jan 21 03:05:52 PM PST 24 Jan 21 03:09:29 PM PST 24 11859636346 ps
T147 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1325179332 Jan 21 03:05:47 PM PST 24 Jan 21 03:16:50 PM PST 24 4717234289 ps
T824 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3346579884 Jan 21 03:07:13 PM PST 24 Jan 21 03:07:22 PM PST 24 74419719 ps
T825 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1050612480 Jan 21 03:06:03 PM PST 24 Jan 21 03:06:05 PM PST 24 9725056 ps
T826 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4166695893 Jan 21 03:06:43 PM PST 24 Jan 21 03:06:49 PM PST 24 108314019 ps
T827 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3737175471 Jan 21 03:05:46 PM PST 24 Jan 21 03:05:48 PM PST 24 11923878 ps
T171 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3382101578 Jan 21 03:06:39 PM PST 24 Jan 21 03:07:16 PM PST 24 477163998 ps
T828 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.363600937 Jan 21 03:07:23 PM PST 24 Jan 21 03:07:28 PM PST 24 23113999 ps
T138 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1127829339 Jan 21 03:27:04 PM PST 24 Jan 21 03:33:37 PM PST 24 11346259685 ps
T829 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1028954132 Jan 21 03:07:12 PM PST 24 Jan 21 03:07:26 PM PST 24 877808722 ps
T830 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1998475487 Jan 21 03:07:30 PM PST 24 Jan 21 03:07:33 PM PST 24 8329043 ps
T152 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1730202795 Jan 21 03:05:55 PM PST 24 Jan 21 03:17:13 PM PST 24 4421309219 ps
T831 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2922034991 Jan 21 03:38:57 PM PST 24 Jan 21 03:39:03 PM PST 24 35266610 ps
T832 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2167145951 Jan 21 03:05:55 PM PST 24 Jan 21 03:05:57 PM PST 24 11404540 ps
T141 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2063908021 Jan 21 03:07:23 PM PST 24 Jan 21 03:12:35 PM PST 24 7270875626 ps
T833 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3532709501 Jan 21 03:14:15 PM PST 24 Jan 21 03:14:42 PM PST 24 328836124 ps
T834 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.872767122 Jan 21 03:07:12 PM PST 24 Jan 21 03:07:19 PM PST 24 15500511 ps
T168 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2528945582 Jan 21 03:06:41 PM PST 24 Jan 21 03:06:44 PM PST 24 115400449 ps
T835 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4285743944 Jan 21 03:05:53 PM PST 24 Jan 21 03:11:36 PM PST 24 31663899999 ps
T836 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2851391832 Jan 21 03:05:43 PM PST 24 Jan 21 03:06:04 PM PST 24 3189288010 ps
T148 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1108711920 Jan 21 03:05:56 PM PST 24 Jan 21 03:07:52 PM PST 24 11558978030 ps
T837 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3956426047 Jan 21 03:06:14 PM PST 24 Jan 21 03:14:41 PM PST 24 16441538830 ps
T838 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.428332803 Jan 21 03:07:29 PM PST 24 Jan 21 03:07:31 PM PST 24 12661721 ps
T175 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3977810345 Jan 21 03:05:41 PM PST 24 Jan 21 03:05:44 PM PST 24 50886337 ps
T153 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2614336369 Jan 21 03:06:13 PM PST 24 Jan 21 03:09:45 PM PST 24 3147573279 ps
T839 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.740972036 Jan 21 03:06:30 PM PST 24 Jan 21 03:07:07 PM PST 24 527469803 ps
T125 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.114076597 Jan 21 03:06:02 PM PST 24 Jan 21 03:23:25 PM PST 24 136213097510 ps
T840 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3395999906 Jan 21 03:07:30 PM PST 24 Jan 21 03:07:33 PM PST 24 16297588 ps
T154 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1419850238 Jan 21 03:06:33 PM PST 24 Jan 21 03:27:29 PM PST 24 64263133311 ps
T841 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2577898880 Jan 21 03:06:58 PM PST 24 Jan 21 03:07:04 PM PST 24 40469899 ps
T842 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3061188749 Jan 21 03:06:16 PM PST 24 Jan 21 03:06:27 PM PST 24 217877233 ps
T142 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3283118661 Jan 21 03:06:16 PM PST 24 Jan 21 03:15:59 PM PST 24 4746935968 ps
T843 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3299172679 Jan 21 03:06:49 PM PST 24 Jan 21 03:15:08 PM PST 24 7186266726 ps
T172 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4175561900 Jan 21 03:06:51 PM PST 24 Jan 21 03:06:57 PM PST 24 73169932 ps
T844 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.672640991 Jan 21 03:06:14 PM PST 24 Jan 21 03:06:38 PM PST 24 339585592 ps
T845 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.461793969 Jan 21 03:07:29 PM PST 24 Jan 21 03:07:32 PM PST 24 14628938 ps
T846 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1032411565 Jan 21 03:05:53 PM PST 24 Jan 21 03:06:05 PM PST 24 522850319 ps
T847 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.84910525 Jan 21 03:05:57 PM PST 24 Jan 21 03:08:16 PM PST 24 2126947745 ps
T151 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3092099352 Jan 21 03:32:05 PM PST 24 Jan 21 03:48:28 PM PST 24 15298507099 ps
T848 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.213469811 Jan 21 03:06:06 PM PST 24 Jan 21 03:06:08 PM PST 24 6479276 ps
T849 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.277492744 Jan 21 03:06:55 PM PST 24 Jan 21 03:06:57 PM PST 24 9802717 ps
T176 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3129910670 Jan 21 03:06:06 PM PST 24 Jan 21 03:06:54 PM PST 24 705270448 ps
T850 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.14863450 Jan 21 03:05:39 PM PST 24 Jan 21 03:05:44 PM PST 24 76221746 ps

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1779709962
Short name T14
Test name
Test status
Simulation time 1602637004 ps
CPU time 129.66 seconds
Started Jan 21 03:05:41 PM PST 24
Finished Jan 21 03:07:51 PM PST 24
Peak memory 256676 kb
Host smart-0f75e512-11df-4854-ae57-29ddd53c906d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1779709962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1779709962
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3114320608
Short name T7
Test name
Test status
Simulation time 75313978846 ps
CPU time 5103.2 seconds
Started Jan 21 09:25:09 PM PST 24
Finished Jan 21 10:50:18 PM PST 24
Peak memory 305632 kb
Host smart-2d25d8d0-2cb4-4c66-96e4-f611d79ab2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114320608 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3114320608
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3633123266
Short name T28
Test name
Test status
Simulation time 682225140 ps
CPU time 22.29 seconds
Started Jan 21 03:06:07 PM PST 24
Finished Jan 21 03:06:30 PM PST 24
Peak memory 236960 kb
Host smart-b48f9987-93b6-4dd2-8a29-831a92239e29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3633123266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3633123266
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3494401251
Short name T3
Test name
Test status
Simulation time 29069161280 ps
CPU time 1811.55 seconds
Started Jan 21 09:33:44 PM PST 24
Finished Jan 21 10:03:58 PM PST 24
Peak memory 271940 kb
Host smart-b83bb46e-1edf-427a-8337-5aba9522b666
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494401251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3494401251
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2612257925
Short name T11
Test name
Test status
Simulation time 211990124 ps
CPU time 13.14 seconds
Started Jan 21 09:22:37 PM PST 24
Finished Jan 21 09:22:54 PM PST 24
Peak memory 272768 kb
Host smart-d160e250-bd4e-4fca-88ea-63bb7906d536
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2612257925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2612257925
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1769961400
Short name T236
Test name
Test status
Simulation time 224372548769 ps
CPU time 2519.76 seconds
Started Jan 21 09:27:36 PM PST 24
Finished Jan 21 10:09:39 PM PST 24
Peak memory 286872 kb
Host smart-70d64038-3e90-4c74-abbc-3ad82b139761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769961400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1769961400
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.463993723
Short name T122
Test name
Test status
Simulation time 32431413558 ps
CPU time 1178.64 seconds
Started Jan 21 03:06:18 PM PST 24
Finished Jan 21 03:25:58 PM PST 24
Peak memory 272684 kb
Host smart-966762d4-2cb8-41c3-b05a-7091efd75ceb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463993723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.463993723
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2311493606
Short name T33
Test name
Test status
Simulation time 28182958561 ps
CPU time 2076.82 seconds
Started Jan 21 09:28:03 PM PST 24
Finished Jan 21 10:02:45 PM PST 24
Peak memory 281088 kb
Host smart-fe26cd25-a453-42f6-ab34-d35c5b18268f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311493606 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2311493606
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.742370188
Short name T159
Test name
Test status
Simulation time 23562495 ps
CPU time 1.81 seconds
Started Jan 21 03:07:26 PM PST 24
Finished Jan 21 03:07:29 PM PST 24
Peak memory 236188 kb
Host smart-4b76148e-9daf-4f02-9423-8c34e37bf6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=742370188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.742370188
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2637718082
Short name T117
Test name
Test status
Simulation time 9493648344 ps
CPU time 356.63 seconds
Started Jan 21 03:05:35 PM PST 24
Finished Jan 21 03:11:33 PM PST 24
Peak memory 272660 kb
Host smart-15747a68-7e54-4006-9364-1e1e5d371cf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2637718082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2637718082
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.661481453
Short name T60
Test name
Test status
Simulation time 85817771238 ps
CPU time 7544.62 seconds
Started Jan 21 09:31:36 PM PST 24
Finished Jan 21 11:37:46 PM PST 24
Peak memory 371048 kb
Host smart-b1aa50f7-91b2-4ad1-82aa-295b229bba5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661481453 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.661481453
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3075080156
Short name T89
Test name
Test status
Simulation time 120296736211 ps
CPU time 2156.52 seconds
Started Jan 21 09:30:09 PM PST 24
Finished Jan 21 10:06:27 PM PST 24
Peak memory 281740 kb
Host smart-be2d604d-8091-4410-8153-f54b90fb3cda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075080156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3075080156
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3071038349
Short name T139
Test name
Test status
Simulation time 42575515693 ps
CPU time 673.35 seconds
Started Jan 21 03:06:41 PM PST 24
Finished Jan 21 03:17:55 PM PST 24
Peak memory 265108 kb
Host smart-33252c88-cbc0-4dfc-94ea-4bf3a4c345c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071038349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3071038349
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.744405200
Short name T8
Test name
Test status
Simulation time 15910354358 ps
CPU time 643.28 seconds
Started Jan 21 09:48:53 PM PST 24
Finished Jan 21 09:59:40 PM PST 24
Peak memory 246664 kb
Host smart-1d9eeedc-bbd8-4673-96e1-9298b4936c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744405200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.744405200
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3092099352
Short name T151
Test name
Test status
Simulation time 15298507099 ps
CPU time 981.95 seconds
Started Jan 21 03:32:05 PM PST 24
Finished Jan 21 03:48:28 PM PST 24
Peak memory 265196 kb
Host smart-d1288779-4768-4e4b-ac34-37190035522a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092099352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3092099352
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3057075365
Short name T71
Test name
Test status
Simulation time 55790962262 ps
CPU time 3787.05 seconds
Started Jan 21 09:22:09 PM PST 24
Finished Jan 21 10:25:19 PM PST 24
Peak memory 304932 kb
Host smart-c47162dc-074d-4d73-8d43-0fc99b501110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057075365 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3057075365
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.752736971
Short name T118
Test name
Test status
Simulation time 12496732502 ps
CPU time 1034.7 seconds
Started Jan 21 03:05:42 PM PST 24
Finished Jan 21 03:22:58 PM PST 24
Peak memory 265032 kb
Host smart-02fef862-cc06-4e1b-b8d8-91a2c22835f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752736971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.752736971
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2440251416
Short name T316
Test name
Test status
Simulation time 159882922971 ps
CPU time 2450.95 seconds
Started Jan 21 09:28:03 PM PST 24
Finished Jan 21 10:08:56 PM PST 24
Peak memory 272020 kb
Host smart-991d5721-1bba-401c-99ce-049f316cc8a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440251416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2440251416
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.261194862
Short name T4
Test name
Test status
Simulation time 220169480257 ps
CPU time 3219.27 seconds
Started Jan 21 09:57:24 PM PST 24
Finished Jan 21 10:51:05 PM PST 24
Peak memory 287016 kb
Host smart-f60245b2-7da4-4984-89ae-8b22275a7035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261194862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.261194862
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2224930700
Short name T29
Test name
Test status
Simulation time 5394191386 ps
CPU time 350.84 seconds
Started Jan 21 03:06:13 PM PST 24
Finished Jan 21 03:12:05 PM PST 24
Peak memory 272620 kb
Host smart-84abfcb9-2acb-421e-bfcd-8c4276038942
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2224930700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2224930700
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1688330781
Short name T298
Test name
Test status
Simulation time 82710456154 ps
CPU time 561.3 seconds
Started Jan 21 09:34:02 PM PST 24
Finished Jan 21 09:43:41 PM PST 24
Peak memory 245580 kb
Host smart-6f59f235-eed3-4646-ab33-0193a0d23079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688330781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1688330781
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4003629799
Short name T143
Test name
Test status
Simulation time 3914526744 ps
CPU time 140.01 seconds
Started Jan 21 03:06:04 PM PST 24
Finished Jan 21 03:08:25 PM PST 24
Peak memory 256344 kb
Host smart-e26d0cf7-f93e-42df-b8d8-94ae16051333
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003629799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4003629799
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1926249843
Short name T85
Test name
Test status
Simulation time 22299749468 ps
CPU time 1295.88 seconds
Started Jan 21 09:35:38 PM PST 24
Finished Jan 21 09:57:23 PM PST 24
Peak memory 284240 kb
Host smart-3deb5914-edf9-4708-95f8-1c6ed01f0f79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926249843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1926249843
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2648959316
Short name T329
Test name
Test status
Simulation time 187954657430 ps
CPU time 2022.9 seconds
Started Jan 21 09:31:25 PM PST 24
Finished Jan 21 10:05:22 PM PST 24
Peak memory 271764 kb
Host smart-b2c03e72-a758-4509-ba4a-ae099fde90ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648959316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2648959316
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.175702683
Short name T114
Test name
Test status
Simulation time 95957787 ps
CPU time 10.84 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:29 PM PST 24
Peak memory 252244 kb
Host smart-0fa7e32b-fec3-4dee-a638-4793d55a9e00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=175702683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.175702683
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1717048220
Short name T311
Test name
Test status
Simulation time 46600944035 ps
CPU time 518.89 seconds
Started Jan 21 09:35:01 PM PST 24
Finished Jan 21 09:43:47 PM PST 24
Peak memory 246660 kb
Host smart-3dc7daee-54c0-4b1f-ab9b-dc28ce081506
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717048220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1717048220
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.739725301
Short name T87
Test name
Test status
Simulation time 71892446277 ps
CPU time 4793.18 seconds
Started Jan 21 09:37:58 PM PST 24
Finished Jan 21 10:57:56 PM PST 24
Peak memory 321860 kb
Host smart-058c6c16-90f3-4bb7-9623-458d90772ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739725301 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.739725301
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1127829339
Short name T138
Test name
Test status
Simulation time 11346259685 ps
CPU time 387.74 seconds
Started Jan 21 03:27:04 PM PST 24
Finished Jan 21 03:33:37 PM PST 24
Peak memory 265056 kb
Host smart-e8a50c95-1a14-4645-bc1e-14d97dd30bef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1127829339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1127829339
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4219408684
Short name T20
Test name
Test status
Simulation time 159168768650 ps
CPU time 4868.45 seconds
Started Jan 21 09:27:27 PM PST 24
Finished Jan 21 10:48:38 PM PST 24
Peak memory 304784 kb
Host smart-65d02cd4-8be8-403e-9442-e997873a2307
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219408684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4219408684
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.564897448
Short name T137
Test name
Test status
Simulation time 13419597525 ps
CPU time 922.39 seconds
Started Jan 21 03:06:42 PM PST 24
Finished Jan 21 03:22:05 PM PST 24
Peak memory 270488 kb
Host smart-4ed59292-2fd2-424e-a723-c09d0edf0fca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564897448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.564897448
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2558054948
Short name T309
Test name
Test status
Simulation time 11859347182 ps
CPU time 480.11 seconds
Started Jan 21 10:06:17 PM PST 24
Finished Jan 21 10:14:24 PM PST 24
Peak memory 246612 kb
Host smart-051f429b-18c2-4ad8-bd0c-b519f910e313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558054948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2558054948
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3634866783
Short name T340
Test name
Test status
Simulation time 6788435 ps
CPU time 1.56 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:19 PM PST 24
Peak memory 236160 kb
Host smart-03090f2c-db34-4aa4-934c-077a92274ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3634866783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3634866783
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.633660722
Short name T328
Test name
Test status
Simulation time 159834213847 ps
CPU time 2551.95 seconds
Started Jan 21 09:21:59 PM PST 24
Finished Jan 21 10:04:37 PM PST 24
Peak memory 286304 kb
Host smart-7218b9d3-1fa5-4777-b912-da6b74c145a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633660722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.633660722
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3990682577
Short name T32
Test name
Test status
Simulation time 74203098485 ps
CPU time 2627.99 seconds
Started Jan 21 09:23:52 PM PST 24
Finished Jan 21 10:07:50 PM PST 24
Peak memory 296896 kb
Host smart-15f27088-311c-493f-8d20-1e7429d0b241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990682577 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3990682577
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1271368804
Short name T258
Test name
Test status
Simulation time 210510765943 ps
CPU time 3483.82 seconds
Started Jan 21 09:33:28 PM PST 24
Finished Jan 21 10:31:35 PM PST 24
Peak memory 301104 kb
Host smart-330bea30-2455-4f4b-b296-ea98522184e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271368804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1271368804
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2739693438
Short name T37
Test name
Test status
Simulation time 52543867719 ps
CPU time 561.35 seconds
Started Jan 21 09:26:35 PM PST 24
Finished Jan 21 09:36:01 PM PST 24
Peak memory 246588 kb
Host smart-68b9f2a5-14c1-4f20-8fb4-fe011b0c200b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739693438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2739693438
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2869835109
Short name T128
Test name
Test status
Simulation time 6383551257 ps
CPU time 345.99 seconds
Started Jan 21 03:05:57 PM PST 24
Finished Jan 21 03:11:44 PM PST 24
Peak memory 265052 kb
Host smart-c331cd0a-362b-4a94-b689-9b33572125c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2869835109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2869835109
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3811120276
Short name T83
Test name
Test status
Simulation time 39470094472 ps
CPU time 1080.53 seconds
Started Jan 21 09:25:09 PM PST 24
Finished Jan 21 09:43:15 PM PST 24
Peak memory 272336 kb
Host smart-7cff3358-bf4f-4e49-9c13-802f60295ff3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811120276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3811120276
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2854365600
Short name T591
Test name
Test status
Simulation time 35988568864 ps
CPU time 902.21 seconds
Started Jan 21 10:21:43 PM PST 24
Finished Jan 21 10:36:50 PM PST 24
Peak memory 272704 kb
Host smart-5bcffef6-c4cf-40ea-9c12-44bc06b38722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854365600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2854365600
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1134439107
Short name T242
Test name
Test status
Simulation time 44442044125 ps
CPU time 2861.26 seconds
Started Jan 21 09:24:11 PM PST 24
Finished Jan 21 10:12:05 PM PST 24
Peak memory 280956 kb
Host smart-2a765ad0-b184-4e6b-a6d5-b06b87cff4ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134439107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1134439107
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2528945582
Short name T168
Test name
Test status
Simulation time 115400449 ps
CPU time 3.25 seconds
Started Jan 21 03:06:41 PM PST 24
Finished Jan 21 03:06:44 PM PST 24
Peak memory 236160 kb
Host smart-0d4d743d-8fbb-4f58-b9eb-952c40c62c00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2528945582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2528945582
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3741605137
Short name T249
Test name
Test status
Simulation time 41505442180 ps
CPU time 2485.94 seconds
Started Jan 21 09:27:03 PM PST 24
Finished Jan 21 10:08:39 PM PST 24
Peak memory 289040 kb
Host smart-2cbfc8d2-61e4-4c60-9af8-469a930a3f09
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741605137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3741605137
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2614336369
Short name T153
Test name
Test status
Simulation time 3147573279 ps
CPU time 211.45 seconds
Started Jan 21 03:06:13 PM PST 24
Finished Jan 21 03:09:45 PM PST 24
Peak memory 264912 kb
Host smart-b9140e9a-5bd1-47bc-8753-c591b002411a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2614336369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2614336369
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2080195485
Short name T300
Test name
Test status
Simulation time 11336941850 ps
CPU time 467.19 seconds
Started Jan 21 09:31:25 PM PST 24
Finished Jan 21 09:39:26 PM PST 24
Peak memory 248112 kb
Host smart-c30a8fc4-0640-4924-830d-636fc7d9baf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080195485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2080195485
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3123414955
Short name T220
Test name
Test status
Simulation time 13650861067 ps
CPU time 1057.84 seconds
Started Jan 21 09:36:31 PM PST 24
Finished Jan 21 09:54:18 PM PST 24
Peak memory 286852 kb
Host smart-f68440dd-15a6-4fa9-a0f8-149d46d7138e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123414955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3123414955
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2719576896
Short name T119
Test name
Test status
Simulation time 94797368014 ps
CPU time 1232.07 seconds
Started Jan 21 03:07:10 PM PST 24
Finished Jan 21 03:27:45 PM PST 24
Peak memory 264972 kb
Host smart-3ee501cf-916d-424f-9dd0-5cc445572fd6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719576896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2719576896
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1799283025
Short name T39
Test name
Test status
Simulation time 971712471 ps
CPU time 11.1 seconds
Started Jan 21 09:21:39 PM PST 24
Finished Jan 21 09:21:54 PM PST 24
Peak memory 272760 kb
Host smart-8995347a-f47e-404d-a782-d8d3283a052d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1799283025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1799283025
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2939904901
Short name T210
Test name
Test status
Simulation time 16760835 ps
CPU time 2.23 seconds
Started Jan 21 09:21:38 PM PST 24
Finished Jan 21 09:21:44 PM PST 24
Peak memory 248356 kb
Host smart-f8fc481a-9746-409e-9cbf-e79be6612f7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2939904901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2939904901
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1199190326
Short name T208
Test name
Test status
Simulation time 58954468 ps
CPU time 3.24 seconds
Started Jan 21 09:22:09 PM PST 24
Finished Jan 21 09:22:15 PM PST 24
Peak memory 248364 kb
Host smart-508dc154-5833-4953-9811-da707f2c4b2b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1199190326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1199190326
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1982391104
Short name T198
Test name
Test status
Simulation time 29295219 ps
CPU time 2.38 seconds
Started Jan 21 09:25:09 PM PST 24
Finished Jan 21 09:25:17 PM PST 24
Peak memory 248344 kb
Host smart-69d601b8-1b75-4ba6-92fe-b89475aff293
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1982391104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1982391104
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1066284464
Short name T212
Test name
Test status
Simulation time 56235030 ps
CPU time 3.35 seconds
Started Jan 21 09:27:20 PM PST 24
Finished Jan 21 09:27:25 PM PST 24
Peak memory 248352 kb
Host smart-74a49f18-c06a-4ce8-9ace-d7b26e5589a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1066284464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1066284464
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3484766512
Short name T314
Test name
Test status
Simulation time 44486960419 ps
CPU time 498.9 seconds
Started Jan 21 09:24:37 PM PST 24
Finished Jan 21 09:33:03 PM PST 24
Peak memory 245696 kb
Host smart-91b2d132-0eca-455b-9bac-edb70d2c01b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484766512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3484766512
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3665572897
Short name T291
Test name
Test status
Simulation time 1701727430 ps
CPU time 52.32 seconds
Started Jan 21 09:27:08 PM PST 24
Finished Jan 21 09:28:07 PM PST 24
Peak memory 246012 kb
Host smart-e82ce400-5f6c-4715-a637-223c2643e1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36655
72897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3665572897
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.4153271255
Short name T36
Test name
Test status
Simulation time 85098357175 ps
CPU time 4534.82 seconds
Started Jan 21 09:27:36 PM PST 24
Finished Jan 21 10:43:15 PM PST 24
Peak memory 337240 kb
Host smart-9bfde118-1d8e-4222-98eb-575b09c2e0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153271255 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.4153271255
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2189024772
Short name T330
Test name
Test status
Simulation time 171205890919 ps
CPU time 3460.87 seconds
Started Jan 21 10:30:15 PM PST 24
Finished Jan 21 11:28:08 PM PST 24
Peak memory 288652 kb
Host smart-e070aa80-9dcc-4b9d-ba1d-46049a9dce46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189024772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2189024772
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3819268648
Short name T247
Test name
Test status
Simulation time 323528989791 ps
CPU time 5820.46 seconds
Started Jan 21 09:28:13 PM PST 24
Finished Jan 21 11:05:22 PM PST 24
Peak memory 321932 kb
Host smart-be2449d9-4567-425d-aad4-a5366538494b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819268648 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3819268648
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3540026205
Short name T257
Test name
Test status
Simulation time 19450928718 ps
CPU time 595.16 seconds
Started Jan 21 09:28:23 PM PST 24
Finished Jan 21 09:38:24 PM PST 24
Peak memory 253676 kb
Host smart-4226ef77-8735-47d1-9872-a166234d033c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540026205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3540026205
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.430193289
Short name T274
Test name
Test status
Simulation time 51055505067 ps
CPU time 1656.63 seconds
Started Jan 21 09:30:40 PM PST 24
Finished Jan 21 09:58:35 PM PST 24
Peak memory 288684 kb
Host smart-c2d1e6cc-d985-41f9-b4d8-62fc4e497314
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430193289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.430193289
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.510622778
Short name T327
Test name
Test status
Simulation time 146493462554 ps
CPU time 2366.58 seconds
Started Jan 21 09:32:01 PM PST 24
Finished Jan 21 10:11:51 PM PST 24
Peak memory 280956 kb
Host smart-b941b083-3b06-401b-bf58-30316ef7e80d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510622778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.510622778
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1192095373
Short name T250
Test name
Test status
Simulation time 50128952855 ps
CPU time 2916.22 seconds
Started Jan 21 09:36:56 PM PST 24
Finished Jan 21 10:25:49 PM PST 24
Peak memory 305616 kb
Host smart-d9cc6cac-b659-4832-b199-4f30aca4ee79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192095373 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1192095373
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.370745484
Short name T280
Test name
Test status
Simulation time 303670656021 ps
CPU time 5141.2 seconds
Started Jan 21 09:33:00 PM PST 24
Finished Jan 21 10:58:52 PM PST 24
Peak memory 321516 kb
Host smart-6d4d73d6-e5f8-4799-8ca9-f192a229ad53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370745484 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.370745484
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.176392177
Short name T169
Test name
Test status
Simulation time 2556000001 ps
CPU time 92.46 seconds
Started Jan 21 03:05:58 PM PST 24
Finished Jan 21 03:07:32 PM PST 24
Peak memory 240220 kb
Host smart-e071a318-a74e-4828-90a0-d5d023fe8e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=176392177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.176392177
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1108711920
Short name T148
Test name
Test status
Simulation time 11558978030 ps
CPU time 113.92 seconds
Started Jan 21 03:05:56 PM PST 24
Finished Jan 21 03:07:52 PM PST 24
Peak memory 265640 kb
Host smart-0fead85a-34f7-4e66-8d57-1e3c22ea43f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1108711920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1108711920
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.904135516
Short name T126
Test name
Test status
Simulation time 2271368525 ps
CPU time 158.14 seconds
Started Jan 21 03:06:27 PM PST 24
Finished Jan 21 03:09:05 PM PST 24
Peak memory 256792 kb
Host smart-b7280fd7-3493-4ae2-9fbd-3457d665c725
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=904135516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.904135516
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2259943469
Short name T319
Test name
Test status
Simulation time 57724721533 ps
CPU time 559.23 seconds
Started Jan 21 09:21:59 PM PST 24
Finished Jan 21 09:31:25 PM PST 24
Peak memory 249332 kb
Host smart-b3272d00-2534-44fb-9359-1a3b53f658df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259943469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2259943469
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2790348566
Short name T267
Test name
Test status
Simulation time 54881527210 ps
CPU time 2601.64 seconds
Started Jan 21 09:25:33 PM PST 24
Finished Jan 21 10:08:57 PM PST 24
Peak memory 321276 kb
Host smart-5fd2e74f-dbf3-41db-9ff8-c9efa9604b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790348566 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2790348566
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3513393344
Short name T189
Test name
Test status
Simulation time 234140959877 ps
CPU time 2020.92 seconds
Started Jan 21 09:26:26 PM PST 24
Finished Jan 21 10:00:13 PM PST 24
Peak memory 280896 kb
Host smart-8abdce45-db53-4598-84a8-3dc6fe122911
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513393344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3513393344
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3366181707
Short name T15
Test name
Test status
Simulation time 317213303534 ps
CPU time 7714.95 seconds
Started Jan 21 09:29:01 PM PST 24
Finished Jan 21 11:37:49 PM PST 24
Peak memory 394020 kb
Host smart-1f400ee4-1004-43c7-8ce0-b7131569e7ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366181707 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3366181707
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.657889202
Short name T240
Test name
Test status
Simulation time 2866689307 ps
CPU time 69.64 seconds
Started Jan 21 09:29:22 PM PST 24
Finished Jan 21 09:30:41 PM PST 24
Peak memory 255076 kb
Host smart-c09ecc2c-724b-49e2-9c39-af6ea9bf01d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657889202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.657889202
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2990877354
Short name T86
Test name
Test status
Simulation time 126870163 ps
CPU time 9.77 seconds
Started Jan 21 09:29:29 PM PST 24
Finished Jan 21 09:29:46 PM PST 24
Peak memory 248104 kb
Host smart-070b8dff-9252-4e7a-ac2c-087708c2fc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29908
77354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2990877354
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2184866069
Short name T46
Test name
Test status
Simulation time 51918332471 ps
CPU time 3159.84 seconds
Started Jan 21 09:30:48 PM PST 24
Finished Jan 21 10:23:46 PM PST 24
Peak memory 305232 kb
Host smart-4dc6070c-9ada-425b-b5f2-d3f159da2521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184866069 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2184866069
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.556741286
Short name T275
Test name
Test status
Simulation time 1143756070 ps
CPU time 33.83 seconds
Started Jan 21 09:31:10 PM PST 24
Finished Jan 21 09:31:53 PM PST 24
Peak memory 248084 kb
Host smart-817bd49e-1a2f-4dda-b70a-e7b74b64f4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55674
1286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.556741286
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2686148509
Short name T241
Test name
Test status
Simulation time 10408716957 ps
CPU time 170.9 seconds
Started Jan 21 09:31:34 PM PST 24
Finished Jan 21 09:34:47 PM PST 24
Peak memory 256368 kb
Host smart-bbabae35-8abc-411c-b367-2add3df23d2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686148509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2686148509
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3727316673
Short name T287
Test name
Test status
Simulation time 19088104493 ps
CPU time 719.56 seconds
Started Jan 21 09:33:15 PM PST 24
Finished Jan 21 09:45:21 PM PST 24
Peak memory 264712 kb
Host smart-8144f322-64e9-4f85-a8df-6ffc1efdb58b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727316673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3727316673
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3533618389
Short name T68
Test name
Test status
Simulation time 449644160 ps
CPU time 29.64 seconds
Started Jan 21 09:35:54 PM PST 24
Finished Jan 21 09:36:30 PM PST 24
Peak memory 254336 kb
Host smart-02549ef4-123a-4fdf-80ad-80dc1629df0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35336
18389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3533618389
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3521906561
Short name T288
Test name
Test status
Simulation time 22282243862 ps
CPU time 1362.74 seconds
Started Jan 21 09:23:53 PM PST 24
Finished Jan 21 09:46:46 PM PST 24
Peak memory 285300 kb
Host smart-11368b86-0837-4186-99ad-7e67bb40d497
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521906561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3521906561
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2395036173
Short name T318
Test name
Test status
Simulation time 13695304486 ps
CPU time 295.4 seconds
Started Jan 21 09:21:28 PM PST 24
Finished Jan 21 09:26:26 PM PST 24
Peak memory 245696 kb
Host smart-aff1a5e7-f838-4787-a4ed-560a77f16631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395036173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2395036173
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4178844604
Short name T121
Test name
Test status
Simulation time 2021815349 ps
CPU time 156.24 seconds
Started Jan 21 03:06:38 PM PST 24
Finished Jan 21 03:09:15 PM PST 24
Peak memory 264064 kb
Host smart-6fcd91ee-4246-4596-a2eb-cacbce57d9b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4178844604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.4178844604
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4175561900
Short name T172
Test name
Test status
Simulation time 73169932 ps
CPU time 4.82 seconds
Started Jan 21 03:06:51 PM PST 24
Finished Jan 21 03:06:57 PM PST 24
Peak memory 235240 kb
Host smart-b55025ba-a37b-41eb-8fc1-d4e0329a0344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4175561900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4175561900
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2836698555
Short name T178
Test name
Test status
Simulation time 1201657600 ps
CPU time 45.52 seconds
Started Jan 21 03:06:18 PM PST 24
Finished Jan 21 03:07:05 PM PST 24
Peak memory 239140 kb
Host smart-e0f66dc7-3f99-4456-9341-70595cb18c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2836698555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2836698555
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3305592775
Short name T166
Test name
Test status
Simulation time 87069114 ps
CPU time 5.55 seconds
Started Jan 21 03:06:55 PM PST 24
Finished Jan 21 03:07:01 PM PST 24
Peak memory 236092 kb
Host smart-ae6e4f80-d4cd-450d-af63-b6d66b97ef60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3305592775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3305592775
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1648808546
Short name T156
Test name
Test status
Simulation time 6530128839 ps
CPU time 86.51 seconds
Started Jan 21 03:07:12 PM PST 24
Finished Jan 21 03:08:47 PM PST 24
Peak memory 239076 kb
Host smart-ad621492-3dee-4423-bbf2-eb6b8cf987d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1648808546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1648808546
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3977810345
Short name T175
Test name
Test status
Simulation time 50886337 ps
CPU time 2.41 seconds
Started Jan 21 03:05:41 PM PST 24
Finished Jan 21 03:05:44 PM PST 24
Peak memory 236632 kb
Host smart-820c6c56-3643-4e72-821c-d24c7243971e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3977810345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3977810345
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1657371760
Short name T140
Test name
Test status
Simulation time 19245979457 ps
CPU time 351.37 seconds
Started Jan 21 03:06:24 PM PST 24
Finished Jan 21 03:12:16 PM PST 24
Peak memory 272356 kb
Host smart-8dc7dbbe-598d-4652-bf7b-841ceb7505f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1657371760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1657371760
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3988292056
Short name T116
Test name
Test status
Simulation time 3625525807 ps
CPU time 176.85 seconds
Started Jan 21 03:06:38 PM PST 24
Finished Jan 21 03:09:36 PM PST 24
Peak memory 265016 kb
Host smart-1bf89341-bb73-4017-9234-05d31b0002e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3988292056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3988292056
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2682987940
Short name T130
Test name
Test status
Simulation time 1103465985 ps
CPU time 99.73 seconds
Started Jan 21 03:05:56 PM PST 24
Finished Jan 21 03:07:37 PM PST 24
Peak memory 256700 kb
Host smart-9df11895-819f-41b7-8a7d-e7e4841b80cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2682987940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2682987940
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2857410046
Short name T170
Test name
Test status
Simulation time 1136847846 ps
CPU time 36.42 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:53 PM PST 24
Peak memory 238872 kb
Host smart-b01559c8-c179-49c7-bfe3-6619e2cb618b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2857410046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2857410046
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1652237155
Short name T174
Test name
Test status
Simulation time 4229122560 ps
CPU time 45.28 seconds
Started Jan 21 03:06:18 PM PST 24
Finished Jan 21 03:07:05 PM PST 24
Peak memory 236440 kb
Host smart-769fa2e5-ec16-43e2-b702-d7ab433c6eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1652237155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1652237155
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2567305823
Short name T167
Test name
Test status
Simulation time 1307223050 ps
CPU time 45.17 seconds
Started Jan 21 03:43:59 PM PST 24
Finished Jan 21 03:44:45 PM PST 24
Peak memory 240152 kb
Host smart-ad2127d1-dce8-49f2-ad80-a82125a78e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2567305823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2567305823
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3142486237
Short name T155
Test name
Test status
Simulation time 46287144 ps
CPU time 2.67 seconds
Started Jan 21 03:06:33 PM PST 24
Finished Jan 21 03:06:37 PM PST 24
Peak memory 236080 kb
Host smart-7798a468-1ec2-478e-937f-d001aa02badc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3142486237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3142486237
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3382101578
Short name T171
Test name
Test status
Simulation time 477163998 ps
CPU time 36.41 seconds
Started Jan 21 03:06:39 PM PST 24
Finished Jan 21 03:07:16 PM PST 24
Peak memory 240124 kb
Host smart-005330f5-1666-44c2-aa9f-5239b3b0dc91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3382101578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3382101578
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.380243576
Short name T165
Test name
Test status
Simulation time 611548110 ps
CPU time 20.57 seconds
Started Jan 21 03:06:51 PM PST 24
Finished Jan 21 03:07:12 PM PST 24
Peak memory 244700 kb
Host smart-6c8a2f42-1bba-4250-ad4d-e21f2b001fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=380243576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.380243576
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3158920308
Short name T173
Test name
Test status
Simulation time 296304107 ps
CPU time 20.71 seconds
Started Jan 21 03:07:12 PM PST 24
Finished Jan 21 03:07:41 PM PST 24
Peak memory 239984 kb
Host smart-7f22de4b-7c3e-4397-9b96-75f6b48eab94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3158920308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3158920308
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.330420545
Short name T180
Test name
Test status
Simulation time 1875905852 ps
CPU time 36.57 seconds
Started Jan 21 03:05:51 PM PST 24
Finished Jan 21 03:06:28 PM PST 24
Peak memory 239120 kb
Host smart-90269ec4-1ad9-4cec-8e52-1dcee6a5e864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=330420545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.330420545
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3498324641
Short name T179
Test name
Test status
Simulation time 955364253 ps
CPU time 36.98 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:54 PM PST 24
Peak memory 239724 kb
Host smart-06cfa11b-f949-4cba-90c1-6815bdd764ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3498324641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3498324641
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3129910670
Short name T176
Test name
Test status
Simulation time 705270448 ps
CPU time 47.93 seconds
Started Jan 21 03:06:06 PM PST 24
Finished Jan 21 03:06:54 PM PST 24
Peak memory 236332 kb
Host smart-e005acc3-110e-44fe-8791-6d4f1d933fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3129910670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3129910670
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3237083318
Short name T30
Test name
Test status
Simulation time 8629363113 ps
CPU time 385.33 seconds
Started Jan 21 09:36:55 PM PST 24
Finished Jan 21 09:43:38 PM PST 24
Peak memory 246676 kb
Host smart-6be51aa5-8760-4fd1-92e4-15784011c1fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237083318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3237083318
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2477686859
Short name T788
Test name
Test status
Simulation time 578096694 ps
CPU time 67.62 seconds
Started Jan 21 03:05:39 PM PST 24
Finished Jan 21 03:06:47 PM PST 24
Peak memory 240072 kb
Host smart-a92657e4-288a-4242-a6aa-8b26d0f11ee4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2477686859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2477686859
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1848674182
Short name T195
Test name
Test status
Simulation time 8559456245 ps
CPU time 269.77 seconds
Started Jan 21 03:05:44 PM PST 24
Finished Jan 21 03:10:15 PM PST 24
Peak memory 236152 kb
Host smart-b60ed556-c825-4cc8-b9d4-181128316d88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1848674182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1848674182
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2962191830
Short name T144
Test name
Test status
Simulation time 99311653 ps
CPU time 5.63 seconds
Started Jan 21 03:05:43 PM PST 24
Finished Jan 21 03:05:50 PM PST 24
Peak memory 239956 kb
Host smart-5122e4d3-c210-47b4-bd5a-454ce52797ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2962191830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2962191830
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2491837151
Short name T814
Test name
Test status
Simulation time 18869679 ps
CPU time 3.79 seconds
Started Jan 21 03:05:45 PM PST 24
Finished Jan 21 03:05:49 PM PST 24
Peak memory 239916 kb
Host smart-16018372-5898-4612-9d6f-d034770d6f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491837151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2491837151
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3050079199
Short name T817
Test name
Test status
Simulation time 266174414 ps
CPU time 5.14 seconds
Started Jan 21 03:05:41 PM PST 24
Finished Jan 21 03:05:47 PM PST 24
Peak memory 235088 kb
Host smart-e6939aba-46d5-463f-b8ef-f6969050f853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3050079199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3050079199
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2718838738
Short name T185
Test name
Test status
Simulation time 9018062 ps
CPU time 1.64 seconds
Started Jan 21 03:05:41 PM PST 24
Finished Jan 21 03:05:43 PM PST 24
Peak memory 236024 kb
Host smart-ccd41154-0a1c-4ec1-bfb2-2e948d77df44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2718838738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2718838738
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.774630294
Short name T771
Test name
Test status
Simulation time 1366751362 ps
CPU time 23.78 seconds
Started Jan 21 03:05:41 PM PST 24
Finished Jan 21 03:06:05 PM PST 24
Peak memory 240084 kb
Host smart-c56fb23f-6016-4745-b6c9-3c1e6c4e6290
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=774630294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.774630294
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3822656719
Short name T120
Test name
Test status
Simulation time 24090502571 ps
CPU time 510.47 seconds
Started Jan 21 03:17:13 PM PST 24
Finished Jan 21 03:25:44 PM PST 24
Peak memory 268192 kb
Host smart-ad9753b2-366f-4a85-b724-9506522f0497
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822656719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3822656719
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3532709501
Short name T833
Test name
Test status
Simulation time 328836124 ps
CPU time 24.66 seconds
Started Jan 21 03:14:15 PM PST 24
Finished Jan 21 03:14:42 PM PST 24
Peak memory 247936 kb
Host smart-b019aa8d-dc53-4db3-99f6-22eb12e823d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3532709501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3532709501
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3053051405
Short name T790
Test name
Test status
Simulation time 24916414992 ps
CPU time 154.11 seconds
Started Jan 21 03:05:45 PM PST 24
Finished Jan 21 03:08:20 PM PST 24
Peak memory 240168 kb
Host smart-9d16d682-d565-4369-8ab9-675088289e78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3053051405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3053051405
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3710666814
Short name T21
Test name
Test status
Simulation time 821571905 ps
CPU time 93.15 seconds
Started Jan 21 03:05:44 PM PST 24
Finished Jan 21 03:07:19 PM PST 24
Peak memory 235204 kb
Host smart-830ff9b5-4398-414a-ad07-1d00c259748e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3710666814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3710666814
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2362435277
Short name T815
Test name
Test status
Simulation time 142500842 ps
CPU time 10.02 seconds
Started Jan 21 03:05:42 PM PST 24
Finished Jan 21 03:05:52 PM PST 24
Peak memory 240080 kb
Host smart-099fd4e7-b31e-4e5a-afb5-44c6b035bc33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2362435277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2362435277
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.14863450
Short name T850
Test name
Test status
Simulation time 76221746 ps
CPU time 4.45 seconds
Started Jan 21 03:05:39 PM PST 24
Finished Jan 21 03:05:44 PM PST 24
Peak memory 237612 kb
Host smart-03fdd38b-db04-4454-be55-02c1bfafe786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14863450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.alert_handler_csr_mem_rw_with_rand_reset.14863450
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1171051526
Short name T765
Test name
Test status
Simulation time 61432895 ps
CPU time 3.31 seconds
Started Jan 21 03:05:47 PM PST 24
Finished Jan 21 03:05:51 PM PST 24
Peak memory 239916 kb
Host smart-29b5e3e9-3d9d-4a7d-a30a-17b06ccce454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1171051526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1171051526
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3737175471
Short name T827
Test name
Test status
Simulation time 11923878 ps
CPU time 1.31 seconds
Started Jan 21 03:05:46 PM PST 24
Finished Jan 21 03:05:48 PM PST 24
Peak memory 236160 kb
Host smart-d6a00448-1c34-45c6-8f8e-8baa907151dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3737175471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3737175471
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2851391832
Short name T836
Test name
Test status
Simulation time 3189288010 ps
CPU time 20.18 seconds
Started Jan 21 03:05:43 PM PST 24
Finished Jan 21 03:06:04 PM PST 24
Peak memory 244372 kb
Host smart-a0efa4e9-ed0c-4961-86ac-5fac8e55a707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2851391832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2851391832
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1325179332
Short name T147
Test name
Test status
Simulation time 4717234289 ps
CPU time 661.94 seconds
Started Jan 21 03:05:47 PM PST 24
Finished Jan 21 03:16:50 PM PST 24
Peak memory 265144 kb
Host smart-244715cf-0739-4bbd-837a-d10aed01f1b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325179332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1325179332
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1440437901
Short name T758
Test name
Test status
Simulation time 292517252 ps
CPU time 8.86 seconds
Started Jan 21 03:05:43 PM PST 24
Finished Jan 21 03:05:52 PM PST 24
Peak memory 240096 kb
Host smart-06e1c218-e692-4241-b9c8-f79abe93281e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1440437901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1440437901
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4267798142
Short name T797
Test name
Test status
Simulation time 173907530 ps
CPU time 3.55 seconds
Started Jan 21 03:05:47 PM PST 24
Finished Jan 21 03:05:52 PM PST 24
Peak memory 236520 kb
Host smart-2236284e-1506-469b-b73c-4ced98ce21f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4267798142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.4267798142
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.430638492
Short name T791
Test name
Test status
Simulation time 26410790 ps
CPU time 5.29 seconds
Started Jan 21 03:06:21 PM PST 24
Finished Jan 21 03:06:29 PM PST 24
Peak memory 251148 kb
Host smart-25bb49bf-804b-4f67-9244-0227f94d81e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430638492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.430638492
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.353647561
Short name T762
Test name
Test status
Simulation time 35425007 ps
CPU time 5.16 seconds
Started Jan 21 03:06:24 PM PST 24
Finished Jan 21 03:06:30 PM PST 24
Peak memory 235212 kb
Host smart-085270fc-2a2a-4344-892d-420ce5b65967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=353647561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.353647561
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.518733175
Short name T341
Test name
Test status
Simulation time 11705099 ps
CPU time 1.69 seconds
Started Jan 21 03:06:17 PM PST 24
Finished Jan 21 03:06:21 PM PST 24
Peak memory 236128 kb
Host smart-efcbc92e-468d-47ab-bf45-d792a4e3ea44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=518733175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.518733175
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4156716393
Short name T766
Test name
Test status
Simulation time 91398656 ps
CPU time 11.8 seconds
Started Jan 21 03:06:17 PM PST 24
Finished Jan 21 03:06:31 PM PST 24
Peak memory 240104 kb
Host smart-792e68de-b249-4b8f-882f-cd45b7ddc237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4156716393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4156716393
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.434199153
Short name T819
Test name
Test status
Simulation time 1174534514 ps
CPU time 8.43 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:26 PM PST 24
Peak memory 248400 kb
Host smart-be9a4987-ffd8-4401-8f7d-5002b46177e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=434199153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.434199153
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.438630602
Short name T777
Test name
Test status
Simulation time 129848156 ps
CPU time 4.52 seconds
Started Jan 21 03:06:38 PM PST 24
Finished Jan 21 03:06:44 PM PST 24
Peak memory 236156 kb
Host smart-b87a6b30-f1af-4827-8ec1-0725d6ed5d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438630602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.438630602
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3702820452
Short name T349
Test name
Test status
Simulation time 62489074 ps
CPU time 5.55 seconds
Started Jan 21 03:06:43 PM PST 24
Finished Jan 21 03:06:49 PM PST 24
Peak memory 239732 kb
Host smart-72882fd5-840f-4859-837c-6f1cd5e5051b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3702820452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3702820452
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1011246693
Short name T744
Test name
Test status
Simulation time 8033221 ps
CPU time 1.57 seconds
Started Jan 21 03:06:41 PM PST 24
Finished Jan 21 03:06:43 PM PST 24
Peak memory 234256 kb
Host smart-86c92b83-d35f-4730-88fc-6f9f9a71a6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1011246693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1011246693
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3319114802
Short name T146
Test name
Test status
Simulation time 651800034 ps
CPU time 24.76 seconds
Started Jan 21 03:06:33 PM PST 24
Finished Jan 21 03:06:59 PM PST 24
Peak memory 244276 kb
Host smart-1912e958-241b-4da0-b130-924592aafee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3319114802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3319114802
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3785808286
Short name T127
Test name
Test status
Simulation time 9447893734 ps
CPU time 606.93 seconds
Started Jan 21 03:46:28 PM PST 24
Finished Jan 21 03:56:37 PM PST 24
Peak memory 265252 kb
Host smart-5cd857eb-74ea-482a-9db9-6b180bf1b569
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785808286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3785808286
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2763993409
Short name T801
Test name
Test status
Simulation time 151402424 ps
CPU time 5.92 seconds
Started Jan 21 03:06:34 PM PST 24
Finished Jan 21 03:06:41 PM PST 24
Peak memory 251528 kb
Host smart-8a1989b8-0b31-400f-923f-c4210cd8228e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2763993409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2763993409
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2904040971
Short name T798
Test name
Test status
Simulation time 825934685 ps
CPU time 7.46 seconds
Started Jan 21 03:06:25 PM PST 24
Finished Jan 21 03:06:34 PM PST 24
Peak memory 250992 kb
Host smart-9a96ff69-e439-4672-821a-dcdfb12d3241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904040971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2904040971
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4120138551
Short name T821
Test name
Test status
Simulation time 76503031 ps
CPU time 3.51 seconds
Started Jan 21 03:06:30 PM PST 24
Finished Jan 21 03:06:35 PM PST 24
Peak memory 239816 kb
Host smart-3fda45c2-9ada-46c2-8881-637feaf86957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4120138551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4120138551
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.740972036
Short name T839
Test name
Test status
Simulation time 527469803 ps
CPU time 36.49 seconds
Started Jan 21 03:06:30 PM PST 24
Finished Jan 21 03:07:07 PM PST 24
Peak memory 244336 kb
Host smart-48fb00e5-9322-4e8f-8764-60e9debd947e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=740972036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.740972036
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2231841065
Short name T787
Test name
Test status
Simulation time 622255941 ps
CPU time 11.55 seconds
Started Jan 21 03:06:25 PM PST 24
Finished Jan 21 03:06:38 PM PST 24
Peak memory 248332 kb
Host smart-6cd32292-71fc-450a-bed7-a43ad2bc20dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2231841065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2231841065
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4036203858
Short name T804
Test name
Test status
Simulation time 20888249 ps
CPU time 4.3 seconds
Started Jan 21 03:06:29 PM PST 24
Finished Jan 21 03:06:35 PM PST 24
Peak memory 248260 kb
Host smart-6712e1f7-2d26-437c-9ffb-f2ffca108854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036203858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.4036203858
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3047934687
Short name T149
Test name
Test status
Simulation time 20265318 ps
CPU time 3.33 seconds
Started Jan 21 03:06:33 PM PST 24
Finished Jan 21 03:06:38 PM PST 24
Peak memory 238840 kb
Host smart-c3948f60-e5f3-4b39-bf65-b1bde2206c2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3047934687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3047934687
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3459606555
Short name T789
Test name
Test status
Simulation time 28645530 ps
CPU time 1.5 seconds
Started Jan 21 03:06:33 PM PST 24
Finished Jan 21 03:06:36 PM PST 24
Peak memory 236024 kb
Host smart-9dfb346f-d4cf-4164-bdca-e6dbc7a74987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3459606555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3459606555
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2399321641
Short name T782
Test name
Test status
Simulation time 178131968 ps
CPU time 21.05 seconds
Started Jan 21 03:06:39 PM PST 24
Finished Jan 21 03:07:01 PM PST 24
Peak memory 244320 kb
Host smart-9a71a5f3-c561-4de4-bc38-90047cc9710c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2399321641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2399321641
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3459374806
Short name T134
Test name
Test status
Simulation time 66348838399 ps
CPU time 1330.64 seconds
Started Jan 21 03:06:30 PM PST 24
Finished Jan 21 03:28:42 PM PST 24
Peak memory 265036 kb
Host smart-4157b9dc-df53-4fbb-8c40-e2d29b3f71df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459374806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3459374806
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3492559979
Short name T162
Test name
Test status
Simulation time 620543889 ps
CPU time 12.12 seconds
Started Jan 21 03:06:32 PM PST 24
Finished Jan 21 03:06:46 PM PST 24
Peak memory 248228 kb
Host smart-fca4ca0a-6b8f-4305-8802-41ebaabcdde3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3492559979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3492559979
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3359655035
Short name T818
Test name
Test status
Simulation time 152569246 ps
CPU time 4.68 seconds
Started Jan 21 03:06:44 PM PST 24
Finished Jan 21 03:06:49 PM PST 24
Peak memory 238396 kb
Host smart-1ee02519-bd0d-4aec-bd07-0ce779a34437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359655035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3359655035
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3738812350
Short name T24
Test name
Test status
Simulation time 259887761 ps
CPU time 5.23 seconds
Started Jan 21 03:06:41 PM PST 24
Finished Jan 21 03:06:47 PM PST 24
Peak memory 235944 kb
Host smart-613f4372-0e03-4e3b-bcaf-34cb495892f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3738812350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3738812350
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1045642647
Short name T746
Test name
Test status
Simulation time 34058663 ps
CPU time 1.53 seconds
Started Jan 21 03:06:41 PM PST 24
Finished Jan 21 03:06:44 PM PST 24
Peak memory 235248 kb
Host smart-1a42b627-1ff5-477e-9b03-f150cc7b6e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1045642647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1045642647
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.451492340
Short name T769
Test name
Test status
Simulation time 804968874 ps
CPU time 49.28 seconds
Started Jan 21 03:06:41 PM PST 24
Finished Jan 21 03:07:31 PM PST 24
Peak memory 248188 kb
Host smart-efe5311f-bf24-4fa0-9481-a7ac66fbc64c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=451492340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.451492340
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1419850238
Short name T154
Test name
Test status
Simulation time 64263133311 ps
CPU time 1255.34 seconds
Started Jan 21 03:06:33 PM PST 24
Finished Jan 21 03:27:29 PM PST 24
Peak memory 273196 kb
Host smart-68118abb-ddcd-46d8-9598-ced45011e641
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419850238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1419850238
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4166695893
Short name T826
Test name
Test status
Simulation time 108314019 ps
CPU time 4.61 seconds
Started Jan 21 03:06:43 PM PST 24
Finished Jan 21 03:06:49 PM PST 24
Peak memory 249808 kb
Host smart-5ea9c202-d732-428f-8a5d-055372d132fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4166695893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4166695893
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3603122002
Short name T183
Test name
Test status
Simulation time 142514262 ps
CPU time 2.95 seconds
Started Jan 21 03:06:42 PM PST 24
Finished Jan 21 03:06:47 PM PST 24
Peak memory 236248 kb
Host smart-47d2bfb9-ae84-4d0b-b2f7-2b98bc7c95b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3603122002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3603122002
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2577898880
Short name T841
Test name
Test status
Simulation time 40469899 ps
CPU time 4.53 seconds
Started Jan 21 03:06:58 PM PST 24
Finished Jan 21 03:07:04 PM PST 24
Peak memory 255756 kb
Host smart-5f9af72d-74c2-42e1-9c3f-c049a220cf5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577898880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2577898880
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4139424835
Short name T783
Test name
Test status
Simulation time 124822787 ps
CPU time 9.89 seconds
Started Jan 21 03:06:49 PM PST 24
Finished Jan 21 03:07:00 PM PST 24
Peak memory 236064 kb
Host smart-6cd57e8a-de5f-4e1f-89ef-b33004f6980b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4139424835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.4139424835
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.975956495
Short name T793
Test name
Test status
Simulation time 8746748 ps
CPU time 1.55 seconds
Started Jan 21 03:06:58 PM PST 24
Finished Jan 21 03:07:01 PM PST 24
Peak memory 236076 kb
Host smart-25aa2e25-6060-433a-b57e-afbc9bd5ee8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=975956495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.975956495
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1612966495
Short name T800
Test name
Test status
Simulation time 511539741 ps
CPU time 36.37 seconds
Started Jan 21 03:06:50 PM PST 24
Finished Jan 21 03:07:27 PM PST 24
Peak memory 243432 kb
Host smart-cb7cdf63-0427-4ef5-b730-e35a6578694e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1612966495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1612966495
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.17899961
Short name T123
Test name
Test status
Simulation time 2280566685 ps
CPU time 159.57 seconds
Started Jan 21 03:06:39 PM PST 24
Finished Jan 21 03:09:19 PM PST 24
Peak memory 265056 kb
Host smart-a714d19f-b4ca-48be-896a-8967d054fd87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17899961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_error
s.17899961
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3640681763
Short name T805
Test name
Test status
Simulation time 42724261 ps
CPU time 6.11 seconds
Started Jan 21 03:06:57 PM PST 24
Finished Jan 21 03:07:05 PM PST 24
Peak memory 248136 kb
Host smart-fcb92158-ea50-4d29-be1c-df46eda0d2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3640681763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3640681763
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.724907514
Short name T745
Test name
Test status
Simulation time 37701778 ps
CPU time 3.98 seconds
Started Jan 21 03:35:58 PM PST 24
Finished Jan 21 03:36:03 PM PST 24
Peak memory 239460 kb
Host smart-5e822731-e658-4c22-b465-9ebb4e7e1586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724907514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.724907514
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.145511684
Short name T763
Test name
Test status
Simulation time 129068870 ps
CPU time 5.83 seconds
Started Jan 21 03:06:55 PM PST 24
Finished Jan 21 03:07:01 PM PST 24
Peak memory 236064 kb
Host smart-fb3f3b2b-d768-4340-89ad-4b03e1fe4d04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=145511684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.145511684
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1671626231
Short name T749
Test name
Test status
Simulation time 9676987 ps
CPU time 1.57 seconds
Started Jan 21 03:07:01 PM PST 24
Finished Jan 21 03:07:11 PM PST 24
Peak memory 235268 kb
Host smart-045fc6e0-fe5e-4299-8225-95417694672a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1671626231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1671626231
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.74531639
Short name T184
Test name
Test status
Simulation time 1218964479 ps
CPU time 21.45 seconds
Started Jan 21 03:07:03 PM PST 24
Finished Jan 21 03:07:31 PM PST 24
Peak memory 243472 kb
Host smart-7709e1d9-e884-4b60-97de-9111bc2b8159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=74531639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outs
tanding.74531639
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1654315941
Short name T132
Test name
Test status
Simulation time 4960808743 ps
CPU time 212.52 seconds
Started Jan 21 03:06:56 PM PST 24
Finished Jan 21 03:10:29 PM PST 24
Peak memory 256792 kb
Host smart-13f99691-b739-4407-8cd4-36c86fedd665
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1654315941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1654315941
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3299172679
Short name T843
Test name
Test status
Simulation time 7186266726 ps
CPU time 498.16 seconds
Started Jan 21 03:06:49 PM PST 24
Finished Jan 21 03:15:08 PM PST 24
Peak memory 264928 kb
Host smart-3798d134-0db5-45f9-a1fd-a841711a606a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299172679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3299172679
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1209491402
Short name T26
Test name
Test status
Simulation time 171217354 ps
CPU time 12.88 seconds
Started Jan 21 03:06:52 PM PST 24
Finished Jan 21 03:07:05 PM PST 24
Peak memory 247900 kb
Host smart-022a1ae0-08f0-4fae-9f65-d7328a140dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1209491402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1209491402
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1617818241
Short name T177
Test name
Test status
Simulation time 62186858 ps
CPU time 6.77 seconds
Started Jan 21 03:07:16 PM PST 24
Finished Jan 21 03:07:30 PM PST 24
Peak memory 251600 kb
Host smart-d66c2773-e4ab-489b-935e-069eeb9a00ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617818241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1617818241
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1130053928
Short name T181
Test name
Test status
Simulation time 314755391 ps
CPU time 6.14 seconds
Started Jan 21 03:07:11 PM PST 24
Finished Jan 21 03:07:19 PM PST 24
Peak memory 239856 kb
Host smart-77b0084b-7fcb-4c43-88a7-e8ce0f21dc84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1130053928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1130053928
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.277492744
Short name T849
Test name
Test status
Simulation time 9802717 ps
CPU time 1.65 seconds
Started Jan 21 03:06:55 PM PST 24
Finished Jan 21 03:06:57 PM PST 24
Peak memory 236148 kb
Host smart-6a616d6f-e8fd-46e0-8c50-ea11f75a7e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=277492744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.277492744
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2875354502
Short name T808
Test name
Test status
Simulation time 180826024 ps
CPU time 28.52 seconds
Started Jan 21 03:07:15 PM PST 24
Finished Jan 21 03:07:52 PM PST 24
Peak memory 248296 kb
Host smart-b8da9606-ddf2-4165-b8b3-3aa446a6adea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2875354502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2875354502
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2189200875
Short name T131
Test name
Test status
Simulation time 2302145004 ps
CPU time 176.4 seconds
Started Jan 21 03:06:57 PM PST 24
Finished Jan 21 03:09:55 PM PST 24
Peak memory 265880 kb
Host smart-66b89baf-47ef-49d5-9433-d4a1c5057526
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2189200875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2189200875
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2922034991
Short name T831
Test name
Test status
Simulation time 35266610 ps
CPU time 4.65 seconds
Started Jan 21 03:38:57 PM PST 24
Finished Jan 21 03:39:03 PM PST 24
Peak memory 249988 kb
Host smart-b69459dc-b5cb-4831-8821-9f9e9a3afc8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2922034991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2922034991
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.371712860
Short name T807
Test name
Test status
Simulation time 34905432 ps
CPU time 4.05 seconds
Started Jan 21 03:07:13 PM PST 24
Finished Jan 21 03:07:25 PM PST 24
Peak memory 236216 kb
Host smart-9fd0cba6-84aa-45fb-9330-b1547596703c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371712860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.371712860
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2679329098
Short name T346
Test name
Test status
Simulation time 83339531 ps
CPU time 6.07 seconds
Started Jan 21 03:07:12 PM PST 24
Finished Jan 21 03:07:20 PM PST 24
Peak memory 236024 kb
Host smart-e365886e-e042-487f-a70f-3d62bd6b1e69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2679329098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2679329098
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.670696216
Short name T772
Test name
Test status
Simulation time 22682277 ps
CPU time 1.41 seconds
Started Jan 21 03:07:14 PM PST 24
Finished Jan 21 03:07:25 PM PST 24
Peak memory 236060 kb
Host smart-94d5b1b8-3686-4668-a799-cdbc44990243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=670696216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.670696216
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1392342018
Short name T770
Test name
Test status
Simulation time 94528051 ps
CPU time 13.11 seconds
Started Jan 21 03:07:12 PM PST 24
Finished Jan 21 03:07:33 PM PST 24
Peak memory 244196 kb
Host smart-3faadc6c-ff55-4963-9ce7-3ddcef902433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1392342018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1392342018
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3183406056
Short name T115
Test name
Test status
Simulation time 3153570973 ps
CPU time 103.83 seconds
Started Jan 21 03:07:13 PM PST 24
Finished Jan 21 03:09:05 PM PST 24
Peak memory 257080 kb
Host smart-b24575bd-68ad-474a-adc6-3a1c2add64f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3183406056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3183406056
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1028954132
Short name T829
Test name
Test status
Simulation time 877808722 ps
CPU time 11.72 seconds
Started Jan 21 03:07:12 PM PST 24
Finished Jan 21 03:07:26 PM PST 24
Peak memory 252476 kb
Host smart-76a3f0e9-4983-44d0-b6de-77dd1af815df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1028954132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1028954132
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3956804650
Short name T750
Test name
Test status
Simulation time 313131321 ps
CPU time 7.46 seconds
Started Jan 21 03:07:13 PM PST 24
Finished Jan 21 03:07:29 PM PST 24
Peak memory 252168 kb
Host smart-a51b12ee-01dd-494c-b701-11ca706dc146
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956804650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3956804650
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.594655174
Short name T786
Test name
Test status
Simulation time 20586965 ps
CPU time 4.03 seconds
Started Jan 21 03:07:12 PM PST 24
Finished Jan 21 03:07:24 PM PST 24
Peak memory 239892 kb
Host smart-6d232ac9-43a5-48b1-9c28-ac0993785615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=594655174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.594655174
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.872767122
Short name T834
Test name
Test status
Simulation time 15500511 ps
CPU time 1.3 seconds
Started Jan 21 03:07:12 PM PST 24
Finished Jan 21 03:07:19 PM PST 24
Peak memory 234472 kb
Host smart-f83da3c8-1d84-4ff4-bef0-c4e363cdbb2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=872767122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.872767122
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2892092791
Short name T25
Test name
Test status
Simulation time 173723805 ps
CPU time 9.93 seconds
Started Jan 21 03:07:13 PM PST 24
Finished Jan 21 03:07:31 PM PST 24
Peak memory 243356 kb
Host smart-87ecede0-ddb8-4627-9766-b54ffa7c2880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2892092791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2892092791
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2063908021
Short name T141
Test name
Test status
Simulation time 7270875626 ps
CPU time 308.08 seconds
Started Jan 21 03:07:23 PM PST 24
Finished Jan 21 03:12:35 PM PST 24
Peak memory 265128 kb
Host smart-50fc1e0a-f14d-41a3-868f-5459526b7e74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2063908021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2063908021
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1508434634
Short name T129
Test name
Test status
Simulation time 5029608767 ps
CPU time 685.1 seconds
Started Jan 21 03:07:13 PM PST 24
Finished Jan 21 03:18:46 PM PST 24
Peak memory 265028 kb
Host smart-b17f4741-f1df-46d1-bcf1-75d7d95c86fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508434634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1508434634
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3452222179
Short name T163
Test name
Test status
Simulation time 211960360 ps
CPU time 16.9 seconds
Started Jan 21 03:07:13 PM PST 24
Finished Jan 21 03:07:39 PM PST 24
Peak memory 248228 kb
Host smart-c732b2b6-83aa-4ae4-8edb-4ee5d7305feb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452222179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3452222179
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.6974201
Short name T145
Test name
Test status
Simulation time 4731971797 ps
CPU time 171.31 seconds
Started Jan 21 03:05:54 PM PST 24
Finished Jan 21 03:08:47 PM PST 24
Peak memory 240128 kb
Host smart-551cc1c0-a8c3-4b0f-9ca6-4abb080e2961
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=6974201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.6974201
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1081926513
Short name T823
Test name
Test status
Simulation time 11859636346 ps
CPU time 216.31 seconds
Started Jan 21 03:05:52 PM PST 24
Finished Jan 21 03:09:29 PM PST 24
Peak memory 236160 kb
Host smart-dfe480d8-c89d-475b-93b7-1da89d2a250f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1081926513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1081926513
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1829467449
Short name T810
Test name
Test status
Simulation time 76722336 ps
CPU time 3.89 seconds
Started Jan 21 03:05:56 PM PST 24
Finished Jan 21 03:06:02 PM PST 24
Peak memory 239980 kb
Host smart-24775026-1ca3-45c4-b09c-c4dea810badb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1829467449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1829467449
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.10345289
Short name T748
Test name
Test status
Simulation time 834511661 ps
CPU time 6.63 seconds
Started Jan 21 03:05:56 PM PST 24
Finished Jan 21 03:06:04 PM PST 24
Peak memory 251284 kb
Host smart-0f33d2e8-2866-427b-9b0f-594c722d0954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10345289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.alert_handler_csr_mem_rw_with_rand_reset.10345289
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3681523592
Short name T773
Test name
Test status
Simulation time 249195445 ps
CPU time 6.13 seconds
Started Jan 21 03:05:54 PM PST 24
Finished Jan 21 03:06:01 PM PST 24
Peak memory 236020 kb
Host smart-eb4ebbf4-74be-4a3b-bc4c-28317eb6b3c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3681523592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3681523592
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2167145951
Short name T832
Test name
Test status
Simulation time 11404540 ps
CPU time 1.44 seconds
Started Jan 21 03:05:55 PM PST 24
Finished Jan 21 03:05:57 PM PST 24
Peak memory 234520 kb
Host smart-a092455a-080d-43db-9e96-557c4bf3da7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2167145951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2167145951
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1007282290
Short name T776
Test name
Test status
Simulation time 88103923 ps
CPU time 14.26 seconds
Started Jan 21 03:05:50 PM PST 24
Finished Jan 21 03:06:04 PM PST 24
Peak memory 244320 kb
Host smart-706556bd-8822-4f9d-8165-d13c63e9048c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1007282290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1007282290
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2614982017
Short name T158
Test name
Test status
Simulation time 345634919 ps
CPU time 12.76 seconds
Started Jan 21 03:05:55 PM PST 24
Finished Jan 21 03:06:10 PM PST 24
Peak memory 248000 kb
Host smart-da3a8b6c-b045-4a3e-8e7f-6a5a05fce2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2614982017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2614982017
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3346579884
Short name T824
Test name
Test status
Simulation time 74419719 ps
CPU time 1.4 seconds
Started Jan 21 03:07:13 PM PST 24
Finished Jan 21 03:07:22 PM PST 24
Peak memory 236048 kb
Host smart-6e36acd2-ba1e-48ed-a566-2785f9f0be75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3346579884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3346579884
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2278625389
Short name T27
Test name
Test status
Simulation time 16380044 ps
CPU time 1.39 seconds
Started Jan 21 03:07:24 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 235308 kb
Host smart-2edd8fae-7c43-4fad-8971-f92b06e5672c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2278625389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2278625389
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1928514842
Short name T784
Test name
Test status
Simulation time 8167179 ps
CPU time 1.43 seconds
Started Jan 21 03:07:22 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 236172 kb
Host smart-445ea23b-1210-4e87-832e-b62db0f45c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1928514842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1928514842
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2075088194
Short name T796
Test name
Test status
Simulation time 20442134 ps
CPU time 1.18 seconds
Started Jan 21 03:07:26 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 235164 kb
Host smart-36dcd36d-66c4-4c0a-84a4-dea704614706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2075088194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2075088194
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3268374082
Short name T794
Test name
Test status
Simulation time 11766236 ps
CPU time 1.69 seconds
Started Jan 21 03:07:24 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 235148 kb
Host smart-a5c383d0-e21b-47f6-af96-3323d1091f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3268374082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3268374082
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3043358404
Short name T785
Test name
Test status
Simulation time 13668347 ps
CPU time 1.47 seconds
Started Jan 21 03:07:25 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 235144 kb
Host smart-69e95f0f-3551-4439-a465-ea2220574e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3043358404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3043358404
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.517954723
Short name T342
Test name
Test status
Simulation time 20185087 ps
CPU time 1.41 seconds
Started Jan 21 03:07:20 PM PST 24
Finished Jan 21 03:07:25 PM PST 24
Peak memory 236024 kb
Host smart-5dc07f39-2924-4129-ba1f-4126acf4b90e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=517954723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.517954723
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.363600937
Short name T828
Test name
Test status
Simulation time 23113999 ps
CPU time 1.48 seconds
Started Jan 21 03:07:23 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 235204 kb
Host smart-5502dc70-871b-4dae-901f-0880c767f149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=363600937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.363600937
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1742637311
Short name T795
Test name
Test status
Simulation time 25446638 ps
CPU time 1.26 seconds
Started Jan 21 03:07:21 PM PST 24
Finished Jan 21 03:07:25 PM PST 24
Peak memory 235168 kb
Host smart-951a7b71-1cfe-464a-bc17-4c304b9bc55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1742637311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1742637311
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3068634063
Short name T822
Test name
Test status
Simulation time 1063345333 ps
CPU time 137.24 seconds
Started Jan 21 03:05:54 PM PST 24
Finished Jan 21 03:08:12 PM PST 24
Peak memory 239976 kb
Host smart-137f138e-258a-4726-9a83-809485e13cdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3068634063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3068634063
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2124307332
Short name T767
Test name
Test status
Simulation time 856711665 ps
CPU time 105.57 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:08:03 PM PST 24
Peak memory 235652 kb
Host smart-3d861888-09d2-44b9-9343-ccaf8ed8c42d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2124307332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2124307332
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1032411565
Short name T846
Test name
Test status
Simulation time 522850319 ps
CPU time 11.02 seconds
Started Jan 21 03:05:53 PM PST 24
Finished Jan 21 03:06:05 PM PST 24
Peak memory 239900 kb
Host smart-7187fbc5-05d5-4791-abb3-20d242900a6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1032411565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1032411565
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3576550786
Short name T806
Test name
Test status
Simulation time 30882189 ps
CPU time 3.96 seconds
Started Jan 21 03:05:55 PM PST 24
Finished Jan 21 03:06:01 PM PST 24
Peak memory 239880 kb
Host smart-f5acd99c-fad3-472f-9132-ab9b0454bb83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576550786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3576550786
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4114375945
Short name T345
Test name
Test status
Simulation time 20299848 ps
CPU time 3.4 seconds
Started Jan 21 03:05:55 PM PST 24
Finished Jan 21 03:06:00 PM PST 24
Peak memory 235428 kb
Host smart-9a1a6a2f-0def-4c1c-8fe3-bbdfd658094b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4114375945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4114375945
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3528532657
Short name T186
Test name
Test status
Simulation time 20954173 ps
CPU time 1.47 seconds
Started Jan 21 03:05:58 PM PST 24
Finished Jan 21 03:06:00 PM PST 24
Peak memory 235260 kb
Host smart-8c0752ce-0521-40e1-9a86-d7bba224f259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3528532657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3528532657
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.558096209
Short name T157
Test name
Test status
Simulation time 169690040 ps
CPU time 21.83 seconds
Started Jan 21 03:05:53 PM PST 24
Finished Jan 21 03:06:16 PM PST 24
Peak memory 248192 kb
Host smart-8d2a025e-f010-44d1-8142-5e534e7dc7a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=558096209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.558096209
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4285743944
Short name T835
Test name
Test status
Simulation time 31663899999 ps
CPU time 341.88 seconds
Started Jan 21 03:05:53 PM PST 24
Finished Jan 21 03:11:36 PM PST 24
Peak memory 264996 kb
Host smart-14ec0dc1-1f7f-43a7-a901-1227324a507b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285743944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.4285743944
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3278943652
Short name T760
Test name
Test status
Simulation time 365814790 ps
CPU time 12.88 seconds
Started Jan 21 03:05:55 PM PST 24
Finished Jan 21 03:06:09 PM PST 24
Peak memory 248244 kb
Host smart-4d24b0c2-358d-486d-91b6-acbf1329ee75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278943652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3278943652
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1173145280
Short name T753
Test name
Test status
Simulation time 6748016 ps
CPU time 1.45 seconds
Started Jan 21 03:07:22 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 235132 kb
Host smart-8a0d854f-febf-4fc5-afae-96b11c8924ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1173145280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1173145280
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1210435200
Short name T809
Test name
Test status
Simulation time 21288897 ps
CPU time 1.48 seconds
Started Jan 21 03:07:23 PM PST 24
Finished Jan 21 03:07:28 PM PST 24
Peak memory 236048 kb
Host smart-ce0b51b7-45a9-4e70-aeec-bfdd1bb68b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1210435200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1210435200
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4119180033
Short name T238
Test name
Test status
Simulation time 9715572 ps
CPU time 1.62 seconds
Started Jan 21 03:07:21 PM PST 24
Finished Jan 21 03:07:26 PM PST 24
Peak memory 235264 kb
Host smart-995e3d40-8af0-4370-8422-615229a5c341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4119180033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4119180033
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3395999906
Short name T840
Test name
Test status
Simulation time 16297588 ps
CPU time 1.8 seconds
Started Jan 21 03:07:30 PM PST 24
Finished Jan 21 03:07:33 PM PST 24
Peak memory 235244 kb
Host smart-af1411e4-95f6-46a2-8b11-8982771269af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3395999906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3395999906
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.451332573
Short name T812
Test name
Test status
Simulation time 17565918 ps
CPU time 1.85 seconds
Started Jan 21 03:07:29 PM PST 24
Finished Jan 21 03:07:31 PM PST 24
Peak memory 234192 kb
Host smart-b8369d6e-f90b-4390-8c71-d31d713957ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=451332573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.451332573
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.798283030
Short name T160
Test name
Test status
Simulation time 7612903 ps
CPU time 1.41 seconds
Started Jan 21 03:07:30 PM PST 24
Finished Jan 21 03:07:33 PM PST 24
Peak memory 235164 kb
Host smart-68d8292a-dc93-4475-b153-f7bc91ff1d0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=798283030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.798283030
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2633636099
Short name T754
Test name
Test status
Simulation time 10435672 ps
CPU time 1.59 seconds
Started Jan 21 03:07:31 PM PST 24
Finished Jan 21 03:07:34 PM PST 24
Peak memory 234260 kb
Host smart-54858efe-a55a-4e6f-9d53-0f99d90597eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2633636099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2633636099
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.669969922
Short name T759
Test name
Test status
Simulation time 16568159 ps
CPU time 1.55 seconds
Started Jan 21 03:07:33 PM PST 24
Finished Jan 21 03:07:35 PM PST 24
Peak memory 236076 kb
Host smart-a6976512-3167-43a1-9495-22ec7401000a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=669969922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.669969922
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.820520071
Short name T751
Test name
Test status
Simulation time 15303531 ps
CPU time 1.33 seconds
Started Jan 21 03:07:29 PM PST 24
Finished Jan 21 03:07:32 PM PST 24
Peak memory 236040 kb
Host smart-18115949-2d95-48d0-8e1d-af4f3bf9f05a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=820520071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.820520071
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1998475487
Short name T830
Test name
Test status
Simulation time 8329043 ps
CPU time 1.48 seconds
Started Jan 21 03:07:30 PM PST 24
Finished Jan 21 03:07:33 PM PST 24
Peak memory 234164 kb
Host smart-6c090ffb-3312-405b-b268-ee87f67bb4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1998475487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1998475487
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.84910525
Short name T847
Test name
Test status
Simulation time 2126947745 ps
CPU time 137.7 seconds
Started Jan 21 03:05:57 PM PST 24
Finished Jan 21 03:08:16 PM PST 24
Peak memory 236088 kb
Host smart-c4fee8aa-4f2f-4bde-87d1-4281b1b8cd8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=84910525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.84910525
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3956426047
Short name T837
Test name
Test status
Simulation time 16441538830 ps
CPU time 505.72 seconds
Started Jan 21 03:06:14 PM PST 24
Finished Jan 21 03:14:41 PM PST 24
Peak memory 240072 kb
Host smart-d6f2a709-7a79-44b3-9254-d9e48528cd3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3956426047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3956426047
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.779777111
Short name T811
Test name
Test status
Simulation time 266934451 ps
CPU time 6.44 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:25 PM PST 24
Peak memory 240020 kb
Host smart-f6abd112-9237-4517-a526-eb16ed3d7991
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=779777111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.779777111
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.313194655
Short name T816
Test name
Test status
Simulation time 55751725 ps
CPU time 3.63 seconds
Started Jan 21 03:06:14 PM PST 24
Finished Jan 21 03:06:18 PM PST 24
Peak memory 237116 kb
Host smart-5fd93ced-e9b2-4a43-ac09-1316f0f1b559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313194655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.313194655
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3012950522
Short name T780
Test name
Test status
Simulation time 125098106 ps
CPU time 8.45 seconds
Started Jan 21 03:18:50 PM PST 24
Finished Jan 21 03:19:01 PM PST 24
Peak memory 235992 kb
Host smart-403480b1-2c67-4e34-bad2-985e9d084b39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3012950522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3012950522
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.852540600
Short name T775
Test name
Test status
Simulation time 16178795 ps
CPU time 1.81 seconds
Started Jan 21 03:05:58 PM PST 24
Finished Jan 21 03:06:01 PM PST 24
Peak memory 234236 kb
Host smart-b231f801-ab1d-4ff0-b1c0-93f4c0d97951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=852540600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.852540600
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1819742826
Short name T799
Test name
Test status
Simulation time 1211190019 ps
CPU time 37.76 seconds
Started Jan 21 03:06:15 PM PST 24
Finished Jan 21 03:06:54 PM PST 24
Peak memory 239812 kb
Host smart-0a7f9bc8-cc57-4845-ab89-08dd8879b663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1819742826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1819742826
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1730202795
Short name T152
Test name
Test status
Simulation time 4421309219 ps
CPU time 677.8 seconds
Started Jan 21 03:05:55 PM PST 24
Finished Jan 21 03:17:13 PM PST 24
Peak memory 265040 kb
Host smart-dddcd960-be1f-456f-926c-9f86bd56ab8b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730202795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1730202795
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.428332803
Short name T838
Test name
Test status
Simulation time 12661721 ps
CPU time 1.4 seconds
Started Jan 21 03:07:29 PM PST 24
Finished Jan 21 03:07:31 PM PST 24
Peak memory 236152 kb
Host smart-e31cf3eb-c29d-4c87-b06b-a4570d79cfba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=428332803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.428332803
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1990867212
Short name T343
Test name
Test status
Simulation time 8525814 ps
CPU time 1.4 seconds
Started Jan 21 03:07:31 PM PST 24
Finished Jan 21 03:07:34 PM PST 24
Peak memory 236168 kb
Host smart-5ed13545-deb1-4985-b88b-8617bd1b8c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1990867212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1990867212
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.461793969
Short name T845
Test name
Test status
Simulation time 14628938 ps
CPU time 1.31 seconds
Started Jan 21 03:07:29 PM PST 24
Finished Jan 21 03:07:32 PM PST 24
Peak memory 234280 kb
Host smart-f88b122a-7605-411c-a558-88eff7ca2444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=461793969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.461793969
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1016242254
Short name T757
Test name
Test status
Simulation time 10174531 ps
CPU time 1.27 seconds
Started Jan 21 03:07:30 PM PST 24
Finished Jan 21 03:07:33 PM PST 24
Peak memory 234260 kb
Host smart-29ea4876-9b14-493f-9003-eb5daa04080b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016242254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1016242254
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1451084457
Short name T792
Test name
Test status
Simulation time 6450742 ps
CPU time 1.43 seconds
Started Jan 21 03:07:34 PM PST 24
Finished Jan 21 03:07:36 PM PST 24
Peak memory 234276 kb
Host smart-719fa126-44f3-4f6f-8b36-d9bf274059d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1451084457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1451084457
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3341808077
Short name T351
Test name
Test status
Simulation time 24539799 ps
CPU time 1.64 seconds
Started Jan 21 03:07:33 PM PST 24
Finished Jan 21 03:07:35 PM PST 24
Peak memory 236188 kb
Host smart-690c1b85-220b-49e8-b4da-85f68494cf08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3341808077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3341808077
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1069017857
Short name T344
Test name
Test status
Simulation time 22024245 ps
CPU time 1.42 seconds
Started Jan 21 03:07:41 PM PST 24
Finished Jan 21 03:07:48 PM PST 24
Peak memory 235308 kb
Host smart-0624dcb2-382a-41e3-be4c-2cf9800156be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1069017857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1069017857
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.933157328
Short name T761
Test name
Test status
Simulation time 12794934 ps
CPU time 1.71 seconds
Started Jan 21 03:07:40 PM PST 24
Finished Jan 21 03:07:48 PM PST 24
Peak memory 236136 kb
Host smart-9549622c-2f48-484f-af63-aa6f0ece41ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=933157328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.933157328
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2501240592
Short name T820
Test name
Test status
Simulation time 16624317 ps
CPU time 1.36 seconds
Started Jan 21 03:07:46 PM PST 24
Finished Jan 21 03:07:49 PM PST 24
Peak memory 236108 kb
Host smart-b0f2d2b8-2ab8-41a9-8092-8cb1e3589b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2501240592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2501240592
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2522426161
Short name T764
Test name
Test status
Simulation time 23703851 ps
CPU time 1.33 seconds
Started Jan 21 03:07:44 PM PST 24
Finished Jan 21 03:07:49 PM PST 24
Peak memory 236172 kb
Host smart-9e2994bc-390a-4758-8c4b-36c4ead8cb3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2522426161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2522426161
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.163806096
Short name T756
Test name
Test status
Simulation time 66298211 ps
CPU time 7.31 seconds
Started Jan 21 03:06:13 PM PST 24
Finished Jan 21 03:06:21 PM PST 24
Peak memory 250272 kb
Host smart-ee4ec6b2-8fa4-4863-b003-e2ec791b9c08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163806096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.163806096
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3435660072
Short name T802
Test name
Test status
Simulation time 96591342 ps
CPU time 8.35 seconds
Started Jan 21 03:06:09 PM PST 24
Finished Jan 21 03:06:19 PM PST 24
Peak memory 236020 kb
Host smart-77488546-a923-4789-80ea-988c4bda5eb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3435660072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3435660072
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.213469811
Short name T848
Test name
Test status
Simulation time 6479276 ps
CPU time 1.39 seconds
Started Jan 21 03:06:06 PM PST 24
Finished Jan 21 03:06:08 PM PST 24
Peak memory 236024 kb
Host smart-abc9fb92-a59b-4c7c-a7a7-fc202dcaf418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=213469811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.213469811
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.970058005
Short name T22
Test name
Test status
Simulation time 181466550 ps
CPU time 25.15 seconds
Started Jan 21 03:06:13 PM PST 24
Finished Jan 21 03:06:39 PM PST 24
Peak memory 244168 kb
Host smart-7dbff0e6-4328-45e4-b8de-3ebebe625f58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=970058005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.970058005
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3656190179
Short name T124
Test name
Test status
Simulation time 21253495949 ps
CPU time 360.1 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:12:19 PM PST 24
Peak memory 265012 kb
Host smart-9a623871-f903-43b4-bfb3-16c2b4fd54ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3656190179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3656190179
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3283118661
Short name T142
Test name
Test status
Simulation time 4746935968 ps
CPU time 581.93 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:15:59 PM PST 24
Peak memory 264944 kb
Host smart-c17dcc91-08ac-4bc0-96eb-2648cc70a311
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283118661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3283118661
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3061188749
Short name T842
Test name
Test status
Simulation time 217877233 ps
CPU time 8.33 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:27 PM PST 24
Peak memory 251572 kb
Host smart-24a6df4f-0c35-49e1-aecf-82e610ab0dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3061188749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3061188749
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3687552650
Short name T768
Test name
Test status
Simulation time 128787500 ps
CPU time 4.05 seconds
Started Jan 21 03:06:04 PM PST 24
Finished Jan 21 03:06:08 PM PST 24
Peak memory 236552 kb
Host smart-57db6a7b-aad2-4a80-b482-ce97979a361f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687552650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3687552650
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4290588532
Short name T348
Test name
Test status
Simulation time 327514905 ps
CPU time 4.88 seconds
Started Jan 21 03:06:15 PM PST 24
Finished Jan 21 03:06:20 PM PST 24
Peak memory 235956 kb
Host smart-f07579bc-d119-44fb-8d4a-e904018eb2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4290588532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4290588532
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1050612480
Short name T825
Test name
Test status
Simulation time 9725056 ps
CPU time 1.38 seconds
Started Jan 21 03:06:03 PM PST 24
Finished Jan 21 03:06:05 PM PST 24
Peak memory 235264 kb
Host smart-c1ee67fa-a22f-4ea9-8bf7-720e0fe359ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1050612480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1050612480
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.672640991
Short name T844
Test name
Test status
Simulation time 339585592 ps
CPU time 23.38 seconds
Started Jan 21 03:06:14 PM PST 24
Finished Jan 21 03:06:38 PM PST 24
Peak memory 244208 kb
Host smart-cee25343-9e7e-41fa-b423-c3edf2b2a3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=672640991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.672640991
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.114076597
Short name T125
Test name
Test status
Simulation time 136213097510 ps
CPU time 1042.41 seconds
Started Jan 21 03:06:02 PM PST 24
Finished Jan 21 03:23:25 PM PST 24
Peak memory 265024 kb
Host smart-a384fc82-6f7d-4668-b009-e63cb15dd206
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114076597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.114076597
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3728949372
Short name T813
Test name
Test status
Simulation time 3401034158 ps
CPU time 15.57 seconds
Started Jan 21 03:06:02 PM PST 24
Finished Jan 21 03:06:19 PM PST 24
Peak memory 254616 kb
Host smart-4f4b2dca-f36c-4d93-a11d-d212bcbf0e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3728949372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3728949372
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3040716136
Short name T237
Test name
Test status
Simulation time 74755844 ps
CPU time 8.11 seconds
Started Jan 21 03:06:19 PM PST 24
Finished Jan 21 03:06:28 PM PST 24
Peak memory 251396 kb
Host smart-69e6d1dd-be78-4f1f-b4e3-07445a5ee049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040716136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3040716136
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1763451429
Short name T781
Test name
Test status
Simulation time 73719783 ps
CPU time 3.55 seconds
Started Jan 21 03:06:05 PM PST 24
Finished Jan 21 03:06:10 PM PST 24
Peak memory 239936 kb
Host smart-dda12f2c-522c-438e-8bc5-cb20758ef3d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1763451429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1763451429
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4204668144
Short name T774
Test name
Test status
Simulation time 6156601 ps
CPU time 1.49 seconds
Started Jan 21 03:06:03 PM PST 24
Finished Jan 21 03:06:05 PM PST 24
Peak memory 236116 kb
Host smart-fb597b35-2900-4eee-b1c1-0c462dddae5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4204668144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4204668144
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2833312469
Short name T778
Test name
Test status
Simulation time 164783811 ps
CPU time 22.95 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:40 PM PST 24
Peak memory 244352 kb
Host smart-861de5f3-f33a-492c-8063-36f8e6ac18a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2833312469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2833312469
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3214701129
Short name T135
Test name
Test status
Simulation time 10596568440 ps
CPU time 323.12 seconds
Started Jan 21 03:06:02 PM PST 24
Finished Jan 21 03:11:26 PM PST 24
Peak memory 266856 kb
Host smart-be06f142-504f-4f85-ad13-cf0baf5d14a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214701129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3214701129
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3037198199
Short name T161
Test name
Test status
Simulation time 64768680 ps
CPU time 5.19 seconds
Started Jan 21 03:06:17 PM PST 24
Finished Jan 21 03:06:24 PM PST 24
Peak memory 250468 kb
Host smart-cbd15b58-ff5a-454a-a5f5-7d6892e13545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3037198199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3037198199
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3881846736
Short name T752
Test name
Test status
Simulation time 58854718 ps
CPU time 6.64 seconds
Started Jan 21 03:06:11 PM PST 24
Finished Jan 21 03:06:18 PM PST 24
Peak memory 251864 kb
Host smart-ddc86005-c941-473f-8a3d-e0e9b94842de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881846736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3881846736
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1789536339
Short name T347
Test name
Test status
Simulation time 65167461 ps
CPU time 5.96 seconds
Started Jan 21 03:06:15 PM PST 24
Finished Jan 21 03:06:22 PM PST 24
Peak memory 235120 kb
Host smart-ec1664a2-7790-4ec5-851d-26eba277fa18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1789536339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1789536339
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2160178767
Short name T350
Test name
Test status
Simulation time 10529966 ps
CPU time 1.3 seconds
Started Jan 21 03:06:19 PM PST 24
Finished Jan 21 03:06:21 PM PST 24
Peak memory 234116 kb
Host smart-5073e475-d4ef-4760-a63d-8e2fa8e49cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2160178767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2160178767
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.989589148
Short name T755
Test name
Test status
Simulation time 189980910 ps
CPU time 23.6 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:41 PM PST 24
Peak memory 243448 kb
Host smart-9b333467-8468-496d-ac28-a478f965fd29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=989589148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.989589148
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3497204062
Short name T133
Test name
Test status
Simulation time 4558926354 ps
CPU time 595.05 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:16:12 PM PST 24
Peak memory 272604 kb
Host smart-4047c480-04de-40b2-81a5-4ca8c29d48f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497204062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3497204062
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.527308906
Short name T164
Test name
Test status
Simulation time 1101194590 ps
CPU time 18.73 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:36 PM PST 24
Peak memory 248504 kb
Host smart-755ffa6b-50c6-4502-8002-c97606311a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=527308906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.527308906
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1685384173
Short name T779
Test name
Test status
Simulation time 36456736 ps
CPU time 4.33 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:06:21 PM PST 24
Peak memory 238036 kb
Host smart-f6687952-0d31-45db-8faa-06eb3b6e1e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685384173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1685384173
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2368287910
Short name T182
Test name
Test status
Simulation time 22259986 ps
CPU time 3.94 seconds
Started Jan 21 03:06:24 PM PST 24
Finished Jan 21 03:06:28 PM PST 24
Peak memory 239792 kb
Host smart-b86f562a-84c2-4a40-b73e-5de368ba3510
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2368287910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2368287910
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1885773846
Short name T803
Test name
Test status
Simulation time 18650437 ps
CPU time 1.31 seconds
Started Jan 21 03:06:23 PM PST 24
Finished Jan 21 03:06:26 PM PST 24
Peak memory 236168 kb
Host smart-449d7f30-ad27-4091-8466-e3b534fb8f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1885773846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1885773846
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1718565188
Short name T747
Test name
Test status
Simulation time 2706731913 ps
CPU time 52.26 seconds
Started Jan 21 03:06:16 PM PST 24
Finished Jan 21 03:07:09 PM PST 24
Peak memory 248412 kb
Host smart-3fc2c5a7-1374-4c45-a47e-dc488b0959bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1718565188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1718565188
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.629860690
Short name T150
Test name
Test status
Simulation time 2064630238 ps
CPU time 153.38 seconds
Started Jan 21 03:06:23 PM PST 24
Finished Jan 21 03:08:58 PM PST 24
Peak memory 264872 kb
Host smart-00b8229d-a6da-4053-b1db-333510d52b9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=629860690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.629860690
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2151992446
Short name T136
Test name
Test status
Simulation time 45029450282 ps
CPU time 611.67 seconds
Started Jan 21 03:06:24 PM PST 24
Finished Jan 21 03:16:37 PM PST 24
Peak memory 265048 kb
Host smart-0eca11b6-2551-40bd-b1b8-b334e20f3fb7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151992446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2151992446
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4018242686
Short name T23
Test name
Test status
Simulation time 270592819 ps
CPU time 16.95 seconds
Started Jan 21 03:06:12 PM PST 24
Finished Jan 21 03:06:30 PM PST 24
Peak memory 249408 kb
Host smart-82a71272-6dd6-491a-8874-878646624e15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4018242686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4018242686
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3946294787
Short name T683
Test name
Test status
Simulation time 59508157280 ps
CPU time 1751.69 seconds
Started Jan 21 10:00:33 PM PST 24
Finished Jan 21 10:29:57 PM PST 24
Peak memory 271956 kb
Host smart-d092506f-c063-4d13-9e5e-f5e11eab769c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946294787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3946294787
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3440141160
Short name T223
Test name
Test status
Simulation time 172420529 ps
CPU time 10.09 seconds
Started Jan 21 09:21:29 PM PST 24
Finished Jan 21 09:21:41 PM PST 24
Peak memory 239876 kb
Host smart-5965a20d-40da-4bf0-9197-ab7cc170df4b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3440141160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3440141160
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.765834097
Short name T43
Test name
Test status
Simulation time 2421599334 ps
CPU time 112.28 seconds
Started Jan 21 10:34:01 PM PST 24
Finished Jan 21 10:35:55 PM PST 24
Peak memory 249080 kb
Host smart-fdc335d3-4be4-45d5-83bd-722567179d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76583
4097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.765834097
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1564516467
Short name T81
Test name
Test status
Simulation time 1427602069 ps
CPU time 10.01 seconds
Started Jan 21 09:21:28 PM PST 24
Finished Jan 21 09:21:39 PM PST 24
Peak memory 247276 kb
Host smart-a6e86461-4f45-46f9-a8ea-6c297de57e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15645
16467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1564516467
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3396125808
Short name T294
Test name
Test status
Simulation time 179587494304 ps
CPU time 1285.64 seconds
Started Jan 21 09:21:31 PM PST 24
Finished Jan 21 09:42:59 PM PST 24
Peak memory 282560 kb
Host smart-f3922dff-7b5e-4c0c-82d6-d7b8b287d193
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396125808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3396125808
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2283405615
Short name T636
Test name
Test status
Simulation time 39129687728 ps
CPU time 1008.7 seconds
Started Jan 21 09:21:28 PM PST 24
Finished Jan 21 09:38:18 PM PST 24
Peak memory 269344 kb
Host smart-59778c8a-c061-4d8f-9f16-efed31538f42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283405615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2283405615
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2449762767
Short name T381
Test name
Test status
Simulation time 1239979102 ps
CPU time 34.05 seconds
Started Jan 21 09:21:28 PM PST 24
Finished Jan 21 09:22:03 PM PST 24
Peak memory 248040 kb
Host smart-ff555fb8-b780-4545-b13c-362ab42c051f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
62767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2449762767
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3609339678
Short name T733
Test name
Test status
Simulation time 319826077 ps
CPU time 27.77 seconds
Started Jan 21 09:21:32 PM PST 24
Finished Jan 21 09:22:02 PM PST 24
Peak memory 253476 kb
Host smart-cf6334fa-e474-4eaf-b76e-6cfa801b5815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36093
39678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3609339678
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2113158127
Short name T586
Test name
Test status
Simulation time 252974545 ps
CPU time 28.93 seconds
Started Jan 21 09:21:32 PM PST 24
Finished Jan 21 09:22:03 PM PST 24
Peak memory 248000 kb
Host smart-b9d75830-b680-4d03-9e50-9ab4326850f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
58127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2113158127
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1859578309
Short name T475
Test name
Test status
Simulation time 2958781356 ps
CPU time 28.68 seconds
Started Jan 21 09:21:22 PM PST 24
Finished Jan 21 09:21:53 PM PST 24
Peak memory 248200 kb
Host smart-8e1d4225-2c2e-43db-9a18-a145ca4044d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18595
78309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1859578309
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3302690318
Short name T501
Test name
Test status
Simulation time 90438912164 ps
CPU time 1584.56 seconds
Started Jan 21 09:31:36 PM PST 24
Finished Jan 21 09:58:25 PM PST 24
Peak memory 268648 kb
Host smart-3754106b-3bec-4dcd-910c-e151cb298ca0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302690318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3302690318
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3710494650
Short name T101
Test name
Test status
Simulation time 58373945309 ps
CPU time 1067.57 seconds
Started Jan 21 09:21:38 PM PST 24
Finished Jan 21 09:39:28 PM PST 24
Peak memory 281960 kb
Host smart-bbd730bb-5b7a-4096-998c-feba4f137ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710494650 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3710494650
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4219962366
Short name T672
Test name
Test status
Simulation time 18956627944 ps
CPU time 1072.2 seconds
Started Jan 21 09:22:00 PM PST 24
Finished Jan 21 09:39:58 PM PST 24
Peak memory 264576 kb
Host smart-98d0ed82-dad4-411f-b03a-f7f5202567c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219962366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4219962366
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1305994619
Short name T192
Test name
Test status
Simulation time 752249394 ps
CPU time 21.08 seconds
Started Jan 21 09:22:11 PM PST 24
Finished Jan 21 09:22:34 PM PST 24
Peak memory 239908 kb
Host smart-2fea8885-1131-4486-8ac1-30d381436655
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1305994619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1305994619
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2452974524
Short name T482
Test name
Test status
Simulation time 1513360011 ps
CPU time 42.84 seconds
Started Jan 21 09:21:49 PM PST 24
Finished Jan 21 09:22:38 PM PST 24
Peak memory 250476 kb
Host smart-990ced56-c847-497e-9b2c-5d9c60a327ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
74524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2452974524
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.633587973
Short name T673
Test name
Test status
Simulation time 174596022 ps
CPU time 9.92 seconds
Started Jan 21 09:21:48 PM PST 24
Finished Jan 21 09:22:04 PM PST 24
Peak memory 248144 kb
Host smart-127a2103-5b14-4695-a62b-69c71403c855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63358
7973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.633587973
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3702336525
Short name T90
Test name
Test status
Simulation time 180955508420 ps
CPU time 1769.18 seconds
Started Jan 21 09:22:00 PM PST 24
Finished Jan 21 09:51:35 PM PST 24
Peak memory 271872 kb
Host smart-1e93a144-1fd2-4780-977c-3b4a409f9b84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702336525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3702336525
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1981189652
Short name T58
Test name
Test status
Simulation time 1109928245 ps
CPU time 32.88 seconds
Started Jan 21 09:21:40 PM PST 24
Finished Jan 21 09:22:16 PM PST 24
Peak memory 248108 kb
Host smart-cdb403d9-127b-44c0-bda5-e1b6cddb296e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
89652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1981189652
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2630924843
Short name T278
Test name
Test status
Simulation time 1474627740 ps
CPU time 31.88 seconds
Started Jan 21 09:21:47 PM PST 24
Finished Jan 21 09:22:24 PM PST 24
Peak memory 248136 kb
Host smart-31a43161-6372-4697-81b3-6178ed2194e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26309
24843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2630924843
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1720375410
Short name T13
Test name
Test status
Simulation time 1159264730 ps
CPU time 13.16 seconds
Started Jan 21 09:22:08 PM PST 24
Finished Jan 21 09:22:24 PM PST 24
Peak memory 271888 kb
Host smart-61b29a86-b64f-4f85-b9e8-7557a32a0267
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1720375410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1720375410
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3693499146
Short name T359
Test name
Test status
Simulation time 2721088005 ps
CPU time 24.96 seconds
Started Jan 21 09:22:00 PM PST 24
Finished Jan 21 09:22:31 PM PST 24
Peak memory 248180 kb
Host smart-436a4273-5263-45c6-a199-6c7b7cfe4c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36934
99146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3693499146
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1282823706
Short name T529
Test name
Test status
Simulation time 133453323 ps
CPU time 9.3 seconds
Started Jan 21 09:21:38 PM PST 24
Finished Jan 21 09:21:50 PM PST 24
Peak memory 248144 kb
Host smart-351dabef-5b50-46d9-86a8-4a496b088f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12828
23706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1282823706
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.478853290
Short name T618
Test name
Test status
Simulation time 16514927336 ps
CPU time 517.92 seconds
Started Jan 21 09:22:06 PM PST 24
Finished Jan 21 09:30:47 PM PST 24
Peak memory 256296 kb
Host smart-1db2e9b4-e777-4a85-b35d-68e2ce5bdc3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478853290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.478853290
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2416019074
Short name T631
Test name
Test status
Simulation time 95333681393 ps
CPU time 2903.6 seconds
Started Jan 21 09:24:36 PM PST 24
Finished Jan 21 10:13:08 PM PST 24
Peak memory 288248 kb
Host smart-f856bbf6-fd47-472b-b24b-70e7cd0166e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416019074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2416019074
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3901416150
Short name T667
Test name
Test status
Simulation time 831554913 ps
CPU time 20.57 seconds
Started Jan 21 09:25:08 PM PST 24
Finished Jan 21 09:25:34 PM PST 24
Peak memory 239924 kb
Host smart-b65d21c9-c065-4270-9b33-4e9d36bea7b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3901416150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3901416150
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1132052788
Short name T414
Test name
Test status
Simulation time 223896146 ps
CPU time 11.84 seconds
Started Jan 21 09:24:37 PM PST 24
Finished Jan 21 09:24:56 PM PST 24
Peak memory 247228 kb
Host smart-eff16422-8150-41d1-bf8c-d29239488124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
52788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1132052788
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2102901940
Short name T532
Test name
Test status
Simulation time 710368537 ps
CPU time 15.67 seconds
Started Jan 21 09:24:37 PM PST 24
Finished Jan 21 09:25:00 PM PST 24
Peak memory 248132 kb
Host smart-f942a6f1-55c1-4e94-b322-ef01f3fe06d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029
01940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2102901940
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1139519144
Short name T321
Test name
Test status
Simulation time 78475766309 ps
CPU time 2582.84 seconds
Started Jan 21 09:24:37 PM PST 24
Finished Jan 21 10:07:47 PM PST 24
Peak memory 288120 kb
Host smart-31d342ef-ad97-4444-877a-c99745d52453
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139519144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1139519144
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.435260546
Short name T72
Test name
Test status
Simulation time 87039280668 ps
CPU time 956.25 seconds
Started Jan 21 09:25:10 PM PST 24
Finished Jan 21 09:41:12 PM PST 24
Peak memory 271940 kb
Host smart-e1950278-a59e-4b80-bf34-edca494bee7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435260546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.435260546
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3940020061
Short name T64
Test name
Test status
Simulation time 7219801512 ps
CPU time 36.37 seconds
Started Jan 21 09:24:30 PM PST 24
Finished Jan 21 09:25:18 PM PST 24
Peak memory 248216 kb
Host smart-dbd2bfb5-c8a5-448b-a4a5-983e6c6c7695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
20061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3940020061
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2069892109
Short name T537
Test name
Test status
Simulation time 11630524888 ps
CPU time 50.02 seconds
Started Jan 21 09:24:37 PM PST 24
Finished Jan 21 09:25:34 PM PST 24
Peak memory 250512 kb
Host smart-ea79d0ee-63d3-423f-b5f3-4bfbb78526f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20698
92109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2069892109
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2320221408
Short name T457
Test name
Test status
Simulation time 208735323 ps
CPU time 25.64 seconds
Started Jan 21 09:24:36 PM PST 24
Finished Jan 21 09:25:09 PM PST 24
Peak memory 253216 kb
Host smart-4801d7a6-a18b-40fd-ac6c-24e2c9bd0e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
21408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2320221408
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1867218650
Short name T635
Test name
Test status
Simulation time 1071074934 ps
CPU time 58.87 seconds
Started Jan 21 09:24:26 PM PST 24
Finished Jan 21 09:25:39 PM PST 24
Peak memory 248080 kb
Host smart-b69d9f94-84dc-4fa5-84f7-f4f45d327f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
18650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1867218650
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1943109285
Short name T202
Test name
Test status
Simulation time 42030157 ps
CPU time 3.65 seconds
Started Jan 21 10:34:22 PM PST 24
Finished Jan 21 10:34:27 PM PST 24
Peak memory 248364 kb
Host smart-d6e5e110-9fae-465e-9abd-c9a10b323744
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1943109285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1943109285
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1209762563
Short name T493
Test name
Test status
Simulation time 34969196534 ps
CPU time 2006.8 seconds
Started Jan 21 09:25:11 PM PST 24
Finished Jan 21 09:58:44 PM PST 24
Peak memory 272292 kb
Host smart-c6dba661-740c-40e8-8749-d3b46aad4547
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209762563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1209762563
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.178518241
Short name T388
Test name
Test status
Simulation time 1313451154 ps
CPU time 24.78 seconds
Started Jan 21 10:12:21 PM PST 24
Finished Jan 21 10:12:47 PM PST 24
Peak memory 239908 kb
Host smart-6e8c7213-d671-4008-9e51-27dfc141c0ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=178518241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.178518241
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4155819258
Short name T423
Test name
Test status
Simulation time 6499807031 ps
CPU time 202.51 seconds
Started Jan 21 09:25:11 PM PST 24
Finished Jan 21 09:28:39 PM PST 24
Peak memory 248152 kb
Host smart-eb197d3e-afba-48b7-aca3-d4c7af59bd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41558
19258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4155819258
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.798564855
Short name T524
Test name
Test status
Simulation time 93555148 ps
CPU time 6.08 seconds
Started Jan 21 09:25:07 PM PST 24
Finished Jan 21 09:25:19 PM PST 24
Peak memory 237796 kb
Host smart-8a501d8e-d55c-4ca2-9e28-299723bcff5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79856
4855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.798564855
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3399805567
Short name T549
Test name
Test status
Simulation time 11119323032 ps
CPU time 882.09 seconds
Started Jan 21 09:25:11 PM PST 24
Finished Jan 21 09:39:59 PM PST 24
Peak memory 271912 kb
Host smart-63c5a77f-6cff-4d0d-9a44-1289b694d507
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399805567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3399805567
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1729353210
Short name T604
Test name
Test status
Simulation time 150751677804 ps
CPU time 2275.65 seconds
Started Jan 21 09:25:11 PM PST 24
Finished Jan 21 10:03:13 PM PST 24
Peak memory 288616 kb
Host smart-1f01fc66-87ad-4ef1-bda0-66cc25411385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729353210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1729353210
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2212537351
Short name T607
Test name
Test status
Simulation time 12942840024 ps
CPU time 519.94 seconds
Started Jan 21 09:25:10 PM PST 24
Finished Jan 21 09:33:55 PM PST 24
Peak memory 246616 kb
Host smart-f858dfac-af36-4b04-bb00-dece9bff5091
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212537351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2212537351
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3278414891
Short name T648
Test name
Test status
Simulation time 315219702 ps
CPU time 25.6 seconds
Started Jan 21 09:25:08 PM PST 24
Finished Jan 21 09:25:39 PM PST 24
Peak memory 248124 kb
Host smart-aa97959f-e9f0-454b-8a3e-225b0b1298e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32784
14891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3278414891
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.396956324
Short name T450
Test name
Test status
Simulation time 966096953 ps
CPU time 23.38 seconds
Started Jan 21 09:25:09 PM PST 24
Finished Jan 21 09:25:38 PM PST 24
Peak memory 247112 kb
Host smart-a6ec80e6-cb40-4771-954b-3a0c508b05a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39695
6324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.396956324
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.637991055
Short name T556
Test name
Test status
Simulation time 778948608 ps
CPU time 52.39 seconds
Started Jan 21 09:25:13 PM PST 24
Finished Jan 21 09:26:11 PM PST 24
Peak memory 251208 kb
Host smart-20f99af2-318a-4389-a61c-9dfde9e9e273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63799
1055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.637991055
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2754779362
Short name T544
Test name
Test status
Simulation time 4213572250 ps
CPU time 37.14 seconds
Started Jan 21 09:25:08 PM PST 24
Finished Jan 21 09:25:51 PM PST 24
Peak memory 248220 kb
Host smart-ce81ee10-9088-40c4-8b77-a4361d283ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27547
79362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2754779362
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.750191107
Short name T19
Test name
Test status
Simulation time 29167815881 ps
CPU time 1160.51 seconds
Started Jan 21 11:43:59 PM PST 24
Finished Jan 22 12:03:22 AM PST 24
Peak memory 288540 kb
Host smart-3c26ed06-d880-400d-a313-613459907aea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750191107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.750191107
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.825740727
Short name T539
Test name
Test status
Simulation time 108555665957 ps
CPU time 5332.47 seconds
Started Jan 21 10:02:17 PM PST 24
Finished Jan 21 11:31:19 PM PST 24
Peak memory 304824 kb
Host smart-c2841297-b603-4034-8285-adc52e5759da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825740727 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.825740727
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1239348924
Short name T207
Test name
Test status
Simulation time 25013998 ps
CPU time 2.97 seconds
Started Jan 21 09:25:30 PM PST 24
Finished Jan 21 09:25:36 PM PST 24
Peak memory 248376 kb
Host smart-6a58db94-3e39-4c78-9084-e44d97231c3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1239348924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1239348924
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3076513957
Short name T76
Test name
Test status
Simulation time 18987653955 ps
CPU time 1149.85 seconds
Started Jan 21 10:02:46 PM PST 24
Finished Jan 21 10:22:00 PM PST 24
Peak memory 286772 kb
Host smart-0da2f558-0702-4d22-a186-61a80767cce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076513957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3076513957
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2642052043
Short name T627
Test name
Test status
Simulation time 724279213 ps
CPU time 20.24 seconds
Started Jan 21 09:25:34 PM PST 24
Finished Jan 21 09:25:59 PM PST 24
Peak memory 248092 kb
Host smart-6af601c4-1ee4-4b08-a8e2-1bd0fe956df4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2642052043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2642052043
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3618301481
Short name T694
Test name
Test status
Simulation time 5204347349 ps
CPU time 110.22 seconds
Started Jan 21 09:25:18 PM PST 24
Finished Jan 21 09:27:14 PM PST 24
Peak memory 250516 kb
Host smart-8c847175-7101-4582-be6e-c80c81af9d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183
01481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3618301481
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3798950112
Short name T449
Test name
Test status
Simulation time 354228811 ps
CPU time 10.28 seconds
Started Jan 21 09:25:19 PM PST 24
Finished Jan 21 09:25:34 PM PST 24
Peak memory 250136 kb
Host smart-0d4775d1-1e86-4702-b80d-528e98717974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37989
50112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3798950112
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2780899419
Short name T325
Test name
Test status
Simulation time 104450498861 ps
CPU time 2341.1 seconds
Started Jan 21 09:25:19 PM PST 24
Finished Jan 21 10:04:25 PM PST 24
Peak memory 272548 kb
Host smart-485f6ba7-754d-4126-9287-79c083453154
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780899419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2780899419
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2602162816
Short name T577
Test name
Test status
Simulation time 124835647928 ps
CPU time 2291.77 seconds
Started Jan 21 09:25:31 PM PST 24
Finished Jan 21 10:03:45 PM PST 24
Peak memory 288168 kb
Host smart-c8d43a8a-b553-4cfb-a0ff-1f0ac91c3009
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602162816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2602162816
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1242105510
Short name T312
Test name
Test status
Simulation time 9875454171 ps
CPU time 102.43 seconds
Started Jan 21 09:25:21 PM PST 24
Finished Jan 21 09:27:07 PM PST 24
Peak memory 249144 kb
Host smart-409c466d-adb6-4977-9bbe-6d0e96d501df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242105510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1242105510
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.74274991
Short name T585
Test name
Test status
Simulation time 492065749 ps
CPU time 33.34 seconds
Started Jan 21 09:37:15 PM PST 24
Finished Jan 21 09:37:57 PM PST 24
Peak memory 248132 kb
Host smart-c5479a8c-9bf1-4809-904e-a02c1eb8313e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74274
991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.74274991
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3406948415
Short name T605
Test name
Test status
Simulation time 184162992 ps
CPU time 12.76 seconds
Started Jan 21 09:25:19 PM PST 24
Finished Jan 21 09:25:37 PM PST 24
Peak memory 252832 kb
Host smart-fd88d388-71c8-4fdf-a856-6f82ef532610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
48415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3406948415
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4184253482
Short name T590
Test name
Test status
Simulation time 600227903 ps
CPU time 12.13 seconds
Started Jan 21 09:36:16 PM PST 24
Finished Jan 21 09:36:31 PM PST 24
Peak memory 248128 kb
Host smart-190a80cf-115b-409e-bcf1-f771d5f79262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41842
53482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4184253482
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.969463700
Short name T451
Test name
Test status
Simulation time 1001573321 ps
CPU time 14.27 seconds
Started Jan 21 09:25:18 PM PST 24
Finished Jan 21 09:25:38 PM PST 24
Peak memory 250392 kb
Host smart-af2664e4-bf81-4ace-8224-5aa2a7a7d395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96946
3700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.969463700
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1546853416
Short name T625
Test name
Test status
Simulation time 102230307587 ps
CPU time 3500.38 seconds
Started Jan 21 09:25:33 PM PST 24
Finished Jan 21 10:23:56 PM PST 24
Peak memory 288292 kb
Host smart-9c50726d-1c86-4943-9fc0-cbe66dad3849
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546853416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1546853416
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.419992901
Short name T197
Test name
Test status
Simulation time 27908108 ps
CPU time 2.54 seconds
Started Jan 21 09:26:05 PM PST 24
Finished Jan 21 09:26:13 PM PST 24
Peak memory 249444 kb
Host smart-7c4662f7-8308-46d4-a64a-16b8640d7645
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=419992901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.419992901
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3214882705
Short name T82
Test name
Test status
Simulation time 32448736307 ps
CPU time 2126.77 seconds
Started Jan 21 09:26:08 PM PST 24
Finished Jan 21 10:01:42 PM PST 24
Peak memory 280940 kb
Host smart-1756dd1c-9906-4d29-982a-bedae4d25b74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214882705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3214882705
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3261033301
Short name T424
Test name
Test status
Simulation time 255831643 ps
CPU time 9.96 seconds
Started Jan 21 09:26:07 PM PST 24
Finished Jan 21 09:26:23 PM PST 24
Peak memory 239916 kb
Host smart-05ee4518-a6d6-4b3c-b236-873d0c1573c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3261033301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3261033301
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1009758874
Short name T361
Test name
Test status
Simulation time 2158462999 ps
CPU time 129.43 seconds
Started Jan 21 09:25:30 PM PST 24
Finished Jan 21 09:27:42 PM PST 24
Peak memory 250396 kb
Host smart-482e03ad-897b-4f56-b77d-919fc250859b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10097
58874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1009758874
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.300155670
Short name T476
Test name
Test status
Simulation time 596494855 ps
CPU time 30.59 seconds
Started Jan 21 09:25:30 PM PST 24
Finished Jan 21 09:26:03 PM PST 24
Peak memory 248120 kb
Host smart-bbd83e23-ccb7-44a9-8e66-ea4e29e2c4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
5670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.300155670
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1685862423
Short name T736
Test name
Test status
Simulation time 39231852785 ps
CPU time 2685.24 seconds
Started Jan 21 09:26:05 PM PST 24
Finished Jan 21 10:10:56 PM PST 24
Peak memory 288200 kb
Host smart-afa1c5e1-30b6-423d-a47e-f32798c132af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685862423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1685862423
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.411229146
Short name T547
Test name
Test status
Simulation time 3750957096 ps
CPU time 151.18 seconds
Started Jan 21 09:26:06 PM PST 24
Finished Jan 21 09:28:44 PM PST 24
Peak memory 246680 kb
Host smart-d291beed-3a1c-4ce5-81bf-156a683d86a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411229146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.411229146
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2010868310
Short name T494
Test name
Test status
Simulation time 360564454 ps
CPU time 26.4 seconds
Started Jan 21 09:25:33 PM PST 24
Finished Jan 21 09:26:01 PM PST 24
Peak memory 248068 kb
Host smart-f155d7e9-924b-4ae3-a450-474cd120664f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108
68310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2010868310
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2433543965
Short name T458
Test name
Test status
Simulation time 59768158 ps
CPU time 4.22 seconds
Started Jan 21 09:25:32 PM PST 24
Finished Jan 21 09:25:38 PM PST 24
Peak memory 237812 kb
Host smart-d1238e15-10c7-497a-8ea9-3da0e6ccb474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24335
43965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2433543965
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3160921845
Short name T492
Test name
Test status
Simulation time 35663933 ps
CPU time 4.88 seconds
Started Jan 21 09:26:07 PM PST 24
Finished Jan 21 09:26:18 PM PST 24
Peak memory 239872 kb
Host smart-7b4f9164-49fa-4141-8ac8-484aa2dd60b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31609
21845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3160921845
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2160099970
Short name T412
Test name
Test status
Simulation time 708142532 ps
CPU time 36.26 seconds
Started Jan 21 09:25:31 PM PST 24
Finished Jan 21 09:26:10 PM PST 24
Peak memory 248132 kb
Host smart-9e019f68-c54d-4d1e-8af6-a92eea904a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21600
99970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2160099970
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.448757410
Short name T671
Test name
Test status
Simulation time 47707170491 ps
CPU time 1542.67 seconds
Started Jan 21 09:58:39 PM PST 24
Finished Jan 21 10:24:24 PM PST 24
Peak memory 272268 kb
Host smart-5a958483-b834-40f1-b224-82a39dc0a350
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448757410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.448757410
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1163193798
Short name T477
Test name
Test status
Simulation time 15479238967 ps
CPU time 1485.1 seconds
Started Jan 21 09:26:12 PM PST 24
Finished Jan 21 09:51:03 PM PST 24
Peak memory 288020 kb
Host smart-86ad6c7d-556a-47f6-87b0-e1a9588b145e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163193798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1163193798
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2950499544
Short name T209
Test name
Test status
Simulation time 44701236 ps
CPU time 2.62 seconds
Started Jan 21 09:26:17 PM PST 24
Finished Jan 21 09:26:27 PM PST 24
Peak memory 248352 kb
Host smart-83d253ca-1291-4bac-96d6-1090cd7b20f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2950499544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2950499544
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3958465982
Short name T277
Test name
Test status
Simulation time 46652415793 ps
CPU time 847.64 seconds
Started Jan 21 09:26:06 PM PST 24
Finished Jan 21 09:40:20 PM PST 24
Peak memory 264572 kb
Host smart-0b5b8e44-b21b-4c24-abf2-3d545d0dc0eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958465982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3958465982
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.853955377
Short name T703
Test name
Test status
Simulation time 1053485179 ps
CPU time 35.67 seconds
Started Jan 21 09:26:22 PM PST 24
Finished Jan 21 09:27:04 PM PST 24
Peak memory 239912 kb
Host smart-12a2a91f-1a57-4b89-86a6-7aa6209d98f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=853955377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.853955377
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3086421137
Short name T719
Test name
Test status
Simulation time 13063174007 ps
CPU time 70.26 seconds
Started Jan 21 09:26:14 PM PST 24
Finished Jan 21 09:27:30 PM PST 24
Peak memory 248176 kb
Host smart-c73cabbd-d70a-4a58-8257-4ecc2c751b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30864
21137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3086421137
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3085328994
Short name T292
Test name
Test status
Simulation time 290182036 ps
CPU time 30.75 seconds
Started Jan 21 09:26:12 PM PST 24
Finished Jan 21 09:26:49 PM PST 24
Peak memory 254564 kb
Host smart-633c4b79-b2ae-4be6-a1ac-114bbc3e3c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
28994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3085328994
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.189379287
Short name T334
Test name
Test status
Simulation time 37804849344 ps
CPU time 2251.61 seconds
Started Jan 21 09:26:09 PM PST 24
Finished Jan 21 10:03:48 PM PST 24
Peak memory 288004 kb
Host smart-4cff61dc-9afd-4762-81d2-d75b1feecba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189379287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.189379287
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4282767245
Short name T411
Test name
Test status
Simulation time 47764083906 ps
CPU time 1319.9 seconds
Started Jan 21 09:26:04 PM PST 24
Finished Jan 21 09:48:09 PM PST 24
Peak memory 280936 kb
Host smart-549cf665-a230-4aa9-83d5-b1cb06892f4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282767245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4282767245
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.144414139
Short name T302
Test name
Test status
Simulation time 42755789996 ps
CPU time 339.19 seconds
Started Jan 21 09:26:12 PM PST 24
Finished Jan 21 09:31:57 PM PST 24
Peak memory 250216 kb
Host smart-9342736e-4642-4a62-b86a-c3f13bc53060
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144414139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.144414139
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2461223168
Short name T77
Test name
Test status
Simulation time 7448238454 ps
CPU time 53.25 seconds
Started Jan 21 09:26:08 PM PST 24
Finished Jan 21 09:27:08 PM PST 24
Peak memory 248200 kb
Host smart-a660f6cd-444c-499b-bf3f-3b091f5ce61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24612
23168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2461223168
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3871255768
Short name T94
Test name
Test status
Simulation time 2428123687 ps
CPU time 40.9 seconds
Started Jan 21 09:26:07 PM PST 24
Finished Jan 21 09:26:54 PM PST 24
Peak memory 248688 kb
Host smart-45499550-e99c-4f4f-9452-9719d26ba9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
55768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3871255768
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4156716707
Short name T454
Test name
Test status
Simulation time 703425305 ps
CPU time 50.31 seconds
Started Jan 21 09:26:07 PM PST 24
Finished Jan 21 09:27:04 PM PST 24
Peak memory 250628 kb
Host smart-4d8906e7-1364-48c6-8144-4eaf798ce4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
16707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4156716707
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3228322099
Short name T572
Test name
Test status
Simulation time 58537643 ps
CPU time 4.89 seconds
Started Jan 21 09:26:06 PM PST 24
Finished Jan 21 09:26:18 PM PST 24
Peak memory 239912 kb
Host smart-626fecfa-1b4a-40b8-afb0-2a533f71cf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283
22099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3228322099
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.572216640
Short name T354
Test name
Test status
Simulation time 5396809777 ps
CPU time 285.81 seconds
Started Jan 21 09:26:19 PM PST 24
Finished Jan 21 09:31:12 PM PST 24
Peak memory 250260 kb
Host smart-81a09f11-9e0b-43b4-9c3c-ef8e18c3a37d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572216640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.572216640
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1038023619
Short name T251
Test name
Test status
Simulation time 87257458485 ps
CPU time 8083.93 seconds
Started Jan 21 09:26:17 PM PST 24
Finished Jan 21 11:41:10 PM PST 24
Peak memory 394336 kb
Host smart-09e6592a-a93a-4d82-9b86-705d87fddfd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038023619 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1038023619
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.832996117
Short name T211
Test name
Test status
Simulation time 174607501 ps
CPU time 4.03 seconds
Started Jan 21 09:26:27 PM PST 24
Finished Jan 21 09:26:36 PM PST 24
Peak memory 248376 kb
Host smart-85d7c4c2-a2b5-4bca-82bc-4c914831c403
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=832996117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.832996117
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2106804547
Short name T706
Test name
Test status
Simulation time 104344250062 ps
CPU time 1894.42 seconds
Started Jan 21 09:26:25 PM PST 24
Finished Jan 21 09:58:05 PM PST 24
Peak memory 272420 kb
Host smart-4f6cd8e9-92dd-4847-879c-babaeeb381e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106804547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2106804547
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2951011318
Short name T593
Test name
Test status
Simulation time 1602054248 ps
CPU time 36.94 seconds
Started Jan 21 09:26:26 PM PST 24
Finished Jan 21 09:27:09 PM PST 24
Peak memory 239908 kb
Host smart-57b2b8f6-1361-4717-9efd-b99fe5e32f69
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2951011318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2951011318
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3085637837
Short name T480
Test name
Test status
Simulation time 8651901804 ps
CPU time 150.39 seconds
Started Jan 21 09:26:25 PM PST 24
Finished Jan 21 09:29:01 PM PST 24
Peak memory 250180 kb
Host smart-0d872776-963c-4080-b4e6-7a3ce6c27a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30856
37837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3085637837
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2009822339
Short name T552
Test name
Test status
Simulation time 5086897926 ps
CPU time 61.33 seconds
Started Jan 21 09:26:27 PM PST 24
Finished Jan 21 09:27:33 PM PST 24
Peak memory 254704 kb
Host smart-eaf9ec0c-2715-4d35-b9d3-8a90ea3565a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20098
22339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2009822339
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2224963489
Short name T695
Test name
Test status
Simulation time 42764796903 ps
CPU time 1089.77 seconds
Started Jan 21 09:26:26 PM PST 24
Finished Jan 21 09:44:41 PM PST 24
Peak memory 272400 kb
Host smart-1a45719e-5734-48a1-9042-eb770a5935c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224963489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2224963489
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.552233166
Short name T523
Test name
Test status
Simulation time 28155289301 ps
CPU time 1675.75 seconds
Started Jan 21 09:26:26 PM PST 24
Finished Jan 21 09:54:28 PM PST 24
Peak memory 272300 kb
Host smart-7c66179f-6449-4b42-8444-adfd21defd77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552233166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.552233166
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2307678512
Short name T194
Test name
Test status
Simulation time 8986480994 ps
CPU time 387.31 seconds
Started Jan 21 10:10:20 PM PST 24
Finished Jan 21 10:16:51 PM PST 24
Peak memory 248184 kb
Host smart-b476e61e-f118-4316-b916-d2314daee283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307678512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2307678512
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2008595135
Short name T611
Test name
Test status
Simulation time 84682128 ps
CPU time 9.22 seconds
Started Jan 21 09:26:29 PM PST 24
Finished Jan 21 09:26:42 PM PST 24
Peak memory 248132 kb
Host smart-04b37712-bd8e-45ff-85b2-e6e911cc7bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085
95135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2008595135
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1160390090
Short name T47
Test name
Test status
Simulation time 89877598 ps
CPU time 12.07 seconds
Started Jan 21 09:26:26 PM PST 24
Finished Jan 21 09:26:43 PM PST 24
Peak memory 251448 kb
Host smart-da04ccf5-20f6-40e5-9981-0e29b874c460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11603
90090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1160390090
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3734563521
Short name T711
Test name
Test status
Simulation time 603381326 ps
CPU time 17.67 seconds
Started Jan 21 09:26:26 PM PST 24
Finished Jan 21 09:26:49 PM PST 24
Peak memory 248112 kb
Host smart-4329817a-cb39-4093-aee1-b608342f6ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37345
63521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3734563521
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4255874367
Short name T215
Test name
Test status
Simulation time 3154988055 ps
CPU time 47.43 seconds
Started Jan 21 09:26:22 PM PST 24
Finished Jan 21 09:27:16 PM PST 24
Peak memory 248176 kb
Host smart-81af4d34-e288-47c2-bd09-fb0e1df7b813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42558
74367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4255874367
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1588400643
Short name T712
Test name
Test status
Simulation time 54482033117 ps
CPU time 3607.69 seconds
Started Jan 21 10:09:11 PM PST 24
Finished Jan 21 11:09:21 PM PST 24
Peak memory 305352 kb
Host smart-f7c32752-57be-4a6f-bfd6-95be82d4ef03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588400643 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1588400643
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4022129912
Short name T196
Test name
Test status
Simulation time 44680833 ps
CPU time 2.45 seconds
Started Jan 21 09:26:52 PM PST 24
Finished Jan 21 09:27:05 PM PST 24
Peak memory 249456 kb
Host smart-cd989c7f-0796-43ea-9872-a677b4e60812
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4022129912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4022129912
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3590929106
Short name T5
Test name
Test status
Simulation time 71392185132 ps
CPU time 1333.28 seconds
Started Jan 21 09:49:55 PM PST 24
Finished Jan 21 10:12:17 PM PST 24
Peak memory 272124 kb
Host smart-742e68cc-0ef4-4003-900e-ad986fb3195d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590929106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3590929106
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1468792642
Short name T741
Test name
Test status
Simulation time 351209311 ps
CPU time 10.03 seconds
Started Jan 21 09:26:49 PM PST 24
Finished Jan 21 09:27:08 PM PST 24
Peak memory 239920 kb
Host smart-63ede398-0e04-45b5-ae5d-d882466e5074
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1468792642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1468792642
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1926113101
Short name T503
Test name
Test status
Simulation time 8812718592 ps
CPU time 247.82 seconds
Started Jan 21 09:26:35 PM PST 24
Finished Jan 21 09:30:48 PM PST 24
Peak memory 249156 kb
Host smart-b271c427-d7d6-4902-8d2a-fd8bb9f29914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19261
13101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1926113101
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3299156556
Short name T265
Test name
Test status
Simulation time 1320356380 ps
CPU time 42.4 seconds
Started Jan 21 09:26:35 PM PST 24
Finished Jan 21 09:27:22 PM PST 24
Peak memory 247440 kb
Host smart-ed147c85-5f69-4928-88d8-8dfe6729c56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32991
56556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3299156556
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.698266418
Short name T55
Test name
Test status
Simulation time 20071363308 ps
CPU time 1345.69 seconds
Started Jan 21 09:26:38 PM PST 24
Finished Jan 21 09:49:11 PM PST 24
Peak memory 272536 kb
Host smart-29f1fa11-1d8a-4a05-8b3b-3fa042383018
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698266418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.698266418
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.786635144
Short name T54
Test name
Test status
Simulation time 8440835462 ps
CPU time 836.08 seconds
Started Jan 21 09:26:49 PM PST 24
Finished Jan 21 09:40:53 PM PST 24
Peak memory 264536 kb
Host smart-04be8cef-0d78-436e-ad05-5cafafdddd65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786635144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.786635144
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3085252659
Short name T687
Test name
Test status
Simulation time 446868218 ps
CPU time 30.55 seconds
Started Jan 21 09:26:36 PM PST 24
Finished Jan 21 09:27:14 PM PST 24
Peak memory 248100 kb
Host smart-c38573d5-6fdc-48f8-8455-5bf968a6ebc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
52659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3085252659
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.426789467
Short name T516
Test name
Test status
Simulation time 1342526400 ps
CPU time 43.96 seconds
Started Jan 21 09:26:38 PM PST 24
Finished Jan 21 09:27:29 PM PST 24
Peak memory 247984 kb
Host smart-ef21ad08-3d01-4d58-97d5-66e28613c086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42678
9467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.426789467
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1158514360
Short name T488
Test name
Test status
Simulation time 257809310 ps
CPU time 18.37 seconds
Started Jan 21 09:26:35 PM PST 24
Finished Jan 21 09:26:58 PM PST 24
Peak memory 253392 kb
Host smart-40aca138-a8a4-4c63-b581-f15e44f95697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11585
14360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1158514360
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2767100627
Short name T364
Test name
Test status
Simulation time 1232465857 ps
CPU time 24.02 seconds
Started Jan 21 09:26:36 PM PST 24
Finished Jan 21 09:27:07 PM PST 24
Peak memory 248048 kb
Host smart-3903b2b0-23e2-4255-a8be-4ecf0c4282f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27671
00627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2767100627
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2369840595
Short name T2
Test name
Test status
Simulation time 1056322140 ps
CPU time 29.56 seconds
Started Jan 21 09:26:49 PM PST 24
Finished Jan 21 09:27:28 PM PST 24
Peak memory 248128 kb
Host smart-b517fb55-9172-40c5-9c8d-58ae4b79a011
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369840595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2369840595
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.4116206867
Short name T62
Test name
Test status
Simulation time 58626917194 ps
CPU time 5762.95 seconds
Started Jan 21 09:26:46 PM PST 24
Finished Jan 21 11:02:59 PM PST 24
Peak memory 367676 kb
Host smart-141f0029-6fda-4a3f-a24f-c36a269030d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116206867 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.4116206867
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3088989571
Short name T213
Test name
Test status
Simulation time 37676415 ps
CPU time 3.63 seconds
Started Jan 21 09:27:00 PM PST 24
Finished Jan 21 09:27:15 PM PST 24
Peak memory 248388 kb
Host smart-110df8db-e8cd-44f3-95e5-d83f1e9590f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3088989571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3088989571
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3975046635
Short name T642
Test name
Test status
Simulation time 175559928567 ps
CPU time 3015.55 seconds
Started Jan 21 09:26:59 PM PST 24
Finished Jan 21 10:17:27 PM PST 24
Peak memory 288468 kb
Host smart-7c60ef05-a8f2-4487-9433-1ed0c69065f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975046635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3975046635
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1245023760
Short name T365
Test name
Test status
Simulation time 521859867 ps
CPU time 21.58 seconds
Started Jan 21 09:27:01 PM PST 24
Finished Jan 21 09:27:33 PM PST 24
Peak memory 248148 kb
Host smart-0d5210c8-d0ae-4e9c-8166-c724b6b7b4b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1245023760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1245023760
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2395204109
Short name T589
Test name
Test status
Simulation time 423856886 ps
CPU time 24.96 seconds
Started Jan 21 09:26:50 PM PST 24
Finished Jan 21 09:27:25 PM PST 24
Peak memory 248100 kb
Host smart-fcd9cc69-53c6-42d3-b118-bfa2774767ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
04109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2395204109
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2793942886
Short name T560
Test name
Test status
Simulation time 146233543 ps
CPU time 16.07 seconds
Started Jan 21 09:26:47 PM PST 24
Finished Jan 21 09:27:12 PM PST 24
Peak memory 248108 kb
Host smart-5ee964ca-704f-4ad3-869d-03e7cff9af4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27939
42886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2793942886
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.840338478
Short name T335
Test name
Test status
Simulation time 77612240056 ps
CPU time 2252.53 seconds
Started Jan 21 09:27:01 PM PST 24
Finished Jan 21 10:04:45 PM PST 24
Peak memory 288432 kb
Host smart-06edc96a-e50c-4b3c-aeb2-d32cbb8adebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840338478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.840338478
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2032979453
Short name T610
Test name
Test status
Simulation time 109880182152 ps
CPU time 1695.01 seconds
Started Jan 21 09:27:00 PM PST 24
Finished Jan 21 09:55:27 PM PST 24
Peak memory 264600 kb
Host smart-4b231047-fb89-4b26-9f49-b8bd9cada27e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032979453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2032979453
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1245220130
Short name T602
Test name
Test status
Simulation time 22415109600 ps
CPU time 234.96 seconds
Started Jan 21 09:26:59 PM PST 24
Finished Jan 21 09:31:06 PM PST 24
Peak memory 246652 kb
Host smart-183a20c9-ae77-40b7-9ef6-bb2874865775
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245220130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1245220130
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1308017727
Short name T41
Test name
Test status
Simulation time 4065479599 ps
CPU time 59.89 seconds
Started Jan 21 09:26:48 PM PST 24
Finished Jan 21 09:27:56 PM PST 24
Peak memory 248192 kb
Host smart-9437287c-f25f-4ddf-87c2-b6b3ad9ba01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13080
17727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1308017727
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4099893201
Short name T1
Test name
Test status
Simulation time 700046907 ps
CPU time 11.63 seconds
Started Jan 21 09:26:46 PM PST 24
Finished Jan 21 09:27:06 PM PST 24
Peak memory 248116 kb
Host smart-13d9cef5-f2bc-477c-9bd7-4620e0824bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
93201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4099893201
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4006410750
Short name T649
Test name
Test status
Simulation time 899158049 ps
CPU time 27.88 seconds
Started Jan 21 09:27:00 PM PST 24
Finished Jan 21 09:27:39 PM PST 24
Peak memory 246204 kb
Host smart-773b3adb-ac57-4cec-8ca6-496597c2d28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40064
10750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4006410750
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3939846413
Short name T666
Test name
Test status
Simulation time 803307554 ps
CPU time 8.95 seconds
Started Jan 21 09:26:49 PM PST 24
Finished Jan 21 09:27:08 PM PST 24
Peak memory 250172 kb
Host smart-a486b345-80be-4f4c-bb57-063a0af72d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39398
46413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3939846413
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2780709090
Short name T286
Test name
Test status
Simulation time 124710453941 ps
CPU time 6802.04 seconds
Started Jan 21 09:27:08 PM PST 24
Finished Jan 21 11:20:37 PM PST 24
Peak memory 371000 kb
Host smart-57256d78-dfbf-4498-8e35-d6589e01d3a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780709090 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2780709090
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1638122360
Short name T339
Test name
Test status
Simulation time 22766751029 ps
CPU time 1027.51 seconds
Started Jan 21 09:27:10 PM PST 24
Finished Jan 21 09:44:23 PM PST 24
Peak memory 281528 kb
Host smart-91e30e4e-84c8-48d9-a318-6424bb2c7a8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638122360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1638122360
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.4231772598
Short name T416
Test name
Test status
Simulation time 104170792 ps
CPU time 6.65 seconds
Started Jan 21 09:27:10 PM PST 24
Finished Jan 21 09:27:22 PM PST 24
Peak memory 239912 kb
Host smart-cb42f58b-50dc-425d-ab6d-814a5aa7e761
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4231772598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4231772598
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.772585074
Short name T428
Test name
Test status
Simulation time 150702502 ps
CPU time 6.65 seconds
Started Jan 21 09:27:12 PM PST 24
Finished Jan 21 09:27:23 PM PST 24
Peak memory 239896 kb
Host smart-937fc159-e994-4cf3-ab58-ffad14eebd1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77258
5074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.772585074
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1637558651
Short name T553
Test name
Test status
Simulation time 127038719 ps
CPU time 6.22 seconds
Started Jan 21 09:27:10 PM PST 24
Finished Jan 21 09:27:22 PM PST 24
Peak memory 237852 kb
Host smart-7da59cb7-047e-468a-bddc-48276f017b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16375
58651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1637558651
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2492278370
Short name T333
Test name
Test status
Simulation time 9227088231 ps
CPU time 866.99 seconds
Started Jan 21 09:27:09 PM PST 24
Finished Jan 21 09:41:42 PM PST 24
Peak memory 272796 kb
Host smart-9d5df2c2-e82e-46d6-a3df-f67ff0a94068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492278370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2492278370
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3165638147
Short name T445
Test name
Test status
Simulation time 31504857635 ps
CPU time 1817.74 seconds
Started Jan 21 09:55:14 PM PST 24
Finished Jan 21 10:25:44 PM PST 24
Peak memory 265800 kb
Host smart-21a56f56-3aa8-49ff-bf93-e18c2ce7b0e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165638147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3165638147
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.986699107
Short name T521
Test name
Test status
Simulation time 22369453741 ps
CPU time 258.98 seconds
Started Jan 21 09:27:10 PM PST 24
Finished Jan 21 09:31:35 PM PST 24
Peak memory 250176 kb
Host smart-e18b6394-7be2-4557-8733-5518b0b091f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986699107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.986699107
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.492741385
Short name T517
Test name
Test status
Simulation time 169875236 ps
CPU time 12.9 seconds
Started Jan 21 09:37:53 PM PST 24
Finished Jan 21 09:38:08 PM PST 24
Peak memory 248028 kb
Host smart-38fddf12-2605-425b-b80f-4a7babc6342f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49274
1385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.492741385
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3773043070
Short name T510
Test name
Test status
Simulation time 1281676986 ps
CPU time 11.84 seconds
Started Jan 21 09:27:07 PM PST 24
Finished Jan 21 09:27:26 PM PST 24
Peak memory 248112 kb
Host smart-14808076-2625-409c-b038-087d50b91f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37730
43070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3773043070
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2138231466
Short name T372
Test name
Test status
Simulation time 30697805 ps
CPU time 3.55 seconds
Started Jan 21 09:27:11 PM PST 24
Finished Jan 21 09:27:20 PM PST 24
Peak memory 239908 kb
Host smart-7ba8d794-4012-42bc-82c6-ffa7194de134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21382
31466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2138231466
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2738984789
Short name T69
Test name
Test status
Simulation time 6805904466 ps
CPU time 662.52 seconds
Started Jan 21 09:27:21 PM PST 24
Finished Jan 21 09:38:25 PM PST 24
Peak memory 272784 kb
Host smart-1cb7ef7f-a642-451a-bfde-06619ef79bf8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738984789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2738984789
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3385158958
Short name T596
Test name
Test status
Simulation time 54611400008 ps
CPU time 5657.47 seconds
Started Jan 21 09:27:19 PM PST 24
Finished Jan 21 11:01:39 PM PST 24
Peak memory 337076 kb
Host smart-010a360b-d24c-4583-b857-66572430b794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385158958 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3385158958
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.673407770
Short name T199
Test name
Test status
Simulation time 21890799 ps
CPU time 2.95 seconds
Started Jan 21 09:27:27 PM PST 24
Finished Jan 21 09:27:31 PM PST 24
Peak memory 248388 kb
Host smart-8f5000fd-e51c-43c3-a195-55344da8ac8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=673407770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.673407770
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3667978161
Short name T690
Test name
Test status
Simulation time 14824350532 ps
CPU time 1165.26 seconds
Started Jan 21 09:27:26 PM PST 24
Finished Jan 21 09:46:53 PM PST 24
Peak memory 264600 kb
Host smart-934b65cf-689f-4bbd-b1fe-f8964d5213db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667978161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3667978161
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1221355837
Short name T651
Test name
Test status
Simulation time 433019996 ps
CPU time 8.93 seconds
Started Jan 21 09:27:27 PM PST 24
Finished Jan 21 09:27:38 PM PST 24
Peak memory 239904 kb
Host smart-b7e5ff3c-a1fb-4bea-bb50-c9a17d6ec484
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1221355837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1221355837
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2444153795
Short name T74
Test name
Test status
Simulation time 1066788886 ps
CPU time 27.84 seconds
Started Jan 21 09:27:19 PM PST 24
Finished Jan 21 09:27:49 PM PST 24
Peak memory 248092 kb
Host smart-9986e428-ad61-4d34-8263-a87816492b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24441
53795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2444153795
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1509467240
Short name T426
Test name
Test status
Simulation time 317358606 ps
CPU time 30.48 seconds
Started Jan 21 09:27:26 PM PST 24
Finished Jan 21 09:27:58 PM PST 24
Peak memory 248296 kb
Host smart-e6b99319-29bb-4a31-b786-426a33e14b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15094
67240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1509467240
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1953899137
Short name T324
Test name
Test status
Simulation time 161250454177 ps
CPU time 2426.52 seconds
Started Jan 21 09:27:27 PM PST 24
Finished Jan 21 10:07:55 PM PST 24
Peak memory 272636 kb
Host smart-2b04e57f-faa3-485c-8c26-7cd67fd85ca8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953899137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1953899137
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.138695363
Short name T103
Test name
Test status
Simulation time 25266182010 ps
CPU time 1118.65 seconds
Started Jan 21 09:27:27 PM PST 24
Finished Jan 21 09:46:08 PM PST 24
Peak memory 271848 kb
Host smart-3685d6b1-92ae-41d0-941e-ee01322dd828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138695363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.138695363
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3410873317
Short name T305
Test name
Test status
Simulation time 31168204696 ps
CPU time 318.56 seconds
Started Jan 21 09:43:18 PM PST 24
Finished Jan 21 09:48:41 PM PST 24
Peak memory 246692 kb
Host smart-68a12c00-e424-4730-a93a-109df1739e35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410873317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3410873317
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1946013387
Short name T692
Test name
Test status
Simulation time 1464981462 ps
CPU time 27.7 seconds
Started Jan 21 10:37:46 PM PST 24
Finished Jan 21 10:38:22 PM PST 24
Peak memory 248132 kb
Host smart-4dde4092-dcd3-4a75-93c2-7809fed2afb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19460
13387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1946013387
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2274635173
Short name T574
Test name
Test status
Simulation time 603986203 ps
CPU time 25.64 seconds
Started Jan 21 09:27:25 PM PST 24
Finished Jan 21 09:27:53 PM PST 24
Peak memory 248128 kb
Host smart-464e3fca-8812-4f3e-a902-a49d6cc644fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22746
35173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2274635173
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2074678644
Short name T474
Test name
Test status
Simulation time 280056964 ps
CPU time 29.22 seconds
Started Jan 21 10:38:29 PM PST 24
Finished Jan 21 10:39:02 PM PST 24
Peak memory 248096 kb
Host smart-de92d529-2f87-4b9e-b192-40d5308f803d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
78644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2074678644
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1403064292
Short name T594
Test name
Test status
Simulation time 87455221 ps
CPU time 11.02 seconds
Started Jan 21 09:27:26 PM PST 24
Finished Jan 21 09:27:39 PM PST 24
Peak memory 248160 kb
Host smart-1a956f97-8460-400c-9154-ec0da55a54a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14030
64292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1403064292
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2369957871
Short name T203
Test name
Test status
Simulation time 111572747 ps
CPU time 3.11 seconds
Started Jan 21 09:22:38 PM PST 24
Finished Jan 21 09:22:46 PM PST 24
Peak memory 248356 kb
Host smart-a8d6c4cc-c69a-4816-8780-220c28f15818
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2369957871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2369957871
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2887481998
Short name T739
Test name
Test status
Simulation time 6834759846 ps
CPU time 673.01 seconds
Started Jan 21 10:34:20 PM PST 24
Finished Jan 21 10:45:34 PM PST 24
Peak memory 272024 kb
Host smart-85f5b1be-5cad-4f75-981c-7156a38483d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887481998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2887481998
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3316686635
Short name T193
Test name
Test status
Simulation time 10086832583 ps
CPU time 39.7 seconds
Started Jan 21 09:22:29 PM PST 24
Finished Jan 21 09:23:12 PM PST 24
Peak memory 239916 kb
Host smart-d38eaaae-c607-4ee9-8094-cf871cd8baa6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3316686635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3316686635
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2852767840
Short name T512
Test name
Test status
Simulation time 1924173585 ps
CPU time 108.27 seconds
Started Jan 21 09:22:17 PM PST 24
Finished Jan 21 09:24:07 PM PST 24
Peak memory 248084 kb
Host smart-8de012fd-1b79-48ad-b597-2db43c40181f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527
67840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2852767840
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.353634997
Short name T382
Test name
Test status
Simulation time 117489645 ps
CPU time 10.64 seconds
Started Jan 21 10:50:57 PM PST 24
Finished Jan 21 10:51:08 PM PST 24
Peak memory 247368 kb
Host smart-f14c920d-b54d-45e4-a09c-eeae079682e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35363
4997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.353634997
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2012610990
Short name T665
Test name
Test status
Simulation time 267760686671 ps
CPU time 2803.68 seconds
Started Jan 21 09:22:29 PM PST 24
Finished Jan 21 10:09:16 PM PST 24
Peak memory 288976 kb
Host smart-09e6231b-bc56-4ed4-a33f-e73855e0e03c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012610990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2012610990
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4127384460
Short name T384
Test name
Test status
Simulation time 27406539894 ps
CPU time 1556.5 seconds
Started Jan 21 09:59:14 PM PST 24
Finished Jan 21 10:25:12 PM PST 24
Peak memory 264812 kb
Host smart-2158e49e-ad46-474f-a5a6-c3dc12745e66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127384460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4127384460
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4278445042
Short name T299
Test name
Test status
Simulation time 35697098802 ps
CPU time 267.47 seconds
Started Jan 21 09:22:26 PM PST 24
Finished Jan 21 09:26:59 PM PST 24
Peak memory 246716 kb
Host smart-14633c78-1cf2-4de6-aa35-aa888cae2d98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278445042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4278445042
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1241847738
Short name T437
Test name
Test status
Simulation time 628231949 ps
CPU time 15.32 seconds
Started Jan 21 09:59:20 PM PST 24
Finished Jan 21 09:59:38 PM PST 24
Peak memory 251192 kb
Host smart-2985c0e2-ec9a-48a5-a37e-1ab3f1cb08aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12418
47738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1241847738
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1414258730
Short name T443
Test name
Test status
Simulation time 506648065 ps
CPU time 7.26 seconds
Started Jan 21 09:22:16 PM PST 24
Finished Jan 21 09:22:25 PM PST 24
Peak memory 251572 kb
Host smart-392bfcbf-d82b-4bb9-a946-958f1a4eda68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14142
58730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1414258730
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2700087964
Short name T6
Test name
Test status
Simulation time 1925136001 ps
CPU time 47.42 seconds
Started Jan 21 09:31:11 PM PST 24
Finished Jan 21 09:32:08 PM PST 24
Peak memory 248120 kb
Host smart-9150eb4c-dd8c-489f-8c0c-e82d35b8a655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000
87964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2700087964
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3991521379
Short name T603
Test name
Test status
Simulation time 1570599790 ps
CPU time 21.32 seconds
Started Jan 21 09:22:09 PM PST 24
Finished Jan 21 09:22:32 PM PST 24
Peak memory 250192 kb
Host smart-690e6201-b15e-4d38-9044-363066129f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
21379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3991521379
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.4018165064
Short name T623
Test name
Test status
Simulation time 53558094171 ps
CPU time 3001.59 seconds
Started Jan 21 09:22:38 PM PST 24
Finished Jan 21 10:12:45 PM PST 24
Peak memory 288512 kb
Host smart-a4bfe6ee-3b3c-4d44-b334-aba87dc2db00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018165064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.4018165064
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.871768696
Short name T659
Test name
Test status
Simulation time 21817150771 ps
CPU time 1285.95 seconds
Started Jan 21 09:22:38 PM PST 24
Finished Jan 21 09:44:08 PM PST 24
Peak memory 288532 kb
Host smart-830ebbd1-7ece-46ed-94fc-5d92c3ef0e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871768696 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.871768696
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.834526647
Short name T421
Test name
Test status
Simulation time 15559927926 ps
CPU time 317.68 seconds
Started Jan 21 09:27:36 PM PST 24
Finished Jan 21 09:32:57 PM PST 24
Peak memory 250196 kb
Host smart-f9c8612e-6fa2-4722-95c8-25649e5e833d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83452
6647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.834526647
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3145225917
Short name T580
Test name
Test status
Simulation time 492161708 ps
CPU time 35.67 seconds
Started Jan 21 09:27:37 PM PST 24
Finished Jan 21 09:28:16 PM PST 24
Peak memory 254452 kb
Host smart-654c6acb-18e8-4601-b742-e63348673a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31452
25917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3145225917
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2774668164
Short name T100
Test name
Test status
Simulation time 36692106498 ps
CPU time 991.37 seconds
Started Jan 21 09:27:47 PM PST 24
Finished Jan 21 09:44:22 PM PST 24
Peak memory 287968 kb
Host smart-a7f1bc33-0992-4fd0-b50c-eadbfc9cbe73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774668164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2774668164
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.947099656
Short name T308
Test name
Test status
Simulation time 19995012325 ps
CPU time 439.51 seconds
Started Jan 21 09:27:47 PM PST 24
Finished Jan 21 09:35:11 PM PST 24
Peak memory 250264 kb
Host smart-9069d401-f79d-46ed-a67e-1f30bc45a5c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947099656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.947099656
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2660330817
Short name T368
Test name
Test status
Simulation time 517065743 ps
CPU time 34.86 seconds
Started Jan 21 09:27:38 PM PST 24
Finished Jan 21 09:28:17 PM PST 24
Peak memory 248132 kb
Host smart-a1df13ae-a1fc-499e-abe0-4120e2b1ff3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
30817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2660330817
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2328728614
Short name T51
Test name
Test status
Simulation time 825952479 ps
CPU time 48.71 seconds
Started Jan 21 09:27:35 PM PST 24
Finished Jan 21 09:28:26 PM PST 24
Peak memory 252440 kb
Host smart-a5a795ca-6994-4804-8c17-4c26b99f8d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
28614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2328728614
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3231267601
Short name T418
Test name
Test status
Simulation time 205694779 ps
CPU time 5.01 seconds
Started Jan 21 09:27:37 PM PST 24
Finished Jan 21 09:27:46 PM PST 24
Peak memory 237836 kb
Host smart-1ee139bf-3c7e-4748-be6c-205cfd288f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32312
67601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3231267601
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2464075273
Short name T616
Test name
Test status
Simulation time 1302897154 ps
CPU time 23.09 seconds
Started Jan 21 09:27:38 PM PST 24
Finished Jan 21 09:28:05 PM PST 24
Peak memory 248116 kb
Host smart-f9fad2ff-5143-4941-87ac-d14abdfe9561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24640
75273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2464075273
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3123031016
Short name T290
Test name
Test status
Simulation time 80626404319 ps
CPU time 2600.64 seconds
Started Jan 21 09:28:02 PM PST 24
Finished Jan 21 10:11:25 PM PST 24
Peak memory 288504 kb
Host smart-c7179ab2-9bc9-48ac-9f21-75da7d4dd88e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123031016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3123031016
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1670911006
Short name T453
Test name
Test status
Simulation time 26095502121 ps
CPU time 1860.61 seconds
Started Jan 21 09:28:04 PM PST 24
Finished Jan 21 09:59:14 PM PST 24
Peak memory 282548 kb
Host smart-7b122164-920e-4741-ada6-794dab21da34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670911006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1670911006
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.654107163
Short name T729
Test name
Test status
Simulation time 7033661609 ps
CPU time 225.67 seconds
Started Jan 21 09:28:03 PM PST 24
Finished Jan 21 09:31:55 PM PST 24
Peak memory 250248 kb
Host smart-1eaaa50e-6179-486d-9308-d118c892b529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65410
7163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.654107163
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3407556885
Short name T525
Test name
Test status
Simulation time 2506427076 ps
CPU time 74.83 seconds
Started Jan 21 09:28:05 PM PST 24
Finished Jan 21 09:29:29 PM PST 24
Peak memory 250552 kb
Host smart-498ac3de-4182-40e8-80ec-72a098eb4c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34075
56885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3407556885
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1711085251
Short name T393
Test name
Test status
Simulation time 99748866490 ps
CPU time 2668.86 seconds
Started Jan 21 09:28:12 PM PST 24
Finished Jan 21 10:12:49 PM PST 24
Peak memory 288516 kb
Host smart-a6828b39-6e3a-4deb-9b7f-70c6591b0722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711085251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1711085251
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.259147006
Short name T317
Test name
Test status
Simulation time 6638801461 ps
CPU time 142.56 seconds
Started Jan 21 09:28:09 PM PST 24
Finished Jan 21 09:30:38 PM PST 24
Peak memory 253820 kb
Host smart-00451fe5-a8fa-4e85-a65a-46097bc41754
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259147006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.259147006
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2038736228
Short name T61
Test name
Test status
Simulation time 382001517 ps
CPU time 17.72 seconds
Started Jan 21 09:28:03 PM PST 24
Finished Jan 21 09:28:27 PM PST 24
Peak memory 256304 kb
Host smart-ffc135e0-a304-4d05-bb56-887a978f2258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
36228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2038736228
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.516918638
Short name T104
Test name
Test status
Simulation time 1635660664 ps
CPU time 27.66 seconds
Started Jan 21 09:28:04 PM PST 24
Finished Jan 21 09:28:39 PM PST 24
Peak memory 254456 kb
Host smart-e4ed6538-4cb7-4083-b864-bea34124286a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51691
8638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.516918638
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.125012687
Short name T645
Test name
Test status
Simulation time 86390446 ps
CPU time 7.02 seconds
Started Jan 21 09:28:03 PM PST 24
Finished Jan 21 09:28:12 PM PST 24
Peak memory 239940 kb
Host smart-11c8af04-e5d7-4731-ae2b-56557fccc2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12501
2687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.125012687
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3598670038
Short name T378
Test name
Test status
Simulation time 998148389 ps
CPU time 17.49 seconds
Started Jan 21 09:28:03 PM PST 24
Finished Jan 21 09:28:23 PM PST 24
Peak memory 250416 kb
Host smart-27136190-8143-4bef-be5c-09807932a5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35986
70038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3598670038
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1684367339
Short name T640
Test name
Test status
Simulation time 221700561579 ps
CPU time 2860.5 seconds
Started Jan 21 09:28:14 PM PST 24
Finished Jan 21 10:16:03 PM PST 24
Peak memory 288684 kb
Host smart-6fb38c1c-6561-493c-8bec-d4aa4757fb7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684367339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1684367339
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1549065965
Short name T486
Test name
Test status
Simulation time 33417574499 ps
CPU time 643.94 seconds
Started Jan 21 09:28:12 PM PST 24
Finished Jan 21 09:39:04 PM PST 24
Peak memory 266092 kb
Host smart-58002837-1474-4188-a0d7-15d723c09a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549065965 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1549065965
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2973918142
Short name T540
Test name
Test status
Simulation time 76335829498 ps
CPU time 2425.44 seconds
Started Jan 21 09:28:13 PM PST 24
Finished Jan 21 10:08:46 PM PST 24
Peak memory 288684 kb
Host smart-ba731ba5-c465-401b-b9b1-7ff08c4cf1fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973918142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2973918142
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1760660418
Short name T218
Test name
Test status
Simulation time 1825539581 ps
CPU time 86.07 seconds
Started Jan 21 09:28:12 PM PST 24
Finished Jan 21 09:29:46 PM PST 24
Peak memory 250304 kb
Host smart-0e295136-8548-41e8-b855-11811f3c4040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
60418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1760660418
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2037829251
Short name T613
Test name
Test status
Simulation time 76729404 ps
CPU time 11.7 seconds
Started Jan 21 09:28:11 PM PST 24
Finished Jan 21 09:28:29 PM PST 24
Peak memory 247348 kb
Host smart-aace09dc-a0ea-460c-8b25-93670bf34d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20378
29251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2037829251
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3408144914
Short name T567
Test name
Test status
Simulation time 12856932652 ps
CPU time 1279.71 seconds
Started Jan 21 09:28:12 PM PST 24
Finished Jan 21 09:49:40 PM PST 24
Peak memory 285968 kb
Host smart-d5ae3785-3299-4df8-90ba-18c1257e76de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408144914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3408144914
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1591477112
Short name T592
Test name
Test status
Simulation time 390513769314 ps
CPU time 1344.89 seconds
Started Jan 21 09:28:12 PM PST 24
Finished Jan 21 09:50:45 PM PST 24
Peak memory 264476 kb
Host smart-42e0ee5e-b8dc-402b-b6e1-02e8ed39302d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591477112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1591477112
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1357160931
Short name T307
Test name
Test status
Simulation time 9723306103 ps
CPU time 425.28 seconds
Started Jan 21 09:28:12 PM PST 24
Finished Jan 21 09:35:25 PM PST 24
Peak memory 249144 kb
Host smart-d1dd7c57-9dc0-4a12-8824-44520bdf7e05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357160931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1357160931
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4204104277
Short name T536
Test name
Test status
Simulation time 487882599 ps
CPU time 21.57 seconds
Started Jan 21 09:28:11 PM PST 24
Finished Jan 21 09:28:39 PM PST 24
Peak memory 248088 kb
Host smart-dc8b1de8-cebb-49cd-9eb6-be70002d5328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42041
04277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4204104277
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1420395365
Short name T688
Test name
Test status
Simulation time 418949991 ps
CPU time 8.64 seconds
Started Jan 21 09:28:13 PM PST 24
Finished Jan 21 09:28:30 PM PST 24
Peak memory 239028 kb
Host smart-c5e9be37-960f-4aef-a054-e310cf82fb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14203
95365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1420395365
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1864630570
Short name T709
Test name
Test status
Simulation time 646853708 ps
CPU time 30.86 seconds
Started Jan 21 09:28:14 PM PST 24
Finished Jan 21 09:28:53 PM PST 24
Peak memory 254388 kb
Host smart-d407d698-63ab-47d4-8386-82caa3fcef31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18646
30570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1864630570
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2642223120
Short name T417
Test name
Test status
Simulation time 171390635 ps
CPU time 6.86 seconds
Started Jan 21 09:28:11 PM PST 24
Finished Jan 21 09:28:25 PM PST 24
Peak memory 248124 kb
Host smart-e075daf1-9322-4daa-8569-63a794de5147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26422
23120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2642223120
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3593406643
Short name T662
Test name
Test status
Simulation time 164366043181 ps
CPU time 2817.48 seconds
Started Jan 21 09:28:13 PM PST 24
Finished Jan 21 10:15:19 PM PST 24
Peak memory 288456 kb
Host smart-efc4a115-b1b4-4b3b-9fc6-88c4d7f6fb20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593406643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3593406643
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3445277390
Short name T576
Test name
Test status
Simulation time 8614913933 ps
CPU time 824.14 seconds
Started Jan 21 09:28:22 PM PST 24
Finished Jan 21 09:42:12 PM PST 24
Peak memory 264644 kb
Host smart-40e0acd4-93d9-46c9-8fda-5398249c030a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445277390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3445277390
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.4136290932
Short name T653
Test name
Test status
Simulation time 2645383772 ps
CPU time 151.55 seconds
Started Jan 21 09:28:20 PM PST 24
Finished Jan 21 09:30:57 PM PST 24
Peak memory 248152 kb
Host smart-d143adb2-f583-4eb3-aeea-76e91755f1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41362
90932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4136290932
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3827327540
Short name T425
Test name
Test status
Simulation time 194004383 ps
CPU time 10.02 seconds
Started Jan 21 09:28:21 PM PST 24
Finished Jan 21 09:28:37 PM PST 24
Peak memory 248068 kb
Host smart-48be34f1-a435-40d4-96e5-9e1fbf9d5888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38273
27540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3827327540
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2103507817
Short name T654
Test name
Test status
Simulation time 90330125779 ps
CPU time 1298.96 seconds
Started Jan 21 09:28:22 PM PST 24
Finished Jan 21 09:50:07 PM PST 24
Peak memory 264564 kb
Host smart-78ddc8b4-aa4e-459d-8d7f-4eef852b6f7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103507817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2103507817
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3553844106
Short name T693
Test name
Test status
Simulation time 70856742307 ps
CPU time 1163.86 seconds
Started Jan 21 09:28:22 PM PST 24
Finished Jan 21 09:47:52 PM PST 24
Peak memory 272160 kb
Host smart-63dda000-010d-499e-93c7-850d34eb28a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553844106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3553844106
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3497480176
Short name T559
Test name
Test status
Simulation time 25823773522 ps
CPU time 100.99 seconds
Started Jan 21 09:28:21 PM PST 24
Finished Jan 21 09:30:08 PM PST 24
Peak memory 246476 kb
Host smart-6fcccca9-9563-4126-b214-bfa2986fc17a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497480176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3497480176
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2238804266
Short name T716
Test name
Test status
Simulation time 2708840098 ps
CPU time 59.54 seconds
Started Jan 21 09:28:12 PM PST 24
Finished Jan 21 09:29:20 PM PST 24
Peak memory 248100 kb
Host smart-53ac87e7-038e-420a-891a-b0e369a9a216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
04266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2238804266
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.422358894
Short name T601
Test name
Test status
Simulation time 3865177694 ps
CPU time 46.55 seconds
Started Jan 21 09:28:21 PM PST 24
Finished Jan 21 09:29:13 PM PST 24
Peak memory 248176 kb
Host smart-3315eed3-7c9a-4890-b307-0153999c7d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42235
8894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.422358894
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2314918499
Short name T105
Test name
Test status
Simulation time 9642315900 ps
CPU time 65.94 seconds
Started Jan 21 09:28:27 PM PST 24
Finished Jan 21 09:29:39 PM PST 24
Peak memory 248212 kb
Host smart-b638b745-3ae7-4b41-9cc8-fae7eca92eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23149
18499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2314918499
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.420783150
Short name T565
Test name
Test status
Simulation time 5114318375 ps
CPU time 31.86 seconds
Started Jan 21 09:28:11 PM PST 24
Finished Jan 21 09:28:51 PM PST 24
Peak memory 248172 kb
Host smart-bafeb227-a918-40e7-9361-b1fb69f3bd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42078
3150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.420783150
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3661697739
Short name T727
Test name
Test status
Simulation time 19442658846 ps
CPU time 1163.94 seconds
Started Jan 21 09:28:23 PM PST 24
Finished Jan 21 09:47:53 PM PST 24
Peak memory 272904 kb
Host smart-9b37222f-cafe-4af1-bcbd-bdabe911772f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661697739 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3661697739
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.970893956
Short name T658
Test name
Test status
Simulation time 64695830375 ps
CPU time 1181.87 seconds
Started Jan 21 09:28:53 PM PST 24
Finished Jan 21 09:48:48 PM PST 24
Peak memory 270408 kb
Host smart-ca32c589-bf5c-46a0-a96e-9b73b011ade8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970893956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.970893956
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.263376114
Short name T355
Test name
Test status
Simulation time 15556590602 ps
CPU time 206.92 seconds
Started Jan 21 09:28:31 PM PST 24
Finished Jan 21 09:32:06 PM PST 24
Peak memory 249160 kb
Host smart-a87e4415-0002-4197-9bd0-0e76d52950a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26337
6114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.263376114
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.171847488
Short name T80
Test name
Test status
Simulation time 1405915668 ps
CPU time 32.55 seconds
Started Jan 21 09:28:31 PM PST 24
Finished Jan 21 09:29:11 PM PST 24
Peak memory 248236 kb
Host smart-083e56f9-1843-41be-a715-85894b22ae1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
7488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.171847488
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.454897249
Short name T332
Test name
Test status
Simulation time 63116172881 ps
CPU time 1367.07 seconds
Started Jan 21 09:28:42 PM PST 24
Finished Jan 21 09:51:44 PM PST 24
Peak memory 280960 kb
Host smart-21fde588-8f16-4af2-8262-ccede4d79535
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454897249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.454897249
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2535863879
Short name T444
Test name
Test status
Simulation time 29579031979 ps
CPU time 698.22 seconds
Started Jan 21 09:28:47 PM PST 24
Finished Jan 21 09:40:39 PM PST 24
Peak memory 271992 kb
Host smart-403a59eb-cd78-44f7-9804-72ceb714478e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535863879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2535863879
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1577002372
Short name T548
Test name
Test status
Simulation time 13955622185 ps
CPU time 574.79 seconds
Started Jan 21 09:28:44 PM PST 24
Finished Jan 21 09:38:34 PM PST 24
Peak memory 246720 kb
Host smart-964d4e20-a954-409a-8803-c738fd7a43ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577002372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1577002372
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4257842575
Short name T705
Test name
Test status
Simulation time 217598591 ps
CPU time 19.25 seconds
Started Jan 21 10:44:19 PM PST 24
Finished Jan 21 10:44:42 PM PST 24
Peak memory 251200 kb
Host smart-70c810f2-1962-4d40-8719-6344d12b7174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
42575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4257842575
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.511624051
Short name T285
Test name
Test status
Simulation time 372782638 ps
CPU time 39.36 seconds
Started Jan 21 09:28:30 PM PST 24
Finished Jan 21 09:29:17 PM PST 24
Peak memory 248100 kb
Host smart-e714a535-ce5f-4b65-9484-ef7836a3ac90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51162
4051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.511624051
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3675316159
Short name T269
Test name
Test status
Simulation time 1308691045 ps
CPU time 42.77 seconds
Started Jan 21 09:28:34 PM PST 24
Finished Jan 21 09:29:24 PM PST 24
Peak memory 248028 kb
Host smart-f9800ef0-7356-4d27-bf50-2310513c3daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36753
16159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3675316159
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.848775662
Short name T497
Test name
Test status
Simulation time 744502066 ps
CPU time 42.01 seconds
Started Jan 21 10:50:00 PM PST 24
Finished Jan 21 10:50:44 PM PST 24
Peak memory 248128 kb
Host smart-b0fe1d97-10d2-4f4f-b26e-dc363e30db8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84877
5662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.848775662
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1625295352
Short name T65
Test name
Test status
Simulation time 190382613530 ps
CPU time 3413.3 seconds
Started Jan 21 09:28:53 PM PST 24
Finished Jan 21 10:26:00 PM PST 24
Peak memory 288980 kb
Host smart-65df2236-5a1b-42e7-bf0d-c4fd0ff68266
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625295352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1625295352
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2111684376
Short name T248
Test name
Test status
Simulation time 429430598173 ps
CPU time 7347.91 seconds
Started Jan 21 09:28:52 PM PST 24
Finished Jan 21 11:31:35 PM PST 24
Peak memory 320612 kb
Host smart-91d7c12d-62f0-4934-b232-5c2d7f31e471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111684376 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2111684376
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3380158189
Short name T284
Test name
Test status
Simulation time 24106399797 ps
CPU time 1710.11 seconds
Started Jan 21 09:50:52 PM PST 24
Finished Jan 21 10:19:27 PM PST 24
Peak memory 272164 kb
Host smart-993f5624-c717-49c6-9dfb-186af2be7243
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380158189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3380158189
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3571999043
Short name T353
Test name
Test status
Simulation time 1496430953 ps
CPU time 66.98 seconds
Started Jan 21 09:28:49 PM PST 24
Finished Jan 21 09:30:10 PM PST 24
Peak memory 248084 kb
Host smart-989aab44-853b-4482-b16c-04671497ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35719
99043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3571999043
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.605411847
Short name T621
Test name
Test status
Simulation time 5240100203 ps
CPU time 51.87 seconds
Started Jan 21 09:28:49 PM PST 24
Finished Jan 21 09:29:55 PM PST 24
Peak memory 250636 kb
Host smart-b49a89c2-f683-4aa9-9e8e-5fc743819972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60541
1847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.605411847
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.4103942435
Short name T296
Test name
Test status
Simulation time 15804976522 ps
CPU time 1302.12 seconds
Started Jan 21 09:29:00 PM PST 24
Finished Jan 21 09:50:55 PM PST 24
Peak memory 272732 kb
Host smart-9e882d92-4338-4d93-a838-a0cc78ebf16f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103942435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.4103942435
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.873015667
Short name T439
Test name
Test status
Simulation time 27216691447 ps
CPU time 1701.78 seconds
Started Jan 21 09:29:03 PM PST 24
Finished Jan 21 09:57:37 PM PST 24
Peak memory 270816 kb
Host smart-806344a1-fb5a-49cd-be63-b5152fc2c25c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873015667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.873015667
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3730671802
Short name T304
Test name
Test status
Simulation time 3065997518 ps
CPU time 51.63 seconds
Started Jan 21 09:29:01 PM PST 24
Finished Jan 21 09:30:06 PM PST 24
Peak memory 248020 kb
Host smart-b14c3db2-6cd9-4d3a-95ad-4d1d94739381
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730671802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3730671802
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3480367428
Short name T535
Test name
Test status
Simulation time 319466541 ps
CPU time 20.83 seconds
Started Jan 21 09:28:43 PM PST 24
Finished Jan 21 09:29:19 PM PST 24
Peak memory 248132 kb
Host smart-6d3fe86a-8fe1-48b0-83fa-017ca86e0ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34803
67428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3480367428
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.820899996
Short name T107
Test name
Test status
Simulation time 997274195 ps
CPU time 24.54 seconds
Started Jan 21 10:22:24 PM PST 24
Finished Jan 21 10:22:57 PM PST 24
Peak memory 248108 kb
Host smart-e4b4ec2d-4269-493c-9ca4-2235f09d639f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82089
9996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.820899996
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1830737872
Short name T253
Test name
Test status
Simulation time 3339325114 ps
CPU time 48.47 seconds
Started Jan 21 10:20:17 PM PST 24
Finished Jan 21 10:21:13 PM PST 24
Peak memory 248152 kb
Host smart-1f5ff0d8-1626-4b77-9c93-810294ac82f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18307
37872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1830737872
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3441614435
Short name T725
Test name
Test status
Simulation time 1220068971 ps
CPU time 69.84 seconds
Started Jan 21 10:34:47 PM PST 24
Finished Jan 21 10:36:00 PM PST 24
Peak memory 248080 kb
Host smart-629ec25d-e6ac-44db-99d9-2cec1b13025f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34416
14435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3441614435
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2592882209
Short name T263
Test name
Test status
Simulation time 49072196271 ps
CPU time 2620.37 seconds
Started Jan 21 09:29:02 PM PST 24
Finished Jan 21 10:12:55 PM PST 24
Peak memory 285080 kb
Host smart-bc44e7e5-3dc6-40be-ab8f-db5e89b788ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592882209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2592882209
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3378575108
Short name T391
Test name
Test status
Simulation time 45839400636 ps
CPU time 1474.62 seconds
Started Jan 21 09:29:26 PM PST 24
Finished Jan 21 09:54:09 PM PST 24
Peak memory 288576 kb
Host smart-621db245-4872-4a48-be59-8239cb777f0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378575108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3378575108
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.66904521
Short name T661
Test name
Test status
Simulation time 15361823287 ps
CPU time 187.33 seconds
Started Jan 21 10:10:19 PM PST 24
Finished Jan 21 10:13:30 PM PST 24
Peak memory 249220 kb
Host smart-5df5059f-1529-48a8-a740-e321e3782ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66904
521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.66904521
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.284762808
Short name T499
Test name
Test status
Simulation time 365410508 ps
CPU time 25.58 seconds
Started Jan 21 09:29:12 PM PST 24
Finished Jan 21 09:29:49 PM PST 24
Peak memory 248128 kb
Host smart-64564d4e-b1e1-4ca9-a0a7-cdd3fd7243f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28476
2808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.284762808
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.537220082
Short name T322
Test name
Test status
Simulation time 9731935795 ps
CPU time 848.39 seconds
Started Jan 21 09:29:23 PM PST 24
Finished Jan 21 09:43:40 PM PST 24
Peak memory 271828 kb
Host smart-35619d87-32ba-438c-8765-cc7c4e3b6daf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537220082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.537220082
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2537198726
Short name T219
Test name
Test status
Simulation time 250881051401 ps
CPU time 1654.32 seconds
Started Jan 21 09:29:22 PM PST 24
Finished Jan 21 09:57:06 PM PST 24
Peak memory 270404 kb
Host smart-289f9998-ef28-4117-a46b-480d1dba64cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537198726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2537198726
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2744682709
Short name T464
Test name
Test status
Simulation time 23302529024 ps
CPU time 419.4 seconds
Started Jan 21 09:29:24 PM PST 24
Finished Jan 21 09:36:33 PM PST 24
Peak memory 248208 kb
Host smart-34750eb7-37f1-42dc-b867-84bda3112750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744682709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2744682709
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.451524022
Short name T34
Test name
Test status
Simulation time 391485759 ps
CPU time 9.21 seconds
Started Jan 21 09:29:13 PM PST 24
Finished Jan 21 09:29:34 PM PST 24
Peak memory 250676 kb
Host smart-8ca758c8-0593-4fd6-8e8f-d5c28994cea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45152
4022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.451524022
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4265394858
Short name T459
Test name
Test status
Simulation time 72048803 ps
CPU time 2.8 seconds
Started Jan 21 09:29:14 PM PST 24
Finished Jan 21 09:29:29 PM PST 24
Peak memory 237860 kb
Host smart-190b6521-7f19-4504-862d-58db63ce47a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42653
94858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4265394858
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.815731557
Short name T455
Test name
Test status
Simulation time 9875281361 ps
CPU time 32.17 seconds
Started Jan 21 09:29:24 PM PST 24
Finished Jan 21 09:30:05 PM PST 24
Peak memory 254836 kb
Host smart-9e186d0a-ab8b-4baf-9695-5da8c97b292b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81573
1557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.815731557
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3228920917
Short name T682
Test name
Test status
Simulation time 335798171 ps
CPU time 20.5 seconds
Started Jan 21 09:29:04 PM PST 24
Finished Jan 21 09:29:36 PM PST 24
Peak memory 248348 kb
Host smart-3a0fd58b-0b59-456e-9456-7ed86b48a89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
20917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3228920917
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1576575442
Short name T502
Test name
Test status
Simulation time 86960805759 ps
CPU time 2248.3 seconds
Started Jan 21 10:57:26 PM PST 24
Finished Jan 21 11:34:57 PM PST 24
Peak memory 305436 kb
Host smart-63378562-cddd-4db9-a7a5-08231f78e5e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576575442 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1576575442
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.705640376
Short name T558
Test name
Test status
Simulation time 146251758427 ps
CPU time 2386.4 seconds
Started Jan 21 09:29:34 PM PST 24
Finished Jan 21 10:09:26 PM PST 24
Peak memory 272564 kb
Host smart-cfb1c376-2951-4fcd-b6e5-7ab5a53e7f17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705640376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.705640376
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.142616171
Short name T500
Test name
Test status
Simulation time 1756934710 ps
CPU time 100.56 seconds
Started Jan 21 09:29:31 PM PST 24
Finished Jan 21 09:31:18 PM PST 24
Peak memory 250416 kb
Host smart-9ecc0f0d-9935-42d0-a4b1-7c0782a01bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
6171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.142616171
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1163414518
Short name T655
Test name
Test status
Simulation time 976858665 ps
CPU time 46 seconds
Started Jan 21 09:29:34 PM PST 24
Finished Jan 21 09:30:25 PM PST 24
Peak memory 254484 kb
Host smart-03bbe943-e3e7-453b-b407-eca64f89a684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11634
14518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1163414518
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2453316498
Short name T569
Test name
Test status
Simulation time 80154382038 ps
CPU time 1219.95 seconds
Started Jan 21 09:29:41 PM PST 24
Finished Jan 21 09:50:12 PM PST 24
Peak memory 285840 kb
Host smart-3f049ed7-36c4-4969-903e-ad12bdb98bbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453316498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2453316498
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1720023739
Short name T581
Test name
Test status
Simulation time 13967021415 ps
CPU time 1539.05 seconds
Started Jan 21 09:29:41 PM PST 24
Finished Jan 21 09:55:32 PM PST 24
Peak memory 288208 kb
Host smart-bb04b226-13f9-41d9-be5c-fba491ba64a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720023739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1720023739
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.368374112
Short name T273
Test name
Test status
Simulation time 34679122859 ps
CPU time 515.21 seconds
Started Jan 21 09:29:33 PM PST 24
Finished Jan 21 09:38:14 PM PST 24
Peak memory 246632 kb
Host smart-b2067a8c-0fd7-4fbc-912b-d8d323af9ede
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368374112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.368374112
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1084342390
Short name T715
Test name
Test status
Simulation time 346127779 ps
CPU time 36.12 seconds
Started Jan 21 09:29:33 PM PST 24
Finished Jan 21 09:30:15 PM PST 24
Peak memory 248040 kb
Host smart-35712f97-3a9a-4ed4-983d-14f4ee408f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
42390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1084342390
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3866362994
Short name T42
Test name
Test status
Simulation time 1167944362 ps
CPU time 35.14 seconds
Started Jan 21 09:29:35 PM PST 24
Finished Jan 21 09:30:16 PM PST 24
Peak memory 246012 kb
Host smart-06c5a698-dcf6-4b95-81ee-4278c12a18f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
62994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3866362994
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3094100988
Short name T622
Test name
Test status
Simulation time 935847292 ps
CPU time 34.75 seconds
Started Jan 21 09:29:29 PM PST 24
Finished Jan 21 09:30:11 PM PST 24
Peak memory 250168 kb
Host smart-34b1a801-d0f9-46d3-bfc7-0fb13400acf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30941
00988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3094100988
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.20544927
Short name T578
Test name
Test status
Simulation time 2086825388 ps
CPU time 116.15 seconds
Started Jan 21 09:29:48 PM PST 24
Finished Jan 21 09:31:55 PM PST 24
Peak memory 256328 kb
Host smart-486a881b-5525-46b6-b7b5-0042110fdbd7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_hand
ler_stress_all.20544927
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1892335135
Short name T262
Test name
Test status
Simulation time 166114734380 ps
CPU time 1924.89 seconds
Started Jan 21 09:29:49 PM PST 24
Finished Jan 21 10:02:06 PM PST 24
Peak memory 286956 kb
Host smart-20929ce0-18cb-4bca-908d-b5911648de8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892335135 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1892335135
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3589912746
Short name T527
Test name
Test status
Simulation time 403466969620 ps
CPU time 3119.92 seconds
Started Jan 21 09:30:07 PM PST 24
Finished Jan 21 10:22:28 PM PST 24
Peak memory 288276 kb
Host smart-42816017-c947-49cb-ad2c-cc4679014662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589912746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3589912746
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1611073338
Short name T405
Test name
Test status
Simulation time 279387835 ps
CPU time 5.16 seconds
Started Jan 21 09:30:07 PM PST 24
Finished Jan 21 09:30:33 PM PST 24
Peak memory 238116 kb
Host smart-9a70942f-8600-40bf-af9e-25febe3bad4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16110
73338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1611073338
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.523019898
Short name T419
Test name
Test status
Simulation time 6345167834 ps
CPU time 46.5 seconds
Started Jan 21 09:30:10 PM PST 24
Finished Jan 21 09:31:17 PM PST 24
Peak memory 248128 kb
Host smart-1ae85f45-0a77-4bde-8b20-77cedc1130de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52301
9898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.523019898
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.373910011
Short name T675
Test name
Test status
Simulation time 18421179575 ps
CPU time 1259.07 seconds
Started Jan 21 09:30:09 PM PST 24
Finished Jan 21 09:51:29 PM PST 24
Peak memory 264576 kb
Host smart-ea70c17a-5a89-42b8-b716-f61db3ad0d7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373910011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.373910011
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1652449146
Short name T9
Test name
Test status
Simulation time 22785865338 ps
CPU time 416.69 seconds
Started Jan 21 09:30:09 PM PST 24
Finished Jan 21 09:37:26 PM PST 24
Peak memory 246596 kb
Host smart-8eb9aa5e-9af0-4475-8419-748429ae97f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652449146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1652449146
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3316488034
Short name T528
Test name
Test status
Simulation time 1308837265 ps
CPU time 50.8 seconds
Started Jan 21 09:29:57 PM PST 24
Finished Jan 21 09:31:02 PM PST 24
Peak memory 248100 kb
Host smart-7a539f1b-871d-4ea8-9e26-5790062da56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
88034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3316488034
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2642433681
Short name T38
Test name
Test status
Simulation time 634601520 ps
CPU time 38.27 seconds
Started Jan 21 09:29:56 PM PST 24
Finished Jan 21 09:30:48 PM PST 24
Peak memory 247268 kb
Host smart-ec9e2ca4-68c6-4f91-9e37-ec0ee74371a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26424
33681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2642433681
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3344971748
Short name T394
Test name
Test status
Simulation time 83389050 ps
CPU time 9.47 seconds
Started Jan 21 09:30:09 PM PST 24
Finished Jan 21 09:30:39 PM PST 24
Peak memory 248136 kb
Host smart-b5d2cb0e-c817-4145-87ee-fa1a480bfefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449
71748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3344971748
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4293917829
Short name T380
Test name
Test status
Simulation time 812114498 ps
CPU time 25.81 seconds
Started Jan 21 09:29:48 PM PST 24
Finished Jan 21 09:30:25 PM PST 24
Peak memory 248116 kb
Host smart-88a3e40b-560c-4d5f-a0cf-30c47ff9e518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42939
17829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4293917829
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1278144197
Short name T542
Test name
Test status
Simulation time 159779311651 ps
CPU time 1745.74 seconds
Started Jan 21 10:00:03 PM PST 24
Finished Jan 21 10:29:15 PM PST 24
Peak memory 281148 kb
Host smart-696521b3-0f09-4cfb-b1e9-d117df585e10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278144197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1278144197
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2964427463
Short name T110
Test name
Test status
Simulation time 15076538193 ps
CPU time 2044.06 seconds
Started Jan 21 09:30:07 PM PST 24
Finished Jan 21 10:04:32 PM PST 24
Peak memory 302768 kb
Host smart-e3b961b9-c35b-4cfc-85ae-f2ee27a9cb0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964427463 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2964427463
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.475470246
Short name T67
Test name
Test status
Simulation time 362478609472 ps
CPU time 2210.46 seconds
Started Jan 21 09:30:18 PM PST 24
Finished Jan 21 10:07:36 PM PST 24
Peak memory 289012 kb
Host smart-108ca65f-8650-454d-8613-6acfffa9f02a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475470246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.475470246
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3502374788
Short name T620
Test name
Test status
Simulation time 414944807 ps
CPU time 41.07 seconds
Started Jan 21 09:30:17 PM PST 24
Finished Jan 21 09:31:24 PM PST 24
Peak memory 248080 kb
Host smart-84ae32ee-92fd-4fe0-8eed-dc2c377bba93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023
74788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3502374788
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4282841498
Short name T217
Test name
Test status
Simulation time 99697420 ps
CPU time 7.27 seconds
Started Jan 21 09:30:17 PM PST 24
Finished Jan 21 09:30:51 PM PST 24
Peak memory 239940 kb
Host smart-a9860705-10e2-475d-8bfc-9ab42dcd343f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42828
41498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4282841498
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.115367443
Short name T509
Test name
Test status
Simulation time 71488175349 ps
CPU time 1091.34 seconds
Started Jan 21 10:07:58 PM PST 24
Finished Jan 21 10:26:11 PM PST 24
Peak memory 272788 kb
Host smart-0fe4823b-36d9-4b7e-9a46-1b7dd0246982
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115367443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.115367443
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3557598197
Short name T420
Test name
Test status
Simulation time 135518946632 ps
CPU time 1140.86 seconds
Started Jan 21 09:41:01 PM PST 24
Finished Jan 21 10:00:13 PM PST 24
Peak memory 283508 kb
Host smart-9f7a9e0b-605f-431c-b619-70b02e964f7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557598197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3557598197
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.534016863
Short name T738
Test name
Test status
Simulation time 39741420743 ps
CPU time 433.7 seconds
Started Jan 21 09:30:18 PM PST 24
Finished Jan 21 09:37:59 PM PST 24
Peak memory 245700 kb
Host smart-b5a00f9a-32d8-406a-9f42-7a3693fcacc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534016863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.534016863
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1363626284
Short name T400
Test name
Test status
Simulation time 3432401515 ps
CPU time 32.73 seconds
Started Jan 21 09:30:09 PM PST 24
Finished Jan 21 09:31:03 PM PST 24
Peak memory 248188 kb
Host smart-a7afe2c9-d70c-4670-848e-a4a8c55f4ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13636
26284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1363626284
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.508968445
Short name T505
Test name
Test status
Simulation time 133844400 ps
CPU time 8.9 seconds
Started Jan 21 09:30:18 PM PST 24
Finished Jan 21 09:30:53 PM PST 24
Peak memory 248044 kb
Host smart-500ca21a-e3fd-4580-9050-6e2a03279604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50896
8445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.508968445
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1094068435
Short name T254
Test name
Test status
Simulation time 552300024 ps
CPU time 35.99 seconds
Started Jan 21 09:30:17 PM PST 24
Finished Jan 21 09:31:19 PM PST 24
Peak memory 248140 kb
Host smart-ccb1bb58-f3a9-4a75-9ad8-04d1f8ed7ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
68435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1094068435
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3150229132
Short name T369
Test name
Test status
Simulation time 94608128 ps
CPU time 7.64 seconds
Started Jan 21 09:30:09 PM PST 24
Finished Jan 21 09:30:37 PM PST 24
Peak memory 239924 kb
Host smart-e854744e-7000-4156-8bfa-901f1cef838e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
29132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3150229132
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1259251256
Short name T546
Test name
Test status
Simulation time 19544790907 ps
CPU time 1567.82 seconds
Started Jan 21 09:30:29 PM PST 24
Finished Jan 21 09:57:00 PM PST 24
Peak memory 304924 kb
Host smart-03f3c178-66b0-447b-a373-35c3440c71c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259251256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1259251256
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.203267346
Short name T433
Test name
Test status
Simulation time 153996183862 ps
CPU time 2517.24 seconds
Started Jan 21 09:54:24 PM PST 24
Finished Jan 21 10:36:35 PM PST 24
Peak memory 286940 kb
Host smart-9e23d0c6-8299-4432-b04f-b9d3c4cf6bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203267346 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.203267346
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1925000817
Short name T201
Test name
Test status
Simulation time 197562588 ps
CPU time 4.35 seconds
Started Jan 21 09:23:09 PM PST 24
Finished Jan 21 09:23:17 PM PST 24
Peak memory 248372 kb
Host smart-30ea22ec-9811-45dc-a174-a62156fe954a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1925000817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1925000817
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1413690014
Short name T554
Test name
Test status
Simulation time 16394764948 ps
CPU time 1429.23 seconds
Started Jan 21 09:22:55 PM PST 24
Finished Jan 21 09:46:47 PM PST 24
Peak memory 285628 kb
Host smart-20f86166-ef43-4f9a-aaeb-3dc9f8506c6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413690014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1413690014
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1163350239
Short name T231
Test name
Test status
Simulation time 774243607 ps
CPU time 19.17 seconds
Started Jan 21 09:23:14 PM PST 24
Finished Jan 21 09:23:43 PM PST 24
Peak memory 239916 kb
Host smart-941012bb-a9a4-4c5a-85e3-7e11eb59b6a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1163350239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1163350239
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1239453307
Short name T452
Test name
Test status
Simulation time 199127836 ps
CPU time 4.2 seconds
Started Jan 21 09:22:57 PM PST 24
Finished Jan 21 09:23:03 PM PST 24
Peak memory 237840 kb
Host smart-cf301f67-890b-4f47-a712-00f5b5c1a310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12394
53307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1239453307
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2393169689
Short name T468
Test name
Test status
Simulation time 321695526 ps
CPU time 14.59 seconds
Started Jan 21 09:22:53 PM PST 24
Finished Jan 21 09:23:10 PM PST 24
Peak memory 248048 kb
Host smart-79fe0b8a-1597-4fc2-a510-4427678a02de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931
69689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2393169689
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.780837044
Short name T323
Test name
Test status
Simulation time 217204920203 ps
CPU time 3252.08 seconds
Started Jan 21 09:23:09 PM PST 24
Finished Jan 21 10:17:26 PM PST 24
Peak memory 288632 kb
Host smart-bb04f2f0-db04-4f88-a503-b37581a4cdda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780837044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.780837044
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4226113708
Short name T533
Test name
Test status
Simulation time 238679341945 ps
CPU time 2734.56 seconds
Started Jan 21 09:23:12 PM PST 24
Finished Jan 21 10:08:50 PM PST 24
Peak memory 282780 kb
Host smart-2e431f9c-63ff-4c9f-a57b-58770118c46e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226113708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4226113708
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2305363073
Short name T579
Test name
Test status
Simulation time 15144470828 ps
CPU time 590.15 seconds
Started Jan 21 09:22:56 PM PST 24
Finished Jan 21 09:32:48 PM PST 24
Peak memory 245640 kb
Host smart-6abd848a-d173-46fd-9154-ad141359e9fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305363073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2305363073
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1028710724
Short name T543
Test name
Test status
Simulation time 366929935 ps
CPU time 31.85 seconds
Started Jan 21 09:22:37 PM PST 24
Finished Jan 21 09:23:13 PM PST 24
Peak memory 248140 kb
Host smart-f9fda5f9-61fd-4fbf-bee9-ba77df60715b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10287
10724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1028710724
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1306963498
Short name T440
Test name
Test status
Simulation time 215110257 ps
CPU time 12.47 seconds
Started Jan 21 09:22:40 PM PST 24
Finished Jan 21 09:22:58 PM PST 24
Peak memory 253132 kb
Host smart-01d3cc6d-2f28-4f5e-bcf4-7ee3085962e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13069
63498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1306963498
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.76871989
Short name T40
Test name
Test status
Simulation time 910375796 ps
CPU time 23.63 seconds
Started Jan 21 09:42:58 PM PST 24
Finished Jan 21 09:43:23 PM PST 24
Peak memory 272764 kb
Host smart-9e4cdfa0-2b46-49f6-903a-2a62327ce950
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=76871989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.76871989
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.707165004
Short name T264
Test name
Test status
Simulation time 558295437 ps
CPU time 33.06 seconds
Started Jan 21 09:22:56 PM PST 24
Finished Jan 21 09:23:31 PM PST 24
Peak memory 246284 kb
Host smart-0e8e348a-4b37-4292-8f2d-6f868fdd040e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70716
5004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.707165004
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2330165903
Short name T609
Test name
Test status
Simulation time 1155183517 ps
CPU time 20.26 seconds
Started Jan 21 09:22:39 PM PST 24
Finished Jan 21 09:23:05 PM PST 24
Peak memory 248100 kb
Host smart-99b62f91-b4a3-4f54-9bdb-c1051fdda281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23301
65903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2330165903
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.197269194
Short name T188
Test name
Test status
Simulation time 64684482120 ps
CPU time 1923.41 seconds
Started Jan 21 09:23:10 PM PST 24
Finished Jan 21 09:55:18 PM PST 24
Peak memory 289084 kb
Host smart-ca39da6d-c79f-4974-b64d-8ff02b9d8dc6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197269194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.197269194
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3815685628
Short name T573
Test name
Test status
Simulation time 39298289354 ps
CPU time 4011.82 seconds
Started Jan 21 09:23:11 PM PST 24
Finished Jan 21 10:30:07 PM PST 24
Peak memory 330268 kb
Host smart-30a89e09-867c-43c0-b9cd-c467c57c2fd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815685628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3815685628
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4215676921
Short name T467
Test name
Test status
Simulation time 78745714616 ps
CPU time 1814.75 seconds
Started Jan 21 09:30:38 PM PST 24
Finished Jan 21 10:01:11 PM PST 24
Peak memory 272680 kb
Host smart-4f4eb681-f532-46d7-8696-1dc022df37c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215676921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4215676921
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.169054955
Short name T407
Test name
Test status
Simulation time 3072843036 ps
CPU time 108.56 seconds
Started Jan 21 09:30:38 PM PST 24
Finished Jan 21 09:32:45 PM PST 24
Peak memory 248248 kb
Host smart-9cffb1a8-da39-47c0-b67b-a570be026cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16905
4955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.169054955
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3276573707
Short name T708
Test name
Test status
Simulation time 690085796 ps
CPU time 47.24 seconds
Started Jan 21 09:30:30 PM PST 24
Finished Jan 21 09:31:40 PM PST 24
Peak memory 248448 kb
Host smart-2c057aef-2be6-44fd-a3ef-a91257949cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32765
73707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3276573707
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2951111900
Short name T320
Test name
Test status
Simulation time 25911954289 ps
CPU time 1489.71 seconds
Started Jan 21 09:56:30 PM PST 24
Finished Jan 21 10:21:22 PM PST 24
Peak memory 271348 kb
Host smart-462e5585-5016-48a8-908f-ce76140fccac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951111900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2951111900
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3987062759
Short name T664
Test name
Test status
Simulation time 52582169999 ps
CPU time 1376.35 seconds
Started Jan 21 10:06:26 PM PST 24
Finished Jan 21 10:29:34 PM PST 24
Peak memory 280856 kb
Host smart-47d38261-dad6-4e2e-816e-c670e338c89a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987062759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3987062759
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1819565947
Short name T680
Test name
Test status
Simulation time 572504298 ps
CPU time 31.68 seconds
Started Jan 21 09:30:29 PM PST 24
Finished Jan 21 09:31:24 PM PST 24
Peak memory 253804 kb
Host smart-b4411034-043b-4cc8-8c33-8c04db95a388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
65947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1819565947
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.187571236
Short name T31
Test name
Test status
Simulation time 1383122973 ps
CPU time 23 seconds
Started Jan 21 09:30:29 PM PST 24
Finished Jan 21 09:31:15 PM PST 24
Peak memory 248296 kb
Host smart-a3a3e284-32de-4a8f-9b6e-1e9a309bc499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18757
1236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.187571236
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2440230771
Short name T221
Test name
Test status
Simulation time 50962290 ps
CPU time 4.46 seconds
Started Jan 21 10:18:51 PM PST 24
Finished Jan 21 10:19:01 PM PST 24
Peak memory 237804 kb
Host smart-4a4991ec-9f8f-4884-8461-58a92262c816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
30771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2440230771
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3190896394
Short name T479
Test name
Test status
Simulation time 483571847 ps
CPU time 7.04 seconds
Started Jan 21 09:30:30 PM PST 24
Finished Jan 21 09:31:00 PM PST 24
Peak memory 239856 kb
Host smart-3b0a1d0b-2010-4ed5-be50-b4414541f99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31908
96394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3190896394
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1350273519
Short name T99
Test name
Test status
Simulation time 34485254790 ps
CPU time 2225.14 seconds
Started Jan 21 09:59:14 PM PST 24
Finished Jan 21 10:36:21 PM PST 24
Peak memory 271724 kb
Host smart-0f8f54ee-e559-4b04-8ae8-ad71513bef56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350273519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1350273519
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3106228052
Short name T413
Test name
Test status
Simulation time 1341444440 ps
CPU time 86.78 seconds
Started Jan 21 09:30:59 PM PST 24
Finished Jan 21 09:32:40 PM PST 24
Peak memory 251384 kb
Host smart-707e6a0c-11fb-4b4e-992b-111cc3dc063e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
28052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3106228052
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1904596350
Short name T504
Test name
Test status
Simulation time 68245285 ps
CPU time 5.29 seconds
Started Jan 21 09:30:57 PM PST 24
Finished Jan 21 09:31:18 PM PST 24
Peak memory 237908 kb
Host smart-46046214-565f-4f3a-961e-6141dcd0ebe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19045
96350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1904596350
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3685526118
Short name T331
Test name
Test status
Simulation time 60656142756 ps
CPU time 1226.2 seconds
Started Jan 21 09:54:15 PM PST 24
Finished Jan 21 10:14:59 PM PST 24
Peak memory 272740 kb
Host smart-70b90633-e536-47f5-abd1-f57bfc4bec1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685526118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3685526118
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1946165364
Short name T281
Test name
Test status
Simulation time 224389652187 ps
CPU time 1664.38 seconds
Started Jan 21 09:30:59 PM PST 24
Finished Jan 21 09:58:58 PM PST 24
Peak memory 287628 kb
Host smart-936d90b1-b2b5-40aa-a931-3d4aab3f592e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946165364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1946165364
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3030263489
Short name T507
Test name
Test status
Simulation time 3786843195 ps
CPU time 162.91 seconds
Started Jan 21 09:30:57 PM PST 24
Finished Jan 21 09:33:57 PM PST 24
Peak memory 250228 kb
Host smart-6596c3f5-a4c7-4fe3-9a05-4990ca8895a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030263489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3030263489
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2956051145
Short name T660
Test name
Test status
Simulation time 1494344186 ps
CPU time 44.58 seconds
Started Jan 21 09:30:48 PM PST 24
Finished Jan 21 09:31:50 PM PST 24
Peak memory 248084 kb
Host smart-701d673e-f285-4058-ba49-7218663390c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
51145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2956051145
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.25256385
Short name T728
Test name
Test status
Simulation time 2225079302 ps
CPU time 55.75 seconds
Started Jan 21 09:30:48 PM PST 24
Finished Jan 21 09:32:01 PM PST 24
Peak memory 248148 kb
Host smart-108679bc-cc46-4e49-8cc9-5010176e1832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256
385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.25256385
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1321009292
Short name T639
Test name
Test status
Simulation time 216449301 ps
CPU time 24.91 seconds
Started Jan 21 09:30:56 PM PST 24
Finished Jan 21 09:31:38 PM PST 24
Peak memory 250348 kb
Host smart-0d3e7016-e353-40f8-831a-27ca4f7579ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13210
09292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1321009292
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1625674055
Short name T726
Test name
Test status
Simulation time 3039207583 ps
CPU time 51.09 seconds
Started Jan 21 09:30:50 PM PST 24
Finished Jan 21 09:32:00 PM PST 24
Peak memory 248220 kb
Host smart-01f8ef0d-c0e0-472e-8748-d36b442d1c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
74055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1625674055
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.958916388
Short name T112
Test name
Test status
Simulation time 259988007517 ps
CPU time 3841.6 seconds
Started Jan 21 09:30:57 PM PST 24
Finished Jan 21 10:35:15 PM PST 24
Peak memory 297300 kb
Host smart-8e204f7e-2144-4b4a-b686-09f299446ec1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958916388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.958916388
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3750145546
Short name T245
Test name
Test status
Simulation time 220800944596 ps
CPU time 7686.94 seconds
Started Jan 21 09:30:57 PM PST 24
Finished Jan 21 11:39:21 PM PST 24
Peak memory 338428 kb
Host smart-205a959a-4fbd-4b47-8742-1076c336316d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750145546 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3750145546
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1280083755
Short name T472
Test name
Test status
Simulation time 16027946997 ps
CPU time 1721.37 seconds
Started Jan 21 09:31:17 PM PST 24
Finished Jan 21 10:00:09 PM PST 24
Peak memory 289068 kb
Host smart-8ed204f9-7bc1-4909-9c73-1d20a80444f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280083755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1280083755
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3387079835
Short name T489
Test name
Test status
Simulation time 12194886910 ps
CPU time 194.87 seconds
Started Jan 21 09:31:17 PM PST 24
Finished Jan 21 09:34:42 PM PST 24
Peak memory 248220 kb
Host smart-11324133-9d55-4623-85a7-a86dd6dd6d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33870
79835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3387079835
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1621665363
Short name T84
Test name
Test status
Simulation time 493195707 ps
CPU time 26.94 seconds
Started Jan 21 09:57:34 PM PST 24
Finished Jan 21 09:58:05 PM PST 24
Peak memory 247096 kb
Host smart-1b96ea91-97a6-4875-8946-97cf1d080c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
65363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1621665363
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1952421371
Short name T373
Test name
Test status
Simulation time 227616958157 ps
CPU time 1115.39 seconds
Started Jan 21 09:31:33 PM PST 24
Finished Jan 21 09:50:31 PM PST 24
Peak memory 282776 kb
Host smart-36db7e16-ca4d-4f36-b4c0-77118554bf19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952421371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1952421371
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1475951637
Short name T481
Test name
Test status
Simulation time 1175983050 ps
CPU time 14.72 seconds
Started Jan 21 09:31:08 PM PST 24
Finished Jan 21 09:31:31 PM PST 24
Peak memory 256220 kb
Host smart-c6af894e-a712-44c1-ac79-4137a688bf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14759
51637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1475951637
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2360213492
Short name T268
Test name
Test status
Simulation time 257594212 ps
CPU time 10.53 seconds
Started Jan 21 10:23:47 PM PST 24
Finished Jan 21 10:24:03 PM PST 24
Peak memory 248112 kb
Host smart-8db00785-ceac-4c0e-ba5a-3a135ac29d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
13492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2360213492
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3845344848
Short name T495
Test name
Test status
Simulation time 7662704561 ps
CPU time 41.19 seconds
Started Jan 21 09:31:09 PM PST 24
Finished Jan 21 09:31:58 PM PST 24
Peak memory 248192 kb
Host smart-604eccca-7561-402d-b483-95dbfbd15542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38453
44848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3845344848
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1309488285
Short name T513
Test name
Test status
Simulation time 39773858351 ps
CPU time 1395.37 seconds
Started Jan 21 09:31:49 PM PST 24
Finished Jan 21 09:55:30 PM PST 24
Peak memory 272520 kb
Host smart-9b83cb52-11df-4fa0-ae7a-28fe89d5918c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309488285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1309488285
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.135239448
Short name T679
Test name
Test status
Simulation time 23275049032 ps
CPU time 372.73 seconds
Started Jan 21 09:31:47 PM PST 24
Finished Jan 21 09:38:26 PM PST 24
Peak memory 250148 kb
Host smart-7d5cb815-3744-484e-b0da-c5a396417ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13523
9448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.135239448
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.627663949
Short name T252
Test name
Test status
Simulation time 886738273 ps
CPU time 57.9 seconds
Started Jan 21 09:31:34 PM PST 24
Finished Jan 21 09:32:55 PM PST 24
Peak memory 248092 kb
Host smart-c79bd161-8f4a-4825-ad43-7765027d8349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62766
3949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.627663949
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2032599581
Short name T511
Test name
Test status
Simulation time 44183547725 ps
CPU time 1546.64 seconds
Started Jan 21 09:31:55 PM PST 24
Finished Jan 21 09:58:06 PM PST 24
Peak memory 272480 kb
Host smart-526c9e98-d4c9-4165-b628-e5e68b0b94f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032599581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2032599581
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2998276153
Short name T704
Test name
Test status
Simulation time 39123485539 ps
CPU time 98.93 seconds
Started Jan 21 09:31:58 PM PST 24
Finished Jan 21 09:34:00 PM PST 24
Peak memory 246516 kb
Host smart-5faeb245-d4e8-43bd-a401-703ae8c07f57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998276153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2998276153
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3000622129
Short name T363
Test name
Test status
Simulation time 440696824 ps
CPU time 32.4 seconds
Started Jan 21 09:31:33 PM PST 24
Finished Jan 21 09:32:27 PM PST 24
Peak memory 248124 kb
Host smart-ff715c91-3200-4296-8a29-b576592175ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006
22129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3000622129
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3480744637
Short name T518
Test name
Test status
Simulation time 229572642 ps
CPU time 11.98 seconds
Started Jan 21 09:31:36 PM PST 24
Finished Jan 21 09:32:14 PM PST 24
Peak memory 248324 kb
Host smart-fdf2e18a-5f48-4419-b6ce-1ab83629eb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34807
44637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3480744637
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.999790297
Short name T256
Test name
Test status
Simulation time 6659537868 ps
CPU time 55.89 seconds
Started Jan 21 09:31:54 PM PST 24
Finished Jan 21 09:33:14 PM PST 24
Peak memory 253552 kb
Host smart-23320dc9-6c46-4071-b396-11194d9b99f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99979
0297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.999790297
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1091205138
Short name T508
Test name
Test status
Simulation time 2262381417 ps
CPU time 37.92 seconds
Started Jan 21 09:31:35 PM PST 24
Finished Jan 21 09:32:37 PM PST 24
Peak memory 254788 kb
Host smart-a42c2f47-efd0-47e8-9b60-33dda7e04988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10912
05138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1091205138
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3625719209
Short name T650
Test name
Test status
Simulation time 5430287775 ps
CPU time 371.39 seconds
Started Jan 21 09:31:58 PM PST 24
Finished Jan 21 09:38:33 PM PST 24
Peak memory 256352 kb
Host smart-eab14650-a004-4860-84c5-cca879659d5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625719209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3625719209
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.847099979
Short name T111
Test name
Test status
Simulation time 186578881298 ps
CPU time 3195.14 seconds
Started Jan 21 09:31:53 PM PST 24
Finished Jan 21 10:25:33 PM PST 24
Peak memory 297924 kb
Host smart-63df33b2-87a5-4ee6-ba7a-12f2d5b1c657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847099979 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.847099979
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3144821138
Short name T483
Test name
Test status
Simulation time 83576120620 ps
CPU time 1316.05 seconds
Started Jan 21 10:05:16 PM PST 24
Finished Jan 21 10:27:14 PM PST 24
Peak memory 280980 kb
Host smart-d6bfc838-8642-40f9-bbe1-b6a859b9a21a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144821138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3144821138
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1019336945
Short name T541
Test name
Test status
Simulation time 1682563393 ps
CPU time 96.84 seconds
Started Jan 21 09:32:02 PM PST 24
Finished Jan 21 09:34:02 PM PST 24
Peak memory 253596 kb
Host smart-f3c75dea-3639-4b1a-aba4-b6c69f126865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10193
36945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1019336945
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1219132058
Short name T696
Test name
Test status
Simulation time 759757412 ps
CPU time 18.36 seconds
Started Jan 21 09:32:03 PM PST 24
Finished Jan 21 09:32:44 PM PST 24
Peak memory 250216 kb
Host smart-70418a26-3c49-4fd5-b304-8578f06330db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
32058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1219132058
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2281707278
Short name T338
Test name
Test status
Simulation time 173782522721 ps
CPU time 2235.55 seconds
Started Jan 21 09:32:19 PM PST 24
Finished Jan 21 10:09:56 PM PST 24
Peak memory 272700 kb
Host smart-3f277a0c-454f-4ebe-a200-a7a12127a92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281707278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2281707278
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4283039725
Short name T684
Test name
Test status
Simulation time 16468085633 ps
CPU time 989.55 seconds
Started Jan 21 10:07:55 PM PST 24
Finished Jan 21 10:24:26 PM PST 24
Peak memory 272544 kb
Host smart-2edcd4c6-8e3b-47eb-976d-d3f9b1a20d8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283039725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4283039725
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2728989829
Short name T530
Test name
Test status
Simulation time 10978501028 ps
CPU time 436.48 seconds
Started Jan 21 10:26:07 PM PST 24
Finished Jan 21 10:33:38 PM PST 24
Peak memory 246660 kb
Host smart-d0203814-f404-46ae-af5b-83898a6da24d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728989829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2728989829
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3869767070
Short name T669
Test name
Test status
Simulation time 788570804 ps
CPU time 20.83 seconds
Started Jan 21 09:31:56 PM PST 24
Finished Jan 21 09:32:40 PM PST 24
Peak memory 248068 kb
Host smart-7494255e-3686-459f-806e-ed334f8aa64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
67070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3869767070
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1919391293
Short name T608
Test name
Test status
Simulation time 1835382986 ps
CPU time 29.61 seconds
Started Jan 21 09:31:59 PM PST 24
Finished Jan 21 09:32:52 PM PST 24
Peak memory 253564 kb
Host smart-28b35ac8-66c5-44d5-8002-083b36dd54d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19193
91293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1919391293
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.698152647
Short name T434
Test name
Test status
Simulation time 8930626711 ps
CPU time 34.21 seconds
Started Jan 21 10:52:35 PM PST 24
Finished Jan 21 10:53:13 PM PST 24
Peak memory 248152 kb
Host smart-b0e16763-2feb-4fbb-845d-9afbd04f92b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69815
2647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.698152647
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.222041642
Short name T730
Test name
Test status
Simulation time 1110952843 ps
CPU time 63.02 seconds
Started Jan 21 09:31:57 PM PST 24
Finished Jan 21 09:33:23 PM PST 24
Peak memory 248060 kb
Host smart-b63c6f46-2a40-4d5d-81fe-4c7c9143346f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22204
1642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.222041642
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3821304963
Short name T66
Test name
Test status
Simulation time 156516439454 ps
CPU time 2791.83 seconds
Started Jan 21 09:32:20 PM PST 24
Finished Jan 21 10:19:13 PM PST 24
Peak memory 287696 kb
Host smart-077f4e25-6837-49ef-81f7-83d3b94bc7e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821304963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3821304963
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4127062746
Short name T397
Test name
Test status
Simulation time 82102917228 ps
CPU time 1600.78 seconds
Started Jan 21 09:32:21 PM PST 24
Finished Jan 21 09:59:23 PM PST 24
Peak memory 288792 kb
Host smart-7bc03a45-7b56-432d-bf97-feecfb56a452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127062746 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4127062746
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2380350349
Short name T92
Test name
Test status
Simulation time 25432400377 ps
CPU time 1495.92 seconds
Started Jan 21 09:32:26 PM PST 24
Finished Jan 21 09:57:42 PM PST 24
Peak memory 288788 kb
Host smart-223c26b8-fd33-4eaa-9805-db397deb52b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380350349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2380350349
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.137421956
Short name T462
Test name
Test status
Simulation time 39002303614 ps
CPU time 161.61 seconds
Started Jan 21 09:32:26 PM PST 24
Finished Jan 21 09:35:28 PM PST 24
Peak memory 249224 kb
Host smart-51790a2e-9c9e-4b55-980f-d1f19f77d171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13742
1956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.137421956
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1988434868
Short name T442
Test name
Test status
Simulation time 451379717 ps
CPU time 25.37 seconds
Started Jan 21 10:22:15 PM PST 24
Finished Jan 21 10:22:45 PM PST 24
Peak memory 248124 kb
Host smart-b2825732-60d9-49d6-bc19-3f999c21fb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19884
34868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1988434868
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3424269567
Short name T283
Test name
Test status
Simulation time 90169642444 ps
CPU time 2757.04 seconds
Started Jan 21 09:32:26 PM PST 24
Finished Jan 21 10:18:43 PM PST 24
Peak memory 288448 kb
Host smart-694582d4-0106-4561-8e2e-87b67e31c6de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424269567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3424269567
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2880391267
Short name T571
Test name
Test status
Simulation time 151236953821 ps
CPU time 1480.48 seconds
Started Jan 21 09:32:37 PM PST 24
Finished Jan 21 09:57:35 PM PST 24
Peak memory 286140 kb
Host smart-e56ab03f-3a0b-4f0d-bc89-518ee77e633d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880391267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2880391267
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4118729463
Short name T44
Test name
Test status
Simulation time 31165681214 ps
CPU time 228.14 seconds
Started Jan 21 09:32:26 PM PST 24
Finished Jan 21 09:36:34 PM PST 24
Peak memory 250176 kb
Host smart-473e4a4b-542c-413d-a282-5876dfff0c8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118729463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4118729463
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2119168686
Short name T498
Test name
Test status
Simulation time 1294100992 ps
CPU time 11.22 seconds
Started Jan 21 10:50:11 PM PST 24
Finished Jan 21 10:50:25 PM PST 24
Peak memory 248084 kb
Host smart-f1ecd35f-b4de-4d0b-b594-fb6fc80cbded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
68686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2119168686
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3057491263
Short name T643
Test name
Test status
Simulation time 404464693 ps
CPU time 19.79 seconds
Started Jan 21 09:56:49 PM PST 24
Finished Jan 21 09:57:16 PM PST 24
Peak memory 246208 kb
Host smart-ad244719-672d-4f9c-b979-a79a8a2aea6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30574
91263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3057491263
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3137177544
Short name T429
Test name
Test status
Simulation time 876517595 ps
CPU time 60.88 seconds
Started Jan 21 09:32:27 PM PST 24
Finished Jan 21 09:33:47 PM PST 24
Peak memory 254728 kb
Host smart-9b55aa03-65f0-4575-840a-90b228b480e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31371
77544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3137177544
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1626360322
Short name T403
Test name
Test status
Simulation time 109083519 ps
CPU time 8.55 seconds
Started Jan 21 09:32:17 PM PST 24
Finished Jan 21 09:32:47 PM PST 24
Peak memory 248076 kb
Host smart-2d75bb4b-7731-403f-a952-edf6eead0f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16263
60322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1626360322
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.63904490
Short name T102
Test name
Test status
Simulation time 71257007542 ps
CPU time 2145.82 seconds
Started Jan 21 09:32:35 PM PST 24
Finished Jan 21 10:08:39 PM PST 24
Peak memory 288596 kb
Host smart-1e7a9a9e-1f45-4095-a3ed-aaf6f7c52f6f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63904490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_hand
ler_stress_all.63904490
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2489679950
Short name T697
Test name
Test status
Simulation time 9861810328 ps
CPU time 622.39 seconds
Started Jan 21 09:32:35 PM PST 24
Finished Jan 21 09:43:16 PM PST 24
Peak memory 267792 kb
Host smart-b8361dc0-5f7d-404d-9889-d2e36d11eaba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489679950 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2489679950
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2725658673
Short name T399
Test name
Test status
Simulation time 233022805683 ps
CPU time 1872.38 seconds
Started Jan 21 09:33:00 PM PST 24
Finished Jan 21 10:04:23 PM PST 24
Peak memory 282304 kb
Host smart-3537f7ce-cc76-470d-8de0-0e7480cce371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725658673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2725658673
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2944114450
Short name T742
Test name
Test status
Simulation time 230017833 ps
CPU time 9.3 seconds
Started Jan 21 09:32:46 PM PST 24
Finished Jan 21 09:33:10 PM PST 24
Peak memory 248132 kb
Host smart-f95c9be4-7309-4d68-bd7b-747f2fca90dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
14450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2944114450
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2825901257
Short name T550
Test name
Test status
Simulation time 262305617 ps
CPU time 22.64 seconds
Started Jan 21 09:32:45 PM PST 24
Finished Jan 21 09:33:22 PM PST 24
Peak memory 248156 kb
Host smart-042d17da-e977-4270-926e-8e49d9a1eaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
01257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2825901257
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3803203726
Short name T226
Test name
Test status
Simulation time 39643948841 ps
CPU time 2381.21 seconds
Started Jan 21 09:32:57 PM PST 24
Finished Jan 21 10:12:50 PM PST 24
Peak memory 272696 kb
Host smart-e44b98fb-15ac-43ad-ba9a-fc7fad69b582
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803203726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3803203726
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3801398388
Short name T53
Test name
Test status
Simulation time 49615817932 ps
CPU time 819.66 seconds
Started Jan 21 09:32:57 PM PST 24
Finished Jan 21 09:46:47 PM PST 24
Peak memory 264596 kb
Host smart-ce1edc8f-6dd7-4148-965d-ee4fd6ec6d56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801398388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3801398388
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.84933983
Short name T216
Test name
Test status
Simulation time 7012903160 ps
CPU time 303.24 seconds
Started Jan 21 09:32:56 PM PST 24
Finished Jan 21 09:38:11 PM PST 24
Peak memory 246688 kb
Host smart-a5a72265-84e2-463e-a69a-57cd056ef02e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84933983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.84933983
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.496432184
Short name T232
Test name
Test status
Simulation time 475088989 ps
CPU time 9.6 seconds
Started Jan 21 09:32:47 PM PST 24
Finished Jan 21 09:33:11 PM PST 24
Peak memory 248108 kb
Host smart-3add4544-1af2-49d4-87db-2767b9df96ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49643
2184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.496432184
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1226050616
Short name T466
Test name
Test status
Simulation time 930419029 ps
CPU time 62.2 seconds
Started Jan 21 09:32:45 PM PST 24
Finished Jan 21 09:34:02 PM PST 24
Peak memory 248096 kb
Host smart-9056ca21-6a72-4f57-a7bb-d1f470e4228a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12260
50616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1226050616
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3729189847
Short name T534
Test name
Test status
Simulation time 395306826 ps
CPU time 32.17 seconds
Started Jan 21 09:32:44 PM PST 24
Finished Jan 21 09:33:30 PM PST 24
Peak memory 256272 kb
Host smart-ffd3e57d-1d3f-44e3-a111-2f73f8474000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37291
89847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3729189847
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.879982577
Short name T484
Test name
Test status
Simulation time 775757574 ps
CPU time 20.11 seconds
Started Jan 21 09:55:09 PM PST 24
Finished Jan 21 09:55:36 PM PST 24
Peak memory 248152 kb
Host smart-0bea80bb-6942-44b0-8ba2-07a65ea8fd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87998
2577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.879982577
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1942980448
Short name T463
Test name
Test status
Simulation time 50601750272 ps
CPU time 3067.93 seconds
Started Jan 21 09:32:57 PM PST 24
Finished Jan 21 10:24:16 PM PST 24
Peak memory 288376 kb
Host smart-be0cc7ee-6275-4082-b418-2f2c506de0e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942980448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1942980448
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1969162713
Short name T370
Test name
Test status
Simulation time 13277520111 ps
CPU time 1039.33 seconds
Started Jan 21 09:33:08 PM PST 24
Finished Jan 21 09:50:34 PM PST 24
Peak memory 272792 kb
Host smart-f8e8faac-1311-4189-bbc2-ae2b0b9cc4fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969162713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1969162713
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2908885371
Short name T681
Test name
Test status
Simulation time 1666590798 ps
CPU time 109.17 seconds
Started Jan 21 09:33:07 PM PST 24
Finished Jan 21 09:35:04 PM PST 24
Peak memory 248076 kb
Host smart-338c690f-cfae-44aa-9b53-cf59427444f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29088
85371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2908885371
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1463877677
Short name T260
Test name
Test status
Simulation time 1227833639 ps
CPU time 67.72 seconds
Started Jan 21 09:33:09 PM PST 24
Finished Jan 21 09:34:23 PM PST 24
Peak memory 248148 kb
Host smart-2a7b074b-0107-4e8e-839c-2d8e52962514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14638
77677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1463877677
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2509979043
Short name T638
Test name
Test status
Simulation time 25670307499 ps
CPU time 1788.15 seconds
Started Jan 21 09:33:25 PM PST 24
Finished Jan 21 10:03:18 PM PST 24
Peak memory 271676 kb
Host smart-32fcb7c6-c92c-4475-b833-eb84f121922d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509979043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2509979043
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2544557786
Short name T315
Test name
Test status
Simulation time 35754915880 ps
CPU time 409.22 seconds
Started Jan 21 09:33:16 PM PST 24
Finished Jan 21 09:40:11 PM PST 24
Peak memory 246624 kb
Host smart-db6c54b2-5f0c-4f8c-ad8a-ff27fe80534a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544557786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2544557786
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1103679871
Short name T487
Test name
Test status
Simulation time 379726295 ps
CPU time 13.96 seconds
Started Jan 21 10:29:49 PM PST 24
Finished Jan 21 10:30:05 PM PST 24
Peak memory 248052 kb
Host smart-6e3e363a-6eed-4d0d-8440-15ce449439c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11036
79871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1103679871
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2391487125
Short name T674
Test name
Test status
Simulation time 1062171445 ps
CPU time 18.34 seconds
Started Jan 21 10:03:09 PM PST 24
Finished Jan 21 10:03:43 PM PST 24
Peak memory 250276 kb
Host smart-cc65a6e6-f06f-4533-a19e-732faf3ea0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23914
87125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2391487125
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3660891952
Short name T514
Test name
Test status
Simulation time 183529454 ps
CPU time 13.46 seconds
Started Jan 21 10:00:35 PM PST 24
Finished Jan 21 10:00:59 PM PST 24
Peak memory 252500 kb
Host smart-c5c96f37-719c-46cc-bdef-130e7f7b3fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36608
91952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3660891952
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3045046150
Short name T566
Test name
Test status
Simulation time 15841613624 ps
CPU time 60.18 seconds
Started Jan 21 09:32:58 PM PST 24
Finished Jan 21 09:34:09 PM PST 24
Peak memory 248200 kb
Host smart-6b11a9c2-413f-4578-87c0-50fd00ec3c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30450
46150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3045046150
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.788980361
Short name T255
Test name
Test status
Simulation time 180756218362 ps
CPU time 6278.54 seconds
Started Jan 21 09:33:31 PM PST 24
Finished Jan 21 11:18:12 PM PST 24
Peak memory 297476 kb
Host smart-7cdf75fc-5077-4cbd-9a94-1af9d6946671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788980361 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.788980361
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2335884716
Short name T432
Test name
Test status
Simulation time 103723148471 ps
CPU time 3328.12 seconds
Started Jan 21 09:33:39 PM PST 24
Finished Jan 21 10:29:09 PM PST 24
Peak memory 288536 kb
Host smart-668db3f7-aeb0-4986-bee5-6364a3e7b83a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335884716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2335884716
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3995379859
Short name T557
Test name
Test status
Simulation time 937711697 ps
CPU time 73.4 seconds
Started Jan 21 10:00:13 PM PST 24
Finished Jan 21 10:01:37 PM PST 24
Peak memory 250396 kb
Host smart-008c1fcd-71f0-465f-a2e7-3cd615834efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39953
79859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3995379859
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.744209957
Short name T619
Test name
Test status
Simulation time 409922819 ps
CPU time 24.68 seconds
Started Jan 21 09:33:37 PM PST 24
Finished Jan 21 09:34:03 PM PST 24
Peak memory 253400 kb
Host smart-1a047725-fb24-4660-a526-3a1d0e7812ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74420
9957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.744209957
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.93445108
Short name T395
Test name
Test status
Simulation time 193864144161 ps
CPU time 3120.46 seconds
Started Jan 21 09:33:44 PM PST 24
Finished Jan 21 10:25:47 PM PST 24
Peak memory 284964 kb
Host smart-356d9fd8-6e9f-4eb4-98e2-03bc2951bdb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93445108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.93445108
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2368066104
Short name T718
Test name
Test status
Simulation time 1391839524 ps
CPU time 60.04 seconds
Started Jan 21 10:01:57 PM PST 24
Finished Jan 21 10:03:10 PM PST 24
Peak memory 247696 kb
Host smart-81f8b467-9d63-4988-bbed-da075a46eeca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368066104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2368066104
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1361580071
Short name T401
Test name
Test status
Simulation time 2236140994 ps
CPU time 54.77 seconds
Started Jan 21 09:33:36 PM PST 24
Finished Jan 21 09:34:32 PM PST 24
Peak memory 248164 kb
Host smart-95d5b0d1-2630-4e9c-a82d-d2927d5ea3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
80071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1361580071
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3886986989
Short name T408
Test name
Test status
Simulation time 1331517376 ps
CPU time 31.75 seconds
Started Jan 21 09:33:38 PM PST 24
Finished Jan 21 09:34:11 PM PST 24
Peak memory 254480 kb
Host smart-68ea9c6e-37db-4576-ba28-a66e2cb689d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38869
86989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3886986989
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3104809316
Short name T404
Test name
Test status
Simulation time 240159260 ps
CPU time 18.13 seconds
Started Jan 21 09:33:38 PM PST 24
Finished Jan 21 09:33:57 PM PST 24
Peak memory 248052 kb
Host smart-88b099b2-9d80-4769-945d-5c884f1d5a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
09316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3104809316
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2634610081
Short name T402
Test name
Test status
Simulation time 1872456613 ps
CPU time 55.3 seconds
Started Jan 21 10:06:51 PM PST 24
Finished Jan 21 10:08:00 PM PST 24
Peak memory 256232 kb
Host smart-2345e83c-4229-4093-bb7d-c81357c6d812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26346
10081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2634610081
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3084709891
Short name T686
Test name
Test status
Simulation time 1997011525 ps
CPU time 60.5 seconds
Started Jan 21 09:33:44 PM PST 24
Finished Jan 21 09:34:47 PM PST 24
Peak memory 255152 kb
Host smart-40f8811a-39b9-44cb-b1d4-e85ce2595ba4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084709891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3084709891
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1819176948
Short name T243
Test name
Test status
Simulation time 176304936396 ps
CPU time 4513.52 seconds
Started Jan 21 09:33:46 PM PST 24
Finished Jan 21 10:49:02 PM PST 24
Peak memory 349324 kb
Host smart-437dffe3-1b13-4a1b-9dcd-19afce8edfc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819176948 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1819176948
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.960082987
Short name T73
Test name
Test status
Simulation time 159320357300 ps
CPU time 3033.59 seconds
Started Jan 21 09:34:00 PM PST 24
Finished Jan 21 10:24:51 PM PST 24
Peak memory 288412 kb
Host smart-a487dc8b-e498-4ae2-ad1a-d52397e6bf3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960082987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.960082987
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2817822914
Short name T436
Test name
Test status
Simulation time 22973116703 ps
CPU time 182.84 seconds
Started Jan 21 09:33:55 PM PST 24
Finished Jan 21 09:37:15 PM PST 24
Peak memory 249204 kb
Host smart-a689aff6-dd8d-44a0-b1c0-15c5ef83c038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28178
22914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2817822914
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2798904358
Short name T56
Test name
Test status
Simulation time 1593533723 ps
CPU time 51.67 seconds
Started Jan 21 09:33:54 PM PST 24
Finished Jan 21 09:35:01 PM PST 24
Peak memory 254528 kb
Host smart-5c62a9f4-6436-451f-bed2-9be90a9ab7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989
04358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2798904358
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2162188719
Short name T678
Test name
Test status
Simulation time 366183444236 ps
CPU time 1806.71 seconds
Started Jan 21 10:22:24 PM PST 24
Finished Jan 21 10:52:40 PM PST 24
Peak memory 272528 kb
Host smart-fa6c36e6-294f-4cb0-9c2d-a9217b78b49d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162188719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2162188719
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2353283695
Short name T91
Test name
Test status
Simulation time 138174865122 ps
CPU time 2380.85 seconds
Started Jan 21 09:34:02 PM PST 24
Finished Jan 21 10:14:00 PM PST 24
Peak memory 288024 kb
Host smart-f08a5457-ca84-45bd-a49b-82a613ebcc5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353283695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2353283695
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1649497138
Short name T57
Test name
Test status
Simulation time 160455435 ps
CPU time 10.92 seconds
Started Jan 21 09:33:56 PM PST 24
Finished Jan 21 09:34:26 PM PST 24
Peak memory 248132 kb
Host smart-1e7b7355-0754-4c1b-b2f2-f51fda827ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16494
97138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1649497138
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.938814780
Short name T617
Test name
Test status
Simulation time 797690516 ps
CPU time 47.87 seconds
Started Jan 21 09:33:56 PM PST 24
Finished Jan 21 09:35:03 PM PST 24
Peak memory 248132 kb
Host smart-81419e4f-ca99-45ce-bd08-20dd34d42bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93881
4780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.938814780
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2880580832
Short name T473
Test name
Test status
Simulation time 750081886 ps
CPU time 51.75 seconds
Started Jan 21 09:33:59 PM PST 24
Finished Jan 21 09:35:09 PM PST 24
Peak memory 248088 kb
Host smart-69a40225-0e44-4214-b1e9-2215f7dd48a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28805
80832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2880580832
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.151470295
Short name T563
Test name
Test status
Simulation time 767985114 ps
CPU time 32.6 seconds
Started Jan 21 09:33:53 PM PST 24
Finished Jan 21 09:34:33 PM PST 24
Peak memory 256308 kb
Host smart-21882da8-9923-486e-ab36-48722dc6321d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15147
0295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.151470295
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2398787304
Short name T35
Test name
Test status
Simulation time 23932416906 ps
CPU time 1357.41 seconds
Started Jan 21 09:33:59 PM PST 24
Finished Jan 21 09:56:54 PM PST 24
Peak memory 288844 kb
Host smart-655cd796-a6b8-435c-8d23-0f482a8bb66d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398787304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2398787304
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2649984353
Short name T599
Test name
Test status
Simulation time 70740798586 ps
CPU time 1926.31 seconds
Started Jan 21 10:15:09 PM PST 24
Finished Jan 21 10:47:33 PM PST 24
Peak memory 288552 kb
Host smart-767181ee-26c4-42d8-ac2c-b070b7f13675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649984353 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2649984353
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.881158233
Short name T200
Test name
Test status
Simulation time 44803183 ps
CPU time 2.21 seconds
Started Jan 21 09:23:16 PM PST 24
Finished Jan 21 09:23:30 PM PST 24
Peak memory 249436 kb
Host smart-cfb27263-5ce4-4a15-99a6-e404177e6dd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=881158233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.881158233
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2137384092
Short name T282
Test name
Test status
Simulation time 37436485989 ps
CPU time 1347.44 seconds
Started Jan 21 09:45:45 PM PST 24
Finished Jan 21 10:08:21 PM PST 24
Peak memory 272692 kb
Host smart-0d39c84a-b22e-41f4-93f8-016039bb2c5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137384092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2137384092
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1819615323
Short name T17
Test name
Test status
Simulation time 253447680 ps
CPU time 8.68 seconds
Started Jan 21 09:46:41 PM PST 24
Finished Jan 21 09:46:55 PM PST 24
Peak memory 239912 kb
Host smart-cb931e38-86c4-4af1-bbc7-aad8f72e58a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1819615323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1819615323
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3668249577
Short name T431
Test name
Test status
Simulation time 1960252011 ps
CPU time 36.94 seconds
Started Jan 21 09:57:50 PM PST 24
Finished Jan 21 09:58:34 PM PST 24
Peak memory 248112 kb
Host smart-44811404-2ea1-4927-9004-118a9bc08fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
49577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3668249577
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3855145797
Short name T562
Test name
Test status
Simulation time 1486527117 ps
CPU time 55.11 seconds
Started Jan 21 09:41:14 PM PST 24
Finished Jan 21 09:42:12 PM PST 24
Peak memory 250188 kb
Host smart-6d53bc6d-5148-416e-a019-8b8f5fe3e1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
45797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3855145797
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.628312173
Short name T326
Test name
Test status
Simulation time 77424348744 ps
CPU time 1899.31 seconds
Started Jan 21 09:23:06 PM PST 24
Finished Jan 21 09:54:47 PM PST 24
Peak memory 288464 kb
Host smart-a0062777-230d-4dbe-ace8-a34273e448da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628312173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.628312173
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.140271665
Short name T367
Test name
Test status
Simulation time 77196206909 ps
CPU time 685.64 seconds
Started Jan 21 09:38:31 PM PST 24
Finished Jan 21 09:50:02 PM PST 24
Peak memory 264584 kb
Host smart-c0fa9695-a9a7-4ded-87ee-9083b1aa0398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140271665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.140271665
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2462899371
Short name T313
Test name
Test status
Simulation time 13620873766 ps
CPU time 562.87 seconds
Started Jan 21 10:04:02 PM PST 24
Finished Jan 21 10:13:26 PM PST 24
Peak memory 248220 kb
Host smart-143f2dea-57ba-455e-af53-9ab174bd23eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462899371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2462899371
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1203776728
Short name T717
Test name
Test status
Simulation time 389516839 ps
CPU time 26.98 seconds
Started Jan 21 09:44:17 PM PST 24
Finished Jan 21 09:44:47 PM PST 24
Peak memory 248124 kb
Host smart-fca2e603-0dcd-4b1d-a91f-af4d6def94ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037
76728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1203776728
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2507306008
Short name T700
Test name
Test status
Simulation time 550721476 ps
CPU time 32.08 seconds
Started Jan 21 09:56:27 PM PST 24
Finished Jan 21 09:57:02 PM PST 24
Peak memory 248112 kb
Host smart-b5d58560-0131-4a9f-a8f9-96c8d73bbb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25073
06008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2507306008
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3597322796
Short name T12
Test name
Test status
Simulation time 6351902732 ps
CPU time 26.54 seconds
Started Jan 21 09:45:40 PM PST 24
Finished Jan 21 09:46:11 PM PST 24
Peak memory 263764 kb
Host smart-f5b92bf2-91bd-45f2-864d-725ab70b6b36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3597322796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3597322796
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.707654778
Short name T491
Test name
Test status
Simulation time 642694812 ps
CPU time 45.94 seconds
Started Jan 21 09:31:45 PM PST 24
Finished Jan 21 09:32:57 PM PST 24
Peak memory 254472 kb
Host smart-2efe78db-15c5-4563-bdfb-855eed94743e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70765
4778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.707654778
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2771254721
Short name T447
Test name
Test status
Simulation time 399126533 ps
CPU time 30.72 seconds
Started Jan 21 09:42:12 PM PST 24
Finished Jan 21 09:42:46 PM PST 24
Peak memory 248104 kb
Host smart-3d3bd075-66c9-4d4c-8e74-3b308d71886f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27712
54721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2771254721
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2628452616
Short name T79
Test name
Test status
Simulation time 11169539298 ps
CPU time 1142.65 seconds
Started Jan 21 09:23:16 PM PST 24
Finished Jan 21 09:42:31 PM PST 24
Peak memory 288608 kb
Host smart-3ec3f1c0-01c9-4b89-8ed4-b7dbfc84e352
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628452616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2628452616
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2788976714
Short name T430
Test name
Test status
Simulation time 86091194106 ps
CPU time 1801.92 seconds
Started Jan 21 09:23:22 PM PST 24
Finished Jan 21 09:53:32 PM PST 24
Peak memory 289168 kb
Host smart-bee76a9b-0708-4f84-93b3-fa9cfb35be18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788976714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2788976714
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3092949302
Short name T460
Test name
Test status
Simulation time 27031724739 ps
CPU time 1803.55 seconds
Started Jan 21 09:34:44 PM PST 24
Finished Jan 21 10:05:02 PM PST 24
Peak memory 270100 kb
Host smart-42e10c9c-96c3-4ad1-80a6-34baf366da0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092949302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3092949302
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2851075033
Short name T386
Test name
Test status
Simulation time 132324486 ps
CPU time 7.29 seconds
Started Jan 21 09:34:19 PM PST 24
Finished Jan 21 09:34:51 PM PST 24
Peak memory 248116 kb
Host smart-31496432-3ecb-4551-88fb-661bf52ed382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
75033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2851075033
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3573715903
Short name T224
Test name
Test status
Simulation time 297092414 ps
CPU time 22.71 seconds
Started Jan 21 09:34:19 PM PST 24
Finished Jan 21 09:35:06 PM PST 24
Peak memory 248152 kb
Host smart-b7055458-5e0c-4cea-8a95-a1d6278b178c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35737
15903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3573715903
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3114348243
Short name T227
Test name
Test status
Simulation time 73767702572 ps
CPU time 2355.92 seconds
Started Jan 21 09:34:50 PM PST 24
Finished Jan 21 10:14:17 PM PST 24
Peak memory 272200 kb
Host smart-1e5e6d39-cdce-4434-90cd-168f4b8ec92a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114348243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3114348243
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1837023279
Short name T376
Test name
Test status
Simulation time 32568679952 ps
CPU time 878.58 seconds
Started Jan 21 09:34:50 PM PST 24
Finished Jan 21 09:49:40 PM PST 24
Peak memory 266996 kb
Host smart-3d52b80d-50f9-4ede-bc90-7c91bf949443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837023279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1837023279
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4132154230
Short name T310
Test name
Test status
Simulation time 25194070847 ps
CPU time 145.61 seconds
Started Jan 21 09:34:53 PM PST 24
Finished Jan 21 09:37:29 PM PST 24
Peak memory 246692 kb
Host smart-4a9e392b-f62c-4f81-9320-1480519541bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132154230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4132154230
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.650172844
Short name T478
Test name
Test status
Simulation time 4652894992 ps
CPU time 71.34 seconds
Started Jan 21 09:34:12 PM PST 24
Finished Jan 21 09:35:48 PM PST 24
Peak memory 250240 kb
Host smart-32bbd86a-e0b3-4bd3-ad45-92f7d78a9830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65017
2844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.650172844
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.155198139
Short name T390
Test name
Test status
Simulation time 4162160930 ps
CPU time 82.35 seconds
Started Jan 21 09:34:10 PM PST 24
Finished Jan 21 09:35:57 PM PST 24
Peak memory 254776 kb
Host smart-1b366c0d-4187-4081-9ea6-492b59ac7e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15519
8139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.155198139
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3865706958
Short name T702
Test name
Test status
Simulation time 529400210 ps
CPU time 12.31 seconds
Started Jan 21 09:34:43 PM PST 24
Finished Jan 21 09:35:10 PM PST 24
Peak memory 246044 kb
Host smart-40dee958-738e-442e-9b6f-bed03a035175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
06958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3865706958
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3236585375
Short name T70
Test name
Test status
Simulation time 338641356 ps
CPU time 9.39 seconds
Started Jan 21 09:34:10 PM PST 24
Finished Jan 21 09:34:44 PM PST 24
Peak memory 248080 kb
Host smart-2629920b-bcec-409f-8976-4e88ded4d063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32365
85375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3236585375
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.444398886
Short name T657
Test name
Test status
Simulation time 83507382374 ps
CPU time 2657.37 seconds
Started Jan 21 09:34:51 PM PST 24
Finished Jan 21 10:19:19 PM PST 24
Peak memory 288284 kb
Host smart-0586218d-6a14-4855-9dc2-be4ff6b94b7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444398886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.444398886
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2397192054
Short name T106
Test name
Test status
Simulation time 36638539033 ps
CPU time 2365.53 seconds
Started Jan 21 09:34:50 PM PST 24
Finished Jan 21 10:14:27 PM PST 24
Peak memory 288512 kb
Host smart-7cf9ae49-8318-4af6-a3ad-07c0e845fe43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397192054 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2397192054
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2565161702
Short name T595
Test name
Test status
Simulation time 66230332637 ps
CPU time 1962.12 seconds
Started Jan 21 09:34:59 PM PST 24
Finished Jan 21 10:07:49 PM PST 24
Peak memory 272280 kb
Host smart-2bdb96bd-b557-4d17-8a48-8810c0159032
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565161702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2565161702
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.855881424
Short name T600
Test name
Test status
Simulation time 2631620198 ps
CPU time 110.89 seconds
Started Jan 21 09:35:00 PM PST 24
Finished Jan 21 09:36:58 PM PST 24
Peak memory 249420 kb
Host smart-d5e31a94-b5d9-44a6-9e62-4fc4951adf28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85588
1424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.855881424
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3997775330
Short name T734
Test name
Test status
Simulation time 497566053 ps
CPU time 29.71 seconds
Started Jan 21 09:34:50 PM PST 24
Finished Jan 21 09:35:31 PM PST 24
Peak memory 254320 kb
Host smart-0659f96a-1a55-40db-8d53-3b6e912976fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39977
75330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3997775330
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3780101642
Short name T48
Test name
Test status
Simulation time 53139944556 ps
CPU time 763.19 seconds
Started Jan 21 10:30:15 PM PST 24
Finished Jan 21 10:43:10 PM PST 24
Peak memory 264576 kb
Host smart-299fcbc1-cf89-4ba3-8f25-fe35f5c3ff43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780101642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3780101642
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.542476004
Short name T634
Test name
Test status
Simulation time 141552411 ps
CPU time 9.81 seconds
Started Jan 21 09:34:49 PM PST 24
Finished Jan 21 09:35:11 PM PST 24
Peak memory 248036 kb
Host smart-ade7d916-586e-4827-868a-c6745e8b347b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54247
6004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.542476004
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1686146271
Short name T374
Test name
Test status
Simulation time 102944029 ps
CPU time 11.8 seconds
Started Jan 21 09:34:52 PM PST 24
Finished Jan 21 09:35:14 PM PST 24
Peak memory 248116 kb
Host smart-c69dc11e-74b0-4c7d-a559-199391f8458f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16861
46271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1686146271
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2678134658
Short name T259
Test name
Test status
Simulation time 587074545 ps
CPU time 24.19 seconds
Started Jan 21 09:35:01 PM PST 24
Finished Jan 21 09:35:32 PM PST 24
Peak memory 248104 kb
Host smart-6bb323be-fc15-46b9-b405-82c180c2b38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26781
34658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2678134658
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1796004322
Short name T598
Test name
Test status
Simulation time 784232649 ps
CPU time 45.03 seconds
Started Jan 21 09:34:49 PM PST 24
Finished Jan 21 09:35:46 PM PST 24
Peak memory 248032 kb
Host smart-1afbb140-11ba-439c-a047-7ad253bafe1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
04322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1796004322
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2491975603
Short name T606
Test name
Test status
Simulation time 59928270502 ps
CPU time 1807 seconds
Started Jan 21 09:35:14 PM PST 24
Finished Jan 21 10:05:32 PM PST 24
Peak memory 288548 kb
Host smart-d9e01530-9389-4f22-8f59-d9a0e35aebca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491975603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2491975603
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3564568324
Short name T630
Test name
Test status
Simulation time 567111822705 ps
CPU time 4751.03 seconds
Started Jan 21 09:35:11 PM PST 24
Finished Jan 21 10:54:31 PM PST 24
Peak memory 317960 kb
Host smart-7e833a53-e9fe-4102-8a09-2b7d5b2ae6b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564568324 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3564568324
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3092173959
Short name T624
Test name
Test status
Simulation time 142186513446 ps
CPU time 882.42 seconds
Started Jan 21 09:36:44 PM PST 24
Finished Jan 21 09:51:38 PM PST 24
Peak memory 270728 kb
Host smart-9f40bc14-21c2-48c4-910d-2571e7a69a3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092173959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3092173959
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4094097045
Short name T371
Test name
Test status
Simulation time 7073685890 ps
CPU time 122.32 seconds
Started Jan 21 09:36:44 PM PST 24
Finished Jan 21 09:38:58 PM PST 24
Peak memory 247816 kb
Host smart-0e01ef74-5d6b-4ea2-86f0-0f08fb345f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40940
97045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4094097045
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3110041700
Short name T415
Test name
Test status
Simulation time 86096541 ps
CPU time 6.08 seconds
Started Jan 21 09:35:24 PM PST 24
Finished Jan 21 09:35:42 PM PST 24
Peak memory 238048 kb
Host smart-80bd6fa3-0fff-402b-b063-5c425e83a6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31100
41700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3110041700
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1042266554
Short name T676
Test name
Test status
Simulation time 60808778015 ps
CPU time 1379.25 seconds
Started Jan 21 09:35:37 PM PST 24
Finished Jan 21 09:58:46 PM PST 24
Peak memory 288760 kb
Host smart-054b1df9-9f9e-4186-9b6a-081c05bb3dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042266554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1042266554
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1514327234
Short name T222
Test name
Test status
Simulation time 18047272663 ps
CPU time 1271.98 seconds
Started Jan 21 09:35:38 PM PST 24
Finished Jan 21 09:56:59 PM PST 24
Peak memory 264600 kb
Host smart-680fc27f-35a7-40b7-868a-58b6bb28201d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514327234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1514327234
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2537025864
Short name T10
Test name
Test status
Simulation time 47943840361 ps
CPU time 490.78 seconds
Started Jan 21 09:35:38 PM PST 24
Finished Jan 21 09:43:58 PM PST 24
Peak memory 246968 kb
Host smart-dc439c68-e148-4207-84b7-380257d13aa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537025864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2537025864
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3771795216
Short name T446
Test name
Test status
Simulation time 338750060 ps
CPU time 12.39 seconds
Started Jan 21 09:35:15 PM PST 24
Finished Jan 21 09:35:39 PM PST 24
Peak memory 248128 kb
Host smart-708af4e9-7b1b-428c-bdc4-45e559b4281c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37717
95216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3771795216
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.732747511
Short name T470
Test name
Test status
Simulation time 1767199392 ps
CPU time 60.32 seconds
Started Jan 21 09:35:22 PM PST 24
Finished Jan 21 09:36:33 PM PST 24
Peak memory 250176 kb
Host smart-1e5cf799-4758-42fd-aa9f-df2ff6acc842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73274
7511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.732747511
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.848478949
Short name T555
Test name
Test status
Simulation time 4711543285 ps
CPU time 58.75 seconds
Started Jan 21 09:35:23 PM PST 24
Finished Jan 21 09:36:32 PM PST 24
Peak memory 253408 kb
Host smart-1d667a8e-45e7-4160-ad53-1ea61b87c44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84847
8949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.848478949
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.4131179420
Short name T427
Test name
Test status
Simulation time 126886996 ps
CPU time 4.71 seconds
Started Jan 21 09:35:12 PM PST 24
Finished Jan 21 09:35:27 PM PST 24
Peak memory 239856 kb
Host smart-d14e20b5-43fc-4306-9eb0-44f6a94b10d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41311
79420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.4131179420
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.768655706
Short name T109
Test name
Test status
Simulation time 181936478229 ps
CPU time 2853.4 seconds
Started Jan 21 09:35:37 PM PST 24
Finished Jan 21 10:23:21 PM PST 24
Peak memory 296872 kb
Host smart-976b5678-4e8e-42cf-b476-37211ee51e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768655706 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.768655706
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1538347073
Short name T644
Test name
Test status
Simulation time 201935598756 ps
CPU time 1811.48 seconds
Started Jan 21 09:35:57 PM PST 24
Finished Jan 21 10:06:15 PM PST 24
Peak memory 272072 kb
Host smart-ed732891-6afd-4fe5-834c-194701107111
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538347073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1538347073
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.710794878
Short name T740
Test name
Test status
Simulation time 36206660845 ps
CPU time 316.62 seconds
Started Jan 21 09:35:54 PM PST 24
Finished Jan 21 09:41:17 PM PST 24
Peak memory 250248 kb
Host smart-9379ff73-d0a6-483d-81ac-e314a64d2c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71079
4878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.710794878
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2645950563
Short name T389
Test name
Test status
Simulation time 1720606567 ps
CPU time 32.18 seconds
Started Jan 21 09:35:55 PM PST 24
Finished Jan 21 09:36:34 PM PST 24
Peak memory 248100 kb
Host smart-35ed0b3b-01f1-42bf-951e-6a8de2723798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26459
50563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2645950563
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2232357089
Short name T337
Test name
Test status
Simulation time 220137005391 ps
CPU time 2307.34 seconds
Started Jan 21 09:35:56 PM PST 24
Finished Jan 21 10:14:30 PM PST 24
Peak memory 272068 kb
Host smart-5e57543b-c419-43c5-91d3-31f058a952e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232357089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2232357089
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.19474785
Short name T647
Test name
Test status
Simulation time 13222704020 ps
CPU time 1396.79 seconds
Started Jan 21 09:36:03 PM PST 24
Finished Jan 21 09:59:24 PM PST 24
Peak memory 288196 kb
Host smart-a8f0b15f-cdac-4be0-82be-b300da3993a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19474785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.19474785
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1521532513
Short name T633
Test name
Test status
Simulation time 17459403285 ps
CPU time 181.9 seconds
Started Jan 21 09:35:54 PM PST 24
Finished Jan 21 09:39:02 PM PST 24
Peak memory 248188 kb
Host smart-9c39e70d-04c7-4d13-80aa-0aaddb172dfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521532513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1521532513
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.526043431
Short name T358
Test name
Test status
Simulation time 45484041 ps
CPU time 7.69 seconds
Started Jan 21 09:35:38 PM PST 24
Finished Jan 21 09:35:55 PM PST 24
Peak memory 248120 kb
Host smart-a2d0cb95-7cfc-43bc-b98a-65303505d88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52604
3431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.526043431
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4019857713
Short name T88
Test name
Test status
Simulation time 2108044886 ps
CPU time 14.22 seconds
Started Jan 21 09:37:07 PM PST 24
Finished Jan 21 09:37:33 PM PST 24
Peak memory 247480 kb
Host smart-cab66c2e-5d22-473b-b3c4-add562650800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
57713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4019857713
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2563662262
Short name T356
Test name
Test status
Simulation time 670747833 ps
CPU time 17.99 seconds
Started Jan 21 09:35:39 PM PST 24
Finished Jan 21 09:36:06 PM PST 24
Peak memory 248156 kb
Host smart-1b19437f-e225-47ae-9e66-45733f28ef26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25636
62262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2563662262
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3074144796
Short name T16
Test name
Test status
Simulation time 37295504591 ps
CPU time 1786.69 seconds
Started Jan 21 09:36:04 PM PST 24
Finished Jan 21 10:05:55 PM PST 24
Peak memory 299008 kb
Host smart-63440b2e-80da-43b2-af21-0e214e35571a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074144796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3074144796
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.195913152
Short name T108
Test name
Test status
Simulation time 109010339805 ps
CPU time 4731.2 seconds
Started Jan 21 09:36:03 PM PST 24
Finished Jan 21 10:54:59 PM PST 24
Peak memory 354124 kb
Host smart-1276256c-f936-4032-82c1-e071d1b97a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195913152 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.195913152
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3123742483
Short name T448
Test name
Test status
Simulation time 39907090046 ps
CPU time 2594.58 seconds
Started Jan 21 10:05:05 PM PST 24
Finished Jan 21 10:48:22 PM PST 24
Peak memory 288792 kb
Host smart-83ec7dbf-e574-45ba-94eb-036c2c26ac20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123742483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3123742483
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1664359767
Short name T233
Test name
Test status
Simulation time 25172289814 ps
CPU time 132.51 seconds
Started Jan 21 09:37:04 PM PST 24
Finished Jan 21 09:39:31 PM PST 24
Peak memory 247540 kb
Host smart-c048f708-fb74-4341-a253-d51ee3a7f270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16643
59767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1664359767
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.4126871356
Short name T637
Test name
Test status
Simulation time 205335153 ps
CPU time 8.29 seconds
Started Jan 21 09:36:13 PM PST 24
Finished Jan 21 09:36:25 PM PST 24
Peak memory 239956 kb
Host smart-084f7182-35b6-4fc7-8f94-5ca3ed09b96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41268
71356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.4126871356
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1506120385
Short name T575
Test name
Test status
Simulation time 38220671669 ps
CPU time 1326.74 seconds
Started Jan 21 09:36:15 PM PST 24
Finished Jan 21 09:58:25 PM PST 24
Peak memory 288412 kb
Host smart-5435cd04-b45e-4cad-b5f3-f34c7501b0d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506120385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1506120385
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3420955048
Short name T723
Test name
Test status
Simulation time 77387544018 ps
CPU time 2474.5 seconds
Started Jan 21 09:36:17 PM PST 24
Finished Jan 21 10:17:34 PM PST 24
Peak memory 288588 kb
Host smart-514ac15d-0a0b-4398-b72b-d1871b5e6dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420955048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3420955048
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3702256626
Short name T714
Test name
Test status
Simulation time 66590982628 ps
CPU time 257.48 seconds
Started Jan 21 09:36:17 PM PST 24
Finished Jan 21 09:40:37 PM PST 24
Peak memory 248200 kb
Host smart-7438ee44-eccb-443f-9f08-6b4fd7944b9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702256626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3702256626
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2386199951
Short name T626
Test name
Test status
Simulation time 392934107 ps
CPU time 23.89 seconds
Started Jan 21 09:36:02 PM PST 24
Finished Jan 21 09:36:30 PM PST 24
Peak memory 248100 kb
Host smart-937c573c-a2c3-4718-a452-8843359183c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
99951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2386199951
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2222657389
Short name T383
Test name
Test status
Simulation time 3351775321 ps
CPU time 48.61 seconds
Started Jan 21 09:36:10 PM PST 24
Finished Jan 21 09:37:01 PM PST 24
Peak memory 247292 kb
Host smart-abb23720-1e33-4b3b-8bad-97cafe0bef1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
57389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2222657389
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3611973652
Short name T551
Test name
Test status
Simulation time 941102163 ps
CPU time 64.62 seconds
Started Jan 21 09:36:11 PM PST 24
Finished Jan 21 09:37:19 PM PST 24
Peak memory 250444 kb
Host smart-ee59e6d5-64f5-4711-a696-23aae2b4d49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36119
73652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3611973652
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2693501888
Short name T506
Test name
Test status
Simulation time 1340927954 ps
CPU time 31.16 seconds
Started Jan 21 09:36:01 PM PST 24
Finished Jan 21 09:36:37 PM PST 24
Peak memory 248144 kb
Host smart-3c435c98-97ab-417a-89a6-9a59a9979f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26935
01888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2693501888
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.402320107
Short name T587
Test name
Test status
Simulation time 102011397850 ps
CPU time 1272.06 seconds
Started Jan 21 09:49:53 PM PST 24
Finished Jan 21 10:11:13 PM PST 24
Peak memory 280964 kb
Host smart-8a249bff-88d7-4161-b6b7-c6182c8f5465
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402320107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.402320107
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2625752106
Short name T191
Test name
Test status
Simulation time 452736322299 ps
CPU time 10089.1 seconds
Started Jan 21 10:05:17 PM PST 24
Finished Jan 22 12:53:29 AM PST 24
Peak memory 394320 kb
Host smart-dd212ed2-7b67-461e-944d-8e47a6fb9d63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625752106 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2625752106
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1409587668
Short name T272
Test name
Test status
Simulation time 40571987057 ps
CPU time 1616.56 seconds
Started Jan 21 09:36:56 PM PST 24
Finished Jan 21 10:04:10 PM PST 24
Peak memory 288184 kb
Host smart-aa7afecf-d5f9-4e3e-898e-569cb570f128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409587668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1409587668
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3541207281
Short name T49
Test name
Test status
Simulation time 1571686293 ps
CPU time 145.1 seconds
Started Jan 21 09:36:54 PM PST 24
Finished Jan 21 09:39:35 PM PST 24
Peak memory 247848 kb
Host smart-f026d176-967b-46d0-9628-71406ad25e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
07281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3541207281
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2511153579
Short name T266
Test name
Test status
Simulation time 770853213 ps
CPU time 47.69 seconds
Started Jan 21 09:36:56 PM PST 24
Finished Jan 21 09:38:00 PM PST 24
Peak memory 254252 kb
Host smart-0eb39355-8183-453c-b1b1-a33b4356068a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25111
53579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2511153579
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3600095722
Short name T297
Test name
Test status
Simulation time 7800276289 ps
CPU time 780.88 seconds
Started Jan 21 09:36:54 PM PST 24
Finished Jan 21 09:50:10 PM PST 24
Peak memory 272700 kb
Host smart-134efbcf-71be-463f-a120-a6b6c9375d5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600095722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3600095722
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1643727032
Short name T95
Test name
Test status
Simulation time 187816909272 ps
CPU time 2741.9 seconds
Started Jan 21 09:36:56 PM PST 24
Finished Jan 21 10:22:56 PM PST 24
Peak memory 288252 kb
Host smart-c10dd442-500d-46e6-9e6d-802722920d04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643727032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1643727032
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.958326562
Short name T357
Test name
Test status
Simulation time 600942086 ps
CPU time 15.83 seconds
Started Jan 21 09:36:40 PM PST 24
Finished Jan 21 09:37:08 PM PST 24
Peak memory 248132 kb
Host smart-8fd2480b-4b3b-40be-ae21-9f298aeffeed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95832
6562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.958326562
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2243469859
Short name T531
Test name
Test status
Simulation time 1396498786 ps
CPU time 15.24 seconds
Started Jan 21 09:36:40 PM PST 24
Finished Jan 21 09:37:07 PM PST 24
Peak memory 252748 kb
Host smart-fba4b45e-0bc9-4399-b0a5-3ffdb0702003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434
69859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2243469859
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2909807697
Short name T465
Test name
Test status
Simulation time 230344996 ps
CPU time 15.21 seconds
Started Jan 21 10:05:31 PM PST 24
Finished Jan 21 10:05:53 PM PST 24
Peak memory 248104 kb
Host smart-36207f9c-6f24-4b93-aa9c-8be47839ddf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29098
07697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2909807697
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2265522478
Short name T588
Test name
Test status
Simulation time 212084235 ps
CPU time 21.27 seconds
Started Jan 21 09:36:37 PM PST 24
Finished Jan 21 09:37:07 PM PST 24
Peak memory 248032 kb
Host smart-53b44ef9-691f-4a15-bb38-8278131a9ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22655
22478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2265522478
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3266443879
Short name T239
Test name
Test status
Simulation time 64374712825 ps
CPU time 3791.73 seconds
Started Jan 21 09:36:57 PM PST 24
Finished Jan 21 10:40:28 PM PST 24
Peak memory 299048 kb
Host smart-b54d80b3-e983-4d7e-b0cc-4629e6bc5aa0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266443879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3266443879
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1268257153
Short name T614
Test name
Test status
Simulation time 27732059217 ps
CPU time 780.53 seconds
Started Jan 21 09:37:15 PM PST 24
Finished Jan 21 09:50:24 PM PST 24
Peak memory 264776 kb
Host smart-cb5d916b-ef77-4c17-8dba-32eb9d769073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268257153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1268257153
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3550603440
Short name T435
Test name
Test status
Simulation time 8098080941 ps
CPU time 97.76 seconds
Started Jan 21 09:37:12 PM PST 24
Finished Jan 21 09:39:00 PM PST 24
Peak memory 249176 kb
Host smart-9a959fd3-eb26-4bc5-a092-c6cc8b37774c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35506
03440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3550603440
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1693666175
Short name T670
Test name
Test status
Simulation time 1255298271 ps
CPU time 40.9 seconds
Started Jan 21 09:45:56 PM PST 24
Finished Jan 21 09:46:52 PM PST 24
Peak memory 254268 kb
Host smart-b13444c1-0cb8-48ec-b4b8-2b7a116ca0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16936
66175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1693666175
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.434276461
Short name T96
Test name
Test status
Simulation time 90059815512 ps
CPU time 1123.23 seconds
Started Jan 21 09:37:20 PM PST 24
Finished Jan 21 09:56:10 PM PST 24
Peak memory 272760 kb
Host smart-a0808b3e-c417-44cb-90ba-4b77eb3ed3e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434276461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.434276461
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1577158693
Short name T406
Test name
Test status
Simulation time 71395863910 ps
CPU time 2196.87 seconds
Started Jan 21 09:37:20 PM PST 24
Finished Jan 21 10:14:04 PM PST 24
Peak memory 272212 kb
Host smart-88d86323-5c16-4b02-92ef-8a1843ec1ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577158693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1577158693
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.449999864
Short name T301
Test name
Test status
Simulation time 11603359289 ps
CPU time 130.04 seconds
Started Jan 21 09:37:19 PM PST 24
Finished Jan 21 09:39:36 PM PST 24
Peak memory 246588 kb
Host smart-71ee1baa-da42-4325-929f-1693ec32a948
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449999864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.449999864
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2206474629
Short name T396
Test name
Test status
Simulation time 4119831856 ps
CPU time 22.31 seconds
Started Jan 21 09:37:03 PM PST 24
Finished Jan 21 09:37:40 PM PST 24
Peak memory 248188 kb
Host smart-b9bdda6a-87a2-4e9c-b7d0-f9fb4abc8524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22064
74629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2206474629
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1696590454
Short name T526
Test name
Test status
Simulation time 431121977 ps
CPU time 8.26 seconds
Started Jan 21 09:37:02 PM PST 24
Finished Jan 21 09:37:26 PM PST 24
Peak memory 249268 kb
Host smart-464f609a-8fd8-4349-b443-3945511e36ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16965
90454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1696590454
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3288793155
Short name T246
Test name
Test status
Simulation time 1295473912 ps
CPU time 24.66 seconds
Started Jan 21 10:06:32 PM PST 24
Finished Jan 21 10:07:07 PM PST 24
Peak memory 248116 kb
Host smart-f1b5bab3-041e-4180-83e2-bcf147f57e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32887
93155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3288793155
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.130684339
Short name T235
Test name
Test status
Simulation time 314510691 ps
CPU time 17.7 seconds
Started Jan 21 09:36:54 PM PST 24
Finished Jan 21 09:37:28 PM PST 24
Peak memory 248148 kb
Host smart-89ca5049-a34e-4ee4-94ba-950ffbb11e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13068
4339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.130684339
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3810558941
Short name T270
Test name
Test status
Simulation time 13358505938 ps
CPU time 1535.27 seconds
Started Jan 21 09:37:21 PM PST 24
Finished Jan 21 10:03:03 PM PST 24
Peak memory 289056 kb
Host smart-c9f33cd5-71a0-4ff9-a2fe-c645b677062e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810558941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3810558941
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3200092861
Short name T632
Test name
Test status
Simulation time 100029019903 ps
CPU time 6410.38 seconds
Started Jan 21 09:37:20 PM PST 24
Finished Jan 21 11:24:18 PM PST 24
Peak memory 321032 kb
Host smart-ed346d6d-4e58-44f9-aa39-96fedb26184f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200092861 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3200092861
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1957328438
Short name T276
Test name
Test status
Simulation time 73082558142 ps
CPU time 1363.61 seconds
Started Jan 21 09:37:40 PM PST 24
Finished Jan 21 10:00:29 PM PST 24
Peak memory 272200 kb
Host smart-f771baf7-042a-4f45-a67d-abf4ac6d462e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957328438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1957328438
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1667045173
Short name T366
Test name
Test status
Simulation time 787976603 ps
CPU time 50.29 seconds
Started Jan 21 09:37:27 PM PST 24
Finished Jan 21 09:38:25 PM PST 24
Peak memory 247580 kb
Host smart-fc2b733e-aecd-4150-9954-4b95247b4f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16670
45173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1667045173
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2943822040
Short name T584
Test name
Test status
Simulation time 2782105053 ps
CPU time 79.12 seconds
Started Jan 21 10:14:45 PM PST 24
Finished Jan 21 10:16:15 PM PST 24
Peak memory 247316 kb
Host smart-f943b594-58ac-4ddf-b7ac-6ea9d9a23c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
22040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2943822040
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3502314422
Short name T295
Test name
Test status
Simulation time 16260689036 ps
CPU time 1102.84 seconds
Started Jan 21 09:37:51 PM PST 24
Finished Jan 21 09:56:17 PM PST 24
Peak memory 272560 kb
Host smart-1646da68-3a1f-410a-87e1-651411681d11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502314422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3502314422
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2777533122
Short name T710
Test name
Test status
Simulation time 74759148362 ps
CPU time 2336.67 seconds
Started Jan 21 09:37:49 PM PST 24
Finished Jan 21 10:16:49 PM PST 24
Peak memory 282328 kb
Host smart-638ce3ce-23fa-495a-a8d3-14d7a5e9978f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777533122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2777533122
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2243999579
Short name T75
Test name
Test status
Simulation time 73341106140 ps
CPU time 767.52 seconds
Started Jan 21 09:37:49 PM PST 24
Finished Jan 21 09:50:40 PM PST 24
Peak memory 248168 kb
Host smart-a477dd8b-098a-476f-8878-4f4353fc8473
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243999579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2243999579
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2275377038
Short name T229
Test name
Test status
Simulation time 682358289 ps
CPU time 44.24 seconds
Started Jan 21 09:37:20 PM PST 24
Finished Jan 21 09:38:11 PM PST 24
Peak memory 248108 kb
Host smart-8beb5980-56d0-466d-b7fe-65be57979cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22753
77038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2275377038
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.213348056
Short name T98
Test name
Test status
Simulation time 326653809 ps
CPU time 31.96 seconds
Started Jan 21 09:37:22 PM PST 24
Finished Jan 21 09:38:00 PM PST 24
Peak memory 247548 kb
Host smart-9ebb14dd-9ca8-4798-9085-d5ae4476b384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21334
8056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.213348056
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3859064551
Short name T352
Test name
Test status
Simulation time 61755476 ps
CPU time 4.51 seconds
Started Jan 21 11:52:33 PM PST 24
Finished Jan 21 11:52:39 PM PST 24
Peak memory 237896 kb
Host smart-3fc15138-a6f2-4aa3-99a5-4acd94ab0734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590
64551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3859064551
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.866524755
Short name T721
Test name
Test status
Simulation time 212908407 ps
CPU time 22.75 seconds
Started Jan 21 09:37:23 PM PST 24
Finished Jan 21 09:37:51 PM PST 24
Peak memory 250436 kb
Host smart-c39cc509-1ca5-4cb6-8e8b-fa256be5ab73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86652
4755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.866524755
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3653211973
Short name T699
Test name
Test status
Simulation time 63812189448 ps
CPU time 1427.35 seconds
Started Jan 21 09:37:49 PM PST 24
Finished Jan 21 10:01:40 PM PST 24
Peak memory 288600 kb
Host smart-a8b67b4a-0764-4690-a613-7ee0fc6bd806
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653211973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3653211973
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2323251657
Short name T570
Test name
Test status
Simulation time 43396919796 ps
CPU time 1066.54 seconds
Started Jan 21 09:38:07 PM PST 24
Finished Jan 21 09:56:06 PM PST 24
Peak memory 286708 kb
Host smart-94d7eb5b-009e-498e-8f23-f4d6f885fdb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323251657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2323251657
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3098780982
Short name T646
Test name
Test status
Simulation time 45694439269 ps
CPU time 301.09 seconds
Started Jan 21 09:38:07 PM PST 24
Finished Jan 21 09:43:20 PM PST 24
Peak memory 250452 kb
Host smart-265a2253-dd9d-4936-8924-739f16c4ebbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30987
80982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3098780982
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2851500279
Short name T564
Test name
Test status
Simulation time 810443326 ps
CPU time 18.03 seconds
Started Jan 21 09:38:08 PM PST 24
Finished Jan 21 09:38:38 PM PST 24
Peak memory 248140 kb
Host smart-9f10700b-f65e-4aea-b06b-1824470792da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28515
00279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2851500279
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3853503437
Short name T303
Test name
Test status
Simulation time 38481999248 ps
CPU time 2540.8 seconds
Started Jan 21 09:38:15 PM PST 24
Finished Jan 21 10:20:45 PM PST 24
Peak memory 288288 kb
Host smart-c471c1b8-4f49-4d42-b5cc-e465069376c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853503437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3853503437
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1963396975
Short name T732
Test name
Test status
Simulation time 36310011705 ps
CPU time 970.56 seconds
Started Jan 21 09:38:13 PM PST 24
Finished Jan 21 09:54:34 PM PST 24
Peak memory 272676 kb
Host smart-7037753c-2875-4e5b-a68a-ebfae50456bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963396975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1963396975
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3382508607
Short name T519
Test name
Test status
Simulation time 28727751884 ps
CPU time 571.19 seconds
Started Jan 21 09:38:13 PM PST 24
Finished Jan 21 09:47:55 PM PST 24
Peak memory 246724 kb
Host smart-b50c03e1-57eb-4b91-aecd-4b2d0a09fc34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382508607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3382508607
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3635130421
Short name T228
Test name
Test status
Simulation time 2903436395 ps
CPU time 44.46 seconds
Started Jan 21 09:38:04 PM PST 24
Finished Jan 21 09:38:55 PM PST 24
Peak memory 247800 kb
Host smart-54ba4400-a4a6-430f-ad08-1f94896b6040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36351
30421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3635130421
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3663446126
Short name T515
Test name
Test status
Simulation time 91327234 ps
CPU time 8.29 seconds
Started Jan 21 09:38:05 PM PST 24
Finished Jan 21 09:38:24 PM PST 24
Peak memory 248116 kb
Host smart-384db6c8-6627-4c9a-b906-506dcd3e8a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
46126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3663446126
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1126469777
Short name T59
Test name
Test status
Simulation time 1064707693 ps
CPU time 29.56 seconds
Started Jan 21 09:38:07 PM PST 24
Finished Jan 21 09:38:49 PM PST 24
Peak memory 247744 kb
Host smart-3ca1fe89-0fcc-47d4-a1f3-9ae2ab8223a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11264
69777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1126469777
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2354060917
Short name T469
Test name
Test status
Simulation time 1493787091 ps
CPU time 46.18 seconds
Started Jan 21 09:38:04 PM PST 24
Finished Jan 21 09:38:59 PM PST 24
Peak memory 255928 kb
Host smart-39717d54-aa7d-442a-9376-a053ae6cc5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23540
60917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2354060917
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.409158271
Short name T97
Test name
Test status
Simulation time 23136427816 ps
CPU time 1470.18 seconds
Started Jan 21 10:15:10 PM PST 24
Finished Jan 21 10:39:57 PM PST 24
Peak memory 272348 kb
Host smart-d097a661-697c-4bb8-95c4-25542c6e4e1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409158271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.409158271
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1294297387
Short name T422
Test name
Test status
Simulation time 23930142264 ps
CPU time 1735.86 seconds
Started Jan 21 09:38:14 PM PST 24
Finished Jan 21 10:07:20 PM PST 24
Peak memory 285860 kb
Host smart-a369e2d0-bf83-4a89-b4a6-618cc2cbe7aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294297387 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1294297387
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.633999298
Short name T698
Test name
Test status
Simulation time 37609943338 ps
CPU time 2276.79 seconds
Started Jan 21 09:38:44 PM PST 24
Finished Jan 21 10:16:43 PM PST 24
Peak memory 272332 kb
Host smart-abb14b5f-9ae5-4dc1-9ded-f3ee9fb15af1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633999298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.633999298
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3617885028
Short name T737
Test name
Test status
Simulation time 1052611662 ps
CPU time 19.91 seconds
Started Jan 21 09:57:29 PM PST 24
Finished Jan 21 09:57:51 PM PST 24
Peak memory 248108 kb
Host smart-e613de0b-ee0b-409f-89fd-1297b35ea8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
85028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3617885028
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3999367197
Short name T379
Test name
Test status
Simulation time 511748933 ps
CPU time 12.91 seconds
Started Jan 21 10:30:18 PM PST 24
Finished Jan 21 10:30:44 PM PST 24
Peak memory 248068 kb
Host smart-b395cf00-f68d-4474-8e1e-3a8f4623771c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39993
67197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3999367197
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1128338983
Short name T668
Test name
Test status
Simulation time 30404548555 ps
CPU time 798.33 seconds
Started Jan 21 10:07:09 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 271956 kb
Host smart-4b567027-c118-41b8-8439-1c491be59e27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128338983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1128338983
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3682564909
Short name T93
Test name
Test status
Simulation time 44547757588 ps
CPU time 1301.93 seconds
Started Jan 21 09:38:46 PM PST 24
Finished Jan 21 10:00:30 PM PST 24
Peak memory 288624 kb
Host smart-29d01791-b7e0-4d6a-ad8c-6b4861b137d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682564909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3682564909
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3497091007
Short name T545
Test name
Test status
Simulation time 55687991276 ps
CPU time 615.73 seconds
Started Jan 21 10:01:51 PM PST 24
Finished Jan 21 10:12:15 PM PST 24
Peak memory 246704 kb
Host smart-1c045d3c-a718-46a6-a9e5-0a37e52efd71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497091007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3497091007
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2495323539
Short name T724
Test name
Test status
Simulation time 2361073594 ps
CPU time 32.58 seconds
Started Jan 21 09:38:28 PM PST 24
Finished Jan 21 09:39:08 PM PST 24
Peak memory 247804 kb
Host smart-9f534b92-dc5f-43fb-b5f7-8e73011691bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24953
23539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2495323539
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3517272356
Short name T234
Test name
Test status
Simulation time 891155281 ps
CPU time 15.14 seconds
Started Jan 21 09:38:23 PM PST 24
Finished Jan 21 09:38:49 PM PST 24
Peak memory 248012 kb
Host smart-f55789ac-db03-4931-9c41-6798795937b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35172
72356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3517272356
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1436485760
Short name T522
Test name
Test status
Simulation time 242803287 ps
CPU time 31.7 seconds
Started Jan 21 09:57:19 PM PST 24
Finished Jan 21 09:57:53 PM PST 24
Peak memory 245972 kb
Host smart-c41a2737-9b7b-44bf-8a55-6e1f38382e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14364
85760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1436485760
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2189352520
Short name T438
Test name
Test status
Simulation time 2536322354 ps
CPU time 31.9 seconds
Started Jan 21 10:38:02 PM PST 24
Finished Jan 21 10:38:36 PM PST 24
Peak memory 248116 kb
Host smart-d435e264-5143-47a2-bb3e-b6845253d7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21893
52520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2189352520
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4285167180
Short name T561
Test name
Test status
Simulation time 15484578791 ps
CPU time 1347.87 seconds
Started Jan 21 09:38:46 PM PST 24
Finished Jan 21 10:01:15 PM PST 24
Peak memory 285628 kb
Host smart-294ab374-37a7-46c2-958a-065d68cb8779
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285167180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4285167180
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3914032768
Short name T663
Test name
Test status
Simulation time 176336501228 ps
CPU time 4034.7 seconds
Started Jan 21 09:38:52 PM PST 24
Finished Jan 21 10:46:08 PM PST 24
Peak memory 297392 kb
Host smart-117ef7de-9102-4f58-8bc2-8a9e34e5ba0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914032768 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3914032768
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.63119860
Short name T204
Test name
Test status
Simulation time 165581537 ps
CPU time 3.4 seconds
Started Jan 21 09:23:35 PM PST 24
Finished Jan 21 09:23:49 PM PST 24
Peak memory 248388 kb
Host smart-1a3a11dd-4431-4749-b813-31b07d8d3840
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=63119860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.63119860
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2514097555
Short name T691
Test name
Test status
Simulation time 37014716796 ps
CPU time 867.02 seconds
Started Jan 21 09:56:04 PM PST 24
Finished Jan 21 10:10:34 PM PST 24
Peak memory 264564 kb
Host smart-f8687834-f0d4-4920-81a4-a14460fbb936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514097555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2514097555
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.957676783
Short name T461
Test name
Test status
Simulation time 581557058 ps
CPU time 9.18 seconds
Started Jan 21 09:23:29 PM PST 24
Finished Jan 21 09:23:50 PM PST 24
Peak memory 239916 kb
Host smart-713ce6a1-3bb0-4109-b680-f493fa28162b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=957676783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.957676783
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3458949432
Short name T385
Test name
Test status
Simulation time 7426959304 ps
CPU time 120 seconds
Started Jan 21 09:23:21 PM PST 24
Finished Jan 21 09:25:30 PM PST 24
Peak memory 248156 kb
Host smart-79ef93eb-39cc-406b-84b7-89d48576bb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34589
49432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3458949432
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1099335794
Short name T456
Test name
Test status
Simulation time 146516284 ps
CPU time 6.52 seconds
Started Jan 21 09:23:22 PM PST 24
Finished Jan 21 09:23:37 PM PST 24
Peak memory 248388 kb
Host smart-f4c5fd47-1d84-472a-b1f9-22d523518707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10993
35794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1099335794
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.325063600
Short name T293
Test name
Test status
Simulation time 54484651052 ps
CPU time 1536.79 seconds
Started Jan 21 09:23:34 PM PST 24
Finished Jan 21 09:49:22 PM PST 24
Peak memory 288232 kb
Host smart-357ccb49-7dfb-45f5-bc6e-2177e9cd03cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325063600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.325063600
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3672832708
Short name T582
Test name
Test status
Simulation time 12937758563 ps
CPU time 1426.19 seconds
Started Jan 21 09:23:26 PM PST 24
Finished Jan 21 09:47:24 PM PST 24
Peak memory 288256 kb
Host smart-b0e83ecb-b4c4-437c-9843-5cf3b37709cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672832708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3672832708
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.813754097
Short name T306
Test name
Test status
Simulation time 17569053756 ps
CPU time 189.96 seconds
Started Jan 21 09:23:29 PM PST 24
Finished Jan 21 09:26:50 PM PST 24
Peak memory 245644 kb
Host smart-1dffdd28-e647-4757-aadf-8b21d1fc9b34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813754097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.813754097
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1814341043
Short name T520
Test name
Test status
Simulation time 303739468 ps
CPU time 17.8 seconds
Started Jan 21 09:23:15 PM PST 24
Finished Jan 21 09:23:45 PM PST 24
Peak memory 248068 kb
Host smart-bbe06263-0721-46d0-bbd4-baa8fdd185cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18143
41043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1814341043
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3244501524
Short name T409
Test name
Test status
Simulation time 1961908068 ps
CPU time 36.45 seconds
Started Jan 21 09:23:19 PM PST 24
Finished Jan 21 09:24:05 PM PST 24
Peak memory 246180 kb
Host smart-c77876d4-5c2f-44a6-af55-07ba14495a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32445
01524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3244501524
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3863775103
Short name T230
Test name
Test status
Simulation time 1447610151 ps
CPU time 51.59 seconds
Started Jan 21 09:23:32 PM PST 24
Finished Jan 21 09:24:34 PM PST 24
Peak memory 253632 kb
Host smart-6bae2262-6944-44c4-bec6-5bba2cf690b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38637
75103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3863775103
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4179806341
Short name T441
Test name
Test status
Simulation time 1285767150 ps
CPU time 20.57 seconds
Started Jan 21 09:23:17 PM PST 24
Finished Jan 21 09:23:49 PM PST 24
Peak memory 248136 kb
Host smart-80a88c62-867f-4c82-b372-a78c6b963767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41798
06341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4179806341
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4216733966
Short name T271
Test name
Test status
Simulation time 6680453837 ps
CPU time 361.3 seconds
Started Jan 21 09:23:29 PM PST 24
Finished Jan 21 09:29:42 PM PST 24
Peak memory 256300 kb
Host smart-7c682367-cdc8-4c1d-a78a-d28a45393976
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216733966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4216733966
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.856876423
Short name T261
Test name
Test status
Simulation time 54153107206 ps
CPU time 1513.83 seconds
Started Jan 21 09:23:30 PM PST 24
Finished Jan 21 09:48:56 PM PST 24
Peak memory 286824 kb
Host smart-7b161088-f004-4421-b75c-5f29e942c647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856876423 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.856876423
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1518385952
Short name T45
Test name
Test status
Simulation time 38063482 ps
CPU time 3.64 seconds
Started Jan 21 09:23:52 PM PST 24
Finished Jan 21 09:24:05 PM PST 24
Peak memory 248392 kb
Host smart-795f2f2b-49d8-4e06-ada0-45ba48f7959a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1518385952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1518385952
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2570502391
Short name T612
Test name
Test status
Simulation time 148705298338 ps
CPU time 2196.77 seconds
Started Jan 21 09:23:40 PM PST 24
Finished Jan 21 10:00:30 PM PST 24
Peak memory 284908 kb
Host smart-90a24755-aea9-4e61-8b7f-bb8174700529
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570502391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2570502391
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3989657968
Short name T362
Test name
Test status
Simulation time 1950427931 ps
CPU time 23.59 seconds
Started Jan 21 09:23:51 PM PST 24
Finished Jan 21 09:24:23 PM PST 24
Peak memory 239944 kb
Host smart-34101a7b-fcde-41cb-849e-186aedb809b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3989657968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3989657968
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4174061442
Short name T225
Test name
Test status
Simulation time 350239421 ps
CPU time 22.69 seconds
Started Jan 21 09:57:49 PM PST 24
Finished Jan 21 09:58:18 PM PST 24
Peak memory 250156 kb
Host smart-8caa8226-a272-4107-a940-f31e22967937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41740
61442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4174061442
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1405081257
Short name T731
Test name
Test status
Simulation time 486116081 ps
CPU time 8.24 seconds
Started Jan 21 09:23:39 PM PST 24
Finished Jan 21 09:24:00 PM PST 24
Peak memory 239152 kb
Host smart-42921cd6-b494-4d9d-94ab-306e0b6d625d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14050
81257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1405081257
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1247259508
Short name T722
Test name
Test status
Simulation time 20787371296 ps
CPU time 876.43 seconds
Started Jan 21 09:23:42 PM PST 24
Finished Jan 21 09:38:31 PM PST 24
Peak memory 272764 kb
Host smart-657e3f07-fa27-4fe4-a4c4-5cd4ceec4849
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247259508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1247259508
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3494090421
Short name T392
Test name
Test status
Simulation time 68953420324 ps
CPU time 2319.54 seconds
Started Jan 21 09:23:40 PM PST 24
Finished Jan 21 10:02:33 PM PST 24
Peak memory 288324 kb
Host smart-71ed44d4-acc3-4623-926b-015768200e8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494090421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3494090421
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.56288009
Short name T685
Test name
Test status
Simulation time 13577378060 ps
CPU time 152.3 seconds
Started Jan 21 09:23:45 PM PST 24
Finished Jan 21 09:26:28 PM PST 24
Peak memory 249208 kb
Host smart-1a5b4eee-8fe6-4bbf-9f55-d87e8193ce57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56288009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.56288009
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.76819315
Short name T375
Test name
Test status
Simulation time 1904782156 ps
CPU time 30.62 seconds
Started Jan 21 09:23:28 PM PST 24
Finished Jan 21 09:24:11 PM PST 24
Peak memory 248152 kb
Host smart-8f719bc2-b1e5-458e-913c-4bf74cb0fb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76819
315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.76819315
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3895719517
Short name T360
Test name
Test status
Simulation time 755317543 ps
CPU time 9.82 seconds
Started Jan 21 09:23:39 PM PST 24
Finished Jan 21 09:24:02 PM PST 24
Peak memory 248088 kb
Host smart-0e893b4c-a58d-47be-b63f-70aba0a35696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
19517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3895719517
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4083831322
Short name T50
Test name
Test status
Simulation time 779743370 ps
CPU time 50.19 seconds
Started Jan 21 09:23:38 PM PST 24
Finished Jan 21 09:24:42 PM PST 24
Peak memory 254180 kb
Host smart-97a756f2-2491-4cd2-a81e-50aa1e15d141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
31322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4083831322
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1471509902
Short name T583
Test name
Test status
Simulation time 1938208622 ps
CPU time 33.47 seconds
Started Jan 21 10:06:35 PM PST 24
Finished Jan 21 10:07:19 PM PST 24
Peak memory 248096 kb
Host smart-2cf844b9-5d1d-4027-91ed-baea48a1cacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14715
09902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1471509902
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2850430555
Short name T63
Test name
Test status
Simulation time 133273160973 ps
CPU time 2166.68 seconds
Started Jan 21 09:23:56 PM PST 24
Finished Jan 21 10:00:13 PM PST 24
Peak memory 288580 kb
Host smart-99626a8e-c6e1-4e2b-9ba7-6dd5aa3beec0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850430555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2850430555
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.422907731
Short name T214
Test name
Test status
Simulation time 44194612 ps
CPU time 3.85 seconds
Started Jan 21 09:23:53 PM PST 24
Finished Jan 21 09:24:06 PM PST 24
Peak memory 251720 kb
Host smart-19ed6ab1-f5e8-4cf9-b9ba-daee26112840
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=422907731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.422907731
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.327220058
Short name T689
Test name
Test status
Simulation time 38578037986 ps
CPU time 911.94 seconds
Started Jan 21 09:23:52 PM PST 24
Finished Jan 21 09:39:13 PM PST 24
Peak memory 272416 kb
Host smart-769f759f-f917-4cb7-8fa4-f3d2ee3a8cf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327220058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.327220058
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.844015914
Short name T538
Test name
Test status
Simulation time 268774687 ps
CPU time 15.32 seconds
Started Jan 21 09:23:52 PM PST 24
Finished Jan 21 09:24:16 PM PST 24
Peak memory 248148 kb
Host smart-e5d5918e-86f0-4c2d-aa74-a8fbdc8f0c54
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=844015914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.844015914
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2276829363
Short name T387
Test name
Test status
Simulation time 18175864856 ps
CPU time 90.43 seconds
Started Jan 21 09:23:54 PM PST 24
Finished Jan 21 09:25:34 PM PST 24
Peak memory 249136 kb
Host smart-5df64477-f563-489a-8c05-5da4a7877592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22768
29363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2276829363
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3411997358
Short name T377
Test name
Test status
Simulation time 162143790 ps
CPU time 6.29 seconds
Started Jan 21 09:23:51 PM PST 24
Finished Jan 21 09:24:06 PM PST 24
Peak memory 251280 kb
Host smart-c2e49859-741a-44c2-9d78-cd5233fed0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34119
97358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3411997358
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1081306677
Short name T628
Test name
Test status
Simulation time 22116137352 ps
CPU time 1327.77 seconds
Started Jan 21 09:23:53 PM PST 24
Finished Jan 21 09:46:10 PM PST 24
Peak memory 264556 kb
Host smart-4bf4e44f-67ed-41b1-809c-70a0f51e5826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081306677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1081306677
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2435654181
Short name T471
Test name
Test status
Simulation time 14621435054 ps
CPU time 156.04 seconds
Started Jan 21 09:23:56 PM PST 24
Finished Jan 21 09:26:42 PM PST 24
Peak memory 248488 kb
Host smart-046388ca-fb5f-4029-8deb-ce3d02199717
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435654181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2435654181
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2187297089
Short name T652
Test name
Test status
Simulation time 7031534803 ps
CPU time 52.4 seconds
Started Jan 21 09:23:53 PM PST 24
Finished Jan 21 09:24:56 PM PST 24
Peak memory 248152 kb
Host smart-e3da5198-c5f7-48f6-8eba-8ffb154671a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21872
97089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2187297089
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.345017461
Short name T677
Test name
Test status
Simulation time 1626348837 ps
CPU time 22.17 seconds
Started Jan 21 09:23:54 PM PST 24
Finished Jan 21 09:24:26 PM PST 24
Peak memory 252704 kb
Host smart-86a4e719-08ae-43dd-997b-2b991ed00ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34501
7461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.345017461
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3853399305
Short name T244
Test name
Test status
Simulation time 2021139611 ps
CPU time 15.67 seconds
Started Jan 21 09:23:52 PM PST 24
Finished Jan 21 09:24:17 PM PST 24
Peak memory 248320 kb
Host smart-ffc5d458-1466-4dbf-9bcd-53396313d61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38533
99305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3853399305
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.825661219
Short name T568
Test name
Test status
Simulation time 837359975 ps
CPU time 13.79 seconds
Started Jan 21 10:06:26 PM PST 24
Finished Jan 21 10:06:51 PM PST 24
Peak memory 250276 kb
Host smart-d065c239-ed41-422e-843d-b674bb787bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82566
1219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.825661219
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1940039323
Short name T190
Test name
Test status
Simulation time 17893853042 ps
CPU time 1745.08 seconds
Started Jan 21 09:23:53 PM PST 24
Finished Jan 21 09:53:08 PM PST 24
Peak memory 287560 kb
Host smart-50887edd-63c6-46b6-80f2-392d0bda25f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940039323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1940039323
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.620631498
Short name T52
Test name
Test status
Simulation time 31684277147 ps
CPU time 2485 seconds
Started Jan 21 09:24:01 PM PST 24
Finished Jan 21 10:05:39 PM PST 24
Peak memory 289108 kb
Host smart-c1eeb22c-9aa4-4995-bcd3-cc45c6746dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620631498 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.620631498
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2007654547
Short name T206
Test name
Test status
Simulation time 48846327 ps
CPU time 3.9 seconds
Started Jan 21 09:49:13 PM PST 24
Finished Jan 21 09:49:19 PM PST 24
Peak memory 248364 kb
Host smart-112648e1-7df3-43d6-81a0-2656b4d4b6c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2007654547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2007654547
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2503201528
Short name T641
Test name
Test status
Simulation time 131984381420 ps
CPU time 2264.56 seconds
Started Jan 21 09:23:59 PM PST 24
Finished Jan 21 10:01:55 PM PST 24
Peak memory 288184 kb
Host smart-1d9d6842-5594-4581-96f6-01e8c92bfb89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503201528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2503201528
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3706759182
Short name T597
Test name
Test status
Simulation time 1786453405 ps
CPU time 22.45 seconds
Started Jan 21 09:24:07 PM PST 24
Finished Jan 21 09:24:42 PM PST 24
Peak memory 239900 kb
Host smart-232bd9ca-a0cb-49f5-a878-eac26cbf0640
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3706759182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3706759182
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3341448348
Short name T707
Test name
Test status
Simulation time 4039052774 ps
CPU time 16.76 seconds
Started Jan 21 09:24:01 PM PST 24
Finished Jan 21 09:24:31 PM PST 24
Peak memory 250352 kb
Host smart-2b06e43b-8548-41a5-add2-21f07cac4e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33414
48348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3341448348
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1724484221
Short name T615
Test name
Test status
Simulation time 536055622 ps
CPU time 31.39 seconds
Started Jan 21 09:23:58 PM PST 24
Finished Jan 21 09:24:41 PM PST 24
Peak memory 250484 kb
Host smart-c3157b1d-ea95-493f-a086-ae3f7788f06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17244
84221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1724484221
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1547927124
Short name T78
Test name
Test status
Simulation time 29532258367 ps
CPU time 2073.26 seconds
Started Jan 21 09:44:21 PM PST 24
Finished Jan 21 10:18:57 PM PST 24
Peak memory 282144 kb
Host smart-1167f816-62cc-4e9b-acc0-9e37a947b584
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547927124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1547927124
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.811093830
Short name T289
Test name
Test status
Simulation time 7082938518 ps
CPU time 302.42 seconds
Started Jan 21 09:23:59 PM PST 24
Finished Jan 21 09:29:12 PM PST 24
Peak memory 249132 kb
Host smart-0a2bb8a5-5517-4884-a3a1-9b27dd29d4e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811093830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.811093830
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3295220059
Short name T410
Test name
Test status
Simulation time 327307304 ps
CPU time 4.7 seconds
Started Jan 21 09:24:00 PM PST 24
Finished Jan 21 09:24:17 PM PST 24
Peak memory 239896 kb
Host smart-a3ff244d-873d-4895-9bfa-455b31b47750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32952
20059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3295220059
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.700130125
Short name T490
Test name
Test status
Simulation time 2493509386 ps
CPU time 74.54 seconds
Started Jan 21 09:48:00 PM PST 24
Finished Jan 21 09:49:16 PM PST 24
Peak memory 248172 kb
Host smart-0783c148-0b6f-4c5a-b8ed-e29bf68c23b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70013
0125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.700130125
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3905859634
Short name T398
Test name
Test status
Simulation time 240928169 ps
CPU time 9.66 seconds
Started Jan 21 09:23:58 PM PST 24
Finished Jan 21 09:24:18 PM PST 24
Peak memory 248076 kb
Host smart-9948454c-d9f5-461a-8102-41b66be9b210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
59634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3905859634
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1512676229
Short name T713
Test name
Test status
Simulation time 579051358 ps
CPU time 11.99 seconds
Started Jan 21 09:24:00 PM PST 24
Finished Jan 21 09:24:25 PM PST 24
Peak memory 248112 kb
Host smart-5e1d12da-956d-400b-81f9-c833033e4939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15126
76229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1512676229
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.379610073
Short name T743
Test name
Test status
Simulation time 27194630902 ps
CPU time 2707.41 seconds
Started Jan 21 10:05:27 PM PST 24
Finished Jan 21 10:50:37 PM PST 24
Peak memory 321440 kb
Host smart-01f616fd-04f5-488d-a6e2-befc486ffa75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379610073 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.379610073
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1713378470
Short name T205
Test name
Test status
Simulation time 54755896 ps
CPU time 4.21 seconds
Started Jan 21 09:24:25 PM PST 24
Finished Jan 21 09:24:44 PM PST 24
Peak memory 248308 kb
Host smart-d692a4c2-5046-4576-88b7-1758bd08835e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1713378470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1713378470
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2715625385
Short name T720
Test name
Test status
Simulation time 26047595583 ps
CPU time 1596.12 seconds
Started Jan 21 09:24:16 PM PST 24
Finished Jan 21 09:51:09 PM PST 24
Peak memory 281584 kb
Host smart-3e56d26f-7da4-4514-829a-6e7ae8e860c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715625385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2715625385
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.85864958
Short name T656
Test name
Test status
Simulation time 1469340734 ps
CPU time 34.88 seconds
Started Jan 21 09:24:26 PM PST 24
Finished Jan 21 09:25:15 PM PST 24
Peak memory 239944 kb
Host smart-28ce8dab-1b1a-46c3-9adf-2f1beb13cba4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=85864958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.85864958
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.475191222
Short name T629
Test name
Test status
Simulation time 960343373 ps
CPU time 50.04 seconds
Started Jan 21 09:24:15 PM PST 24
Finished Jan 21 09:25:21 PM PST 24
Peak memory 248116 kb
Host smart-1fa66a79-881f-49b3-87da-be9e98fbbd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47519
1222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.475191222
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.680323994
Short name T485
Test name
Test status
Simulation time 511187485 ps
CPU time 17.51 seconds
Started Jan 21 09:24:16 PM PST 24
Finished Jan 21 09:24:50 PM PST 24
Peak memory 250512 kb
Host smart-5f446be3-64c6-4a2d-8fa7-e214f801f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68032
3994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.680323994
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3645494288
Short name T336
Test name
Test status
Simulation time 105304311268 ps
CPU time 1702.78 seconds
Started Jan 21 09:53:45 PM PST 24
Finished Jan 21 10:22:09 PM PST 24
Peak memory 272124 kb
Host smart-2aba637f-96e1-44a7-bfa9-fc9aa511d938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645494288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3645494288
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.74608137
Short name T279
Test name
Test status
Simulation time 77381683926 ps
CPU time 1648.37 seconds
Started Jan 21 09:24:25 PM PST 24
Finished Jan 21 09:52:09 PM PST 24
Peak memory 289036 kb
Host smart-3022b592-9f74-46b1-96e0-ef49a12462ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74608137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.74608137
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2964101008
Short name T701
Test name
Test status
Simulation time 2893949248 ps
CPU time 41.42 seconds
Started Jan 21 09:24:19 PM PST 24
Finished Jan 21 09:25:18 PM PST 24
Peak memory 248136 kb
Host smart-c719e78f-2401-4563-a651-759ce99367da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29641
01008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2964101008
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.148030301
Short name T496
Test name
Test status
Simulation time 513188960 ps
CPU time 32.12 seconds
Started Jan 21 09:24:18 PM PST 24
Finished Jan 21 09:25:08 PM PST 24
Peak memory 248132 kb
Host smart-9c69589a-999d-4b8c-9131-5b1dbcedf203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14803
0301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.148030301
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.4291766072
Short name T187
Test name
Test status
Simulation time 426242775 ps
CPU time 19.1 seconds
Started Jan 21 09:24:16 PM PST 24
Finished Jan 21 09:24:53 PM PST 24
Peak memory 246424 kb
Host smart-3190de4f-dde9-4a4d-b08d-ac11bb991e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
66072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.4291766072
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3579027287
Short name T735
Test name
Test status
Simulation time 3327104825 ps
CPU time 25.02 seconds
Started Jan 21 09:48:04 PM PST 24
Finished Jan 21 09:48:31 PM PST 24
Peak memory 248120 kb
Host smart-fa555e0d-f498-4062-88bf-6d46d10f7ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35790
27287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3579027287
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1790079551
Short name T18
Test name
Test status
Simulation time 51862824202 ps
CPU time 1343.12 seconds
Started Jan 21 09:24:25 PM PST 24
Finished Jan 21 09:47:03 PM PST 24
Peak memory 288876 kb
Host smart-48d9d315-be60-40c6-bb63-944b9677d4c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790079551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1790079551
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1276703490
Short name T113
Test name
Test status
Simulation time 202042707416 ps
CPU time 5636.01 seconds
Started Jan 21 09:24:32 PM PST 24
Finished Jan 21 10:58:39 PM PST 24
Peak memory 337088 kb
Host smart-b0035364-73b4-46ef-a632-82475fad86d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276703490 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1276703490
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%