Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	68274	1			T4	3130		T6	2041		T20	12
class_i[0x1]	61047	1			T18	4		T20	5		T24	4922
class_i[0x2]	53816	1			T38	9		T18	1		T31	274
class_i[0x3]	55789	1			T18	1		T20	12		T39	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60487	1			T4	744		T6	508		T38	1
alert[0x1]	59091	1			T4	769		T6	478		T38	2
alert[0x2]	58893	1			T4	741		T6	512		T38	3
alert[0x3]	60455	1			T4	876		T6	543		T38	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

238668

1

T4

3130

T6

2041

T18

1

esc_ping_fail

258

1

T38

9

T18

5

T39

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60407	1			T4	744		T6	508		T20	5
esc_integrity_fail	alert[0x1]	59032	1			T4	769		T6	478		T18	1
esc_integrity_fail	alert[0x2]	58831	1			T4	741		T6	512		T20	2
esc_integrity_fail	alert[0x3]	60398	1			T4	876		T6	543		T20	13
esc_ping_fail	alert[0x0]	80	1			T38	1		T18	2		T39	1
esc_ping_fail	alert[0x1]	59	1			T38	2		T18	1		T39	3
esc_ping_fail	alert[0x2]	62	1			T38	3		T18	1		T39	2
esc_ping_fail	alert[0x3]	57	1			T38	3		T18	1		T39	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	68210	1			T4	3130		T6	2041		T20	12
esc_integrity_fail	class_i[0x1]	60988	1			T18	1		T20	5		T24	4922
esc_integrity_fail	class_i[0x2]	53737	1			T31	274		T21	7		T23	7
esc_integrity_fail	class_i[0x3]	55733	1			T20	12		T21	1		T23	7
esc_ping_fail	class_i[0x0]	64	1			T39	1		T302	7		T317	1
esc_ping_fail	class_i[0x1]	59	1			T18	3		T317	7		T313	2
esc_ping_fail	class_i[0x2]	79	1			T38	9		T18	1		T39	5
esc_ping_fail	class_i[0x3]	56	1			T18	1		T39	1		T306	7