Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.53	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	5	39	88.64

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	5	39	88.64	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	150	1			T4	2		T6	2		T18	1
index[0x1]	190	1			T2	1		T6	1		T31	1
index[0x2]	172	1			T6	1		T35	1		T72	1
index[0x3]	192	1			T2	1		T4	1		T6	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	211	1			T2	1		T4	1		T7	1
lens_less_than_1000[1]	149	1			T4	1		T6	2		T27	2
lens_less_than_1000[2]	82	1			T21	1		T58	1		T59	1
lens_less_than_1000[3]	100	1			T6	2		T35	1		T21	2
lens_less_than_1000[4]	64	1			T6	1		T102	1		T58	1
lens_less_than_1000[5]	30	1			T2	1		T18	1		T72	1
lens_less_than_1000[6]	33	1			T6	1		T19	1		T27	1
lens_less_than_1000[7]	16	1			T21	2		T119	1		T88	1
lens_less_than_1000[8]	6	1			T133	1		T103	1		T125	1
lens_less_than_1000[9]	2	1			T63	1		T256	1		-	-
len_2	11	1			T4	1		T31	2		T257	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	5	39	88.64	5

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8] , lens_less_than_1000[9]]	--	--	2
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[lens_less_than_1000[8] , lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	54	1			T4	1		T25	3		T258	1
index[0x0]	lens_less_than_1000[1]	33	1			T4	1		T27	1		T59	1
index[0x0]	lens_less_than_1000[2]	18	1			T76	1		T43	1		T111	1
index[0x0]	lens_less_than_1000[3]	15	1			T6	2		T59	1		T66	1
index[0x0]	lens_less_than_1000[4]	12	1			T104	2		T54	1		T259	1
index[0x0]	lens_less_than_1000[5]	4	1			T18	1		T72	1		T260	1
index[0x0]	lens_less_than_1000[6]	5	1			T67	1		T261	2		T262	1
index[0x0]	lens_less_than_1000[7]	7	1			T119	1		T44	1		T105	1
index[0x0]	len_2	2	1			T257	1		T129	1		-	-
index[0x1]	lens_less_than_1000[0]	53	1			T2	1		T208	1		T21	1
index[0x1]	lens_less_than_1000[1]	38	1			T6	1		T27	1		T59	1
index[0x1]	lens_less_than_1000[2]	19	1			T58	1		T263	1		T264	1
index[0x1]	lens_less_than_1000[3]	31	1			T35	1		T41	1		T85	1
index[0x1]	lens_less_than_1000[4]	22	1			T104	1		T256	1		T93	1
index[0x1]	lens_less_than_1000[5]	9	1			T59	1		T42	2		T265	1
index[0x1]	lens_less_than_1000[6]	8	1			T45	1		T266	1		T103	1
index[0x1]	lens_less_than_1000[7]	2	1			T104	1		T107	1		-	-
index[0x1]	lens_less_than_1000[8]	5	1			T133	1		T125	1		T267	1
index[0x1]	len_2	3	1			T31	1		T197	1		T268	1
index[0x2]	lens_less_than_1000[0]	50	1			T35	1		T72	1		T23	4
index[0x2]	lens_less_than_1000[1]	31	1			T21	1		T102	1		T59	1
index[0x2]	lens_less_than_1000[2]	19	1			T21	1		T75	1		T266	1
index[0x2]	lens_less_than_1000[3]	30	1			T21	2		T44	1		T269	1
index[0x2]	lens_less_than_1000[4]	12	1			T45	1		T114	1		T53	1
index[0x2]	lens_less_than_1000[5]	8	1			T45	1		T104	1		T270	1
index[0x2]	lens_less_than_1000[6]	17	1			T6	1		T26	2		T88	1
index[0x2]	lens_less_than_1000[7]	4	1			T21	2		T88	1		T271	1
index[0x2]	len_2	1	1			T272	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	54	1			T7	1		T59	1		T117	1
index[0x3]	lens_less_than_1000[1]	47	1			T6	1		T98	1		T273	1
index[0x3]	lens_less_than_1000[2]	26	1			T59	1		T134	1		T265	1
index[0x3]	lens_less_than_1000[3]	24	1			T60	1		T85	1		T274	1
index[0x3]	lens_less_than_1000[4]	18	1			T6	1		T102	1		T58	1
index[0x3]	lens_less_than_1000[5]	9	1			T2	1		T91	1		T106	1
index[0x3]	lens_less_than_1000[6]	3	1			T19	1		T27	1		T114	1
index[0x3]	lens_less_than_1000[7]	3	1			T237	1		T50	1		T275	1
index[0x3]	lens_less_than_1000[8]	1	1			T103	1		-	-		-	-
index[0x3]	lens_less_than_1000[9]	2	1			T63	1		T256	1		-	-
index[0x3]	len_2	5	1			T4	1		T31	1		T197	1