Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	44	1			T21	2		T58	1		T17	3
class_index[0x1]	47	1			T6	1		T21	1		T17	1
class_index[0x2]	41	1			T6	2		T7	1		T17	1
class_index[0x3]	41	1			T8	1		T72	1		T77	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	60	1			T6	2		T7	1		T77	1
intr_timeout_cnt[1]	46	1			T6	1		T21	2		T59	1
intr_timeout_cnt[2]	15	1			T21	1		T88	1		T89	2
intr_timeout_cnt[3]	11	1			T8	1		T91	1		T197	1
intr_timeout_cnt[4]	4	1			T21	1		T276	1		T277	1
intr_timeout_cnt[5]	17	1			T72	1		T17	3		T95	1
intr_timeout_cnt[6]	6	1			T58	1		T106	1		T278	1
intr_timeout_cnt[7]	4	1			T92	1		T279	1		T262	1
intr_timeout_cnt[8]	3	1			T17	1		T53	1		T280	1
intr_timeout_cnt[9]	7	1			T58	2		T17	1		T259	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	13	1			T87	1		T281	1		T282	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T21	1		T84	1		T85	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T21	1		T88	1		T89	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T278	1		T283	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	1	1			T276	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	7	1			T17	3		T279	2		T284	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T58	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T280	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T259	1		T285	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	14	1			T6	1		T88	1		T90	2
class_index[0x1]	intr_timeout_cnt[1]	18	1			T21	1		T87	1		T44	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T89	1		T286	1		T287	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T91	1		T259	1		T280	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T277	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	4	1			T280	1		T262	1		T288	2
class_index[0x1]	intr_timeout_cnt[6]	1	1			T106	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T279	1		T262	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T17	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	19	1			T6	1		T7	1		T44	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T6	1		T84	2		T94	1
class_index[0x2]	intr_timeout_cnt[2]	1	1			T279	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[3]	2	1			T198	1		T289	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T53	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T278	1		T280	1		T262	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T92	1		T290	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T17	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T291	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	14	1			T77	1		T43	1		T28	1
class_index[0x3]	intr_timeout_cnt[1]	6	1			T59	1		T44	1		T292	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T281	2		T293	1		T294	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T8	1		T197	1		T259	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T21	1		T262	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	5	1			T72	1		T95	1		T287	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T289	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T53	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T58	2		T278	1		-	-