Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341590	1			T1	9		T2	1448		T3	19
all_values[1]	341590	1			T1	9		T2	1448		T3	19
all_values[2]	341590	1			T1	9		T2	1448		T3	19
all_values[3]	341590	1			T1	9		T2	1448		T3	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

680749

1

T1

31

T2

2985

T3

45

auto[1]

685611

1

T1

5

T2

2807

T3

31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

823395

1

T1

32

T2

4995

T3

40

auto[1]

542965

1

T1

4

T2

797

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97750	1			T1	5		T2	362		T3	5
all_values[0]	auto[0]	auto[1]	72137	1			T1	4		T2	360		T3	4
all_values[0]	auto[1]	auto[0]	99510	1			T2	364		T3	5		T4	282
all_values[0]	auto[1]	auto[1]	72193	1			T2	362		T3	5		T4	282
all_values[1]	auto[0]	auto[0]	104502	1			T1	7		T2	757		T3	4
all_values[1]	auto[0]	auto[1]	65994	1			T2	13		T3	4		T4	289
all_values[1]	auto[1]	auto[0]	105389	1			T1	2		T2	666		T3	6
all_values[1]	auto[1]	auto[1]	65705	1			T2	12		T3	5		T4	286
all_values[2]	auto[0]	auto[0]	102528	1			T1	6		T2	714		T3	7
all_values[2]	auto[0]	auto[1]	67869	1			T2	14		T3	6		T4	314
all_values[2]	auto[1]	auto[0]	103679	1			T1	3		T2	709		T3	3
all_values[2]	auto[1]	auto[1]	67514	1			T2	11		T3	3		T4	259
all_values[3]	auto[0]	auto[0]	104469	1			T1	9		T2	749		T3	8
all_values[3]	auto[0]	auto[1]	65500	1			T2	16		T3	7		T4	289
all_values[3]	auto[1]	auto[0]	105568	1			T2	674		T3	2		T4	282
all_values[3]	auto[1]	auto[1]	66053	1			T2	9		T3	2		T4	258