Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	341590	1			T1	9		T2	1448		T3	19
all_pins[1]	341590	1			T1	9		T2	1448		T3	19
all_pins[2]	341590	1			T1	9		T2	1448		T3	19
all_pins[3]	341590	1			T1	9		T2	1448		T3	19

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1094895	1			T1	36		T2	5398		T3	61
values[0x1]	271465	1			T2	394		T3	15		T4	1085
transitions[0x0=>0x1]	181032	1			T2	376		T3	13		T4	691
transitions[0x1=>0x0]	181263	1			T2	376		T3	13		T4	691

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	269397	1			T1	9		T2	1086		T3	14
all_pins[0]	values[0x1]	72193	1			T2	362		T3	5		T4	282
all_pins[0]	transitions[0x0=>0x1]	71570	1			T2	362		T3	5		T4	282
all_pins[0]	transitions[0x1=>0x0]	65661	1			T2	9		T3	2		T4	258
all_pins[1]	values[0x0]	275885	1			T1	9		T2	1436		T3	14
all_pins[1]	values[0x1]	65705	1			T2	12		T3	5		T4	286
all_pins[1]	transitions[0x0=>0x1]	35597	1			T2	5		T3	3		T4	137
all_pins[1]	transitions[0x1=>0x0]	42085	1			T2	355		T3	3		T4	133
all_pins[2]	values[0x0]	274076	1			T1	9		T2	1437		T3	16
all_pins[2]	values[0x1]	67514	1			T2	11		T3	3		T4	259
all_pins[2]	transitions[0x0=>0x1]	37910	1			T2	4		T3	3		T4	126
all_pins[2]	transitions[0x1=>0x0]	36101	1			T2	5		T3	5		T4	153
all_pins[3]	values[0x0]	275537	1			T1	9		T2	1439		T3	17
all_pins[3]	values[0x1]	66053	1			T2	9		T3	2		T4	258
all_pins[3]	transitions[0x0=>0x1]	35955	1			T2	5		T3	2		T4	146
all_pins[3]	transitions[0x1=>0x0]	37416	1			T2	7		T3	3		T4	147