Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	299	1			T176	4		T177	4		T178	4
all_values[1]	299	1			T176	4		T177	4		T178	4
all_values[2]	299	1			T176	4		T177	4		T178	4
all_values[3]	299	1			T176	4		T177	4		T178	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T176

11

T177

10

T178

11

auto[1]

551

1

T176

5

T177

6

T178

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

497

1

T176

8

T177

2

T178

11

auto[1]

699

1

T176

8

T177

14

T178

5

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

741

1

T176

11

T177

6

T178

12

auto[1]

455

1

T176

5

T177

10

T178

4

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

69

1

T176

1

T178

2

T252

1

all_values[0]

auto[0]

auto[0]

auto[1]

37

1

T176

1

T177

1

T252

1

all_values[0]

auto[0]

auto[1]

auto[0]

54

1

T178

1

T253

1

T352

2

all_values[0]

auto[0]

auto[1]

auto[1]

25

1

T353

2

T354

1

T355

2

all_values[0]

auto[1]

auto[0]

auto[1]

61

1

T176

2

T177

2

T178

1

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T177

1

T253

1

T254

5

all_values[1]

auto[0]

auto[0]

auto[0]

62

1

T176

1

T177

1

T178

2

all_values[1]

auto[0]

auto[0]

auto[1]

23

1

T252

1

T353

1

T356

2

all_values[1]

auto[0]

auto[1]

auto[0]

67

1

T177

1

T178

1

T252

1

all_values[1]

auto[0]

auto[1]

auto[1]

38

1

T176

2

T252

1

T254

4

all_values[1]

auto[1]

auto[0]

auto[1]

59

1

T177

1

T252

1

T253

1

all_values[1]

auto[1]

auto[1]

auto[1]

50

1

T176

1

T177

1

T178

1

all_values[2]

auto[0]

auto[0]

auto[0]

66

1

T176

2

T178

1

T252

4

all_values[2]

auto[0]

auto[0]

auto[1]

28

1

T178

1

T352

2

T357

2

all_values[2]

auto[0]

auto[1]

auto[0]

67

1

T176

1

T178

1

T252

2

all_values[2]

auto[0]

auto[1]

auto[1]

26

1

T177

1

T253

1

T357

1

all_values[2]

auto[1]

auto[0]

auto[1]

62

1

T177

2

T178

1

T252

1

all_values[2]

auto[1]

auto[1]

auto[1]

50

1

T176

1

T177

1

T253

2

all_values[3]

auto[0]

auto[0]

auto[0]

76

1

T176

3

T178

2

T252

2

all_values[3]

auto[0]

auto[0]

auto[1]

36

1

T177

1

T254

2

T352

2

all_values[3]

auto[0]

auto[1]

auto[0]

36

1

T178

1

T252

1

T357

1

all_values[3]

auto[0]

auto[1]

auto[1]

31

1

T177

1

T252

3

T253

1

all_values[3]

auto[1]

auto[0]

auto[1]

66

1

T176

1

T177

2

T178

1

all_values[3]

auto[1]

auto[1]

auto[1]

54

1

T252

1

T253

1

T254

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal